ADA4062-2BRZ [ADI]
Tiny, Low Power JFET-Input Op Amp; 微型，低功耗JFET输入运算放大器
| 型号： | ADA4062-2BRZ |
| 厂家： | 
ADI |
| 描述： | Tiny, Low Power JFET-Input Op Amp |
| 文件： | 总20页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tiny, Low Power JFET-Input Op Amp
ADA4062-2
PIN CONFIGURATIONS
FEATURES
Low input bias current: 50 pA maximum
Offset voltage
1.5 mV maximum for ADA4062-2 B grade
2.5 mV maximum for ADA4062-2 A grade
Offset voltage drift: 4 μV/°C typical
Slew rate: 3.3 V/ꢀs typical
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
ADA4062-2
TOP VIEW
(Not to Scale)
OUT B
–IN B
+IN B
Figure 1. 8-Lead Narrow-Body SOIC
CMRR: 90 dB typical
Low supply current: 165 μA typical
High input impedance
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
ADA4062-2
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Unity-gain stable
Packaging: SOIC, MSOP
Figure 2. 8-Lead MSOP
APPLICATIONS
Power control and monitoring
Active filters
Industrial/process control
Body probe electronics
Data acquisition
Integrators
Input buffering
GENERAL DESCRIPTION
Table 1. Low Power Op Amps
The ADA4062-2 is a dual JFET-input amplifier with industry-
leading performance. It offers lower power, offset voltage, drift
and ultralow bias current. The ADA4062-2 B grade features typical
low offset voltage of 0.5 mV, offset drift of 4 μV/°C, and bias current
of 2 pA. The ADA4062-2 is ideal for various applications, including
process control, industrial and instrumentation equipment, active
filtering, data conversion, buffering, and power control and
monitoring. With a low supply current of 165 μA per amplifier,
it is also very well suited for lower power applications. The
ADA4062-2 is specified for the extended industrial temperature
range of −40°C to +125°C and is available in lead-free SOIC and
MSOP packages.
Supply 40 V
36 V
12 V to 16 V
AD8641
AD8663
AD8642
AD8667
5 V
Single
Dual
OP97
AD820
AD8541
OP297
OP282
AD8682
AD822
OP482
AD8684
AD824
AD8542
AD8544
Quad
OP497
AD8643
AD8669
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADA4062-2
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information.............................................................. 14
Notch Filter ................................................................................. 14
High-Side Signal Conditioning ................................................ 14
Micropower Instrumentation Amplifier................................. 14
Phase Reversal ............................................................................ 14
Schematic......................................................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Power Sequencing ........................................................................ 4
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADA4062-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY
= 15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
B Grade
VOS
0.5
0.75
2
1.5
3
2.5
5
50
5
25
2.5
+15
mV
mV
mV
mV
pA
nA
pA
nA
V
−40°C ≤ TA ≤ +125°C
A Grade
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
Input Offset Current
IB
IOS
0.5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
B Grade
−11.5
CMRR
VCM = −11.5 V to +11.5 V
−40°C ≤ TA ≤ +125°C
VCM = −11.5 V to +11.5 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
80
80
74
70
76
72
90
90
83
dB
dB
dB
dB
dB
dB
A Grade
Large-Signal Voltage Gain
AVO
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
∆VOS/∆T −40°C ≤ TA ≤ +125°C
RIN
CINDM
CINCM
4
μV/°C
TΩ
pF
10
1.5
4.8
pF
VOH
VOL
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
13
12.5
13.5
V
V
V
V
Output Voltage Low
−13.8 −13
−12.5
−40°C ≤ TA ≤ +125°C
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
20
4
mA
Ω
f = 100 kHz, AV = 1
Power Supply Rejection Ratio
B Grade
PSRR
VSY
−40°C ≤ TA ≤ +125°C
VSY 4 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
=
4 V to 18 V
80
80
74
70
90
dB
dB
dB
dB
μA
μA
A Grade
=
90
Supply Current per Amplifier
ISY
165
200
220
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
SR
tS
GBP
ΦM
CS
RL = 10 kΩ, CL = 100 pF, AV = 1
To 0.01%, VIN = 2 V step, CL = 100 pF, RL = 5 kΩ, AV = 1
RL = 10 kΩ, AV = 1
RL = 10 kΩ, AV = 1
f = 10 kHz
3.3
3.5
1.4
80
V/μs
μs
MHz
Degrees
dB
130
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1.5
36
5
μV p-p
nV/√Hz
fA/√Hz
Voltage Noise Density
Current Noise Density
Rev. 0 | Page 3 of 20
ADA4062-2
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. It was
measured using a standard 2-layer board.
Parameter
Rating
18 V
VSY
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
VSY
Table 4. Thermal Resistance
Package Type
8-Lead SOIC
8-Lead MSOP
θJA
θJC
43
45
Unit
°C/W
°C/W
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
158
210
Lead Temperature (Soldering, 60 sec) 300°C
POWER SEQUENCING
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The op amp supply voltages must be established simultaneously
with, or before, any input signals are applied. If this is not
possible, the input current must be limited to 10 mA.
ESD CAUTION
Rev. 0 | Page 4 of 20
ADA4062-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
280
70
60
50
40
30
20
10
0
V
V
= ±15V
= 0V
V
V
= ±5V
= 0V
SY
CM
SY
CM
240
200
160
120
80
40
0
–3
–2
–1
0
1
2
3
–4
–3
–2
–1
0
1
2
3
4
V
(mV)
V
(mV)
OS
OS
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage Distribution
40
30
20
10
0
40
30
20
10
0
V
= ±15V
V
= ±5V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
–2
0
2
4
6
8
10
–2
0
2
4
6
8
10
TCV
(µV/°C)
TCV (µV/°C)
OS
OS
Figure 4. Input Offset Voltage Drift Distribution
Figure 7. Input Offset Voltage Drift Distribution
5
4
5
4
V
= ±15V
V
= ±5V
SY
SY
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–15 –12
–9
–6
–3
0
3
6
9
12
15
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
V
(V)
CM
CM
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 5 of 20
ADA4062-2
10000
10000
1000
100
10
V
= ±15V
V
= ±5V
SY
SY
1000
100
10
1
1
0.1
–50
0.1
–50
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Input Bias Current vs. Temperature
Figure 12. Input Bias Current vs. Temperature
5
4
3
2
1
0
3
2
V
= ±15V
V
= ±5V
SY
SY
1
0
–1
–2
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16
–3
–2
–1
0
1
2
3
4
5
V
(V)
V
(V)
CM
CM
Figure 10. Input Bias Current vs. Input Common-Mode Voltage
Figure 13. Input Bias Current vs. Input Common-Mode Voltage
10
10
V
= ±15V
V
= ±5V
SY
SY
V
– V
V
V
– V
V
CC
OH
CC
OH
1
1
– V
EE
– V
EE
OL
OL
0.1
0.01
0.1
0.01
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 11. Output Voltage to Supply Rail vs. Load Current
Figure 14. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 6 of 20
ADA4062-2
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
V
R
= ±15V
V
= ±5V
SY
L
SY
L
= 10kΩ
R
= 10kΩ
V
– V
OH
CC
V
– V
OH
CC
V
– V
EE
OL
V
– V
EE
OL
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Output Voltage to Supply Rail vs. Temperature
Figure 18. Output Voltage to Supply Rail vs. Temperature
120
100
80
120
100
80
120
100
80
120
100
80
V = ±5V
SY
V
= ±15V
SY
PHASE
PHASE
60
60
60
60
40
40
40
40
GAIN
GAIN
20
20
20
20
0
0
0
0
–20
–40
–60
–20
–40
–60
–20
–40
–60
–20
–40
–60
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Open-Loop Gain and Phase vs. Frequency
Figure 16. Open-Loop Gain and Phase vs. Frequency
50
50
V
= ±5V
SY
V
= ±15V
SY
A
A
= +100
= +10
V
A
A
= +100
= +10
V
40
30
40
30
V
V
20
20
10
10
A
= +1
V
A
= +1
V
0
0
–10
–20
–10
–20
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency
Figure 17. Closed-Loop Gain vs. Frequency
Rev. 0 | Page 7 of 20
ADA4062-2
1000
1000
100
10
V
= ±15V
V
= ±5V
SY
SY
100
10
1
A
= +100
= +10
V
A
= +100
= +10
V
A
V
A
V
A
= +1
V
A
= +1
V
1
0.1
100
0.1
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Output Impedance vs. Frequency
Figure 24. Output Impedance vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= ±15V
V
= ±5V
SY
SY
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. CMRR vs. Frequency
Figure 25. CMRR vs. Frequency
120
100
80
140
120
100
80
V
= ±5V
V
= ±15V
SY
SY
60
PSRR+
60
PSRR+
40
40
PSRR–
20
PSRR–
20
0
0
–20
–20
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. PSRR vs. Frequency
Figure 23. PSRR vs. Frequency
Rev. 0 | Page 8 of 20
ADA4062-2
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
A
R
= ±5V
= +1
V
A
R
= ±15V
= +1
SY
SY
V
L
V
L
= 10kΩ
= 10kΩ
10
100
1000
10000
10
100
1000
10000
C
(pF)
C
(pF)
L
L
Figure 27. Small-Signal Overshoot vs. Load Capacitance
Figure 30. Small-Signal Overshoot vs. Load Capacitance
V
V
A
R
C
= ±5V
= 4V p-p
= +1
V
V
A
R
C
= ±15V
= 20V p-p
= +1
SY
IN
SY
IN
V
L
L
V
L
L
= 10kΩ
= 100pF
= 10kΩ
= 100pF
TIME (4µs/DIV)
TIME (10µs/DIV)
Figure 31. Large-Signal Transient Response
Figure 28. Large-Signal Transient Response
V
V
A
R
C
= ±15V
= 100mV p-p
= +1
V
V
A
R
C
= ±5V
SY
IN
SY
IN
V
L
L
= 100mV p-p
= +1
V
L
L
= 10kΩ
= 10kΩ
= 100pF
= 100pF
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 32. Small-Signal Transient Response
Figure 29. Small-Signal Transient Response
Rev. 0 | Page 9 of 20
ADA4062-2
4
4
2
0
V
= ±15V
SY
V
= ±5V
SY
2
INPUT
INPUT
0
OUTPUT
0
OUTPUT
0
–5
–2
–4
–6
–10
–15
–20
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 33. Negative Overload Recovery
Figure 36. Negative Overload Recovery
2
0
2
0
V
= ±15V
V
= ±5V
SY
SY
INPUT
INPUT
–2
–2
15
10
5
4
2
OUTPUT
OUTPUT
0
0
–5
–2
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 34. Positive Overload Recovery
Figure 37. Positive Overload Recovery
V
= ±15V
V
= ±5V
SY
SY
INPUT
INPUT
IDEAL STEP
FUNCTION
OF 10V
+2mV
0V
+10mV
OUTPUT
OUTPUT
ERROR
BAND
0V
ERROR BAND
–10mV
–2mV
TIME (1µs/DIV)
TIME (2µs/DIV)
Figure 35. Positive Settling Time to 0.01%
Figure 38. Positive Settling Time to 0.01%
Rev. 0 | Page 10 of 20
ADA4062-2
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
+2mV
0V
+10mV
0V
OUTPUT
ERROR BAND
OUTPUT
ERROR
BAND
–2mV
–10mV
TIME (2µs/DIV)
TIME (1µs/DIV)
Figure 39. Negative Settling Time to 0.01%
Figure 42. Negative Settling Time to 0.01%
1000
100
10
1000
100
10
V
= ±5V
V
= ±15V
SY
SY
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 40. Voltage Noise Density
Figure 43. Voltage Noise Density
V
= ±15V
V
= ±5V
SY
SY
TIME (1s/DIV)
TIME (1s/DIV)
Figure 41. 0.1 Hz to 10 Hz Noise
Figure 44. 0.1 Hz to 10 Hz Noise
Rev. 0 | Page 11 of 20
ADA4062-2
410
390
370
350
330
310
290
270
410
390
370
350
330
310
290
125°C
85°C
V
= ±15V
SY
V
= ±5V
SY
25°C
–40°C
–50
–25
0
25
50
75
100
125
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
TEMPERATURE (°C)
SUPPLY VOLTAGE (±V)
Figure 45. Supply Current vs. Supply Voltage
Figure 48. Supply Current vs. Temperature
0
–20
0
–20
V
V
R
= ±5V
V
V
R
= ±15V
SY
IN
L
SY
IN
L
= 5V p-p
= 10V p-p
= 10kΩ
= 10kΩ
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 46. Channel Separation vs. Frequency
Figure 49. Channel Separation vs. Frequency
100
10
100
10
V
= ±15V
V
= ±5V
SY
SY
f = 1kHz
f = 1kHz
R
= 10kΩ
R = 10kΩ
L
L
1
1
0.1
0.1
0.01
0.01
0.001
0.001
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 47. THD + N vs. Amplitude
Figure 50. THD + N vs. Amplitude
Rev. 0 | Page 12 of 20
ADA4062-2
10
1
10
1
V
V
= ±15V
V
V
= ±5V
SY
IN
L
SY
IN
L
= 0.5 V rms
= 10kΩ
= 0.5 V rms
= 10kΩ
R
R
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 51. THD + N vs. Frequency
Figure 52. THD + N vs. Frequency
Rev. 0 | Page 13 of 20
ADA4062-2
APPLICATIONS INFORMATION
NOTCH FILTER
HIGH-SIDE SIGNAL CONDITIONING
There are many applications that require the sensing of signals
near the positive rail. The ADA4062-2 can be used in high-side
current sensing applications. Figure 55 shows a high-side signal
conditioning circuit using the ADA4062-2. The ADA4062-2 has
an input common-mode range that includes the positive supply
(−11.5 V ≤ VCM ≤ +15 V). In the circuit, the voltage drop across
a low value resistor, such as the 0.1 Ω shown in Figure 55, is
amplified by a factor of 5 using the ADA4062-2.
A notch filter rejects a specific interfering frequency and can
be implemented using a single op amp. Figure 53 shows a 60 Hz
notch filter that uses the twin T network with the ADA4062-2
configured as a voltage follower. The ADA4062-2 works as a buffer
that provides high input resistance and low output impedance.
The low bias current (2 pA typical) and high input resistance
(10 TΩ typical) of the ADA4062-2 enable large resistors and
small capacitors to be used.
0.1ꢀ
+15V
Alternatively, different combinations of resistors and capacitors
values can be used to achieve the desired notch frequency.
However, the major drawback to this circuit topology is the
need to ensure that all the resistors and capacitors be closely
matched. If they are not closely matched, the notch frequency
offset and drift cause the circuit to attenuate at a frequency
other than the ideal notch frequency.
500kꢀ
R
L
100kꢀ
+15V
100kꢀ
500kꢀ
V
1/2
O
ADA4062-2
–15V
Figure 55. High-Side Signal Conditioning
Therefore, to achieve the desired performance, 1% or better com-
ponent tolerances are usually required. In addition, a notch filter
requires an op amp with a bandwidth of at least 100 to 200 times
the center frequency. Hence, using the ADA4062-2 with a
bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter.
Figure 54 shows the gain of the notch filter with respect to
frequency. At 60 Hz, the notch filter has about 50 dB atten-
uation of signal.
MICROPOWER INSTRUMENTATION AMPLIFIER
The ADA4062-2 is a dual amplifier and is perfectly suited for
applications that require lower supply currents. For supply voltages
of 15 V, the supply current per amplifier is 165 μA typical. The
ADA4062-2 also offers a typical low offset voltage drift of 4 μV/°C
and a very low bias current of 2 pA, which makes it well suited for
instrumentation amplifiers.
Figure 56 shows the classic 2-op-amp instrumentation amplifier
with four resistors using the ADA4062-2. The key to high CMRR
for this instrumentation amplifier are resistors that are well
matched to both the resistive ratio and relative drift. For true
difference amplification, matching of the resistor ratio is very
important, where R3/R4 = R1/R2. Assuming perfectly matched
resistors, the gain of the circuit is 1 + R2/R1, which is approxi-
mately 100. Tighter matching of two op amps in one package,
as is the case with the ADA4062-2, offers a significant boost in
performance over the 3-op-amp configuration. Overall, the circuit
only requires about 330 μA of supply current.
+V
SY
R1
R2
1/2
–V
V
O
804kꢀ
804kꢀ
IN
ADA4062-2
C3
6.6nF
R3
SY
402kꢀ
C1
3.3nF
C2
3.3nF
1
fO
=
2π R
C
1
1
R1 = R2 = 2R3
C3
C1 = C2 =
2
R3
10.1kꢀ
R2
1Mꢀ
Figure 53. Notch Filter Circuit
+15V
R4
+15V
1Mꢀ
20
10
R1
10.1kꢀ
1/2
1/2
V
O
ADA4062-2
0
ADA4062-2
–15V
V1
V2
–10
–20
–30
–40
–50
–60
–70
–80
–15V
V
= 100(V2 – V1)
O
TYPICAL: 0.5mV < │V2 – V1│< 135mV
TYPICAL: –13.8V < V < +13.5V
USE MATCHED RESISTORS
O
Figure 56. Micropower Instrumentation Amplifier
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input common-
mode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input common-
mode voltage range, the output of the amplifiers changes polarity.
10
100
1k
FREQUENCY (Hz)
Figure 54. Notch Filter: Gain vs. Frequency
Rev. 0 | Page 14 of 20
ADA4062-2
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.
V
IN
V
= ±15V
SY
For the ADA4062-2, the output does not phase reverse if one or
both of the inputs exceeds the input voltage range but stays below
the positive supply rail and 0.5 V above the negative supply rail.
With a supply voltage of 15 V, phase reversal occurs when the
input voltage is a negative signal greater than −14.5 V. This is due
to saturation of the input stage leading to forward biasing of the
gate-drain diode. Phase reversal in ADA4062-2 can be prevented
by using a Schottky diode to clamp the input terminals to each
other. In the simple buffer circuit in Figure 57, D1 protects the
op amp against phase reversal and R limits the input current
that flows into the op amp.
V
OUT
TIME (40µs/DIV)
Figure 58. No Phase Reversal
+V
SY
R
10kꢀ
D1
IN5711
1/2
V
O
IN
ADA4062-2
–V
SY
Figure 57. Phase Reversal Solution Circuit
Rev. 0 | Page 15 of 20
ADA4062-2
SCHEMATIC
V
CC
OUT A/
OUT B
+IN A/
+IN B
–IN A/
–IN B
V
EE
Figure 59. Simplified Schematic
Rev. 0 | Page 16 of 20
ADA4062-2
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 60. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 61. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. 0 | Page 17 of 20
ADA4062-2
ORDERING GUIDE
Model
ADA4062-2ARMZ1
ADA4062-2ARMZ-RL1
ADA4062-2ARZ1
ADA4062-2ARZ-R71
ADA4062-2ARZ-RL1
ADA4062-2BRZ1
ADA4062-2BRZ-R71
ADA4062-2BRZ-RL1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package Option
Branding
A25
A25
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
1 Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
ADA4062-2
NOTES
Rev. 0 | Page 19 of 20
ADA4062-2
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07670-0-10/08(0)
Rev. 0 | Page 20 of 20
相关型号：
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