ADF4157BRUZ_技术文档

High Resolution 6 GHz Fractional-N

Frequency Synthesizer

ADF4157

FEATURES

GENERAL DESCRIPTION

RF bandwidth to 6 GHz

25-bit fixed modulus allows subhertz frequency resolution

2.7 V to 3.3 V power supply

Separate V_Pallows extended tuning voltage

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with the following frequency synthesizers:

ADF4110/ADF4111/ADF4112/ADF4113/

ADF4106/ADF4153/ADF4154/ADF4156

Cycle slip reduction for faster lock times

The ADF4157 is a 6 GHz fractional-N frequency synthesizer

with a 25-bit fixed modulus, allowing subhertz frequency

resolution at 6 GHz. It consists of a low noise digital phase

frequency detector (PFD), a precision charge pump, and

a programmable reference divider. There is a Σ-Δ based

fractional interpolator to allow programmable fractional-N

division. The INT and FRAC registers define an overall

N divider, N = INT + (FRAC/2²⁵). The ADF4157 features cycle

slip reduction circuitry, which leads to faster lock times without

the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire interface.

The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

APPLICATIONS

Satellite communications terminals, radar equipment

Instrumentation equipment

Personal mobile radio (PMR)

Base stations for mobile radio

Wireless handsets

FUNCTIONAL BLOCK DIAGRAM

AV

DD

DV

DD

V

R

SET

P

ADF4157

REFERENCE

4-BIT

R COUNTER

×2

REF

IN

DOUBLER

÷2

DIVIDER

+

PHASE

CP

CHARGE

PUMP

FREQUENCY

DETECTOR

–

V

DD

HIGH Z

CSR

DGND

LOCK

DETECT

CURRENT

SETTING

OUTPUT

MUX

MUXOUT

SD

OUT

V

DD

RFCP4 RFCP3 RFCP2 RFCP1

R

N

DIV

RF

A

B

IN

N COUNTER

IN

THIRD ORDER

FRACTIONAL

INTERPOLATOR

CE

CLK

DATA

LE

FRACTION MODULUS

INTEGER

REG

32-BIT

DATA

REGISTER

25

REG

2

AGND

DGND

CPGND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADF4157

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Shift Registers......................................................................9

Program Modes .............................................................................9

Register Maps.................................................................................. 10

FRAC/INT Register (R0) Map.................................................. 11

LSB FRAC Register (R1) Map .................................................. 12

R Divider Register (R2) Map .................................................... 13

Function Register (R3) Map ..................................................... 15

Test Register (R4) Map .............................................................. 16

Applications Information.............................................................. 17

Initialization Sequence .............................................................. 17

RF Synthesizer: A Worked Example........................................ 17

Reference Doubler and Reference Divider ............................. 17

Cycle Slip Reduction for Faster Lock Times........................... 17

Spur Mechanisms ....................................................................... 18

Low Frequency Applications .................................................... 18

Filter Design—ADIsimPLL....................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for the Chip Scale Package.............. 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description........................................................................... 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

RF INT Divider............................................................................. 8

25-Bit Fixed Modulus .................................................................. 8

INT, FRAC, and R Relationship ................................................. 8

RF R Counter ................................................................................ 8

Phase Frequency Detector (PFD) and Charge Pump.............. 9

MUXOUT and LOCK Detect..................................................... 9

REVISION HISTORY

7/07—Revision 0: Initial Revision

Rev. 0 | Page 2 of 20

ADF4157

SPECIFICATIONS

AV_DD= DV_DD= 2.7 V to 3.3 V; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 1.

Parameter

B Version¹

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Frequency (RF_IN)

0.5/6.0

GHz min/max

−10 dBm/0 dBm min/max. For lower frequencies, ensure slew

rate (SR) > 400 V/μs.

REFERENCE CHARACTERISTICS

REF_INInput Frequency

REF_INInput Sensitivity

10/300

0.4/AV_DD

0.7/AV_DD

10

MHz min/max

V p-p min/max

pF max

For f < 10 MHz, ensure slew rate > 50 V/μs.

For 10 MHz < REF_IN< 250 MHz. Biased at AV_DD/2².

For 250 MHz < REF_IN< 300 MHz. Biased at AV_DD/2².

REF_INInput Capacitance

REF_INInput Current

PHASE DETECTOR

Phase Detector Frequency³

CHARGE PUMP

100

μA max

32

MHz max

I_CPSink/Source

Programmable.

High Value

Low Value

Absolute Accuracy

R_SETRange

I_CPThree-State Leakage Current

Matching

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

5

mA typ

μA typ

% typ

kΩ min/max

nA typ

% typ

With R_SET= 5.1 kΩ.

312.5

2.5

2.7/10

1

2

With R_SET= 5.1 kΩ.

Sink and source current.

0.5 V < V_CP< V_P– 0.5.

V_CP= V_P/2.

% typ

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

LOGIC OUTPUTS

V_OH, Output High Voltage

V_OL, Output Low Voltage

POWER SUPPLIES

AV_DD

1.4

0.6

1

V min

V max

μA max

pF max

10

1.4

VDD – 0.4

0.4

V min

V max

Open-drain 1 kΩ pull-up to 1.8 V.

CMOS output chosen.

I_OL= 500 μA.

2.7/3.3

AV_DD

AV_DD/5.5

29

V min/V max

DV_DD

V_P

I_DD

V min/V max

mA max

23 mA typical.

Low Power Sleep Mode

NOISE CHARACTERISTICS

Phase Noise Figure of Merit⁴

ADF4157 Phase Noise Floor⁵

10

μA typ

−207

−137

−133

dBc/Hz typ

@ 10 MHz PFD frequency.

@ 25 MHz PFD frequency.

@ VCO output.

Phase Noise Performance⁶

5800 MHz Output⁷

−87

dBc/Hz typ

@ 2 kHz offset, 25 MHz PFD frequency.

¹Operating temperature of B version is −40°C to +85°C.

²AC-coupling ensures AV_DD/2 bias.

³Guaranteed by design. Sample tested to ensure compliance.

⁴This figure can be used to calculate phase noise for any application. Use the formula –207 + 10log(f_PFD) + 20logN to calculate in-band phase noise performance as seen

at the VCO output.

⁵The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

⁶The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system.

⁷f_REFIN= 100 MHz; f_PFD= 25 MHz; offset frequency = 2 kHz; RF_OUT= 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.

Rev. 0 | Page 3 of 20

ADF4157

TIMING SPECIFICATIONS

AV_DD= DV_DD= 2.7 V to 3.3 V; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 2.

Parameter

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

LE setup time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

20

10

25

10

20

ns min

DATA to CLOCK setup time

DATA to CLOCK hold time

CLOCK high duration

CLOCK low duration

CLOCK to LE setup time

LE pulse width

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

DB23 (MSB)

DB22

DATA

LE

(CONTROL BIT C1)

t₇

t₁

t₆

LE

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 20

ADF4157

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, GND = AGND = DGND = 0 V, V_DD= AV_DD= DV_DD, unless otherwise noted.

Table 3.

Parameter

THERMAL RESISTANCE

Rating

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

V_DDto GND

V_DDto V_DD

V_Pto GND

V_Pto V_DD

Digital I/O Voltage to GND

Analog I/O Voltage to GND

REF_IN, RF_INto GND

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

Reflow Soldering

−0.3 V to +4 V

−0.3 V to +0.3 V

−0.3 V to +5.8 V

−0.3 V to V_DD+ 0.3 V

Table 4. Thermal Resistance

Package Type

TSSOP

LFCSP (Paddle Soldered)

θ_JA

Unit

°C/W

112

30.4

ESD CAUTION

−40°C to +85°C

−65°C to +125°C

150°C

Peak Temperature

Time at Peak Temperature

260°C

40 sec

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 5 of 20

ADF4157

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

R

1

2

3

4

5

6

7

8

16

V

SET

P

15

CP

DV

DD

CPGND

AGND

14 MUXOUT

13

ADF4157

PIN 1

INDICATOR

TOP VIEW

CPGND

AGND

1

2

3

4

5

15 MUXOUT

14 LE

13 DATA

12 CLK

11 CE

LE

(Not to Scale)

RF

B

12 DATA

11 CLK

10 CE

ADF4157

IN

TOP VIEW

RF

B

A

IN

(Not to Scale)

AV

DD

9

REF

DGND

IN

Figure 3. TSSOP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

TSSOP LFCSP Mnemonic Description

1

19

R_SET

Connecting a resistor between this pin and ground sets the maximum charge pump output current.

The relationship between I_CPand R_SETis

25 .5

I_CPMAX

=

R_SET

where:

R_SET= 5.1 kΩ.

I_CPMAX= 5 mA.

2

20

CP

Charge Pump Output. When enabled, this provides I_CPto the external loop filter which, in turn, drives

the external VCO.

3

4

5

1

2, 3

4

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with

a small bypass capacitor, typically 100 pF.

6

7

5

6, 7

RF_INA

AV_DD

Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AV_DDhas a value of 3 V 10%. AV_DDmust have the same voltage as

DV_DD.

8

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-

coupled.

9

10

9, 10

11

DGND

CE

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode.

11

12

13

14

15

12

13

14

15

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is

a high impedance CMOS input.

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the five latches, the latch being selected using the control bits.

This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.

DATA

LE

MUXOUT

16, 17 DV_DD

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. DV_DDhas a value of 3 V 10%. DV_DDmust have the same voltage as

AV_DD.

16

18

V_P

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems where V_DDis 3 V, it can

be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

Rev. 0 | Page 6 of 20

ADF4157

TYPICAL PERFORMANCE CHARACTERISTICS

PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, I_CP= 313 μA, phase noise measurements taken on the Agilent E5052A

phase noise system.

6.00

5.95

5.90

5.85

5.80

5.75

5.70

5.65

10

5

0

CSR ON

–5

–10

–15

–20

–25

–30

–35

–40

P = 4/5

P = 8/9

CSR OFF

–100

0

100 200 300 400 500 600 700 800 900

TIME (µs)

0

1

2

3

4

5

6

7

8

9

FREQUENCY (GHz)

Figure 5. RF Input Sensitivity

Figure 8. Lock Time for 200 MHz Jump from 5705 MHz to 5905 MHz

with CSR On and Off

5.95

0

–5

V

= 3V

DD

5.90

–10

–15

–20

–25

–30

–35

–40

5.85

CSR OFF

5.80

5.75

5.70

CSR ON

5.65

5.60

–100

0

100 200 300 400 500 600 700 800 900

TIME (µs)

0

100

200

300

400

500

FREQUENCY (MHz)

Figure 6. Reference Input Sensitivity

Figure 9. Lock Time for 200 MHz Jump from 5905 MHz to 5705 MHz

with CSR On and Off

0

–20

RF = 5800.25MHz, PFD = 25MHz, N = 232,

FRAC = 335544, FREQUENCY RESOLUTION = 0.74Hz,

6

20kHz LOOP BW, I = 313µA, DSB INTEGRATED PHASE

CP

ERROR = 0.97° RMS, PHASE NOISE @ 2kHz = –87dBc/Hz.

4

–40

–60

2

–80

0

–100

–120

–140

–160

–2

–4

–6

1k

10k

100k

1M

10M

0

0.5

1.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

4.5

5.0

FREQUENCY (Hz)

V

CP

Figure 10. Charge Pump Output Characteristics, Pump Up and Pump Down

Figure 7. Phase Noise and Spurs

(Note that the 250 kHz spur is an integer boundary spur; see the Spur

Mechanisms section for more information.)

Rev. 0 | Page 7 of 20

ADF4157

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

INT, FRAC, AND R RELATIONSHIP

The INT and FRAC values, in conjunction with the R counter,

make it possible to generate output frequencies that are spaced

by fractions of the phase frequency detector (PFD). See the RF

Synthesizer: A Worked Example section for more information.

The RF VCO frequency (RF_OUT) equation is

The reference input stage is shown in Figure 11. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

RF_OUT= f_PFD× (INT + (FRAC/2²⁵))

(1)

POWER-DOWN

CONTROL

where:

100kΩ

RF_OUTis the output frequency of the external voltage controlled

oscillator (VCO).

INT is the preset divide ratio of the binary 12-bit counter (23 to

NC

SW2

TO R COUNTER

REF

IN

NC

SW1

BUFFER

SW3

4095).

NC

FRAC is the numerator of the fractional division (0 to 2²⁵− 1).

Figure 11. Reference Input Stage

f

_PFD= REF_IN× [(1 + D)/(R × (1+T))]

(2)

where:

RF INPUT STAGE

REF_INis the reference input frequency.

D is the REF_INdoubler bit.

R is the preset divide ratio of the binary 5-bit programmable

reference counter (1 to 32).

The RF input stage is shown in Figure 12. It is followed by

a 2-stage limiting amplifier to generate the current-mode logic

(CML) clock levels needed for the prescaler.

T is the REF_INdivide-by-2 bit (0 or 1).

1.6V

BIAS

GENERATOR

RF R COUNTER

AV

DD

The 5-bit RF R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 32 are allowed.

2kΩ

RF

A

B

IN

RF N DIVIDER

N = INT + FRAC/MOD

FROM RF

INPUT STAGE

TO PFD

N-COUNTER

IN

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

INT

REG

MOD

REG

FRAC

VALUE

AGND

Figure 12. RF Input Stage

RF INT DIVIDER

Figure 13. RF N Divider

The RF INT counter allows a division ratio in the PLL feedback

counter. Division ratios from 23 to 4095 are allowed.

25-BIT FIXED MODULUS

The ADF4157 has a 25-bit fixed modulus. This allows output

frequencies to be spaced with a resolution of

f

_RES= f_PFD/2²⁵

where f_PFDis the frequency of the phase frequency detector

(PFD). For example, with a PFD frequency of 10 MHz,

frequency steps of 0.298 Hz are possible.

Rev. 0 | Page 8 of 20

ADF4157

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

INPUT SHIFT REGISTERS

The ADF4157 digital section includes a 5-bit RF R counter,

a 12-bit RF N counter, and a 25-bit FRAC counter. Data is

clocked into the 32-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from

the shift register to one of five latches on the rising edge of LE.

The destination latch is determined by the state of the three

control bits (C3, C2, and C1) in the shift register. These are

the three LSBs, DB2, DB1, and DB0, as shown in Figure 2.

The truth table for these bits is shown in Table 6. Figure 16

shows a summary of how the latches are programmed.

The PFD takes inputs from the R counter and the N counter

and produces an output proportional to the phase and

frequency difference between them. Figure 14 is a simplified

schematic of the phase frequency detector. The PFD includes

a fixed delay element that sets the width of the antibacklash

pulse, which is typically 3 ns. This pulse ensures that there is no

dead zone in the PFD transfer function and gives a consistent

reference spur level.

UP

HI

D1

Q1

U1

PROGRAM MODES

+IN

CLR1

Table 6 and Figure 16 through Figure 21 show how to set up

the program modes in the ADF4157.

CHARGE

PUMP

CP

DELAY

DOWN

U3

Several settings in the ADF4157 are double-buffered. These

include the LSB FRAC value, R counter value, reference doubler,

and current setting. This means that two events have to occur

before the part uses a new value of any of the double-buffered

settings. First, the new value is latched into the device by

writing to the appropriate register. Second, a new write must be

performed on Register R0.

CLR2

D2 Q2

HI

U2

–IN

Figure 14. PFD Simplified Schematic

For example, updating the fractional value can involve a write

to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should

be written to first, followed by the write to R0. The frequency

change begins after the write to R0. Double buffering ensures

that the bits written to in R1 do not take effect until after

the write to R0.

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4157 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M4, M3, M2, and M1 (see Figure

17). Figure 15 shows the MUXOUT section in block diagram

form.

Table 6. C3, C2, and C1 Truth Table

Control Bits

THREE-STATE OUTPUT

C3

0

C2

0

1

C1

0

1

0

1

Register

DV

DD

DV

DD

Register R0

Register R1

Register R2

Register R3

Register R4

DGND

R DIVIDER OUTPUT

N DIVIDER OUTPUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

SERIAL DATA OUTPUT

CLK DIVIDER OUTPUT

R DIVIDER/2

1

0

MUX

CONTROL

MUXOUT

N DIVIDER/2

DGND

Figure 15. MUXOUT Schematic

Rev. 0 | Page 9 of 20

ADF4157

REGISTER MAPS

FRAC/INT REGISTER (R0)

MUXOUT

CONTROL

12-BIT MSB FRACTIONAL VALUE

(FRAC)

CONTROL

BITS

12-BIT INTEGER VALUE (INT)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)

0

LSB FRAC REGISTER (R1)

13-BIT LSB FRACTIONAL VALUE

(FRAC) (DBB)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F13 F12 F11 F10 F9

F8

F7

F6

F5

F4

F3

F2

F1

0

C3(0) C2(0) C1(1)

R DIVIDER REGISTER (R2)

DBB

CURRENT

SETTING

CONTROL

BITS

5-BIT R-COUNTER

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C1 CPI4 CPI3 CPI2 CPI1

0

P1

U2

U1

R5

R4

R3

R2

R1

0

C3(0) C2(1) C1(0)

FUNCTION REGISTER (R3)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

U12

0

U11 U10 U9

U8

U7 C3(0) C2(1) C1(1)

TEST REGISTER (R4)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(1) C2(0) C1(0)

0

NOTES

1. DBB = DOUBLE BUFFERED BIT(S).

Figure 16. Register Summary

Rev. 0 | Page 10 of 20

ADF4157

FRAC/INT REGISTER (R0) MAP

used in Equation 1. See the INT, FRAC, and R Relationship

section for more information.

With R0[2, 1, 0] set to [0, 0, 0], the on-chip Frac/Int register is

programmed as shown in Figure 17.

12-Bit MSB FRAC Value

Reserved Bit

These twelve bits, along with Bits DB[27:15] in the LSB FRAC

register (R1), control what is loaded as the FRAC value into

the fractional interpolator. This is part of what determines the

overall feedback division factor. It is also used in Equation 1.

These 12 bits are the most significant bits (MSB) of the 25-bit

FRAC value, and Bits DB[27:15] in the LSB FRAC register (R1)

are the least significant bits (LSB). See the RF Synthesizer: A

Worked Example section for more information.

The reserved bit should be set to 0 for normal operation.

MUXOUT

The on-chip multiplexer is controlled by DB[30], DB[29],

DB[28] and DB[27] on the ADF4157. See Figure 17 for

the truth table.

12-Bit INT Value

These twelve bits control what is loaded as the INT value. This

is used to determine the overall feedback division factor. It is

MUXOUT

12-BIT MSB FRACTIONAL VALUE

(FRAC)

CONTROL

BITS

12-BIT INTEGER VALUE (INT)

CONTROL

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

M4

M3

M2

M1 N12 N11 N10 N9

N8

N7

N6

N5

N4

N3

N2

N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)

MSB FRACTIONAL VALUE

M4

0

1

M3

M2

M1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OUTPUT

THREE-STATE OUTPUT

DV

F12

0

.

F11

0

.

..........

F2

0

1

.

F1

0

1

0

1

.

(FRAC)*

0

1

0

1

0

1

0

1

0

1

0

1

0

DD

1

DGND

2

R DIVIDER OUTPUT

N DIVIDER OUTPUT

RESERVED

3

.

DIGITAL LOCK DETECT

SERIAL DATA OUTPUT

RESERVED

.

1

0

1

0

1

0

1

4092

4093

4094

4095

RESERVED

CLK DIVIDER

RESERVED

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

RESERVED

REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN

13

R DIVIDER/2

REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2

.

N DIVIDER/2

RESERVED

INTEGER VALUE

N12

N11

N10

N9

N8

0

.

N7

0

.

N6

N5

1

.

N4

0

1

.

N3

1

0

.

N2

1

0

1

.

N1

1

0

1

0

.

(INT)

0

.

0

.

0

.

0

.

0

.

23

24

25

26

.

1

0

1

0

1

4093

4094

4095

Figure 17. FRAC/INT Register (R0) Map

Rev. 0 | Page 11 of 20

ADF4157

LSB FRAC REGISTER (R1) MAP

With R1[2, 1, 0] set to [0, 0, 1], the on-chip LSB FRAC register

is programmed as shown in Figure 18.

value, and Bits DB[14:3] in the INT/FRAC register are the most

significant bits. See the RF Synthesizer: A Worked Example

section for more information.

13-Bit LSB FRAC Value

Reserved Bits

These thirteen bits, along with Bits DB[14:3] in the INT/FRAC

register (R0), control what is loaded as the FRAC value into

the fractional interpolator. This is part of what determines

the overall feedback division factor. It is also used in Equation 1.

These 13 bits are the least significant bits of the 25-bit FRAC

All reserved bits should be set to 0 for normal operation.

13-BIT LSB FRACTIONAL VALUE

CONTROL

RESERVED

(FRAC)

RESERVED

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F13 F12 F11 F10 F9

F8

F7

F6

F5

F4

F3

F2

F1

0

C3(0) C2(0) C1(1)

LSB FRACTIONAL VALUE

(FRAC)*

F25

0

.

F24

0

.

..........

F14

0

1

.

F13

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

8188

8189

8190

8191

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN

13

REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2

.

Figure 18. LSB FRAC Register (R1) Map

Rev. 0 | Page 12 of 20

ADF4157

R DIVIDER REGISTER (R2) MAP

With R1[2, 1, 0] set to [0, 1, 0], the on-chip R divider register is

programmed as shown in Figure 19.

With P = 4/5, N_MIN= 23.

With P = 8/9, N_MIN= 75.

CSR Enable

RDIV2

Setting this bit to 1 enables cycle slip reduction. This is a

method for improving lock times. Note that the signal at the PFD

must have a 50% duty cycle in order for cycle slip reduction to

work. In addition, the charge pump current setting must be set

to a minimum. See the Cycle Slip Reduction for Faster Lock

Times section for more information.

Setting this bit to 1 inserts a divide-by-2 toggle flip flop between

the R counter and the PFD. This can be used to provide a 50%

duty cycle signal at the PFD for use with cycle slip reduction.

Reference Doubler

Setting DB[20] to 0 feeds the REF_INsignal directly to the 5-bit

RF R counter, disabling the doubler. Setting this bit to 1

multiplies the REF_INfrequency by a factor of 2 before feeding

into the 5-bit R counter. When the doubler is disabled,

the REF_INfalling edge is the active edge at the PFD input to

the fractional synthesizer. When the doubler is enabled, both

the rising edge and falling edge of REF_INbecome active edges at

the PFD input.

Note also that the cycle slip reduction feature can only be

operated when the phase detector polarity setting is positive

(DB6 in Register R3). It cannot be used if the phase detector

polarity is set to negative.

Charge Pump Current Setting

DB[27], DB[26], DB[25], and DB[24] set the charge pump

current setting. This should be set to the charge pump current

that the loop filter is designed with (see Figure 19).

The maximum allowed REF_INfrequency when the doubler is

enabled is 30 MHz.

5-Bit R Counter

Prescaler (P/P + 1)

The 5-bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the phase frequency detector (PFD). Division ratios from

1 to 32 are allowed.

The dual-modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division ratio

from the RF_INto the PFD input.

Operating at CML levels, it takes the clock from the RF input

stage and divides it down for the counters. It is based on

a synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating

the ADF4157 above 3 GHz, the prescaler must be set to 8/9.

The prescaler limits the INT value.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Rev. 0 | Page 13 of 20

ADF4157

CURRENT

SETTING

CONTROL

BITS

5-BIT R-COUNTER

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C1 CPI4 CPI3 CPI2 CPI1

0

P1

U2

U1

R5

R4

R3

R2

R1

0

C3(0) C2(1) C1(0)

CYCLE SLIP

REDUCTION

REFERENCE

DOUBLER

C1

0

U1

DISABLED

ENABLED

0

1

DISABLED

ENABLED

1

U2

0

R DIVIDER

DISABLED

ENABLED

1

P1

0

PRESCALER

4/5

8/9

1

I

(mA)

R5

0

.

R4

0

.

R3

0

1

.

R2

0

1

0

.

R1

1

0

1

0

.

R COUNTER DIVIDE RATIO

CP

1

2

3

4

CPI4

CPI3

CPI2

CPI1

5.1kΩ

0.31

0.63

0.94

1.25

1.57

1.88

2.19

2.5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

.

1

0

1

0

1

0

1

0

1

.

29

30

31

32

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.81

3.13

3.44

3.75

4.06

4.38

4.69

5

Figure 19. R Divider Register (R2) Map

Rev. 0 | Page 14 of 20

ADF4157

FUNCTION REGISTER (R3) MAP

With R2[2, 1, 0] set to [0, 1, 1], the on-chip function register is

programmed as shown in Figure 20.

While in software power-down mode, the part retains all

information in its registers. Only when supplies are removed are

the register contents lost.

Reserved Bits

When a power-down is activated, the following events occur:

1. All active dc current paths are removed.

All reserved bits should be set to 0 for normal operation.

Σ-Δ Reset

2. The synthesizer counters are forced to their load state

conditions.

For most applications, DB14 should be set to 0. When DB14 is

set to 0, the Σ-Δ modulator is reset on each write to Register 0.

If it is not required that the Σ-Δ modulator be reset on each

Register 0 write, this bit should be set to 1.

3. The charge pump is forced into three-state mode.

4. The digital lock detect circuitry is reset.

5. The RF_INinput is debiased.

Lock Detect Precision (LDP)

When DB[7] is programmed to 0, 24 consecutive PFD cycles of

15 ns must occur before digital lock detect is set. When this bit

is programmed to 1, 40 consecutive reference cycles of 15 ns

must occur before digital lock detect is set.

6. The input register remains active and capable of loading

and latching data.

RF Charge Pump Three-State

DB[4] puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

Phase Detector Polarity

DB[6] in the ADF4157 sets the phase detector polarity. When

the VCO characteristics are positive, this should be set to 1.

When they are negative, it should be set to 0.

RF Counter Reset

DB[3] is the RF counter reset bit for the ADF4157. When this is

1, the RF synthesizer counters are held in reset. For normal

operation, this bit should be 0.

RF Power-Down

DB[5] on the ADF4157 provides the programmable power-

down mode. Setting this bit to 1 performs a power-down.

Setting this bit to 0 returns the synthesizer to normal operation.

CONTROL

RESERVED

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

U12

0

U11 U10 U9

U8

U7 C3(0) C2(1) C1(1)

COUNTER

U11

0

LDP

U7

RESET

24 PFD CYCLES

40 PFD CYCLES

0

1

DISABLED

ENABLED

1

U12 SD RESET

0

1

ENABLED

DISABLED

CP

U10

0

PD POLARITY

U8

THREE-STATE

NEGATIVE

POSITIVE

0

1

DISABLED

ENABLED

1

U9

0

POWER DOWN

DISABLED

1

ENABLED

Figure 20. Function Register (R3) Map

Rev. 0 | Page 15 of 20

ADF4157

TEST REGISTER (R4) MAP

With R3[2, 1, 0] set to [1, 0, 0], the on-chip test register (R4) is

programmed as shown in Figure 21.

Reserved Bits

DB[31:3] should be set to 0 in this register.

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(1) C2(0) C1(0)

0

SET THESE BITS TO 0

Figure 21. Test Register (R4) Map

Rev. 0 | Page 16 of 20

ADF4157

APPLICATIONS INFORMATION

note that the PFD cannot be operated above 32 MHz due to

a limitation in the speed of the Σ-Δ circuit of the N divider.

INITIALIZATION SEQUENCE

After powering up the part, this programming sequence must

be followed:

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

In fast-locking applications, a wide loop filter bandwidth is

required for fast frequency acquisition, resulting in increased

integrated phase noise and reduced spur attenuation. Using

cycle slip reduction, the loop bandwidth can be kept narrow to

reduce integrated phase noise and attenuate spurs while still

realizing fast lock times.

1. Test Register (R4)

2. Function Register (R3)

3. R Divider Register (R2)

4. LSB FRAC Register (R1)

5. FRAC/INT Register (R0)

RF SYNTHESIZER: A WORKED EXAMPLE

Cycle Slips

The following equation governs how the synthesizer should be

programmed:

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the PLL

to correct, and the charge pump temporarily pumps in the wrong

direction, slowing down the lock time dramatically. The ADF4157

contains a cycle slip reduction circuit to extend the linear range

of the PFD, allowing faster lock times without loop filter changes.

RF_OUT= [N + (FRAC/2²⁵)] × [f_PFD

]

(3)

where:

RF_OUTis the RF frequency output.

N is the integer division factor.

FRAC is the fractionality.

When the ADF4157 detects that a cycle slip is about to occur, it

turns on an extra charge pump current cell. This outputs a constant

current to the loop filter or removes a constant current from the

loop filter (depending on whether the VCO tuning voltage needs

to increase or decrease to acquire the new frequency). The effect is

that the linear range of the PFD is increased. Stability is main-

tained because the current is constant and is not a pulsed current.

f

_PFD= REF_IN× [(1 + D)/(R × (1 + T))]

(4)

where:

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

R is the RF reference division factor.

T is the reference divide-by-2 bit (0 or 1).

For example, in a system where a 5.8002 GHz RF frequency

output (RF_OUT) is required and a 10 MHz reference frequency

input (REF_IN) is available, the frequency resolution is

If the phase error increases again to a point where another cycle

slip is likely, the ADF4157 turns on another charge pump cell.

This continues until the ADF4157 detects that the VCO

frequency has gone past the desired frequency. It then begins to

turn off the extra charge pump cells one by one until they are all

turned off and the frequency is settled.

f

_RES= REF_IN/2²⁵

_RES= 10 MHz/2²⁵= 0.298 Hz

From Equation 4,

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

f

_PFD= [10 MHz × (1 + 0)/1] = 10 MHz

5.8002 GHz = 10 MHz × (N + FRAC/2²⁵)

Calculating N and FRAC values,

Setting Bit DB28 in the R Divider register (R2) to 1 enables

cycle slip reduction. Note that a 45% to 55% duty cycle is

needed on the signal at the PFD in order for CSR to operate

correctly. The reference divide-by-2 flip-flop can help to

provide a 50% duty cycle at the PFD. For example, if a 100 MHz

reference frequency is available, and the user wants to run the

PFD at 10 MHz, setting the R divide factor to 10 results in a 10

MHz PFD signal that is not 50% duty cycle. By setting the R

divide factor to 5 and enabling the reference divide-by-2 bit, a

50% duty cycle 10 MHz signal can be achieved.

N = int(RF_OUT/f_PFD) = 580

FRAC = F_MSB× 2¹³+ F_LSB

F

_MSB= int(((RF_OUT/f_PFD) − N) × 2¹²) = 81

_LSB= int(((((RF_OUT/f_PFD) − N) × 2¹²) − F_MSB) × 2¹³) = 7537

where:

F

_MSBis the 12-bit MSB FRAC value in Register R0.

_LSBis the 13-bit LSB FRAC value in Register R1.

int() makes an integer of the argument in brackets.

REFERENCE DOUBLER AND REFERENCE DIVIDER

Note that the cycle slip reduction feature can only be operated

when the phase detector polarity setting is positive (DB6 in

Register R3). It cannot be used if the phase detector polarity is

set to negative.

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the noise

performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important to

Rev. 0 | Page 17 of 20

ADF4157

SPUR MECHANISMS

LOW FREQUENCY APPLICATIONS

The fractional interpolator in the ADF4157 is a third-order Σ-Δ

modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM

is clocked at the PFD reference rate (f_PFD) that allows PLL output

frequencies to be synthesized at a channel step resolution of

The specification on the RF input is 0.5 GHz minimum;

however, RF frequencies lower than this can be used providing

the minimum slew rate specification of 400 V/ꢀs is met.

An appropriate LVDS driver can be used to square up the RF

signal before it is fed back to the ADF4157 RF input. The FIN1001

from Fairchild Semiconductor is one such LVDS driver.

f

_PFD/MOD. The various spur mechanisms possible with

fractional-N synthesizers, and how they affect the ADF4157,

are discussed in this section.

FILTER DESIGN—ADIsimPLL

Fractional Spurs

A filter design and analysis program is available to help the user

implement PLL design. Visit www.analog.com/pll for a free

download of the ADIsimPLL™ software. The software designs,

simulates, and analyzes the entire PLL frequency domain and

time domain response. Various passive and active filter

architectures are allowed.

In most fractional synthesizers, fractional spurs can appear at

the set channel spacing of the synthesizer. In the ADF4157,

these spurs do not appear. The high value of the fixed modulus

in the ADF4157 makes the Σ-Δ modulator quantization error

spectrum look like broadband noise, effectively spreading

the fractional spurs into noise.

INTERFACING

Integer Boundary Spurs

The ADF4157 has a simple SPI-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When latch enable (LE) is high, the 29 bits that have

been clocked into the input register on each rising edge of

SCLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 6 for the latch truth table.

Interactions between the RF VCO frequency and the PFD

frequency can lead to spurs known as integer boundary spurs.

When these frequencies are not integer related (which is

the purpose of the fractional-N synthesizer), spur sidebands

appear on the VCO output spectrum at an offset frequency that

corresponds to the beat note or difference frequency between

an integer multiple of the PFD and the VCO frequency.

The maximum allowable serial clock rate is 20 MHz.

PCB DESIGN GUIDELINES FOR THE CHIP SCALE

PACKAGE

These spurs are named integer boundary spurs because they are

more noticeable on channels close to integer multiples of the PFD

where the difference frequency can be inside the loop band-

width. These spurs are attenuated by the loop filter.

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the pad.

This ensures that the solder joint size is maximized.

Figure 7 shows an integer boundary spur. The RF frequency is

5800.25 MHz, and the PFD frequency is 25 MHz. The integer

boundary spur is 250 kHz from the carrier at an integer times

the PFD frequency (232 × 25 MHz = 5800 MHz). The spur also

appears on the upper sideband.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. One such

mechanism is the feedthrough of low levels of on-chip reference

switching noise out through the RF_INpin back to the VCO,

resulting in reference spur levels as high as –90 dBc. Care

should be taken in the PCB layout to ensure that the VCO is

well separated from the input reference to avoid a possible

feedthrough path on the board.

Thermal vias can be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated into the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 ounce

of copper to plug the via. The user should connect the printed

circuit board thermal pad to AGND.

Rev. 0 | Page 18 of 20

ADF4157

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 22. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.60

MAX

4.00

BSC SQ

PIN 1

INDICATOR

0.60

MAX

20

1

16

15

PIN 1

INDICATOR

2.25

2.10 SQ

1.95

TOP

VIEW

3.75

BCS SQ

11

10

5

6

0.75

0.55

0.35

0.25 MIN

0.80 MAX

0.65 TYP

0.30

0.23

0.18

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

0.20

REF

SEATING

PLANE

COPLANARITY

0.08

0.50

BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 23. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Description

Temperature Range

−40°C to +85°C

Package Option

ADF4157BRUZ¹

16-Lead Thin Shrink Small Outline Package [TSSOP]

20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

RU-16

CP-20-1

ADF4157BRUZ-RL¹

ADF4157BRUZ-RL7¹

ADF4157BCPZ¹

ADF4157BCPZ-RL¹

ADF4157BCPZ-RL7¹

EVAL-ADF4157EB1Z¹

¹Z = RoHS Compliant Part.

Rev. 0 | Page 19 of 20

ADF4157

NOTES

registered trademarks are the property of their respective owners.

D05874-0-7/07(0)

Rev. 0 | Page 20 of 20


型号：	ADF4157BRUZ
厂家：	ADI
描述：	High Resolution 6 GHz Fractional-N Frequency Synthesizer
文件：	总20页 (文件大小：404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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