ADG819BRMZ [ADI]
0.5 ohm, CMOS, 1.8V to 5.5V, 2:1 Mux/SPDT Switch; 0.5欧姆， CMOS ， 1.8V至5.5V ， 2 ： 1多路复用器/单刀双掷开关
| 型号： | ADG819BRMZ |
| 厂家： | 
ADI |
| 描述： | 0.5 ohm, CMOS, 1.8V to 5.5V, 2:1 Mux/SPDT Switch |
| 文件： | 总16页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.5 Ω, CMOS,
1.8 V to 5.5 V, 2:1 Mux/SPDT Switch
Data Sheet
ADG819
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low on resistance: 0.8 Ω maximum at 125°C
0.25 Ω maximum on resistance flatness
1.8 V to 5.5 V single supply
200 mA current carrying capability
Automotive temperature range: –40°C to +125°C
Rail-to-rail operation
ADG819
S2
D
S1
IN
6-lead SOT-23, 8-lead MSOP, and 6-ball WLCSP packages
Fast switching times
Typical power consumption (<0.01 µW)
TTL-/CMOS-compatible inputs
SWITCHES SHOWN
FOR A LOGIC 1 INPUT
Figure 1.
Pin compatible with the ADG719
APPLICATIONS
Power routing
Battery-powered systems
Communication systems
Data acquisition systems
Cellular phones
Modems
PCMCIA cards
Hard drives
Relay replacement
GENERAL DESCRIPTION
The ADG819 is a monolithic, CMOS, single-pole, double-throw
(SPDT) switch. This switch is designed on a submicron process
that provides low power dissipation yet gives high switching
speed, low on resistance, and low leakage currents.
PRODUCT HIGHLIGHTS
1. Very low on resistance, 0.5 Ω typical.
2. 1.8 V to 5.5 V single-supply operation.
3. High current carrying capability.
Low power consumption and an operating supply range of
1.8 V to 5.5 V make the ADG819 ideal for battery-powered,
portable instruments.
4. Tiny 6-lead SOT-23, 8-lead MSOP, and 6-ball, 1.14 mm ×
2.18 mm WLCSP packages.
Each switch of the ADG819 conducts equally well in both
directions when on. The ADG819 exhibits break-before-make
switching action, thus preventing momentary shorting when
switching channels.
The ADG819 is available in a 6-lead SOT-23 package, an 8-lead
MSOP package, and in a 6-ball WLCSP package. This chip
occupies only a 1.14 mm × 2.18 mm area, making it the ideal
candidate for space-constrained applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved.
ADG819
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions............................6
Typical Performance Characteristics ..............................................7
Test Circuits........................................................................................9
Terminology.................................................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
5/12—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted ADG820 ................................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Change to WLCSP θJA Thermal Impedance Parameter,
Table 3 ................................................................................................ 5
Added Table 5 and Table 6; Renumbered Sequentially ............... 6
Deleted Test Circuit 6; Renumbered Sequentially ....................... 8
Changes to Figure 11 to Figure 14.................................................. 8
Changes to Terminology Section.................................................. 11
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide .......................................................... 13
5/02—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
ADG819
SPECIFICATIONS
VDD = 5 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
−40°C to
+85°C
–40°C to
+125°C
Parameter
25°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
0.8
V
1
0.5
0.6
0.06
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 100 mA; see Figure 16
VS = 0 V to VDD, IS = 100 mA
0.7
On Resistance Match Between
1
Channels, ΔRON
0.08
0.1
0.17
0.1
0.2
0.12
0.25
Ω max
Ω typ
Ω max
1
On Resistance Flatness, RFLAT(ON)
VS = 0 V to VDD, IS = 100 mA
LEAKAGE CURRENTS
VDD = 5.5 V
Source Off Leakage, IS (Off)
0.01
0.25
0.01
0.25
nA typ
nA max
nA typ
nA max
VS = 4.5 V/1 V, VD = 1 V/4.5 V; see Figure 17
3
3
10
25
Channel On Leakage, ID, IS (On)
VS = VD = 1 V, or VS = VD = 4.5 V; see Figure 18
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.005
5
μA typ
μA max
pF typ
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
35
45
10
16
5
ns typ
ns max
ns typ
ns max
ns typ
RL = 50 Ω, CL = 35 pF, VS = 3 V; see Figure 19
RL = 50 Ω, CL = 35 pF, VS = 3 V; see Figure 19
RL = 50 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 20
50
18
55
21
tOFF
Break-Before-Make Time Delay,
tBBM
1
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Bandwidth, –3 dB
CS (Off)
20
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
RL = 50 Ω, CL = 5 pF; see Figure 23
f = 1 MHz
–71
–72
17
80
CD, CS (On)
300
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 5.5 V, digital inputs = 0 V or 5.5 V
0.001
μA typ
1.0
2.0
μA max
1 On resistance parameters tested with IS = 10 mA.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 16
ADG819
Data Sheet
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
–40°C to
+85°C
–40°C to
+125°C
Parameter
25°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
1.6
V
1
0.7
1.4
0.06
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 100 mA; see Figure 16
VS = 0 V to VDD, IS = 100 mA
1.5
On Resistance Match Between
1
Channels, ΔRON
0.13
0.13
Ω max
Ω typ
1
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
0.25
VS = 0 V to VDD, IS = 100 mA
VDD = 3.6 V
Source Off Leakage, IS (Off)
0.01
0.25
0.01
0.25
nA typ
nA max
nA typ
nA max
VS = 3.3 V/1 V, VD = 1 V/3.3 V; see Figure 17
3
3
10
25
Channel On Leakage, ID, IS (On)
VS = VD = 1 V, or VS = VD = 3.3 V; see Figure 18
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.005
5
μA typ
μA max
pF typ
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
40
60
10
16
40
ns typ
ns max
ns typ
ns max
ns typ
RL = 50 Ω, CL = 35 pF, VS = 1.5 V; see Figure 19
RL = 50 Ω, CL = 35 pF, VS = 1.5 V; see Figure 19
RL = 50 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 20
65
18
70
21
tOFF
Break-Before-Make Time Delay,
tBBM
1
ns min
pC typ
dB typ
dB typ
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Bandwidth, –3 dB
CS (Off)
10
VS = 1.5 V, RS = 0 Ω,CL = 1 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
−71
−72
17
80
300
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 23
pF typ
pF typ
f = 1 MHz
f = 1 MHz
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 3.6 V, digital Inputs = 0 V or 3.6 V
0.001
μA typ
1.0
2.0
μA max
1 On resistance parameters tested with IS = 10 mA.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 16
Data Sheet
ADG819
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C, unless otherwise noted
Table 3.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
Analog Inputs1
Digital Inputs1
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx or D
400 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Table 4. Truth Table for the ADG819
Continuous Current, Sx or D
Operating Temperature Range
Industrial
200 mA
IN
Switch S1
Switch S2
Off
0
On
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
1
Off
On
Automotive
Storage Temperature Range
Junction Temperature
MSOP
ESD CAUTION
θJA Thermal Impedance
θJC Thermal Impedance
SOT-23 (4-Layer Board)
θJA Thermal Impedance
WLCSP (4-Layer Board)
θJA Thermal Impedance
206°C/W
44°C/W
119°C/W
80°C/W
300°C
Lead Temperature, Soldering
(10 sec)
IR Reflow, Peak Temperature
(<20 sec)
235°C
1 Overvoltages at IN, Sx, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Rev. A | Page 5 of 16
ADG819
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
S2
1
IN
6
V
D
2
DD
5
S1
3
GND
4
6
5
4
1
2
3
S2
D
IN
ADG819
TOP VIEW
ADG819
TOP VIEW
(BUMPS AT THE BOTTOM)
NOT TO SCALE
V
DD
S1
GND
(Not to Scale)
Figure 3. 6-Ball WLCSP Pin Configuration
Figure 2. 6-Lead SOT-23 Pin Configuration
Table 5. 6-Lead SOT-23 and 6-Ball WLCSP Pin Function Descriptions
Pin No.
SOT-23
WLCSP
Mnemonic
Description
1
2
3
4
5
6
6
5
4
3
2
1
IN
Logic Control Input.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
VDD
GND
S1
D
S2
1
2
3
4
8
7
6
5
S2
D
S1
ADG819
NC
IN
GND
TOP VIEW
(Not to Scale)
V
NC
DD
NC = NO CONNECT
Figure 4. 8-Lead MSOP Pin Configuration
Table 6. 8-Lead MSOP Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
D
S1
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
No Connect. Do not connect to this pin.
Logic Control Input.
No Connect. Do not connect to this pin.
Source Terminal. Can be an input or output.
GND
VDD
NC
IN
NC
S2
Rev. A | Page 6 of 16
Data Sheet
ADG819
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.6
0.4
0.2
0
V
= 3V
T
= 25°C
= 3V
DD
A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 2.7V
DD
T
= +125°C
A
T
= +85°C
A
V
DD
T
= +25°C
A
V
= 3.3V
DD
V = 5V
DD
V
= 4.5V
T
= –40°C
DD
A
V
= 5.5V
DD
0
T
1
2
3
, V (V)
4
5
0
0.5
1.0
1.5
, V (V)
2.0
2.5
3.0
V
D
S
V
D
S
Figure 5. On Resistance vs. VD, VS
Figure 8. On Resistance vs. VD, VS for Different Temperatures
1.0
0.8
0.6
0.4
0.2
0
10
V
= 5V
= 25 C
= 1.8V
DD
A
9
8
7
6
5
4
3
2
1
0
V
DD
T
= +125°C
T
A
= +85°C
A
T
= +25°C
A
T
= –40°C
A
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1.0
, V (V)
1.2
1.4
1.6
1.8
V
V , V (V)
D S
D
S
Figure 6. On Resistance vs. VD, VS
Figure 9. On Resistance vs. VD, VS for Different Temperatures
10
8
50
V
= 3V, 5V
DD
40
30
20
10
0
V
= 3V
DD
tON
V
= 5V
DD
6
4
I
, I (ON)
S
D
2
V
= 3V, 5V
DD
tOFF
0
I (OFF)
S
–2
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Leakage Currents vs. Temperature
Figure 10. tON/tOFF Times vs. Temperature
Rev. A | Page 7 of 16
ADG819
Data Sheet
1
0
250
V
= 3V, 5V
= 25 C
T
= 25°C
DD
A
T
A
200
150
100
50
–1
–2
–3
–4
–5
–6
V
= 3V
V
= 5V
DD
DD
0
–50
–100
–150
–200
0.2
1
10
30
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
V
S
Figure 11. Charge Injection vs. VS (Source Voltage)
Figure 14. On Response vs. Frequency
0
1.8
1.6
1.4
V
A
= 5V, 3V
DD
T = 25°C
A
T
= 25°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
RISING
1.2
1.0
0.8
FALLING
0.6
0.4
0.2
0
0.1
1
2
0
1
2
3
4
5
6
FREQUENCY (MHz)
V
(V)
DD
Figure 15. Logic Threshold Voltage vs. Supply Voltage
Figure 12. Off Isolation vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.1
1
2
FREQUENCY (MHz)
Figure 13. Crosstalk vs. Frequency
Rev. A | Page 8 of 16
Data Sheet
ADG819
TEST CIRCUITS
I
DS
V1
I
(OFF)
I (OFF)
D
S
S
D
S
D
V
S
V
V
D
S
R
= V1 / I
DS
ON
Figure 17. Off Leakage
Figure 16. On Resistance
I
(ON)
D
S
D
NC
V
D
NC = NO CONNECT
Figure 18. On Leakage
V
DD
0.1µF
V
V
IN
DD
50%
50%
90%
90%
V
OUT
R
50
C
L
35pF
L
Ω
V
IN
S
tOFF
tON
GND
Figure 19. Switching Times
V
DD
0.1µF
V
DD
V
50%
50%
IN
0V
S1
V
D
S1
V
OUT
90%
0V
90%
V
OUT
R
50
C
L
35pF
S2
IN
L
Ω
V
S2
tBBM
tBBM
GND
V
IN
Figure 20. Break-Before-Make Time Delay, tBBM
V
DD
V
V
OUT
OUT
Q
= C
V
OUT
INJ
L
V
DD
R
SW OFF
SW OFF
SW OFF
S
V
OUT
V
IN
C
1nF
SW ON
SW ON
L
V
IN
S
V
IN
GND
SW OFF
Figure 21. Charge Injection
Rev. A | Page 9 of 16
ADG819
Data Sheet
V
DD
0.1µF
V
NETWORK
ANALYZER
DD
S
D
50
Ω
IN
50
Ω
V
S
V
OUT
R
L
50
Ω
GND
V
IN
V
OUT
OFF ISOLATION = 20 LOG
V
S
Figure 22. Off Isolation
V
DD
0.1µF
V
NETWORK
ANALYZER
DD
S
50Ω
IN
V
S
D
V
OUT
R
L
50Ω
GND
V
IN
V
WITH SWITCH
OUT
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
Figure 23. Bandwidth
V
DD
0.1µF
NETWORK
ANALYZER
V
DD
S1
S2
V
OUT
R
50
L
Ω
D
R
50
Ω
50
Ω
IN
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
S
Figure 24. Channel-to-Channel Crosstalk
Rev. A | Page 10 of 16
Data Sheet
ADG819
TERMINOLOGY
tON
RON
Delay between applying the digital control input and the output
switching on.
Ohmic resistance between D and Sx.
ΔRON
tOFF
On resistance match between any two channels, that is, RON
maximum − RON minimum.
Delay between applying the digital control input and the output
switching off.
RFLAT(ON)
tBBM
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Off time or on time measured between the 90% points of both
switches when switching from one address state to another.
Charge Injection
IS (Off)
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Source leakage current with the switch off.
ID, IS (On)
Channel-to-Channel Crosstalk
A measure of unwanted signal coupled through from one
channel to another as a result of parasitic capacitance.
Channel leakage current with the switch on.
VD (VS)
Analog voltage on Terminal D and Terminal S.
Off Isolation
VINL
A measure of unwanted signal coupling through an off switch.
Maximum input voltage for Logic 0.
Bandwidth
VINH
Frequency at which the output is attenuated by −3 dB.
Minimum input voltage for Logic 1.
On Response
Frequency response of the on switch.
I
INL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance.
CD, CS (On)
On switch capacitance.
Rev. A | Page 11 of 16
ADG819
Data Sheet
OUTLINE DIMENSIONS
3.00
2.90
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.30 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 25. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 26. 8-Lead mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. A | Page 12 of 16
Data Sheet
ADG819
0.67
0.57
0.47
1.34
1.14
0.94
0.44
0.36
0.28
2
1
SEATING
PLANE
0.32 NOM
0.50
BALL PITCH
A
B
C
BALL A1
IDENTIFIER
2.38
2.18
1.98
0.59
0.24 MAX
COPLANARITY
TOP VIEW
(BALL SIDE DOWN)
0.32
0.50
BOTTOM VIEW
(BALL SIDE UP)
Figure 27. 6-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-6-1)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1
Notes
Temperature Range Package Description
Branding2
SBC
SBC
SNB
SNB
SBC
SBC
SNB
SNB
SBC
SBC
SBC
3
ADG819BCBZ-REEL
ADG819BCBZ-REEL7
ADG819BRM
ADG819BRM-REEL
ADG819BRMZ
ADG819BRMZ-REEL7
ADG819BRT-500RL7
ADG819BRT-REEL7
ADG819BRTZ-500RL7
ADG819BRTZ-REEL
ADG819BRTZ-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
6-Ball Wafer Level Chip Package [WLCSP]
6-Ball Wafer Level Chip Package [WLCSP]
CB-6-1
CB-6-1
RM-8
RM-8
RM-8
RM-8
RJ-6
RJ-6
RJ-6
RJ-6
RJ-6
3
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
3
3
3
3
3
3
1 Z = RoHS Compliant Part.
2 Branding on these packages is limited to three characters due to space constraints.
3 Contact factory for availability.
Rev. A | Page 13 of 16
ADG819
NOTES
Data Sheet
Rev. A | Page 14 of 16
Data Sheet
NOTES
ADG819
Rev. A | Page 15 of 16
ADG819
NOTES
Data Sheet
©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02801-0-5/12(A)
Rev. A | Page 16 of 16
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