ADL5802ACPZ-R7_技术文档

Dual Channel, High IP3,

100 MHz to 6 GHz Active Mixer

ADL5802

FE ATURES

FUNCTIONAL BLOCK DIAGRAM

VPOS RF1+ RF1– GND RF2+RF2–

Power conversion gain of 1.6 dB

Wideband RF, LO, and IF ports

SSB noise figure of 11 dB

24

23

22

21

20

19

1

2

3

4

18

17

16

15

GND

OP2+

OP2–

Input IP3 of 28 dBm

Input P1dB of 12 dBm

Typical LO drive of 0 dBm

Low LO leakage

Single supply operation: 5 V @ 240 mA

Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package

OP1+

OP1–

GND

5

6

14 GND

IP3

BIAS

ADL5802

APPLICATIONS

VPOS

13 VPOS

Cellular base station receivers

Main and diversity receiver designs

Radio link downconverters

7

8

9

10

11

12

LOIN GND VSET

ENBL GND LOIP

Figure 1.

GENERAL DESCRIPTION

The IF outputs are designed for a 200 Ω source impedance and

provide a typical voltage conversion gain of 7.6 dB when loaded

into a 200 Ω load.

The ADL5802 uses high linearity, double-balanced, active mixer

cores with integrated LO buffer amplifiers to provide high

dynamic range frequency conversion from 100 MHz to 6 GHz.

The mixers benefit from a proprietary linearization architecture

that provides enhanced input IP3 performance when subject to

high input levels. A bias adjust feature allows the input linearity,

SSB noise figure, and dc current to be optimized using a single

control pin. The high input linearity allows the device to be used

in demanding cellular applications where in-band blocking

signals may otherwise result in degradation in dynamic perform-

ance. The balanced active mixer arrangement provides superb

LO to RF and LO to IF leakage, typically better than −30 dBm.

The ADL5802 is fabricated using a SiGe high performance IC

process. The device is available in a compact 4 mm × 4 mm,

24-lead LFCSP package and operates over a −40°C to +85°C

temperature range. An evaluation board is also available.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalog Devices for its use, norforany infringements ofpatents or other

rightsofthirdpartiesthat mayresult fromitsuse.Specificationssubjectto changewithoutnotice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADL5802

TABLE OF CONTENTS

Features .............................................................................................. 1

Spur Performance........................................................................21

Circuit Description..........................................................................24

LO Amplifier and Splitter...........................................................24

RF Voltage to Current (V-to-I) Converter ...............................24

Mixer Cores..................................................................................24

Mixer Load ...................................................................................24

Bias Circuit...................................................................................24

Applications Information ...............................................................25

Basic Connections .......................................................................25

RF and LO Ports ..........................................................................25

IF Port ...........................................................................................26

Evaluation Board .............................................................................27

Outline Dimensions ........................................................................29

Ordering Guide............................................................................29

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Downconverter Mode Using a Broadband Balun.................... 7

Downconverter Mode Using a Johanson 2.7 GHz Balun ..... 12

Downconverter Mode Using a Johanson 3.5 GHz Balun ..... 15

Downconverter Mode Using a Johanson 5.7 GHz Balun ..... 18

REVISION HISTORY

11/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADL5802

SPECIFICATIONS

V_S= 5 V, VSET = 4 V, T_A= 25°C, f_LO= (f_RF− 153) MHz, LO power = 0 dBm, Z₀¹= 50 Ω, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RF INPUT INTERFACE

Return Loss

Tunable to >20 dB over a limited bandwidth

18

50

dB

Ω

MHz

Input Impedance

RF Frequency Range

OUTPUT INTERFACE

Output Impedance

IF Frequency Range

DC Bias Voltage²

100

6000

Differential impedance, f = 200 MHz

Can be matched externally to 3000 MHz

Externally generated

240

V_S

Ω

MHz

V

LF

4.75

600

5.25

LO INTERFACE

LO Power

Return Loss

−10

0

18

50

+10

dBm

dB

Ω

Input Impedance

LO Frequency Range

POWER INTERFACE

Supply Voltage

Quiescent Current

Disable Current

100

6000

MHz

4.75

5

5.25

300

V

Resistor programmable

ENBL pin low

Time from ENBL pin low to power-up

Time from ENBL pin high to power-down

220

170

182

28

mA

ns

Enable Time

Disable Time

ns

DYNAMIC PERFORMANCE at f_RF= 900 MHz/1900 MHz

Power Conversion Gain³

f_RF= 900 MHz

f_RF= 1900 MHz

f_RF= 900 MHz

1.5

1.6

7.5

7.6

10

11

18

22

26

28

60

45

12

dB

dBm

dBc

Voltage Conversion Gain⁴

SSB Noise Figure

f_RF= 1900 MHz

f_CENT= 900 MHz

f_CENT= 1900 MHz

f_CENT= 900 MHz

f_CENT= 1900 MHz

f_CENT= 890 MHz

f_CENT= 1890 MHz

f_CENT= 890 MHz

f_CENT= 1890 MHz

f_RF= 900 MHz

SSB Noise Figure Under Blocking⁵

Input Third Order Intercept⁶

Input Second Order Intercept⁷

Input 1 dB Compression Point

f_RF= 1900 MHz

Unfiltered IF output

12

LO to IF Output Leakage

LO to RF Input Leakage

RF to IF Output Isolation

RFI1 to RFI2 Channel Isolation

IF/2 Spurious⁸

−35

−30

25

45

0 dBm input power, f_RF= 900 MHz

0 dBm input power, f_RF= 1900 MHz

−68

−67

−53

−59

IF/3 Spurious⁸

IF/2 Spurious⁸

IF/3 Spurious⁸

DYNAMIC PERFORMANCE at f_RF= 2500 MHz⁹

Power Conversion Gain¹⁰

Voltage Conversion Gain⁴

SSB Noise Figure

SSB Noise Figure Under Blocking¹¹

Input Third Order Intercept⁶

−0.5

5.67

11.5

18

dB

f_CENT= 2145 MHz

f_CENT= 2500 MHz

30

dBm

Rev. 0 | Page 3 of 32

ADL5802

Parameter

Test Conditions/Comments

f_CENT= 2500 MHz

Min

Typ

47

13

36

31

26

42

−52

−56

Max

Unit

dBm

dBc

Input Second Order Intercept⁷

Input 1 dB Compression Point

LO to IF Output Leakage

LO to RF Input Leakage

RF to IF Output Isolation

RFI1 to RFI2 Channel Isolation

IF/2 Spurious⁸

Unfiltered IF output

0 dBm input power

IF/3 Spurious⁸

DYNAMIC PERFORMANCE at f_RF= 3500 MHz¹²

Power Conversion Gain¹³

Voltage Conversion Gain⁴

SSB Noise Figure

−0.5

5.5

12.5

18

25

39

13

33

28

31

dB

dBm

dBc

SSB Noise Figure Under Blocking¹⁴

Input Third Order Intercept⁵

Input Second Order Intercept⁷

Input 1 dB Compression Point

LO to IF Output Leakage

LO to RF Input Leakage

RF to IF Output Isolation

RFI1 to RFI2 Channel Isolation

IF/2 Spurious⁸

f_CENT= 3500 MHz

Unfiltered IF output

39

−46

−63

0 dBm input power

IF/3 Spurious⁸

DYNAMIC PERFORMANCE at f_RF= 5500 MHz¹⁵

Power Conversion Gain¹⁶

Voltage Conversion Gain⁴

SSB Noise Figure

−3

5.67

14

dB

SSB Noise Figure Under Blocking¹⁷

Input Third Order Intercept⁵

Input Second Order Intercept⁷

Input 1 dB Compression Point

LO to IF Output Leakage

LO to RF Input Leakage

RF to IF Output Isolation

RFI1 to RFI2 Channel Isolation

IF/2 Spurious⁸

f_CENT= 5800 MHz

f_CENT= 5500 MHz

17

23

35

13

42

27

50

33

dB

dBm

dBc

Unfiltered IF output

0 dBm input power

−49

−64

IF/3 Spurious⁸

¹Z₀is the characteristic impedance assumed for all measurements and the PCB.

²Supply voltage must be applied from an external circuit through choke inductors.

³Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss.

⁴Z_SOURCE= 50 Ω, differential; Z_LOAD= 200 Ω, differential 5 dBm; Z_{SOURC E}is the impedance of the source instrument; Z_LOADis the load impedance at the output.

⁵f_RF1= f_CENT, f_BLOCKER= (f_CENT− 5) MHz, f_LO= (f_CENT− 153) MHz, blocker level = 0 dBm.

⁶f_RF1= (f_CENT− 1) MHz, f_RF2= f_{C EN T}, f_LO= (f_CENT− 153) MHz, each RF tone at −10 dBm.

⁷f_RF1= f_CENT, f_RF2= (f_CENT+ 100) MHz, f_LO= (f_{C EN T}− 153) MHz, each RF tone at −10 dBm.

⁸For details, see the Spur Performance section.

⁹V_S= 5 V, VSET = 4.5 V, T_A= 25°C, f_LO= (f_RF− 211) MHz, LO power = 0 dBm, Z₀= 50 Ω.

¹⁰Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (2500BL14M050), and PCB loss.

11

f

= f_CENT, f_BLOCKER= (f_CENT− 5) MHz, f_LO= (f_CENT− 235) MHz, blocker level = 0 dBm.

RF1

¹²V_S= 5 V, VSET = 5 V, T_A= 25°C, f_LO= (f_RF− 153) MHz, LO power = 0 dBm, Z₀= 50 Ω.

¹³Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (3600BL14M050), and PCB loss.

14

f

RF1

= f_CENT, f_BLOCKER= (f_CENT− 5) MHz, f_LO= (f_CENT− 153) MHz, blocker level = −20 dBm.

¹⁵V_S= 5 V, VSET = 4.8 V, T_A= 25°C, f_LO= (f_RF− 380) MHz, LO power = 0 dBm, Z₀= 50 Ω.

¹⁶Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (5400BL15B050), and PCB loss.

17

f

RF1

= f_CENT, f_BLOCKER= (f_CENT− 5) MHz, f_LO= (f_CENT− 300) MHz, blocker level = −20 dBm.

Rev. 0 | Page 4 of 32

ADL5802

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

Supply Voltage, VPOS

5.5 V

VSET, ENBL

5.5 V

OP1+, OP1−, OP2+, OP2−

RF Input Power

5.5 V

20 dBm

1.6 W

26.5°C/W

8.7°C/W

150°C

Internal Power Dissipation

θ_JA(Exposed Paddle Soldered Down)¹

θ_JC(at Exposed Paddle)

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

ESD CAUTION

−40°C to +85°C

−65°C to +150°C

¹As measured on the evaluation board. For details, see the Evaluation Board

section.

Rev. 0 | Page 5 of 32

ADL5802

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

GND

OP1+

OP1–

GND

1

2

3

4

5

6

18 GND

17 GND

16 OP2+

15 OP2–

14 GND

13 VPOS

ADL5802

TOP VIEW

(Not to Scale)

VPOS

NOTES

1. THERE IS AN EXPOSED PADDLE THAT

MUST BE SOLDERED TO GROUND.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Function

GND

Device Common (DC Ground).

1, 2, 5, 8, 11,

14, 17, 18, 21

3, 4

OP1+, OP1−

Channel 1 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or

the center tap of the IF transformer.

6, 13, 24

7

9, 10

12

VPOS

ENBL

LOIP, LOIN

VSET

Positive Supply Voltage. 5.0 V nominal.

Device Enable. Pull low or leave disconnected to enable the device; pull high to disable the device.

Differential LO Input Terminals. Internally matched to 50 Ω; must be ac-coupled.

High Input IP3 Bias Control. For high input IP3 performance, apply ~4 V to 5 V. Improved noise figure (NF)

performance and lower supply current can be set by applying ~2 V to 3 V to the VSET pin. A resistor can be

connected to the supply to raise the voltage, whereas a resistor to GND lowers the voltage.

15, 16

OP2−, OP2+

Channel 2 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or

the center tap of the IF transformer.

19, 20

22, 23

RF2−, RF2+

RF1−, RF1+

EPAD

Differential RF Input Terminals for Channel 2. Internally matched to 50 Ω; must be ac-coupled.

Differential RF Input Terminals for Channel 1. Internally matched to 50 Ω; must be ac-coupled.

Exposed Paddle. Must be soldered to ground.

Rev. 0 | Page 6 of 32

ADL5802

TYPICAL PERFORMANCE CHARACTERISTICS

DOWNCONVERTER MODE USING A BROADBAND BALUN

V_S= 5 V, T _A= 25°C, VSET = 4 V, I F = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless

otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.

6

4.0

3.5

3.0

2.5

2.0

1.5

1.0

39.96

33.30

26.64

19.98

13.32

6.66

5

4

T

= –40°C

A

3

T

= +25°C

A

2

1

GAIN = 900MHz

GAIN = 1900MHz

0

INPUT IP3 = 900MHz

INPUT IP3 = 1900MHz

T

= +85°C

A

–1

–2

–3

–4

0

500

1000

1500

2000

2500

3000

3500

–15

–10

–5

0

5

10

15

LO POWER (dBm)

RF FREQUENCY (MHz)

Figure 3. Power Conversion Gain vs. RF Frequency

Figure 6. Power Conversion Gain and Input IP3 vs. LO Power

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

100

MEAN = 1.5

SD = 0.039

80

60

40

20

0

900MHz

1900MHz

0

50

100

150

200

250

IF FREQUENCY (MHz)

GAIN (dB)

Figure 4. Power Conversion Gain vs. IF Frequency

Figure 7. Power Conversion Gain Distribution

3.0

2.5

2.0

1.5

1.0

0.5

0

0.30

0.25

0.20

0.15

0.10

0.05

0

2.5

T

= –40°C

= +25°C

A

2.0

1.5

1.0

0.5

0

A

T

= +85°C

A

GAIN = 900MHz

GAIN = 1900MHz

I

= 900MHz

POS

= 1900MHz

0

1

2

3

4

5

6

4.7

4.8

4.9

5.0

SUPPLY (V)

5.1

5.2

5.3

VSET (V)

Figure 5. Power Conversion Gain and I_POSvs. VSET

Figure 8. Power Conversion Gain vs. Supply Voltage

Rev. 0 | Page 7 of 32

ADL5802

80

70

60

50

40

30

20

10

0

40

35

30

25

20

15

10

5

T

= –40°C

T

= +25°C

A

T

= +85°C

A

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

0

500

1000

1500

2000

2500

3000

3500

500

1000

1500

2000

2500

3000

3500

RF FREQUENCY (MHz)

Figure 9. Input IP3 vs. RF Frequency

Figure 12. Input IP2 vs. RF Frequency

40

35

30

25

20

15

80

70

60

50

40

30

20

10

0

900MHz

1900MHz

900MHz

1900MHz

10

0

50

100

150

200

250

50

100

150

200

250

IF FREQUENCY (MHz)

Figure 13. Input IP2 vs. IF Frequency

Figure 10. Input IP3 vs. IF Frequency

80

70

60

50

40

30

20

10

0

35

30

25

20

15

10

5

900MHz

1900MHz

INPUT IP3 = 900MHz

INPUT IP3 = 1900MHz

NF = 900MHz

NF = 1900MHz

0

1

2

3

4

5

6

1

2

3

4

5

6

VSET (V)

Figure 11. Input IP3, Noise Figure vs. VSET

Figure 14. Input IP2 vs. VSET

Rev. 0 | Page 8 of 32

ADL5802

25

20

15

10

5

20

18

16

14

12

10

8

T

= +85°C

A

T

= –40°C

A

NF vs. IF, RF = 1900MHz

NF vs. IF, RF = 900MHz

T

= +25°C

A

6

4

2

0

100

200

300

400

500

600

700

0

500

1000

1500

2000

2500

3000

3500

IF FREQUENCY (MHz)

RF FREQUENCY (MHz)

Figure 15. Input P1dB vs. RF Frequency

Figure 18. SSB Noise Figure vs. IF Frequency

20

18

16

14

12

10

8

30

25

20

15

10

5

900MHz

NF, RF 1846MHz,

IF 153MHz, BLOCKER 1841MHz

1900MHz

6

NF, RF 951MHZ,

IF 153MHz, BLOCKER 946MHz

4

2

0

–30

–25

–20

–15

–10

–5

0

5

10

0

50

100

150

200

250

BLOCKER LEVEL (dBm)

IF FREQUENCY (MHz)

Figure 16. Input P1dB vs. IF Frequency

Figure 19. SSB Noise Figure vs. Blocker Level

20

18

16

14

12

10

8

18

16

14

12

10

8

T

= +85°C

A

T

= +25°C

A

1900MHz

900MHz

T

= –40°C

A

6

4

2

0

–15

0

–10

–5

0

5

10

15

0

500

1000

1500

2000

2500

3000

3500

LO LEVEL (dBm)

RF FREQUENCY (MHz)

Figure 17. SSB Noise Figure vs. RF Frequency

Figure 20. SSB Noise Figure vs. LO Drive

Rev. 0 | Page 9 of 32

ADL5802

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–0

RF RETURN LOSS 5500MHz BALUN:

5400BL15B050 3pF INPUT CAPACITANCE

–5

–10

–15

–20

–25

–30

–35

T

= –40°C

A

T

= +25°C

A

RF RETURN LOSS 3500MHz BALUN:

3600BL14M050 1.5pF INPUT CAPACITANCE

T

= +85°C

A

RF RETURN LOSS 2500MHz BALUN:

2500BL14M050 3pF INPUT CAPACITANCE

RF RETURN LOSS 900MHz AND 1900MHz BALUN:

TC1-1-13M+ 100pF INPUT CAPACITANCE

–40

0

1000

2000

3000

4000

5000

6000

7000

0

500

1000

1500

2000

2500

3000

3500

FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 21. RF Return Loss Measured Differentially at the RF Port

Figure 24. LO to IF Leakage vs. LO Frequency

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

0

LO RETURN LOSS 2500MHz BALUN:

2500BL14M050 3pF

LO RETURN LOSS 5500MHz BALUN:

INPUT CAPACITANCE

5400BL15B050 3pF

–5

–10

–15

–20

–25

–30

INPUT CAPACITANCE

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

LO RETURN LOSS BALUN:

TC1-1-13M+ 100pF

INPUT CAPACITANCE

LO RETURN LOSS 3500MHz BALUN:

3600BL14M050 1.5pF

INPUT CAPACITANCE

0

500

1000

1500

2000

2500

3000

3500

0

1000

2000

3000

4000

5000

6000

7000

LO FREQUENCY (MHz)

FREQUENCY (MHz)

Figure 22. LO Return Loss Measured Differentially at the LO Port

Figure 25. LO to RF Leakage vs. LO Frequency

0

–10

–20

–30

–40

–50

–60

500

8

6

4

2

400

300

200

100

0

T

= +25°C

A

RESISTANCE

T

= +85°C

A

CAPACITANCE

T

= –40°C

A

0

–2

3000

0

500

1000

1500

2000

2500

3000

3500

10

100

1000

RF FREQUENCY (MHz)

IF FREQUENCY (MHz)

Figure 23. IF Differential Output Impedance (R Parallel C Equivalent)

Figure 26. RF to IF Output Isolation vs. RF Frequency

Rev. 0 | Page 10 of 32

ADL5802

70

65

60

55

50

45

40

35

30

25

20

T

= –40°C

= +85°C

A

T

= +25°C

A

T

A

0

500

1000

1500

2000

2500

3000

3500

RF FREQUENCY (MHz)

Figure 27. RF Channel Isolation

Rev. 0 | Page 11 of 32

ADL5802

DOWNCONVERTER MODE USING A JOHANSON 2.7 GHZ BALUN

V_S= 5 V, T _A= 25°C, VSET = 4.5 V, I F = 2 1 1 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.

Insertion loss of input and output baluns (2500BL14M050, TC4-1W+) is included in the gain measurement.

5

35

30

25

20

15

10

5

4

3

2

T

= –40°C

A

INPUT IP3

1

T

= +25°C

A

0

–1

–2

–3

–4

–5

NOISE FIGURE

T

= +85°C

A

0

1

2

3

4

5

6

1900

2100

2300

2500

2700

2900

3100

VSET (V)

RF FREQUENCY (MHz)

Figure 31. Input IP3, Noise Figure vs. VSET

Figure 28. Power Conversion Gain vs. RF Frequency

0.30

0.27

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

0

60

55

50

45

40

35

30

5

4

3

I

POS

T

= +85°C

A

2

T

= –40°C

A

1

0

GAIN

T

= +25°C

A

–1

–2

–3

–4

–5

1900

2100

2300

2500

2700

2900

3100

0

1

2

3

4

5

6

RF FREQUENCY (MHz)

VSET (V)

Figure 32. Input IP2 vs. RF Frequency

Figure 29. Power Conversion Gain and I_POSvs. VSET

35

30

25

20

15

10

5

50

T

= +85°C

T

= +25°C

A

48

46

44

42

40

38

36

34

32

30

T

= –40°C

A

0

1900

2100

2300

2500

2700

2900

3100

0

1

2

3

4

5

6

VSET (V)

RF FREQUENCY (MHz)

Figure 33. Input IP2 vs. VSET

Figure 30. Input IP3 vs. RF Frequency

Rev. 0 | Page 12 of 32

ADL5802

15

14

13

12

11

10

9

0

–5

T

= +85°C

A

T

= +25°C

A

–10

–15

–20

–25

–30

–35

–40

–45

–50

T

= –40°C

A

T

= –40°C

A

T

= +25°C

A

T

= +85°C

A

8

1900

2100

2300

2500

2700

2900

3100

2100

2300

2500

2700

2900

3100

LO FREQUENCY (MHz)

RF FREQUENCY (MHz)

Figure 34. Input P1dB vs. RF Frequency

Figure 37. LO to IF Leakage vs. LO Frequency

20

18

16

14

12

10

8

–30

–31

–32

–33

–34

–35

–36

–37

–38

–39

–40

T

= +85°C

A

T

= +25°C

A

T

= +25°C

A

T

= +85°C

A

T

= –40°C

A

T

= –40°C

A

6

4

2

0

1800

1900

2100

2300

2500

2700

2900

3100

2000

2200

2400

2600

2800

3000

LO FREQUENCY (MHz)

RF FREQUENCY (MHz)

Figure 38. LO to RF Leakage vs. LO Frequency

Figure 35. SSB Noise Figure vs. RF Frequency

30

25

20

15

10

5

–21

–23

–25

–27

–29

–31

–33

–35

T

= +25°C

A

T

= –40°C

A

NF, RF 2145MHz,

IF 230MHz, BLOCKER 2140MHz

T

= +85°C

A

0

–60

1900

2100

2300

2500

2700

2900

3100

–50

–40

–30

–20

–10

0

10

RF FREQUENCY (MHz)

BLOCKER LEVEL (dBm)

Figure 36. SSB Noise Figure vs. Blocker Level

Figure 39. RF to IF Output Isolation vs. RF Frequency

Rev. 0 | Page 13 of 32

ADL5802

50

48

46

44

42

40

38

36

34

32

T

= –40°C

A

T

= +25°C

A

T

= +85°C

A

30

1900

2100

2300

2500

2700

2900

3100

RF FREQUENCY (MHz)

Figure 40. RF Channel Isolation

Rev. 0 | Page 14 of 32

ADL5802

DOWNCONVERTER MODE USING A JOHANSON 3.5 GHZ BALUN

V_S= 5 V, T _A= 25°C, VSET = 5 V, I F = 1 5 3 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.

Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.

5

25

20

15

10

5

4

3

INPUT IP3

2

T

= –40°C

A

1

T

= +25°C

A

0

NOISE FIGURE

–1

–2

–3

–4

–5

T

= +85°C

A

0

1

2

3

4

5

6

2900

3100

3300

3500

3700

3900

4100

VSET (V)

RF FREQUENCY (MHz)

Figure 44. Input IP3, Noise Figure vs. VSET

Figure 41. Power Conversion Gain vs. RF Frequency

0.30

0.27

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

0

50

48

46

44

42

40

38

36

34

32

30

5

4

3

I

POS

2

T

= –40°C

A

1

0

GAIN

T

= +85°C

A

T = +25°C

A

–1

–2

–3

–4

–5

2900

3100

3300

3500

3700

3900

4100

0

1

2

3

4

5

6

RF FREQUENCY (MHz)

VSET (V)

Figure 45. Input IP2 vs. RF Frequency

Figure 42. Power Conversion Gain and I_POSvs. VSET

30

25

20

15

10

5

50

T

= +85°C

A

48

46

44

42

40

38

36

34

32

30

T

= +25°C

A

T

= –40°C

A

0

2900

3100

3300

3500

3700

3900

4100

0

1

2

3

4

5

6

VSET (V)

RF FREQUENCY (MHz)

Figure 43. Input IP3 vs. RF Frequency

Figure 46. Input IP2 vs. VSET

Rev. 0 | Page 15 of 32

ADL5802

15

14

13

12

11

10

9

–20

–25

–30

–35

–40

–45

–50

T

= +85°C

T

= +25°C

A

T

= +25°C

A

T

= –40°C

A

T

= +85°C

A

T

= –40°C

A

8

2900

3100

3300

3500

3700

3900

4100

3100

3300

3500

3700

3900

4100

LO FREQUENCY (MHz)

RF FREQUENCY (MHz)

Figure 47. Input P1dB vs. RF Frequency

Figure 50. LO to IF Leakage vs. LO Frequency

–20

–22

–24

–26

–28

–30

–32

–34

–36

–38

–40

20

18

16

14

12

10

8

T

= +85°C

A

T

= –40°C

A

T

= +25°C

T

= +25°C

A

T

= +85°C

A

T

= –40°C

A

6

4

2

0

2700

2900

3100

3300

3500

3700

3900

4100

4300

2900

3100

3300

3500

3700

3900

RF FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 48. SSB Noise Figure vs. RF Frequency

Figure 51. LO to RF Leakage vs. LO Frequency

45

40

35

30

25

20

–10

–15

–20

–25

–30

–35

–40

–45

–50

NF, RF 3805MHz,

IF 300MHz, BLOCKER 3800MHz

T

= –40°C

= +25°C

= +85°C

A

15

10

5

0

–60

–50

–40

–30

–20

–10

0

10

2900

3100

3300

3500

3700

3900

BLOCKER LEVEL (dBm)

RF FREQUENCY (MHz)

Figure 49. SSB Noise Figure vs. Blocker Level

Figure 52. RF to IF Output Isolation vs. RF Frequency

Rev. 0 | Page 16 of 32

ADL5802

50

48

46

44

42

40

38

36

34

32

30

T

= +25°C

A

T

= +85°C

T

= –40°C

A

2900

3100

3300

3500

3700

3900

4100

RF FREQUENCY (MHz)

Figure 53. RF Channel Isolation

Rev. 0 | Page 17 of 32

ADL5802

DOWNCONVERTER MODE USING A JOHANSON 5.7 GHZ BALUN

V_S= 5 V, T _A= 25°C, VSET = 4.8 V, I F = 3 8 0 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.

Insertion loss of input and output baluns (5400BL15B050, TC4-1W+) is included in the gain measurement.

25

20

15

10

5

30

24

18

12

6

2

0

IP3

T

= +85°C

A

T

= –40°C

A

–2

–4

–6

–8

NOISE FIGURE

T

= +25°C

A

0

4900

5100

5300

5500

5700

5900

6100

0

1

2

3

4

5

6

RF FREQUENCY (MHz)

VSET (V)

Figure 57. Input IP3, Noise Figure vs. VSET

Figure 54. Power Conversion Gain vs. RF Frequency

60

5

4

0.30

0.27

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

0

55

50

45

40

35

30

25

20

15

10

3

2

T

= +85°C

A

IPOS

GAIN

1

T

= +25°C

= –40°C

A

0

T

A

–1

–2

–3

–4

–5

4900

5100

5300

5500

5700

5900

0

1

2

3

4

5

6

RF FREQUENCY (MHz)

VSET (V)

Figure 58. Input IP2 vs. RF Frequency

Figure 55. Power Conversion Gain and I_POSvs. VSET

50

45

40

35

30

25

20

30

25

20

15

10

5

T

= –40°C

A

T

= +25°C

A

T

= +85°C

A

0

4900

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

5700

5300

RF FREQUENCY (MHz)

5100

5500

5900

6100

VSET (V)

Figure 59. Input IP2 vs. VSET

Figure 56. Input IP3 vs. RF Frequency

Rev. 0 | Page 18 of 32

ADL5802

16

15

14

13

12

11

10

9

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

= –40°C

A

T

= +25°C

A

T

A

= +85°C

8

4900

5100

5300

5500

5700

5900

6100

4900

5100

5300

5500

5700

5900

6100

RF FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 60. Input P1dB vs. RF Frequency

Figure 63. LO to IF Leakage vs. LO Frequency

–15

–17

–19

–21

–23

–25

–27

–29

–31

–33

–35

25

20

15

10

5

T

= –40°C

A

T

= +25°C

A

T

= –40°C

= +25°C

= +85°C

A

T

= +85°C

A

0

4900

5100

5300

5500

5700

5900

6100

4900

5100

5300

5500

5700

5900

6100

RF FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 61. SSB Noise Figure vs. RF Frequency

Figure 64. LO to RF Leakage vs. LO Frequency

45

40

35

30

25

20

15

10

5

–30

–35

–40

–45

–50

–55

–60

–65

–70

T

= +25°C

T

= –40°C

A

NF, RF 5805MHz,

IF 380MHz, BLOCKER 5800MHz

T

= +85°C

A

0

–60

4900

5100

5300

5500

5700

5900

6100

–50

–40

–30

–20

–10

0

BLOCKER LEVEL (dBm)

RF FREQUENCY (MHz)

Figure 62. SSB Noise Figure vs. Blocker Level

Figure 65. RF to IF Output Isolation vs. RF Frequency

Rev. 0 | Page 19 of 32

ADL5802

45

43

41

39

37

35

33

31

29

27

T

= –40°C

= +25°C

= +85°C

A

25

4900

5100

5300

5500

5700

5900

6100

RF FREQUENCY (MHz)

Figure 66. RF Channel Isolation

Rev. 0 | Page 20 of 32

ADL5802

SPUR PERFORMANCE

All spur tables are (N × f_RF) − (M × f_LO) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer

spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for frequencies

less than 6 GHz only. The typical noise floor of the measurement system is −100 dBm.

900 MHz Performance

V_S= 5 V, VS E T = 4 V, T_A= 25°C, RF power = 0 dBm, LO power = 0 dBm, f_RF= 900 MHz, f_LO= 703 MHz, Z₀= 50 Ω.

M

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

0

−35.9

0.0

−25.5

−46.3

−68.2

≤100

−96.4

≤100

−47.3

−19.8

−61.6

−67.3

≤100

−27.4

−64.3

−68.7

−98.0

≤100

−51.5

−30.0

−80.7

−71.0

≤100

−37.5

−75.6

−67.5

≤100

−62.1

−45.0

−88.1

−86.3

≤100

−47.5

−67.8

−79.1

≤100

−34.3

−49.1

−86.7

−91.8

≤100

−55.3

−82.6

≤100

1

2

−69.2

−79.6

≤100

−91.5

≤100

−98.4

≤100

3

4

≤100

5

6

N

7

8

9

10

11

12

13

14

15

2090 MHz Performance

V_S= 5 V, VS E T = 4 V, T_A= 25°C, RF power = 0 dBm, LO power = 0 dBm, f_RF= 2090 MHz, f_LO= 1842 MHz, Z₀= 50 Ω.

M

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

−43.0

0.0

−23.7

−59.6

−53.8

−97.6

≤100

−52.9

−42.2

−67.5

−59.3

≤100

0

1

−26.8

−59.8

−80.5

−68.2

−92.2

−93.7

≤100

−71.9

−67.6

−84.1

−79.3

−97.8

−96.1

≤100

2

3

≤100

4

≤100

5

6

≤100

N

7

8

≤100

9

10

11

12

13

14

15

≤100

Rev. 0 | Page 21 of 32

ADL5802

2600 MHz Performance

V_S= 5 V, VSET = 4.5 V, T_A= 25°C, RF power = 0 dBm, LO power = 0 dBm, f_RF= 2600 MHz, f_LO= 2350 MHz, Z₀= 50 Ω.

M

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

0

−37.9

0.0

−31.5

−62.6

−52.2

−88.7

≤100

−27.5

−75.5

−36.3

−65.8

−56.3

≤100

1

2

−59.7

−75.0

−68.8

−86.8

−82.5

≤100

−90.5

−92.1

−94.4

≤100

3

4

≤100

5

≤100

6

N

7

≤100

8

9

≤100

10

11

12

13

14

15

≤100

3500 MHz Performance

V_S= 5 V, VS E T = 5 V, T_A= 25°C, RF power = 0 dBm, LO power = 0 dBm, f_RF= 3500 MHz, f_LO= 3800 MHz, Z₀= 50 Ω.

M

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

−43.0

0.0

−23.7

−59.6

−53.8

−97.6

≤100

−52.9

−42.2

−67.5

−59.3

≤100

0

1

−26.8

−59.8

−80.5

−68.2

−92.2

−93.7

≤100

−71.9

−67.6

−84.1

−79.3

−97.8

−96.1

≤100

2

3

≤100

4

≤100

5

6

≤100

N

7

8

≤100

9

10

11

12

13

14

15

≤100

Rev. 0 | Page 22 of 32

ADL5802

5800 MHz Performance

V_S= 5 V, VSET= 4.8 V, T_A= 25°C, RF power = −10 dBm, LO power = 0 dBm, f_RF= 5800 MHz, f_LO= 5600 MHz, Z₀= 50 Ω.

M

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

−28.3

0.0

0

−63.6

−80.5

−48.6

1

−92.6

−64.2

2

3

−98.7

−90.5

−98.3

≤100

4

5

−99.4

−81.6

−98.0

−87.2

6

N

7

−95.9

−84.0

−99.5

≤100

8

≤100

9

10

11

12

13

14

15

≤100

−99.6

≤100

−99.8

≤100

Rev. 0 | Page 23 of 32

ADL5802

CIRCUIT DESCRIPTION

The ADL5802 provides two double-balanced active mixers.

These mixers are designed for a 50 Ω input impedance and a

200 Ω output impedance. Both are driven from a common local

oscillator (LO) amplifier. The RF inputs and LO outputs are

differential, providing maximum usable bandwidth at the input

and output ports. The LO also operates with a 50 Ω input

impedance and can, optionally, be operated differentially or

single-ended. The input, output, and LO ports can be operated

over an exceptionally wide frequency range. The ADL5802 can

be configured as a downconvert mixer or as an upconvert mixer.

RF VOLTAGE TO CURRENT (V-TO-I) CONVERTER

The differential RF input signal is applied to a voltage-to-current

converter that converts the differential input voltage to output

currents. The V-to-I converter provides a 50 Ω input

impedance. The V-to-I section bias current can be adjusted up

or down using the VSET pin. Adjusting the current up improves

IP3 and P1dB input but degrades SSB NF. Adjusting the current

down improves SSB NF but degrades IP3 and P1dB input. The

conversion gain remains nearly constant over a wide range of

VSET pin settings, allowing the part to be adjusted dynamically

without affecting the conversion gain. The current adjustment

can be made by connecting a resistor from the VSET pin to the

positive supply to increase the bias current or from the VSET

pin to ground to decrease the bias current. The VSET pin

impedance is approxi-mately 675 Ω in series with two diodes

and an internal current source.

The ADL5802 can be divided into the following sections: the

local oscillator (LO) amplifier and splitter, the RF voltage-to-

current (V-to-I) converter, the mixer cores, the output loads,

and the bias circuit. A simplified block diagram of the device is

shown in Figure 67. The LO block generates a pair of differential

LO signals to drive two mixer cores. The RF input is converted

into current by the V-to-I converters that then feed into the two

mixer cores. The internal differential load of the mixers is

designed for a wideband 200Ω output impedance from the

mixer. Reference currents to each section are generated by the

bias circuit, which can be enabled or disabled using the ENBL

pin. A detailed description of each section of the ADL5802

follows.

MIXER CORES

The ADL5802 has two double-balanced mixers that use high

performance SiGe NPN transistors. These mixers are based on

the Gilbert cell design of four cross-connected transistors.

MIXER LOAD

Each mixer load is designed to use a pair of 100 Ω resistors con-

nected to the positive supply. This provides a 200 Ω differential

output resistance. The mixer output should be pulled to the

positive supply externally using a pair of RF chokes or using an

output transformer with the center tap connected to the positive

supply. It is possible to exclude these components when the mixer

core current is low, but both P1dB and IP3 are then reduced.

VPOS RF1+ RF1– GND RF2+RF2–

24

23

22

21

20

19

1

2

3

4

18

17

16

15

GND

OP2+

OP2–

OP1+

OP1–

The mixer load output can operate from direct current (dc) up to

approximately 500 MHz into a 200 Ω load. For upconversion

applications, the mixer load can be matched using off-chip

matching components. Transmit operation up to 2 GHz is

possible. See the Applications Information section for matching

circuit details.

GND

5

6

14 GND

IP3

ADL5802

BIAS

VPOS

13 VPOS

7

8

9

10

11

12

LOIN GND VSET

ENBL GND LOIP

BIAS CIRCUIT

Figure 67. ADL5802 Block Diagram

A band gap reference circuit generates the reference currents

used by the mixers. The bias circuit can be enabled and disabled

using the ENBL pin. If the ENBL pin is grounded or left open,

the part is enabled. Pulling the ENBL pin high shuts off the bias

circuit and disables the part. However, the ENBL pin does not

alter the current in the LO section and, therefore, does not

provide a true power-down feature. Certain configurations may

require the VSET pin to be connected to the positive supply

through a resistor. This will result in an increased mixer core

current. Unless this resistor to positive supply is removed, bias

current will continue to be supplied to the mixer core.

LO AMPLIFIER AND SPLITTER

The LO input is amplified using a broadband LNA and is then

split and followed by separate LO limiting amplifiers. The LNA

input impedance is nominally 50 Ω. The LO is designed to

accommodate a wide range of LO input power levels. The LO

input is conditioned by the series of amplifiers to provide a well

controlled and limited LO swing to the mixer core, resulting in

excellent IP3. The LO circuit exhibits low additive noise,

resulting in an excellent mixer noise figure and output noise

under RF blocking. For optimal performance, the LO inputs

should be driven differentially but at lower frequencies; single-

ended drive is acceptable.

Rev. 0 | Page 24 of 32

ADL5802

APPLICATIONS INFORMATION

BASIC CONNECTIONS

RF AND LO PORTS

The RF and LO input ports are designed for differential input

impedance of approximately 50 Ω. Figure 69 and Figure 70

illustrate the RF and LO interfaces, respectively. It is recommended

that each of the RF and LO differential ports be driven through a

balun for optimum performance. It is also necessary to ac-

couple both RF and LO ports with the proper size capacitors.

Table 4 lists the recommended components for various RF

frequency bands. The characterization data is available in the

Typical Performance Characteristics section.

The ADL5802 features dual channel mixers with a common

local oscillator (LO). The mixer is designed to translate between

radio frequencies (RF) and intermediate frequencies (IF). For

both upconversion and downconversion applications, RF1+

(Pin 23), RF1− (Pin 22), RF2+ (Pin 20), and RF2− (Pin 19)

must be configured as the input interfaces. OP1+ (Pin 3), OP1−

(Pin 4), OP2+ (Pin 16), and OP2− (Pin 15) must be configured

as the output interfaces. Figure 68 illustrates the basic connections

for ADL5802 operation.

RF1

RF2

T3

T5

C13

C14

C5

C12

VPOS

24

23

22

21

20

19

C8

C11

VPOS RF1+ RF1– GND RF2+ RF2–

1

2

3

4

5

6

GND

18

17

16

15

GND

VPOS

IF1P

OP1+

OP1–

GND

OP2+

OP2–

C16

C15

ADL5802

T2

T4

IF2P

GND 14

VPOS

VPOS 13

VPOS

C10

C7

C6

C9

GND

8

ENBL

7

LOIP LOIN GND VSET

9

10

11

12

VSET

C3

T1

C2

LO

Figure 68. Basic Connections Schematic

Rev. 0 | Page 25 of 32

ADL5802

RF1

RF2

frequency. A variety of suitable choke inductors is commercially

available from manufacturers such as Coilcraft and Murata. An

impedance transforming network may be required to transform

the final load impedance to 200Ω at the IF outputs.

T5

T3

C13 C14

C5 C12

23

22

21

20

19

RF1+ RF1– GND RF2+ RF2–

1

2

3

4

5

GND

OP1+

OP1–

GND

ADL5802

VPOS

Figure 69. ADL5802 RF Interface

IF1P

C16

ADL5802

T4

ADL5802

ENBL GND LOIP LOIN GND

7

8

9

10

11

C3

T1

C2

18

17

16

15

GND

LO

VPOS

T2

Figure 70. ADL5802 LO Interface

OP2+

OP2–

C15

ADL5802

Table 4. Suggested Components for the RF and LO Interfaces

IF2P

RF and LO

Frequency

C2, C3, C5,

C12, C13, C14

T1, T3, T5

GND 14

900 MHz

1900 MHz

2500 MHz

Mini-Circuits® TC1-1-13M+ 100 pF

Mini-Circuits TC1-1-13M+

100 pF

3 pF

Figure 71. Biasing the IF Port Open-Collector Outputs

Using a Center-Tapped Impedance Transformer

Johanson Technology

2500BL14M050

3500 MHz

5500 MHz

1.5 pF

3 pF

Johanson Technology

3600BL14M050

Johanson Technology

5400BL15B050

VPOS

1

2

3

4

5

GND

OP1+

OP1–

GND

C17

L3

IF1 OUT+

Z

IF PORT

IMPEDANCE

TRANSFORMING

NETWORK

Z

= 200Ω

LOAD

ADL5802

L

The IF port features an open-collector differential output

interface. It is necessary to bias the open collector outputs using

one of the schemes presented in Figure 71 and Figure 72.

IF1 OUT–

L4

Figure 71 shows the use of center-tapped impedance transformers.

The turns ratio of the transformer should be selected to provide

the desired impedance transformation. In the case of a 50 Ω

load impedance, a 4:1 impedance ratio transformer should be

used to transform the 50Ω load into a 200 Ω differential load at

the IF output pins.

C18

VPOS

C4

18

17

16

15

GND

L2

Figure 72 shows a differential IF interface where pull-up choke

inductors are used to bias the open-collector outputs. The

shunting impedance of the choke inductors used to couple dc

current into the mixer core should be large enough at the IF

frequency of operation so as not to load down the output

current before it reaches the intended load. Additionally, the dc

current handling capability of the selected choke inductors

must be at least 45 mA. The self-resonant frequency of the

selected choke inductors must be higher than the intended IF

IF2 OUT+

IF2 OUT–

OP2+

OP2–

IMPEDANCE

TRANSFORMING

NETWORK

ADL5802

Z

= 200Ω

L

LOAD

L1

GND 14

C1

VPOS

Figure 72. Biasing the IF Port Open-Collector Outputs

Using Pull-Up Choke Inductors

Rev. 0 | Page 26 of 32

ADL5802

EVALUATION BOARD

An evaluation board is available for the ADL5802. The standard evaluation board is fabricated using Rogers® RO3003 material. Each of

the RF, LO, and IF ports is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown

in Figure 73. Table 5 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 74 and

Figure 75.

RF1

RF2

T5

T3

VPOS

GND

C11

C8

R19

C13 C14

C5 C12

VPOS

VPOS1

24

VPOS RF1+ RF1– GND RF2+ RF2–

GND

23

22

21

20

19

VPOS

C4

GND

1

2

3

4

5

6

18

C17

GND

OP2+

OP2–

17

16

15

14

13

L2

L3

R2

IF1P

IF1N

R14

R16

IF2N

IF2P

OP1+

OP1–

GND

C16

R21

C15

T4

ADL5802

R7

L4

T2

R6

R15

R13

C1

R3

L1

R20

C10

GND

R10

C6

R12

C7

C18

VPOS

C9

VPOS

ENBL GND LOIP LOIN GND VSET

10 11 12

7

8

9

R9

R4

C2

R5

C3

T1

VPOS

VSET

R11

R22

R23

VPOS

LOP

ENBL1

R1

LO

LON

Figure 73. Evaluation Board Schematic

Table 5. Evaluation Board Configuration

Components Function

C1, C4, C6, C7, C8, C9, Power supply decoupling. Nominal supply decoupling

Default Conditions

C6, C7, C8 = 10 pF (size 0402)

C10, C11, C17, C18,

R10, R12, R19, R20,

R21

consists of a 0.01 µF capacitor to ground in parallel with 10

pF capacitors to ground, positioned as close to the device

as possible. Series resistors are provided for enhanced

supply decoupling using optional ferrite chip inductors.

C9, C10, C11 = 0.01 µF (size 0402)

C1, C4, C17, C18 = open (size 0402)

R10, R12, R19, R20, R21 = 0 Ω (size 0402)

C5, C12, C13, C14 = 100 pF (size 0402)

T3, T5 = TC1-1-13M+ (Mini-Circuits)

C5, C12, C13, C14, T3, RF Channel 1 and RF Channel 2 input interfaces. Input

T5, RF1, RF2

channels are ac-coupled through C5, C12, C13, and C14. T3

and T4 are 1:1 baluns used to interface to the 50 Ω

differential inputs.

C15, C16 = 100 pF (size 0402)

C15, C16, L1, L2, L3,

L4, R2, R3, R6, R7,

R13, R14, R15, R16,

R20, R21, T2, T4, IF1,

IF2

IF Channel 1 and IF Channel 2 output interfaces. The 200 Ω

open-collector IF output interfaces are biased through the

center taps of T2 and T4 4:1 impedance transformers. C15

and C16 provide local bypassing with R20 and R21 available

for additional supply bypassing. R6, R7, R13, R14, R15, and

R16 are provided for IF filtering and matching options.

L1, L2, L3, L4 = open (size 0805)

R2, R3, R13, R14, R15, R16, R20, R21 = 0 Ω (size 0402)

R6, R7 = open (size 0402)

T2, T4 = TC4-1W+ (Mini-Circuits)

C2, C3, R4, R5, T1, LO

R1, R9, R11, ENBL1

C2, C3 = 1 nF (size 0402)

R4, R5 = open (size 0402)

T1 = TC1-1-13M+ (Mini-Circuits)

R9 = 10 kΩ (size 0402); R1, R11 = open (size 0402)

Or R1 = 10 kΩ (size 0402);R9, R11 = open (size 0402)

Or R11 = 10 kΩ (size 0402); R1, R9 = open (size 0402)

ENBL1 = 3-pin header and shunt

LO interface. C2 and C3 provide ac coupling for the local

oscillator input. T1 is a 1:1 balun to allow single-ended

interfacing to the differential 50 Ω local oscillator input.

Enable interface. The ADL5802 can be disabled using the 3-

pin ENBL1 header. The ENBL pin is pulled up to VPOS

through R9. R1 is provided as an optional termination for

the high impedance enable interface. If desired, the ENBL

pin can be driven by an external source through the ENBL

SMA connector.

Rev. 0 | Page 27 of 32

ADL5802

Components

Function

Default Conditions

R22, R23, VSET

R22, R23 = open (size 0402)

VSET bias control. R22 and R23 form an optional resistor

divider network between VPOS and GND, allowing for a

fixed bias setting. See the Typical Performance

Characteristics section to choose the recommended VSET

control voltage for the desired frequency band.

EPAD (EP)

Exposed paddle. Must be soldered to ground.

Figure 74. Evaluation Board Top Layer

Figure 75. Evaluation Board Bottom Layer

Rev. 0 | Page 28 of 32

ADL5802

OUTLINE DIMENSIONS

0.60 MAX

4.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

1

24

19

18

0.50

BSC

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

TOP

VIEW

3.75

BSC SQ

EXPOSED

PA D

(BOTTOMVIEW)

0.50

0.40

0.30

6

13

12

7

0.23 MIN

0.80 MAX

0.65 TYP

2.50 REF

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8

Figure 76. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-3)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Model

Package Description

Package Option Ordering Quantity

ADL5802ACPZ-R7¹

ADL5802-EVALZ¹

−40°C to +85°C

24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-3

Evaluation Board

1,500 per Reel

1

¹Z = RoHS Compliant Part.

Rev. 0 | Page 29 of 32

ADL5802

NOTES

Rev. 0 | Page 30 of 32

ADL5802

NOTES

Rev. 0 | Page 31 of 32

ADL5802

NOTES

registered trademarks are the property of their respective owners.

D07882-0-11/09(0)

Rev. 0 | Page 32 of 32


型号：	ADL5802ACPZ-R7
厂家：	ADI
描述：	Dual Channel, High IP3, 100 MHz to 6 GHz Active Mixer 双通道，高IP3 ， 100 MHz至6 GHz有源混频器
文件：	总32页 (文件大小：780K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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