ADP150_VA [ADI]
Ultralow Noise, 150 mA CMOS Linear Regulator; 超低噪声， 150毫安CMOS线性稳压器
| 型号： | ADP150_VA |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise, 150 mA CMOS Linear Regulator |
| 文件： | 总20页 (文件大小：556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise,
150 mA CMOS Linear Regulator
ADP150
TYPICAL APPLICATION CIRCUITS
FEATURES
Ultra low noise: 9 µV rms, independent of VOUT
No additional noise bypass capacitor required
Stable with 1 µF ceramic input and output capacitors
Maximum output current: 150 mA
V
= 2.3V
V
= 1.8V
IN
OUT
1
2
3
VIN
GND
EN
VOUT
NC
5
4
C
IN
C
OUT
1µF
1µF
ON
Input voltage range: 2.2 V to 5.5 V
OFF
Low quiescent current
NC = NO CONNECT
I
GND = 10 µA with zero load
Figure 1. 5-Lead TSOT with Fixed Output Voltage, 1.8 V
Low shutdown current: <1 µA
Low dropout voltage: 105 mV @ 150 mA load
Initial output voltage accuracy: 1%
Up to 14 fixed output voltage options: 1.8 V to 3.3 V
PSRR performance of 70 dB at 10 kHz
Current limit and thermal overload protection
Logic-controlled enable
1
2
V
= 1.8V
OUT
V
= 2.3V
OUT
IN
VIN
VOUT
A
C
C
IN
1µF
1µF
TOP VIEW
(Not to Scale)
ON
EN
GND
B
OFF
5-lead TSOT package
4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP
Figure 2. 4-Ball WLCSP with Fixed Output Voltage, 1.8 V
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
RF, PLL, VCO, and clock power supplies
GENERAL DESCRIPTION
The ADP150 is an ultralow noise (9 µV), low dropout, linear
regulator that operates from 2.2 V to 5.5 V and provides up to
150 mA of output current. The low 105 mV dropout voltage at
150 mA load improves efficiency and allows operation over a
wide input voltage range.
The ADP150 is specifically designed for stable operation with
tiny 1 µF 30% ceramic input and output capacitors to meet
the requirements of high performance, space-constrained
applications.
The ADP150 is available in 14 fixed output voltage options,
ranging from 1.8 V to 3.3 V.
Using an innovative circuit topology, the ADP150 achieves ultralow
noise performance without the necessity of an additional noise
bypass capacitor, making it ideal for noise sensitive analog and
RF applications. The ADP150 also achieves ultralow noise
performance without compromising PSRR or line and load
transient performance. The ADP150 offers the best combination
of ultralow noise and quiescent current consumption to maximize
battery life in portable applications.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP150 is available in tiny
5-lead TSOT and 4-ball, 0.4 mm pitch WLCSP packages for the
smallest footprint solution to meet a variety of portable power
applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved.
ADP150
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 13
Thermal Considerations............................................................ 14
PCB Layout Considerations...................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Recommended Specifications: Input and Output Capacitor.. 4
Absolute Maximum Ratings............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
4/10—Rev. 0 to Rev. A
Changes to Figure 21........................................................................ 9
10/09—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADP150
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
VIN
Conditions
Min
Typ
10
Max
Unit
V
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
TJ = −40°C to +125°C
IOUT = 0 µA
IOUT = 0 µA, TJ = −40°C to +125°C
IOUT = 100 µA
IOUT = 100 µA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
2.2
5.5
IGND
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
22
20
40
60
100
320
1.0
220
0.2
IOUT = 150 mA, TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
SHUTDOWN CURRENT
IGND-SD
OUTPUT VOLTAGE ACCURACY
5-Lead TSOT
VOUT
IOUT = 10 mA
100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
TJ = −40°C to +125°C
−1
−2.5
+1
+1.5
%
%
4-Ball WLCSP
VOUT
IOUT = 10 mA
−1
−2.0
+1
+1.5
%
%
100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
TJ = −40°C to +125°C
REGULATION
Line Regulation
Load Regulation1
5-Lead TSOT
∆VOUT/∆VIN
VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −40°C to +125°C
−0.05
+0.05
%/V
∆VOUT/∆IOUT IOUT = 100 µA to 150 mA
IOUT = 100 µA to 150 mA, TJ = −40°C to +125°C
∆VOUT/∆IOUT IOUT = 100 µA to 150 mA
IOUT = 100 µA to 150 mA, TJ = −40°C to +125°C
IOUT = 10 mA
0.003
0.002
10
%/mA
0.0075 %/mA
%/mA
0.006
4-Ball WLCSP
%/mA
mV
mV
mV
mV
µs
DROPOUT VOLTAGE2
VDROPOUT
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
VOUT = 3.3 V
35
105
160
400
1.96
START-UP TIME3
TSTART-UP
ILIMIT
150
260
CURRENT LIMIT THRESHOLD4
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
190
mA
UVLO
UVLORISE
UVLOFALL
UVLOHYS
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
V
V
mV
1.28
115
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TJ rising
150
15
°C
°C
TSSD-HYS
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
VIH
VIL
VI-LEAKAGE
2.2 V ≤ VIN ≤ 5.5 V
2.2 V ≤ VIN ≤ 5.5 V
EN = IN or GND
EN = IN or GND, TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.8 V
1.2
V
V
µA
µA
0.4
1
0.001
OUTPUT NOISE
OUTNOISE
9
9
9
µV rms
µV rms
µV rms
Rev. A | Page 3 of 20
ADP150
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 0.5 V)
PSRR
10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA
70
dB
10 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA
100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA
70
55
55
70
dB
dB
dB
dB
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 1 V)
100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA
55
dB
1 Based on an end-point calculation using 1 mA and 150 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.2 V.
3 Start-up time is defined as the time between the rising edges of EN to VOUT being at 90% of its nominal value.
4 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT AND OUTPUT CAPACITOR
Minimum Input and Output Capacitance1
Capacitor ESR
CMIN
RESR
TA = −40°C to +125°C
TA = −40°C to +125°C
0.7
0.001
µF
Ω
0.2
1 The minimum input and output capacitance should be greater than 0.7 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R-type and X5R-type capacitors are
recommended, and Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 20
ADP150
ABSOLUTE MAXIMUM RATINGS
Table 3.
The junction-to-ambient thermal resistance (θ ) of the package
JA
is based on modeling and a calculation using a 4-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
Parameter
Rating
VIN to GND
VOUT to GND
−0.3 V to +6.5 V
−0.3 V to VIN
EN to GND
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
board design is required. The value of θcan vary, depending on
JA
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
PCB material, layout, and environmental conditions. The specified
values of θ are based on a 4-layer, 4 inch × 3 inch circuit board.
JA
Refer to JESD 51-7 and JESD 51-9 for detailed information
on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
a calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) by
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP150 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device (PD),
and the junction-to-ambient thermal resistance of the package
(θJA).
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
ΨJB
43
58
Unit
°C/W
°C/W
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
170
260
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) by
TJ = TA + (PD × θJA)
ESD CAUTION
Rev. A | Page 5 of 20
ADP150
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
1
2
3
5
VIN
GND
EN
VOUT
A
B
VIN
VOUT
ADP150
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
4
NC
EN
GND
NC = NO CONNECT
Figure 4. 4-Ball WLCSP Pin Configuration
Figure 3. 5-Lead TSOT Pin Configuration
Table 6. 4-Ball WLCSP Pin Function Descriptions
Table 5. 5-Lead TSOT Pin Function Descriptions
Pin No. Mnemonic Description
Pin No. Mnemonic Description
A1
A2
B1
VIN
Regulator Input Supply. Bypass VIN to
GND with a 1 µF or greater capacitor.
Regulated Output Voltage. Bypass VOUT
to GND with a 1 µF or greater capacitor.
Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
1
VIN
Regulator Input Supply. Bypass VIN to
GND with a 1 µF or greater capacitor.
Ground.
Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
No Connect. Not connected internally.
Regulated Output Voltage. Bypass VOUT
to GND with a 1 µF or greater capacitor.
VOUT
EN
2
3
GND
EN
4
5
NC
VOUT
B2
GND
Ground.
Rev. A | Page 6 of 20
ADP150
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.7 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
3.315
3.310
3.305
3.300
3.295
3.290
3.285
3.280
3.275
3.270
3.265
300
250
200
150
100
50
I
= 150mA
OUT
I
= 100mA
OUT
I
= 50mA
OUT
I
I
I
I
I
I
= 0.1mA
= 1mA
= 10mA
= 50mA
= 100mA
= 150mA
OUT
OUT
OUT
OUT
OUT
OUT
I
= 10mA
OUT
I
= 1mA
OUT
OUT
I
= 0.1mA
0
–40
–5
25
85
125
–40
–5
25
85
125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage (VOUT) vs. Junction Temperature
Figure 8. Ground Current vs. Junction Temperature
3.298
250
200
150
100
50
3.297
3.296
3.295
3.294
3.293
3.292
3.291
3.290
0
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
I
(mA)
I
(mA)
OUT
OUT
Figure 6. Output Voltage (VOUT) vs. Load Current (IOUT
)
Figure 9. Ground Current vs. Load Current (IOUT)
3.300
3.298
3.296
3.294
3.292
3.290
3.288
250
200
150
100
50
I
I
= 150mA
= 100mA
OUT
OUT
I
= 0.1mA
OUT
I
= 1mA
OUT
I
= 10mA
OUT
I
I
= 50mA
OUT
I
= 50mA
OUT
= 10mA
= 1mA
OUT
I
I
I
= 100mA
= 150mA
OUT
OUT
I
= 0.1mA
OUT
OUT
0
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V
(V)
V
IN
(V)
IN
Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN
)
Figure 10. Ground Current vs. Input Voltage (VIN)
Rev. A | Page 7 of 20
ADP150
0.7
0.6
0.5
0.4
0.3
0.2
0.1
700
600
500
400
300
200
100
0
V
V
V
V
V
V
V
V
= 3.6V
= 3.8V
= 4.2V
= 4.4V
= 5.0V
= 5.2V
= 5.4V
= 5.5V
IN
IN
IN
IN
IN
IN
IN
IN
I
I
I
I
= 10mA
= 50mA
= 100mA
= 150mA
OUT
OUT
OUT
OUT
0
–50
–25
0
25
50
75
100
125
3.05
3.10
3.15
3.20
3.25
(A)
3.30
3.35
3.40
3.45
TEMPERATURE (°C)
V
IN
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
I
I
I
I
I
= 100µA
= 1mA
= 10mA
= 100mA
= 150mA
V
V
C
= V
+ 0.5V
= 50mV
OUT
OUT
OUT
OUT
OUT
IN
RIPPLE
= C
OUT
= 1µF
IN
OUT
1
10
100
1000
10
100
1k
10k
100k
1M
10M
I
(mA)
FREQUENCY (Hz)
OUT
Figure 15. Power Supply Rejection Ratio (PSRR) vs. Frequency,
Figure 12. Dropout Voltage vs. Load Current (ILOAD
)
VOUT = 1.8 V, VIN = 2.3 V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
I
I
I
I
I
= 100µA
= 1mA
= 10mA
= 100mA
= 150mA
V
V
C
= V
+ 0.5V
= 50mV
OUT
OUT
OUT
OUT
OUT
I
I
I
I
= 10mA
= 50mA
= 100mA
= 150mA
IN
RIPPLE
= C
OUT
OUT
OUT
OUT
OUT
= 1µF
IN
OUT
10
100
1k
10k
100k
1M
10M
3.05
3.10
3.15
3.20
3.25
(V)
3.30
3.35
3.40
3.45
FREQUENCY (Hz)
V
IN
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Frequency,
OUT = 2.8 V, VIN=3.3 V
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout
V
Rev. A | Page 8 of 20
ADP150
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15
13
11
9
I
I
I
I
I
= 100µA
= 1mA
= 10mA
= 100mA
= 150mA
V
V
V
= 3.3V
= 2.8V
= 1.8V
OUT
OUT
OUT
OUT
OUT
V
V
C
= V
+ 0.5V
= 50mV
OUT
OUT
OUT
IN
RIPPLE
= C
OUT
= 1µF
IN
OUT
7
5
3
1
10
100
1k
10k
100k
1M
10M
0.001
0.01
0.1
1
10
100
1k
FREQUENCY (Hz)
I
(mA)
OUT
Figure 17. Power Supply Rejection Ratio (PSRR) vs. Frequency,
OUT = 3.3 V, VIN = 3.8 V
Figure 20. Output RMS Noise vs. Load Current (IOUT) and
Output Voltage (VOUT), VIN = 5 V, COUT = 1 µF
V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
V
V
C
= V
+ 0.5V
= 50mV
V
V
V
V
V
V
= 1.8V, I
= 2.8V, I
= 3.3V, I
= 1.8V, I
= 2.8V, I
= 3.3V, I
= 100µA
= 100µA
= 100µA
= 150mA
= 150mA
= 150mA
IN
RIPPLE
= C
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
= 1.8V
= 2.8V
= 3.3V
OUT
OUT
OUT
= 1µF
IN
OUT
0.1
0.01
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio (PSRR) vs. Frequency
Various Output Voltages and Load Currents
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 μF
–10
T
V
C
= 50mV
= 1µF
OUT
V
V
V
V
V
V
= 3.8V, I
= 4.3V, I
= 5.3V, I
= 3.8V, I
= 4.3V, I
= 5.3V, I
= 1mA
= 1mA
= 1mA
= 150mA
= 150mA
= 150mA
RIPPLE
= C
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
I
OUT
IN
–20
–30
–40
–50
–60
–70
–80
–90
–100
1mA TO 150mA LOAD STEP
1
V
OUT
2
V
V
= 3.7V
= 3.3V
IN
OUT
CH1 100mA CH2 50mV
M40µs
T
A CH1
112mA
10
100
1k
10k
100k
1M
10M
117.560µs
FREQUENCY (Hz)
Figure 22. Load Transient Response, COUT = 1 µF
Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency with
Various Headroom Voltages (VIN − VOUT), VOUT = 3.3 V
Rev. A | Page 9 of 20
ADP150
T
T
I
OUT
1mA TO 150mA LOAD STEP
V
IN
3.7V TO 4.7V VOLTAGE STEP
OFFSET = 2.7V
1
2
1
2
V
OUT
V
OUT
V
V
= 3.7V
= 3.3V
IN
OUT
CH1 100mA CH2 50mV
M40µs
A CH1
108mA
CH1 1.00V
CH2 10mV
M10µs
A CH1
4.60V
T
118.000µs
T
29.60µs
Figure 25. Line Transient Response, CIN, COUT =1 μF, ILOAD = 150 mA
Figure 23. Load Transient Response, COUT = 4.7 μF
T
V
IN
3.7V TO 4.7V VOLTAGE STEP
OFFSET = 2.7V
1
2
V
OUT
CH1 1.00V
CH2 10mV
M10µs
A CH1
4.60V
T
29.60µs
Figure 24. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1mA
Rev. A | Page 10 of 20
ADP150
THEORY OF OPERATION
The ADP150 is an ultralow noise, low quiescent current, low
dropout linear regulator that operates from 2.2 V to 5.5 V and
can provide up to 150 mA of output current. Drawing a low 220 µA
of quiescent current (typical) at full load makes the ADP150 ideal
for battery-operated portable equipment. Shutdown current
consumption is typically 200 nA.
Internally, the ADP150 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device that is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
Using new innovative design techniques, the ADP150 provides
superior noise performance for noise sensitive analog and
RF applications without the need for a noise bypass capacitor.
The ADP150 is also optimized for use with small 1 µF ceramic
capacitors.
The ADP150 is available in 14 output voltage options, ranging
from 1.8 V to 3.3 V. The ADP150 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on, and when EN is low, VOUT turns
off. For automatic startup, EN can be tied to VIN.
VIN
VOUT
R1
SHORT CIRCUIT,
UVLO, AND
THERMAL
GND
PROTECT
R2
VOLTAGE
REFERENCE
EN
SHUTDOWN
Figure 26. Internal Block Diagram
Rev. A | Page 11 of 20
ADP150
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the ADP150,
as long as they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
Output Capacitor
The ADP150 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO control loop. A minimum of 1 µF
capacitance with an ESR of 1 Ω or less is recommended to
ensure the stability of the ADP150. The transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP150 to large changes in the load current.
Figure 27 and Figure 28 show the transient responses for output
capacitance values of 1 µF and 4.7 µF, respectively.
Figure 29 depicts the capacitance vs. the voltage bias characteristic
of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is about 15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
T
I
OUT
1mA TO 150mA LOAD STEP
1
1.0
0.8
0.6
0.4
0.2
0
2
V
OUT
V
V
= 3.7V
= 3.3V
IN
OUT
CH1 100mA CH2 50mV
M1.0µs
T
A CH1
100mA
716.000µs
Figure 27. Output Transient Response, COUT = 1 µF
T
0
2
4
6
8
10
BIAS VOLTAGE (V)
I
OUT
1mA TO 150mA LOAD STEP
Figure 29. Capacitance vs. Voltage Bias Characteristic
1
2
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
V
OUT
where:
C
BIAS is the effective capacitance at the operating voltage.
V
V
= 3.7V
= 3.3V
IN
OUT
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
CH1 100mA CH2 50mV
M1.0µs
A CH1
108mA
T
240.000ns
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
the CBIAS is 0.94 µF at 1.8 V, as shown in Figure 29.
Figure 28. Output Transient Response, COUT = 4.7 µF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance is encountered. If greater than
1 µF of output capacitance is required, increase the input capacitor
to match the output capacitor.
Substituting these values in Equation 1 yields
CEFF = 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
Rev. A | Page 12 of 20
ADP150
To guarantee the performance of the ADP150, it is imperative
that the effects of the dc bias, temperature, and tolerances on
the behavior of the capacitors be evaluated for each.
The ADP150 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 3.3 V
option is approximately 150 µs from the time the EN active
threshold is crossed to when the output reaches 90% of its final
value. As shown in Figure 32, the start-up time is dependent on the
output voltage setting.
UNDERVOLTAGE LOCKOUT
The ADP150 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.0 V. This ensures that the ADP150 inputs
and output behave in a predictable manner during power-up.
T
EN
ENABLE FEATURE
V
= 3.3V
OUT
The ADP150 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 30,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
V
V
= 2.8V
= 1.8V
OUT
OUT
1
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CH1 1V
CH3 1V
CH2 1V
CH4 1V
M40.0µs
240.000ns
A CH1
3.24V
T
Figure 32. Typical Start-Up Time
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP150 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP150 is designed to limit current when the
output load reaches 260 mA (typical). When the output load
exceeds 260 mA, the output voltage is reduced to maintain a
constant current limit.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
EN
Figure 30. Typical EN Pin Operation
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation)
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing the output current to zero. When
the junction temperature drops below 135°C, the output is turned
on again and the output current is restored to its nominal value.
As shown in Figure 30, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the VIN
voltage; therefore, these thresholds vary with changing input
voltage. Figure 31 shows the typical EN active/inactive thresholds
when the input voltage varies from 2.2 V to 5.5 V.
1.1
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP150 limits current so that only 260 mA is
conducted into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 260 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 260 mA and 0 mA that
continues as long as the short remains at the output.
1.0
RISING
0.9
0.8
FALLING
0.7
0.6
0.5
0.4
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that the junction temperatures do not exceed 125°C.
2.3
2.8
3.3
3.8
4.3
(V)
4.8
5.3
5.5
V
IN
Figure 31. Typical EN Pin Thresholds vs. Input Voltage (VIN
)
Rev. A | Page 13 of 20
ADP150
Power dissipation due to ground current is quite small and can be
ignored. Therefore, the junction temperature equation simplifies to
THERMAL CONSIDERATIONS
In most applications, the ADP150 does not dissipate much heat
due to its high efficiency. However, in applications with high
ambient temperature and high supply voltage to output voltage
differential, the heat dissipated in the package is large enough
that it can cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(3)
As shown in the previous equation, for a given ambient temperature,
input-to-output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 125°C.
Figure 33 to Figure 46 show the junction temperature calculations
for the different ambient temperatures, load currents, VIN-to-VOUT
differentials, and areas of PCB copper.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application is
very important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
140
MAX JUNCTION TEMPERATURE
120
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
100
80
To guarantee reliable operation, the junction temperature of
the ADP150 must not exceed 125°C. To ensure that the junction
temperature stays below 125°C, be aware of the parameters that
contribute to the junction temperature changes. These parameters
include ambient temperature, power dissipation in the power
device, and thermal resistances between the junction and
60
40
20
ambient air (θ ). The θJA number is dependent on the package
assembly compounds that are used and the amount of copper
used to solder the package GND pins to the PCB. Table 7 shows
JA
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
V
IN
OUT
Figure 33. TSOT, 500 mm2 of PCB Copper, TA = 25°C
typical θ values of the 5-lead TSOT and 4-ball WLCSP packages
JA
for various PCB copper sizes. Table 8 shows the typical ΨJB
value of the 5-lead TSOT and 4-b a l l WLC SP.
140
120
100
80
MAX JUNCTION TEMPERATURE
Table 7. Typical θJA Values
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
θJA (°C/W)
Copper Size (mm2)
01
TSOT
170
152
146
134
131
WLCSP
260
159
157
153
50
100
300
500
60
40
20
151
1 Device soldered to minimum size pin traces.
Table 8. Typical ΨJB Values
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
ΨJB (°C/W)
V
IN
OUT
TSOT
WLCSP
Figure 34. TSOT, 100 mm2 of PCB Copper, TA = 25°C
42.8
58.4
Use Equation 2 to calculate the junction temperature.
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND
where:
)
I
LOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Rev. A | Page 14 of 20
ADP150
140
120
100
80
140
120
100
80
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
60
40
20
60
40
20
I
I
I
I
= 1mA
I
I
I
= 75mA
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
0
0.5
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
4.5
4.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
V
V
IN
OUT
IN
OUT
Figure 35. TSOT, 0 mm2 of PCB Copper, TA = 25°C
Figure 38. TSOT, 0 mm2 of PCB Copper, TA = 50°C
140
120
100
80
140
120
100
80
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
60
40
20
60
40
20
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
I
I
I
I
= 1mA
I
I
I
= 75mA
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
0
0.5
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
V
V
IN
IN
OUT
OUT
Figure 36. TSOT, 500 mm2 of PCB Copper, TA = 50°C
Figure 39. TSOT, 100 mm2 of PCB Copper, Board Temperature = 85°C
140
140
120
100
80
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
120
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
100
80
60
40
20
60
40
20
I
I
I
I
= 1mA
I
I
I
= 75mA
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
0
0.5
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
V
V
IN
OUT
IN
OUT
Figure 37. TSOT, 100 mm2 of PCB Copper, TA = 50°C
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C
Rev. A | Page 15 of 20
ADP150
140
120
100
80
140
120
100
80
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
60
40
20
60
40
20
I
I
I
I
= 1mA
I
I
I
= 75mA
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
0
0.5
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
4.5
4.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
4.5
4.5
4.5
V
V
IN
OUT
IN
OUT
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
140
120
100
80
MAX JUNCTION
TEMPERATURE
MAX JUNCTION
TEMPERATURE
60
40
20
60
40
20
I
I
I
I
= 1mA
I
I
I
= 75mA
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
I
I
I
= 1mA
= 10mA
= 25mA
I
I
= 50mA
= 75mA
I
I
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
V
– V
OUT
V
IN
IN
OUT
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C
140
120
100
80
140
120
100
80
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
I
I
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
60
40
20
60
40
20
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
I
I
I
I
= 1mA
I
I
I
= 75mA
= 100mA
= 150mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 25mA
= 50mA
0
0.5
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
1.0
1.5
2.0
2.5
– V
3.0
(V)
3.5
4.0
V
V
IN
IN
OUT
OUT
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C
Figure 46. WLCSP, 100 mm2 of PCB Copper, Board Temperature = 85°C
Rev. A | Page 16 of 20
ADP150
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP150. However, as listed in Table 7, a point of diminishing
returns is reached eventually, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402 size or 0603 size capacitors
and resistors achieves the smallest possible footprint solution on
boards where area is limited.
Figure 48. Example WLCSP PCB Layout
Figure 47. Example TSOT PCB Layout
Rev. A | Page 17 of 20
ADP150
OUTLINE DIMENSIONS
2.90 BSC
5
1
4
3
2.80 BSC
1.60 BSC
2
0.95 BSC
1.90
BSC
*
0.90 MAX
0.70 MIN
*
1.00 MAX
0.20
0.08
8°
4°
0°
0.10 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.660
0.600
0.800
0.760 SQ
0.430
0.540
0.400
0.720
0.370
SEATING
PLANE
2
1
A
B
0.280
0.260
0.240
BALL A1
IDENTIFIER
0.40
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.230
0.200
0.170
0.050 NOM
COPLANARITY
Figure 50.4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-3)
Dimensions show in millimeters
Rev. A | Page 18 of 20
ADP150
ORDERING GUIDE
Temperature
Range (TJ)
Output
Package
Option
Model1
Voltage (V)2 Package Description
Branding
36
3V
63
3X
46
3Y
47
48
ADP150ACBZ-1.8-R7
ADP150ACBZ-2.5-R7
ADP150ACBZ-2.6-R7
ADP150ACBZ-2.75R7
ADP150ACBZ-2.8-R7
ADP150ACBZ-2.85R7
ADP150ACBZ-3.0-R7
ADP150ACBZ-3.3-R7
ADP150AUJZ-1.8-R7
ADP150AUJZ-2.5-R7
ADP150AUJZ-2.8-R7
ADP150AUJZ-3.0-R7
ADP150AUJZ-3.3-R7
ADP150CB-3.3-EVALZ
ADP150UJ-3.3-EVALZ
–40°C to +125°C 1.8
–40°C to +125°C 2.5
–40°C to +125°C 2.6
–40°C to +125°C 2.75
–40°C to +125°C 2.8
–40°C to +125°C 2.85
–40°C to +125°C 3.0
–40°C to +125°C 3.3
–40°C to +125°C 1.8
–40°C to +125°C 2.5
–40°C to +125°C 2.8
–40°C to +125°C 3.0
–40°C to +125°C 3.3
3.3
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
4-Ball Wafer Level Chip Scale Package [WLCSP]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
5-Lead Thin Small Outline Transistor Package [TSOT]
Evaluation Board with WLCSP package
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
CB-4-3
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
LDS
LDZ
LE3
LE2
LEJ
3.3
Evaluation Board with TSOT package
1 Z = RoHS Compliant Part.
2 Up to 14 fixed output voltage options from 1.8 V to 3.3 V are available. For additional voltage options, contact your local Analog Devices, Inc, sales or distribution
representative.
Rev. A | Page 19 of 20
ADP150
NOTES
©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08343-0-4/10(A)
Rev. A | Page 20 of 20
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