ADP3342 [ADI]
Ultralow, IQ, anyCAP Low Dropout Regulator; 超低智商，公司的anyCAP低压降稳压器
| 型号： | ADP3342 |
| 厂家： | 
ADI |
| 描述： | Ultralow, IQ, anyCAP Low Dropout Regulator |
| 文件： | 总8页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Ultralow, IQ, anyCAP
Low Dropout Regulator
a
ADP3342
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Accuracy Over Line and Load: ؎4.0% @ 25؇C,
؎5% Over Temperature
Ultralow Dropout Voltage: 300 mV (Typ) @ 300 mA
Requires Only CO = 1.0 F for Stability
anyCAP = Stable with any Type of Capacitor
(including MLCC)
Current and Thermal Limiting
Low Shutdown Current: < 2 A
1.7 V Յ VIN Յ 6 V
Q1
IN
OUT
VCC
THERMAL
CC
PROTECTION
g
DRIVER
m
PWRGD
SD
BANDGAP +
REF –
2.8 V Յ VCC Յ 6 V
ADP3342
VOUT = 1.2 V ؎5%
–40؇C to +100؇C Ambient Temperature Range
Ultrasmall Thermally Enhanced 8-Lead MSOP Package
GND
APPLICATIONS
Notebook PCs
Desktop PCs
3.3V
GENERAL DESCRIPTION
The ADP3342 is a unique member of the ADP330x family of
precision low dropout anyCAP voltage regulators. The ADP3342
operates with an input voltage range of 1.7 V to 6 V and delivers
a continuous load current up to 300 mA. In order to support the
ability to regulate from such a low input voltage, the power rail
to the IC, VCC, has been split off from the main power rail, VIN,
from which the output is powered.
VCC
ADP3342
V
1.8V
V
OUT
1.2V
IN
IN
OUT
+
+
1F
1F
IN
OUT
SD PWRGD
ON
GND
OFF
The ADP3342 stands out from the conventional LDOs with the
lowest thermal resistance of any MSOP-8 package and an enhanced
process that enables it to offer performance advantages beyond
its competition. Its patented design requires only a 1.0 µF output
capacitor for stability. This device is insensitive to output capacitor
Equivalent Series Resistance (ESR), and is stable with any good
quality capacitor, including ceramic (MLCC) types for space-
restricted applications. The dropout voltage of the ADP3342 is
only 190 mV (typical) at 300 mA. This device also includes a
safety current limit, thermal overload protection and a shutdown
control pin.
Figure 1. Typical Application Circuit
anyCAP is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VCC = 3.0 V, VIN = 1.8 V, CIN = COUT = 1 F, TA = 0؇C to 100؇C and TA = –40؇C to
+100؇C, unless otherwise noted.)
ADP3342–SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT
Voltage Accuracy
VOUT
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
IL = 0.1 mA to 300 mA
TA = 25°C
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
IL = 0.1 mA to 300 mA,
TA = –40°C to +100°C
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
TA = 25°C
IL = 0.1 mA to 300 mA
TA = 25°C
VOUT = 98% of VOUTNOM
IL = 300 mA
IL = 200 mA
IL = 100 mA
–4.0
+4.0
%
–5.0
+5.0
%
Line Regulation
Load Regulation
Dropout Voltage
0.04
0.12
mV/V
mV/mA
VDROP
190
125
70
450
mV
mV
mV
Current Limiting
Output Noise
ILIM
VNOISE
VCC = 3 V, VIN = 1.8 V
f = 10 Hz–100 kHz, CL = 1 µF
IL = 300 mA
450
60
mA
µV rms
OPERATING CURRENTS
Ground Current in Regulation
IGND
IL = 300 mA, TA = –40°C to +100°C
IL = 300 mA, TA = 0°C to 100°C
IL = 300 mA, TA = 25°C
IL = 200 mA
IL = 0.1 mA
IL = 300 mA
3.0
3.0
3.0
2.0
100
100
0.01
8.5
6.0
4.0
mA
mA
mA
mA
µA
175
170
2
VCC Current in Regulation
Ground Current in Shutdown
IVCC
IGNDSD
µA
SD = 0 V, VCC = 6 V, VIN = 1.8 V
µA
SHUTDOWN
Threshold Voltage
VTHSD
ON
VCC – 0.9
V
OFF
0 ≤ SD ≤ 6 V
TA = 25°C VCC = 6 V, VIN = 6 V
TA = 100°C VCC = 6 V, VIN = 6 V
0.6
7
1
V
SD Input Current
Output Current In Shutdown
ISD
IOSD
1.4
0.01
0.01
µA
µA
µA
2
PWRGD
Power Good Output Voltage
IPWRGDL
VPWRGDL
VPWRGD = 1.2 V, VCC = 3.0 V
IPWRGD = 300 µA
0.85
1.5
mA
V
V
2
0.4
300
300
1
2
VPWRGDH IPWRGD = 300 µA
VCC – 0.4
5
Power Good On Time Delay
TD13
TD24
TD35
IL = 3 mA to 300 mA,
COUT = 1 µF to 10 µF
IL = 3 mA to 300 mA,
µs
50
µs
µs
C
OUT = 1 µF to 10 µF
Power Good Off Time Delay
IL = 3 mA to 300 mA,
0.05
COUT = 1 µF to 10 µF
THERMAL PROTECTION
Shutdown Temperature
THPROT
IL = 100 mA
165
°C
NOTES
1Ambient temperature of 100°C corresponds to a junction temperature of 125°C under typical full load test conditions.
2VPWRGDL, VPWRGDH,: Powergood output voltages. Guaranteed by design and characterization.
3TD1: Delay time from VOUT crossing 1 V to PWRGD high. Guaranteed by design.
4TD2: Delay time from SD high to PWRGD high. Guaranteed by design.
5TD3: Delay time between SD low to PWRGD low. Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. 0
ADP3342
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +13 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +13 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . –40°C to +100°C
Operating Junction Temperature Range . . . –40°C to +125°C
OUT
OUT
1
2
3
4
8
7
6
5
IN
IN
ADP3342
TOP VIEW
VCC
GND
(Not to Scale)
SD
PWRGD
JA (2-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157°C/W
JA (4-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
JC
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device
to be permanently damaged.
ORDERING GUIDE
Model
Output Voltage*
Package Option
Marking Code Temperature Range
ADP3342JRM-REEL7 1.2 V
ADP3342ARM-REEL7 1.2 V
RM-8 (MSOP-8)
RM-8 (MSOP-8)
LJA
LJB
0°C to 100°C
–40°C to +100°C
*Contact the factory for other output voltage options.
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 2
OUT
Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be
connected together for proper operation.
3
4
5
6
VCC
Supply Voltage
GND
PWRGD
SD
Ground Pin
Power Good. Used to indicate output is in regulation.
Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shut down
is not used, this pin should be connected to the input pin.
7, 8
IN
Regulator Input. All pins must be connected together for proper operation.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3342 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADP3342–Typical Performance Characteristics
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.23
1.22
1.21
1.20
1.19
1.18
1.17
120
110
100
90
V
= 1.8V
= 3.0V
IN
V
= 1.2V
= 3V
V
= 1.2V
= 3V
OUT
OUT
V
CC
V
V
CC
CC
I
= 0A
L
I
= 0mA
L
I
= 100mA
L
80
I
I
= 200mA
= 300mA
L
70
L
60
50
1.7
2.7
3.7
4.7
5.7
0
50
100
150
200
250
300
1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
INPUTVOLTAGE –V
OUTPUT LOAD – mA
INPUT VOLTAGE – V
TPC 1. Line Regulation Output Voltage
vs. Supply Voltage
TPC 2. Output Voltage vs. Load Current
TPC 3. Ground Current vs. Supply
Voltage
5.50
3.5
1.0
0
V
= 3.0V
= 1.8V
V
= 1.8V
= 3.0V
CC
IN
0.9
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
V
V
IN
3.0
2.5
CC
0.8
0.7
200mA
0.6
0.5
0.4
0.3
0.2
I
I
= 300mA
= 200mA
L
2.0
1.5
1.0
L
300mA
0.1
0
–0.1
–0.2
–0.3
–0.4
I
= 100mA
= 0mA
L
0.5
0
I
L
0
50
100
150
200
250
300
–40 –20
0
20
40
60
80
100
–50 –25
0
25
50
75 100 125 150
OUTPUT LOAD – mA
JUNCTIONTEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
TPC 4. Ground Current vs. Load Current
TPC 5. Output Voltage Variation
vs. Junction Temperature
TPC 6. Ground Current vs. Junction
Temperature
0.25
0.20
0.15
0.10
7.0
V
= 3.0V
= 1.8V
CC
6.5
6.0
5.5
6
V
IN
V
= 1.2V
OUT
SD = V
5
4
3
2
1
IN
= 4⍀
R
L
5.0
4.5
4.0
3.5
MAX
TYP
MIN
3.0
2.5
2.0
0
–1
–2
0.05
0
1.5
1.0
0
200
400
600
800
1000
TIME – s
0
50
100
150
200
250
300
–40 –25 –10
5
20 35 50 65 80 950
OUTPUT LOAD – mA
TEMPERATURE – ؇C
TPC 7. Dropout Voltage vs. Output
Current
TPC 8. Ground Current @ 300 mA
Load vs. Ambient Temperature
TPC 9. Power-Up/Power-Down
–4–
REV. 0
ADP3342
0
V
C
R
= 3V
= 10F
= 4⍀
V
C
R
= 3V
= 1F
= 4⍀
CC
CC
1.3
1.2
1.1
L
L
L
L
1.32
1.22
1.12
3.00
1.80
1.32
1.22
1.12
3.00
1.80
V
= 3V
= 1.8V
= 1F
CC
V
IN
C
L
400
200
5
0
400
800
1200
1600
2000
0
40
80
120
160
200
0
40
80
120
160
200
TIME – s
TIME – s
TIME – s
TPC 10. Line Transient Response
TPC 11. Line Transient Response
TPC 12. Load Transient Response
0
V
= 1.8V
V
R
= 3V
= 4⍀
= 1.8V
IN
CC
1.3
1.2
1.2
0
2.0
1.0
0
L
V
IN
V
= 3V
= 1.8V
= 10F
CC
1.1
V
IN
C
L
3.0
0
400
200
5
1.0
0.5
0
1.8
0
0
400
800
1200
1600
2000
0
200
400
600
800
1000
–200
200
600
1000
1400
1800
TIME – s
TIME – s
TIME – s
TPC 13. Load Transient Response
TPC 14. Short Circuit Current
TPC 15. Power-On/Power-Off
Response from Shutdown
2.0
1.0
2.0
V
= 1.8V
IN
2.0
1.0
0
1.0
0
SD = 3.0V
R
V
= 3V
= 1.8V
= 4⍀
= 4⍀
CC
L
0
V
IN
V
= 3V
= 1.8V
R
CC
L
V
IN
R
= 4⍀
L
3.0
0
3.0
0
1.8
0
1.8
0
3.0
0
0
100
200
300
400
500
200
600
1000
1400
1800
2
6
10
14
18
TIME – s
TIME – s
TIME – s
TPC 16. Turn On Delay
TPC 17. Turn Off Delay
TPC 18. Power-On/Power-Off
Response from VCC
–5–
REV. 0
ADP3342
–20
–30
–40
–50
–60
–70
–80
–90
70
60
V
= 1.2V
OUT
C
= 10F
= 300mA
L
I
L
C
= 1F
= 300mA
L
1.2
0
I
L
50
40
30
20
V
= 1.8V
IN
SD = 3.0V
= 4⍀
C
= 1F
= 50A
L
R
L
I
L
300mA
0mA
3.0
0
1.8
0
C
= 10F
= 50A
L
I
L
10
0
0
200
400
600
800
1000
TIME – s
0
10
20
C
30
– F
40
50
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
L
TPC 19. Power On/Power Off
Response from VIN
TPC 20. Power Supply Ripple
Rejection
TPC 21. RMS Noise vs. CL
(10 Hz–100 Hz)
1.25
100
10
650
V
= 1.2V
= 1mA
OUT
I
L
1.23
0mA
50mA
600
550
500
C
= 10F
L
1.21
1
C
= 1F
L
100mA
200mA
300mA
1.19
1.17
1.15
0.1
0.01
0.001
35
55
75
95 115 135 155 175
10
100
1k
10k
100k
1M
1.5
1.6
1.7
V
1.8
– V
1.9
2.0
AMBIENT TEMPERATURE – ؇C
FREQUENCY – Hz
IN
TPC 22. Output Noise Density
TPC 23. Thermal Protection
TPC 24. Current Limit vs. VIN
3.6
3.0
V
= 1.8V
IN
SD = 3V
400
200
0
5
15
25
35
45
TIME – ms
TPC 25. Current Limiting from VCC
–6–
REV. 0
ADP3342
THEORY OF OPERATION
APPLICATION INFORMATION
PC Application—VCCVID
The new anyCAP LDO ADP3342 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
The ADP3342 has been optimized for PC applications that
require a 1.2 V output for powering the voltage identification
rail, VCCVID. The rail from which the output draws current,
the IN pin, is separated from the rail that powers the IC, the
VCC pin. This allows a higher efficiency design when, as
recommended for the IMVP-3 application, the VCC pin is
connected to a 3.3 V supply to power the IC adequately, and
the IN pin is connected to a 1.8 V supply. The efficiency is
nearly 60% in this case.
VCC
INPUT
Q1
OUTPUT
COMPENSATION
CAPACITOR
ATTENUATION
/V
R1
(a)
(V
)
BANDGAP OUT
C
LOAD
D1
R3
PTAT
V
NONINVERTING
WIDEBAND
DRIVER
Capacitor Selection
OS
g
m
PTAT
As with any voltage regulator, output transient response is a
function of the output capacitance. The ADP3342 is stable with
a wide range of capacitor values, types and ESR (anyCAP).
A capacitor as low as 1 µF is all that is needed for stability; larger
capacitors can be used if high output current surges are anticipated.
The ADP3342 is stable with extremely low ESR capacitors (ESR ≈ 0),
such as multilayer ceramic capacitors (MLCC) or OSCON.
Note that the effective capacitance of some capacitor types may
fall below the minimum at cold temperature. Ensure that the
capacitor provides more than 1 µF at minimum temperature.
R
LOAD
CURRENT
R4
R2
ADP3342
GND
Figure 2. Control Loop Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage”
that is repeatable and very well controlled. The temperature
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility
on the trade-off of noise sources that leads to a low noise design.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground reduces
the circuit's sensitivity to PC board layout. If a larger value output
capacitor is used, then a larger value input capacitor is also
recommended.
Power Good Monitoring Function
The PWRGD pin does not monitor the output voltage directly,
but rather detects whether the internal PNP pass transistor is being
modulated by the regulation loop. This means of detecting PWRGD,
rather than using a voltage threshold detection, provides an inherent
and desirable delay in asserting the PWRGD signal. During
startup or overload, the regulation loop is not in control, so the
PWRGD pin is low.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1 and a second divider consisting
of R3 and R4, the values can be chosen to produce a temperature
stable output. This unique arrangement specifically corrects for
the loading of the divider so that the error resulting from base
current loading in conventional circuits is avoided.
Shutdown Mode
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve reduced
sensitivity to the value, type and ESR of the load capacitance.
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output ON. Pulling SD down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced.
Paddle-Under-Lead Package
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limitations
make designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
The ADP3342 uses a patented paddle-under-lead package design
to ensure the best thermal performance in an MSOP-8 footprint.
This new package uses an electrically isolated die attach that
allows all pins to contribute to heat conduction. This technique
reduces the thermal resistance to 110°C/W on a 4-layer board as
compared to >160°C/W for a standard MSOP-8 leadframe.
Thermal Overload Protection
With the ADP3342 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the output.
Additional advantages of the pole splitting scheme include superior
line noise rejection and very high regulator gain which leads to
excellent line and load regulation.
The ADP3342 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output current
is reduced until the die temperature has dropped to a safe level.
The output current is restored when the die temperature is reduced.
Additional features of the circuit include current limit and thermal
shutdown and noise reduction.
REV. 0
–7–
ADP3342
Current and thermal limit protections are intended to protect the
device against accidental overload conditions. For normal operation,
device power dissipation should be limited by operating conditions
so that junction temperatures will not exceed 150°C.
Assuming ILOAD = 300 mA, IGND = 4 mA, VIN = 1.8 V and
VOUT = 1.2 V, device power dissipation is:
PD = (1.8 −1.2) 300 mA +(1.8) 4 mA = 187 mW
The proprietary package used in the ADP3342 has a thermal
resistance of 110°C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction tem-
perature rise above ambient temperature will be approximately
equal to:
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (VIN –VOUT )ILOAD +(VIN )IGND
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
∆TJA = 0.187W ×110°C W = 20.6°C
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Micro SOIC (MSOP)
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33؇
0.018 (0.46)
0.008 (0.20)
27؇
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
–8–
REV. 0
相关型号：
ADP3342JRM-REEL
IC VREG 1.2 V FIXED POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO8, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3342JRM-REEL
IC VREG 1.2 V FIXED POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO8, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ONSEMI
ADP3342JRM-REEL7
1.2V FIXED POSITIVE LDO REGULATOR, 0.45V DROPOUT, PDSO8, MO-187AA, MSOP-8
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ADP3342JRMZ-REEL
IC VREG 1.2 V FIXED POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO8, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ONSEMI
ADP3342JRMZ-REEL7
IC VREG 1.2 V FIXED POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO8, LEAD FREE, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3342JRMZ-REEL7
1.2V FIXED POSITIVE LDO REGULATOR, 0.45V DROPOUT, PDSO8, LEAD FREE, MO-187AA, MSOP-8
ONSEMI
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