ADP3342JRMZ-REEL7 [ADI]
IC VREG 1.2 V FIXED POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO8, LEAD FREE, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator;
| 型号： | ADP3342JRMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC VREG 1.2 V FIXED POSITIVE LDO REGULATOR, 0.45 V DROPOUT, PDSO8, LEAD FREE, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator 光电二极管 输出元件 调节器 |
| 文件： | 总12页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Ultralow, IQ, anyCAP
Low Dropout Regulator
ADP3342
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Accuracy over line and load: ؎4.0% @ 25؇C,
؎5% over temperature
Ultralow dropout voltage: 190 mV (Typ) @ 300 mA
Requires only CO = 1.0 F for stability
anyCAP architecture stable with any type of capacitor
(including MLCC)
Current and thermal limiting
Low shutdown current: < 2 A
1.7 V < VIN < 6 V
Q1
IN
OUT
VCC
THERMAL
CC
PROTECTION
g
DRIVER
m
PWRGD
SD
BAND GAP +
REF –
2.8 V < VCC < 6 V
ADP3342
V
OUT = 1.2 V ؎5%
–40؇C to +100؇C ambient temperature range
Ultrasmall thermally enhanced 8-lead MSOP package
GND
APPLICATIONS
Notebook PCs
Desktop PCs
3.3V
GENERAL DESCRIPTION
The ADP3342 is a unique member of the ADP330x family of
precision low dropout anyCAP voltage regulators. The ADP3342
operates with an input voltage range of 1.7 V to 6 V and delivers a
continuous load current up to 300 mA. In order to support the
ability to regulate from such a low input voltage, the power rail to
the IC, VCC, has been split off from the main power rail, VIN,
from which the output is powered.
VCC
ADP3342
V
1.8V
V
1.2V
IN
OUT
IN
OUT
+
+
1F
1F
SD PWRGD
ON
GND
OFF
The ADP3342 stands out from the conventional LDOs with
the lowest thermal resistance of any MSOP-8 package and an
enhanced process that enables it to offer performance advan-
tages beyond its competition. Its patented design requires only a
1.0 µF output capacitor for stability. This device is insensitive to
output capacitor equivalent series resistance (ESR) and is stable
with any good quality capacitor, including ceramic (MLCC)
types for space-restricted applications. The dropout voltage of the
ADP3342 is only 190 mV (typical) at 300 mA. This device also
includes a safety current limit, thermal overload protection, and
a shutdown control pin.
Figure 1. Typical Application Circuit
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
(VCC = 3.0 V, VIN = 1.8 V, CIN = COUT = 1 F, TA = 0؇C to 100؇C, and
ADP3342–SPECIFICATIONS1, 2 TA = –40؇C to +100؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT
Voltage Accuracy
VOUT
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
IL = 0.1 mA to 300 mA
TA = 25∞C
–4.0
+4.0
%
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
IL = 0.1 mA to 300 mA
TA = –40∞C to +100∞C
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
TA = 25∞C
IL = 0.1 mA to 300 mA
TA = 25∞C
VOUT = 98% of VOUTNOM
IL = 300 mA
–5.0
+5.0
%
Line Regulation
Load Regulation
Dropout Voltage
0.04
0.12
mV/V
mV/mA
VDROP
190
125
70
450
mV
mV
mV
IL = 200 mA
IL = 100 mA
Current Limiting
Output Noise
ILIM
VNOISE
VCC = 3 V, VIN = 1.8 V
f = 10 Hz–100 kHz, CL = 1 mF
IL = 300 mA
450
60
mA
mV rms
OPERATING CURRENTS
Ground Current in Regulation
IGND
IL = 300 mA, TA = –40∞C to +100∞C
IL = 300 mA, TA = 0∞C to 100∞C
IL = 300 mA, TA = 25∞C
IL = 200 mA
IL = 0.1 mA
IL = 300 mA
3.0
3.0
3.0
2.0
100
100
0.01
8.5
6.0
4.0
mA
mA
mA
mA
mA
175
170
2
VCC Current in Regulation
Ground Current in Shutdown
IVCC
IGNDSD
mA
SD = 0 V, VCC = 6 V, VIN = 1.8 V
mA
SHUTDOWN
Threshold Voltage
VTHSD
ON
VCC – 0.9
V
OFF
0 £ SD £ 6 V
TA = 25∞C, VCC = 6 V, VIN = 6 V
TA = 100∞C, VCC = 6 V, VIN = 6 V
0.6
7
1
V
SD Input Current
Output Current in Shutdown
ISD
IOSD
1.4
0.01
0.01
mA
mA
mA
2
PWRGD
Output Current
Output Low Voltage
Output High Voltage
On-Time Delay
IPWRGDL
VPWRGDL
VPWRGD = 1.2 V, VCC = 3.0 V
IPWRGD = 300 mA
0.85
1.5
mA
V
V
3
0.4
300
300
1
3
VPWRGDH
IPWRGD = 300 mA
VCC – 0.4
5
TD14
IL = 3 mA to 300 mA,
ms
C
OUT = 1 mF to 10 mF
TD25
TD36
IL = 3 mA to 300 mA,
COUT = 1 mF to 10 mF
IL = 3 mA to 300 mA,
COUT = 1 mF to 10 mF
50
ms
ms
Off-Time Delay
0.05
THERMAL PROTECTION
Shutdown Temperature
THPROT
IL = 100 mA
165
∞C
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2Ambient temperature of 100∞C corresponds to a junction temperature of 125∞C under typical full load test conditions.
3VPWRGDL, VPWRGDH: Power good output voltages. Guaranteed by design and characterization.
4TD1: Delay time from VOUT crossing 1 V to PWRGD high. Guaranteed by design.
5TD2: Delay time from SD high to PWRGD high. Guaranteed by design.
6TD3: Delay time between SD low to PWRGD low. Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. C
ADP3342
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +13 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +13 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . –40°C to +100°C
Operating Junction Temperature Range . . . –40°C to +150°C
NC
1
2
3
4
8
7
6
5
NC
IN
ADP3342
OUT
TOP VIEW
VCC
GND
(Not to Scale)
SD
PWRGD
JA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 205°C/W
JA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W
NC = NO CONNECT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
JC
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.
ORDERING GUIDE
Model
Output Voltage
Package Option
Branding
Temperature Range
ADP3342JRM-REEL
ADP3342JRM-REEL7
ADP3342JRMZ-REEL7* 1.2 V
1.2 V
1.2 V
RM-8 (MSOP-8)
RM-8 (MSOP-8)
RM-8 (MSOP-8)
LJA
LJA
LJA
0°C to 100°C
0°C to 100°C
0°C to 100°C
*Z = Pb-free part.
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
No Connection.
1, 8
2
NC
OUT
Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be
connected together for proper operation.
3
4
5
6
VCC
Supply Voltage.
GND
PWRGD
SD
Ground Pin.
Power Good. Used to indicate that output is in regulation.
Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown
is not used, this pin should be connected to the VCC pin.
7
IN
Regulator Input. All pins.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3342 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
–3–
ADP3342–Typical Performance Characteristics
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.23
1.22
1.21
1.20
1.19
1.18
1.17
120
110
100
90
V
V
= 1.8V
IN
V
= 1.2V
V
= 1.2V
= 3V
OUT
OUT
= 3.0V
CC
V
= 3V
V
CC
CC
I
= 0A
L
I
= 0mA
L
I
= 100mA
L
80
I
I
= 200mA
= 300mA
L
70
L
60
50
1.7
2.7
3.7
4.7
5.7
1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
INPUT VOLTAGE – V
0
50
100
150
200
250
300
INPUTVOLTAGE –V
OUTPUT LOAD – mA
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
TPC 2. Output Voltage vs.
Load Current
TPC 3. Ground Current vs.
Supply Voltage
3.5
3.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
0
V
= 1.8V
= 3.0V
V
V
IN
= 3.0V
= 1.8V
IN
CC
V
CC
200mA
2.5
I
I
= 300mA
= 200mA
= 100mA
L
2.0
1.5
1.0
L
300mA
I
–0.1
–0.2
–0.3
–0.4
L
0.5
0
I
= 0mA
L
0
50
100
150
200
250
300
–50 –25
0
25
50
75 100 125 150
–40 –20
0
20
40
60
80
100
OUTPUT LOAD – mA
JUNCTIONTEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
TPC 4. Ground Current vs.
Load Current
TPC 5. Output Voltage Variation
vs. Junction Temperature
TPC 6. Ground Current vs.
Junction Temperature
0.25
0.20
0.15
0.10
7.0
V
= 3.0V
= 1.8V
CC
6.5
6.0
5.5
6
5
V
IN
V
= 1.2V
OUT
SD = V
R
IN
= 4⍀
4
3
2
1
0
L
5.0
4.5
4.0
3.5
MAX
TYP
MIN
3.0
2.5
2.0
0.05
0
–1
–2
1.5
1.0
0
200
400
600
800
1000
TIME – s
0
50
100
150
200
250
300
–40 –25 –10
5
20 35 50 65 80 950
OUTPUT LOAD – mA
TEMPERATURE – ؇C
TPC 9. Power-Up/Power-Down
TPC 8. Ground Current @ 300 mA
Load vs. Ambient Temperature
TPC 7. Dropout Voltage vs.
Output Current
–4–
REV. C
ADP3342
0
V
C
R
= 3V
= 1F
= 4⍀
V
C
R
= 3V
= 10F
= 4⍀
CC
CC
1.3
1.2
1.1
L
L
L
L
1.32
1.22
1.12
3.00
1.80
1.32
1.22
1.12
3.00
1.80
V
= 3V
= 1.8V
= 1F
CC
V
IN
C
L
400
200
5
0
40
80
120
160
200
0
40
80
120
160
200
0
400
800
1200
1600
2000
TIME – s
TIME – s
TIME – s
TPC 10. Line Transient Response
TPC 11. Line Transient Response
TPC 12. Load Transient Response
0
V
= 1.8V
IN
V
R
= 3V
= 4⍀
= 1.8V
CC
1.2
0
1.3
1.2
2.0
1.0
0
L
V
IN
V
= 3V
= 1.8V
= 10F
CC
1.1
V
IN
C
L
3.0
0
1.0
0.5
0
400
200
5
1.8
0
0
200
400
600
800
1000
0
400
800
1200
1600
2000
–200
200
600
1000
1400
1800
TIME – s
TIME – s
TIME – s
TPC 14. Short Circuit Current
TPC 13. Load Transient Response
TPC 15. Power-On/Power-Off
Response from Shutdown
2.0
1.0
2.0
V
= 1.8V
IN
2.0
SD = 3.0V
R
1.0
0
V
= 3V
= 1.8V
= 4⍀
= 4⍀
CC
L
1.0
0
0
V
IN
R
V
= 3V
= 1.8V
L
CC
V
IN
R
= 4⍀
L
3.0
0
3.0
0
1.8
0
1.8
0
3.0
0
0
100
200
300
400
500
200
600
1000
1400
1800
2
6
10
14
18
TIME – s
TIME – s
TIME – s
TPC 16. Turn On Delay
TPC 18. Power-On/Power-Off
Response from VCC
TPC 17. Turn Off Delay
REV. C
–5–
ADP3342
–20
–30
–40
–50
–60
–70
–80
–90
70
60
V
= 1.2V
OUT
C
= 10F
= 300mA
L
I
L
1.2
0
C
= 1F
= 300mA
L
V
= 1.8V
IN
SD = 3.0V
= 4⍀
I
L
50
40
30
20
C
= 1F
= 50A
R
L
L
I
L
3.0
0
300mA
0mA
1.8
0
C
= 10F
= 50A
L
I
L
10
0
0
200
400
600
800
1000
TIME – s
10
100
1k
10k
100k
1M
10M
0
10
20
C
30
– F
40
50
FREQUENCY – Hz
L
TPC 20. Power Supply
Ripple Rejection
TPC 19. Power-On/Power-Off
Response from VIN
TPC 21. RMS Noise vs. CL
(10 Hz to 100 Hz)
1.25
1.23
1.21
1.19
1.17
1.15
100
10
650
600
550
500
V
= 1.2V
= 1mA
OUT
I
L
0mA
50mA
C
= 10F
L
1
C
= 1F
L
100mA
200mA
0.1
300mA
0.01
0.001
35
55
75
95 115 135 155 175
10
100
1k
10k
100k
1M
1.5
1.6
1.7
V
1.8
– V
1.9
2.0
AMBIENT TEMPERATURE – ؇C
FREQUENCY – Hz
IN
TPC 23. Thermal Protection
TPC 22. Output Noise Density
TPC 24. Current Limit vs. VIN
3.6
3.0
V
= 1.8V
IN
SD = 3V
400
200
0
5
15
25
35
45
TIME – ms
TPC 25. Current Limiting from VC
–6–
REV. C
ADP3342
THEORY OF OPERATION
APPLICATION INFORMATION
PC Application—VCCVID
The anyCAP LDO ADP3342 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
The ADP3342 has been optimized for PC applications that
require a 1.2 V output for powering the voltage identification
rail, VCCVID. The rail from which the output draws current,
the IN pin, is separated from the rail that powers the IC, the
VCC pin. This allows a higher efficiency design when, as
recommended for IMVP-3/5 applications, the VCC pin is
connected to a 3.3 V supply to power the IC adequately, and
the IN pin is connected to a 1.8 V supply. The efficiency is
nearly 60% in this case.
VCC
INPUT
Q1
OUTPUT
COMPENSATION
CAPACITOR
ATTENUATION
/V
R1
(a)
(V
)
BAND GAP OUT
C
R
LOAD
D1
R3
PTAT
V
NONINVERTING
WIDEBAND
DRIVER
OS
g
m
PTAT
Capacitor Selection
LOAD
CURRENT
R4
R2
As with any voltage regulator, output transient response is a func-
tion of the output capacitance. The ADP3342 is stable with a wide
range of capacitor values, types, and ESR (anyCAP). A capacitor
as low as 1 µF is all that is needed for stability; larger capacitors
can be used if high output current surges are anticipated. The
ADP3342 is stable with extremely low ESR capacitors (ESR ª 0),
such as multilayer ceramic capacitors (MLCC) or OSCON. Note
that the effective capacitance of some capacitor types may fall
below the minimum at cold temperature. Ensure that the capacitor
provides more than 1 µF at minimum temperature.
ADP3342
GND
Figure 2. Control Loop Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it pro-
duces a large, temperature proportional input offset voltage that is
repeatable and very well controlled. The temperature proportional
offset voltage is combined with the complementary diode voltage to
form a virtual band gap voltage, implicit in the network, although it
never appears explicitly in the circuit. Ultimately, this patented
design makes it possible to control the loop with only one ampli-
fier. This technique also improves the noise characteristics of the
amplifier by providing more flexibility on the trade-off of noise
sources that lead to a low noise design.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advis-
able in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit’s sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider so that the error resulting from base cur-
rent loading in conventional circuits is avoided.
Power Good Monitoring Function
The PWRGD pin does not monitor the output voltage directly
but rather detects whether the internal PNP pass transistor is
being modulated by the regulation loop. This means of detecting
PWRGD, rather than using a voltage threshold detection, provides
an inherent and desirable delay in asserting the PWRGD sig-
nal. During startup or overload, the regulation loop is not in
control, so the PWRGD pin is low.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin, or tying it
to the input pin, will turn the output on. Pulling SD down to 0.4 V
or below, or tying it to ground, will turn the output off. In shut-
down mode, quiescent current is reduced.
Most LDOs place very strict requirements on the range of
ESR values for the output capacitor because they are difficult
to stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value, required to keep conventional
LDOs stable, changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
Thermal Overload Protection
The ADP3342 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C. Under
extreme conditions (i.e., high ambient temperature and power
dissipation) where die temperature starts to rise above 165°C, the
output current is reduced until the die temperature has dropped
to a safe level. The output current is restored when the die tem-
perature is reduced.
With the ADP3342 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the out-
put. Additional advantages of the pole splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. Additional features
of the circuit include current limit, thermal shutdown, and
noise reduction.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be limited by operating
conditions so that junction temperatures will not exceed 150°C.
REV. C
–7–
ADP3342
Calculating Junction Temperature
Device power dissipation is calculated as follows:
Assuming ILOAD = 300 mA, IGND = 4 mA, VIN = 1.8 V, and VOUT
1.2 V, device power dissipation is
=
P = 1.8 V – 1.2 V ¥ 300 mA + 1.8 V ¥ 4 mA = 187 mW
(
)
(
)
D
PD = V – VOUT ¥ I
+VIN ¥ IGND
(
)
IN
LOAD
The ADP3342 is capable of supplying 300 mA @ VIN = 1.8 V
in a typical notebook PC application. If a higher input voltage
is used (such as 3.3 V), the power dissipation of the ADP3342
will be limited by the thermal overload protection. Assuming a
4-layer board, the junction temperature rise above ambient
temperature will be approximately equal to
where ILOAD and IGND are load current and ground current, and
IN and VOUT are input and output voltages, respectively.
V
DTJA = 193 mW ¥ 142∞C / W = 27.4∞C
–8–
REV. C
ADP3342
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8؇
0؇
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
REV. C
–9–
ADP3342
Revision History
Location
Page
11/04—Data Sheet Changed from REV. B to REV. C.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3/03—Data Sheet Changed from REV. A to REV. B.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PC Application—VCCVID section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Deleted Paddle under Lead Package section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
10/02—Data Sheet Changed from REV. 0 to REV. A.
Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–10–
REV. C
–11–
–12–
相关型号：
ADP3367AR-REEL
+5 V Fixed, Adjustable Low-Dropout Linear Voltage Regulator Package: 8 ld SOIC; No of Pins: 8; Temperature Range: Industrial; Container: 2500/Reel
ADI
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