ADUC7128_15_技术文档

Octal, 14-Bit, 50 MSPS,

Serial LVDS, 1.8 V ADC

Data Sheet

AD9252

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

PDWN

DRVDD

DRGND

8 analog-to-digital converters (ADCs) integrated into 1 package

93.5 mW ADC power per channel at 50 MSPS

SNR = 73 dB (to Nyquist)

ENOB = 12 bits

SFDR = 84 dBc (to Nyquist)

AD9252

14

VIN + A

VIN – A

D + A

D – A

SERIAL

LVDS

ADC

14

VIN + B

VIN – B

D + B

D – B

SERIAL

LVDS

Excellent linearity

DNL = 0.4 LSB (typical); INL = 1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

325 MHz, full-power analog bandwidth

2 V p-p input voltage range

VIN + C

VIN – C

D + C

D – C

SERIAL

LVDS

ADC

14

VIN + D

VIN – D

D + D

D – D

SERIAL

LVDS

ADC

VIN + E

VIN – E

SERIAL

LVDS

D + E

D – E

1.8 V supply operation

Serial port control

14

VIN + F

VIN – F

D + F

D – F

SERIAL

LVDS

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

VIN + G

VIN – G

D + G

D – G

SERIAL

LVDS

ADC

14

VIN + H

VIN – H

D + H

D – H

SERIAL

LVDS

VREF

FCO+

FCO–

SENSE

APPLICATIONS

0.5V

DATA RATE

MULTIPLIER

REFT

REFB

REF

SELECT

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

SERIAL PORT

INTERFACE

DCO+

DCO–

SCLK/

DTP

RBIAS AGND CSB SDIO/

ODM

CLK+

CLK–

Tape drives

Figure 1.

Optical networking

Test equipment

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

GENERAL DESCRIPTION

The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip

sample-and-hold circuit designed for low cost, low power, small size,

and ease of use. Operating at a conversion rate of up to 50 MSPS,

it is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is

specified over the industrial temperature range of −40°C to +85°C.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small package.

2. Low Power of 93.5 mW per Channel at 50 MSPS.

3. Ease of Use. A data clock output (DCO) operates up to

350 MHz and supports double data rate (DDR) operation.

4. User Flexibility. SPI control offers a wide range of flexible

features to meet specific system requirements.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock (DCO)

for capturing data on the output and a frame clock (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

5. Pin-Compatible Family. This includes the AD9212 (10-bit)

and AD9222 (12-bit).

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9252* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

TOOLS AND SIMULATIONS

• Visual Analog

• AD9252 IBIS Models

EVALUATION KITS

REFERENCE MATERIALS

• AD9252 Evaluation Board

Customer Case Studies

DOCUMENTATION

Application Notes

• National Instruments Case Study

Technical Articles

• AN-282: Fundamentals of Sampled Data Systems

• AN-345: Grounding for Low-and-High-Frequency Circuits

• MS-2210: Designing Power Supplies for High Speed ADC

DESIGN RESOURCES

• AD9252 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

• AN-501: Aperture Uncertainty and ADC System

Performance

• AN-715: A First Approach to IBIS Models: What They Are

and How They Are Generated

• AN-737: How ADIsimADC Models an ADC

• AN-741: Little Known Characteristics of Phase Noise

• AN-742: Frequency Domain Response of Switched-

Capacitor ADCs

DISCUSSIONS

View all AD9252 EngineerZone Discussions.

• AN-756: Sampled Systems and the Effects of Clock Phase

Noise and Jitter

SAMPLE AND BUY

• AN-812: MicroController-Based Serial Port Interface (SPI)

Visit the product page to see pricing options.

Boot Circuit

• AN-827: A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs

TECHNICAL SUPPORT

• AN-835: Understanding High Speed ADC Testing and

Evaluation

Submit a technical question or find your regional support

number.

• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

• AN-935: Designing an ADC Transformer-Coupled Front

End

Data Sheet

• AD9252: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC

Data Sheet

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AD9252

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Clock Input Considerations...................................................... 19

Serial Port Interface (SPI).............................................................. 27

Hardware Interface..................................................................... 27

Memory Map .................................................................................. 29

Reading the Memory Map Table.............................................. 29

Reserved Locations .................................................................... 29

Default Values............................................................................. 29

Logic Levels................................................................................. 29

Applications Information .............................................................. 32

Design Guidelines ...................................................................... 32

Evaluation Board ............................................................................ 33

Power Supplies............................................................................ 33

Input Signals................................................................................ 33

Output Signals ............................................................................ 33

Default Operation and Jumper Selection Settings................. 34

Alternative Analog Input Drive Configuration...................... 35

Outline Dimensions....................................................................... 52

Ordering Guide .......................................................................... 52

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits ......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 17

Analog Input Considerations.................................................... 17

REVISION HISTORY

12/11—Rev. D to Rev. E

Changes to Digital Outputs and Timing Section....................... 24

Added Table 10 ............................................................................... 24

Changes to Table 11 and Table 12 ................................................ 24

Changes to RBIAS Pin Section ..................................................... 25

Deleted Figure 51 to Figure 52...................................................... 25

Moved Figure 53............................................................................. 25

Changes to Serial Port Interface (SPI) Section........................... 27

Changes to Table 15 ....................................................................... 28

Changes to Reading the Memory Map Table Section ............... 29

Added Applications Information and

Changes to Output Signals Section and Figure 58..................... 33

Change to Default Operation and Jumper Selection Settings

Section.............................................................................................. 34

Added Endnote 2 in Ordering Guide .......................................... 52

4/10—Rev. C to Rev. D

Changes to Address 16 in Table 16............................................... 31

Updated Outline Dimensions....................................................... 52

Changes to Ordering Guide .......................................................... 52

Design Guidelines Sections...................................................... 32

Changes to Input Signals Section................................................. 33

Changes to Output Signals Section.............................................. 33

Changes to Figure 60...................................................................... 33

Changes to Default Operation and Jumper Selection

12/09—Rev. B to Rev. C

Updated Outline Dimensions....................................................... 52

Changes to Ordering Guide .......................................................... 52

7/09—Rev. A to Rev. B

Settings Section.......................................................................... 34

Changes to Alternative Analog Input Drive

Changes to Figure 5........................................................................ 10

Changes to Figure 38 and Figure 39............................................. 18

Changes to Figure 51 and Figure 52............................................. 25

Updated Outline Dimensions....................................................... 52

Configuration Section............................................................... 35

Added Figure 62 and Figure 63 .................................................... 35

Changes to Figure 68...................................................................... 42

Changes to Table 17 ....................................................................... 48

Updated Outline Dimensions....................................................... 52

Changes to Ordering Guide.......................................................... 52

12/07—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Crosstalk Parameter..................................................... 3

Changes to Figure 2 to Figure 4...................................................... 7

Changes to Table 9 Endnote.......................................................... 23

10/06—Revision 0: Initial Version

Rev. E | Page 2 of 52

Data Sheet

AD9252

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9252-50

Typ

Parameter¹

Temperature

Min

Max

Unit

RESOLUTION

14

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Gain Error

Reference Voltage (1 V Mode)

REFERENCE

Full

Guaranteed

±1

±3

±1.5

±0.3

±±

±2.5

±0.7

±1

mV

% FS

LSB

±0.4

±1.5

±4

Full

±2

±17

±21

ppm/°C

Output Voltage Error (VREF = 1 V)

Load Regulation @ 1.0 mA (VREF = 1 V)

Input Resistance

Full

±2

3

6

±30

mV

kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Common-Mode Voltage

Differential Input Capacitance

Analog Bandwidth, Full Power

POWER SUPPLY

Full

2

V p-p

V

pF

AVDD/2

7

325

MHz

AVDD

DRVDD

IAVDD

IDRVDD

Full

1.7

1.±

360

55.5

74±

2

1.9

373.4

5±

773

11

V

mA

mW

Total Power Dissipation (Including Output Drivers)

Power-Down Dissipation

Standby Dissipation²

CROSSTALK

±9

AIN = −0.5 dBFS

Overrange³

Full

−90

dB

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²Can be controlled via the SPI.

³Overrange condition is specific with 6 dB of the full-scale input range.

Rev. E | Page 3 of 52

AD9252

Data Sheet

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9252-50

Typ

Parameter¹

Temperature Min

Max

Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

f_IN= 35 MHz

f_IN= 70 MHz

Full

73.2

73

72.7

71

dB

Full

71

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

f_IN= 35 MHz

f_IN= 70 MHz

Full

72.5

72.2

72

dB

70.2

11.5

73

70.5

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

f_IN= 35 MHz

Full

11.±7

11.±4

11.79

11.5

Bits

f_IN= 70 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

f_IN= 35 MHz

Full

±5

±4

±3

79

dBc

f_IN= 70 MHz

WORST HARMONIC (SECOND OR THIRD)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

f_IN= 35 MHz

f_IN= 70 MHz

Full

−±5

−±4

−±3

−79

dBc

−73

−±0

WORST OTHER (EXCLUDING SECOND OR THIRD)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

f_IN= 35 MHz

Full

−90

−±9

dBc

f_IN= 70 MHz

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS

f_IN1= 15 MHz, f_IN2= 16 MHz

f_IN1= 70 MHz, f_IN2= 71 MHz

25°C

±0.0

dBc

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. E | Page 4 of 52

Data Sheet

AD9252

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9252-50

Typ

Parameter¹

Temperature Min

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

250

1.2

mV p-p

V

kΩ

pF

1.2

20

1.5

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

Full

25°C

3.6

0.3

V

kΩ

pF

30

0.5

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

3.6

0.3

V

Input Resistance

Input Capacitance

25°C

70

0.5

kΩ

pF

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

DRVDD + 0.3

0.3

V

Input Resistance

Input Capacitance

25°C

30

2

kΩ

pF

LOGIC OUTPUT (SDIO/ODM)³

Logic 1 Voltage (I_OH= ±00 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)

Logic Compliance

Full

1.79

V

0.05

LVDS

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

247

1.125

454

1.375

mV

V

Offset binary

LVDS

DIGITAL OUTPUTS (D + x, D − x),

(LOW POWER, REDUCED SIGNAL OPTION)

Logic Compliance

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

150

1.10

250

1.30

mV

V

Offset binary

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²This is specified for LVDS and LVPECL only.

³This is specified for 13 SDIO pins sharing the same connection.

Rev. E | Page 5 of 52

AD9252

Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9252-50

Typ

Parameter¹

Temp

Min

Max

Unit

CLOCK²

Maximum Clock Rate

Minimum Clock Rate

Clock Pulse Width High (t_EH)

Clock Pulse Width Low (t_EL)

OUTPUT PARAMETERS^{2, 3}

Propagation Delay (t_PD)

Rise Time (t_R) (20% to ±0%)

Fall Time (t_F) (20% to ±0%)

FCO Propagation Delay (t_FCO

Full

50

MSPS

ns

10

10.0

ns

Full

25°C

Full

1.5

2.3

300

2.3

3.1

ns

ps

ns

ps

)

4

DCO Propagation Delay (t_CPD

t_FCO+ (t_SAMPLE/2±)

4

DCO to Data Delay (t_DATA

)

(t_SAMPLE/2±) − 300

(t_SAMPLE/2±)

±50

600

375

(t_SAMPLE/2±) + 300

±200

4

DCO to FCO Delay (t_FRAME

)

Data-to-Data Skew (t_DATA-MAX− t_DATA-MIN

Wake-Up Time (Standby)

Wake-Up Time (Power-Down)

Pipeline Latency

)

ns

μs

±

CLK cycles

APERTURE

Aperture Delay (t_A)

Aperture Uncertainty (Jitter)

Out-of-Range Recovery Time

25°C

750

<1

1

ps

ps rms

CLK cycles

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²Can be adjusted via the SPI.

³Measurements were made using a part soldered to FR-4 material.

⁴t_SAMPLE/2± is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. E | Page 6 of 52

Data Sheet

AD9252

TIMING DIAGRAMS

N – 1

VIN ± x

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D – x

D + x

MSB

N – 9

D12

D11

D10

D9

D8

D7

D6

N – 9

D5

N – 9

D4

N – 9

D3

N – 9

D2

N – 9

D1

N – 9

D0

N – 9

MSB

N – 8

D12

N – 8

N – 9 N – 9 N – 9 N – 9 N – 9 N – 9

Figure 2. 14-Bit Data Serial Stream (Default), MSB First

N – 1

VIN ± x

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D – x

D + x

MSB

N – 9

D10

N – 9

D9

N – 9

D8

N – 9

D7

N – 9

D6

N – 9

D5

N – 9

D4

N – 9

D3

N – 9

D2

N – 9

D1

N – 9

D0

N – 9

MSB

N – 8

D10

N – 8

Figure 3. 12-Bit Data Serial Stream, MSB First

Rev. E | Page 7 of 52

AD9252

Data Sheet

N – 1

VIN ± x

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D – x

D + x

LSB

N – 9

D0

D1

D2

D3

D4

D5

D6

N – 9

D7

N – 9

D8

N – 9

D9

N – 9

D10

N – 9

D11

N – 9

D12

N – 9

LSB

N – 8

D0

N – 8

N – 9 N – 9 N – 9 N – 9 N – 9 N – 9

Figure 4. 14-Bit Data Serial Stream, LSB First

Rev. E | Page 8 of 52

Data Sheet

AD9252

ABSOLUTE MAXIMUM RATINGS

Table 5.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/s)

With

Respect To

1

Parameter

ELECTRICAL

AVDD

DRVDD

AGND

Rating

θ_JA

θ_JB

θ_JC

0.6

Unit

°C/W

0.0

1.0

2.5

17.7

15.5

13.9

AGND

−0.3 V to +2.0 V

−0.3 V to +0.3 V

−2.0 V to +2.0 V

−0.3 V to +2.0 V

±.7

DRGND

DRVDD

DRGND

¹θ_JAfor a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

AVDD

Digital Outputs

(D + x, D − x, DCO+,

DCO−, FCO+, FCO−)

ESD CAUTION

CLK+, CLK−

VIN + x, VIN − x

SDIO/ODM

PDWN, SCLK/DTP, CSB

REFT, REFB, RBIAS

VREF, SENSE

AGND

−0.3 V to +3.9 V

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

Storage Temperature

Range (Ambient)

Maximum Junction

Temperature

−40°C to +±5°C

−65°C to +150°C

150°C

Lead Temperature

(Soldering, 10 sec)

300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. E | Page 9 of 52

AD9252

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AVDD

VIN + G

VIN – G

AVDD

VIN – H

VIN + H

AVDD

1

2

3

4

5

6

7

8

9

48 AVDD

47 VIN + B

46 VIN – B

45 AVDD

44 VIN – A

43 VIN + A

42 AVDD

41 PDWN

40 CSB

39 SDIO/ODM

38 SCLK/DTP

37 AVDD

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

AD9252

TOP VIEW

(Not to Scale)

AVDD

CLK–

CLK+ 10

AVDD 11

AVDD 12

DRGND 13

DRVDD 14

D – H 15

36 DRGND

35 DRVDD

34 D + A

D + H 16

33 D – A

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND

Figure 5. 64-Lead LFCSP Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

0

AGND

AVDD

Analog Ground (Exposed Paddle)

1.8 V Analog Supply

1, 4, 7, 8, 11,

12, 37, 42, 45,

48, 51, 59, 62

13, 36

14, 35

2

3

5

DRGND

DRVDD

VIN + G

VIN − G

VIN − H

VIN + H

CLK−

Digital Output Driver Ground

1.8 V Digital Output Driver Supply

ADC G Analog Input True

ADC G Analog Input Complement

ADC H Analog Input Complement

ADC H Analog Input True

6

9

Input Clock Complement

10

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

CLK+

Input Clock True

ADC H Digital Output Complement

ADC H Digital Output True

ADC G Digital Output Complement

ADC G Digital Output True

ADC F Digital Output Complement

ADC F Digital Output True

D − H

D + H

D − G

D + G

D − F

D + F

D − E

D + E

DCO−

DCO+

FCO−

FCO+

D − D

D + D

D − C

ADC E Digital Output Complement

ADC E Digital Output True

Data Clock Digital Output Complement

Data Clock Digital Output True

Frame Clock Digital Output Complement

Frame Clock Digital Output True

ADC D Digital Output Complement

ADC D Digital Output True

ADC C Digital Output Complement

ADC C Digital Output True

ADC B Digital Output Complement

D + C

D − B

Rev. E | Page 10 of 52

Data Sheet

AD9252

Pin No.

32

33

34

3±

39

40

41

43

44

46

47

49

50

52

53

54

55

56

57

5±

60

61

63

64

Mnemonic

D + B

D − A

Description

ADC B Digital Output True

ADC A Digital Output Complement

ADC A Digital Output True

Serial Clock/Digital Test Pattern

Serial Data Input-Output/Output Driver Mode

Chip Select Bar

Power-Down

ADC A Analog Input True

ADC A Analog Input Complement

ADC B Analog Input Complement

ADC B Analog Input True

D + A

SCLK/DTP

SDIO/ODM

CSB

PDWN

VIN + A

VIN − A

VIN − B

VIN + B

VIN + C

VIN − C

VIN − D

VIN + D

RBIAS

SENSE

VREF

REFB

REFT

VIN + E

VIN − E

VIN − F

VIN + F

ADC C Analog Input True

ADC C Analog Input Complement

ADC D Analog Input Complement

ADC D Analog Input True

External Resistor to Set the Internal ADC Core Bias Current

Reference Mode Selection

Voltage Reference Input/Output

Negative Differential Reference

Positive Differential Reference

ADC E Analog Input True

ADC E Analog Input Complement

ADC F Analog Input Complement

ADC F Analog Input True

Rev. E | Page 11 of 52

AD9252

Data Sheet

EQUIVALENT CIRCUITS

DRVDD

V

D – x

D + x

VIN ± x

V

DRGND

Figure 9. Equivalent Digital Output Circuit

Figure 6. Equivalent Analog Input Circuit

10Ω

CLK+

10kΩ

1.25V

1kΩ

SCLK/DTP OR PDWN

10Ω

CLK–

30kΩ

Figure 7. Equivalent Clock Input Circuit

Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit

100Ω

RBIAS

350Ω

SDIO/ODM

30kΩ

Figure 11. Equivalent RBIAS Circuit

Figure 8. Equivalent SDIO/ODM Input Circuit

Rev. E | Page 12 of 52

Data Sheet

AD9252

AVDD

70kΩ

1kΩ

CSB

VREF

6kΩ

Figure 12. Equivalent CSB Input Circuit

Figure 14. Equivalent VREF Circuit

1kΩ

SENSE

Figure 13. Equivalent SENSE Circuit

Rev. E | Page 13 of 52

AD9252

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

AIN = –0.5dBFS

SNR = 71.16dB

ENOB = 11.53 BITS

SFDR = 72.92dBc

SNR = 73.71dB

ENOB = 11.95 BITS

SFDR = 85.86dBc

–20

–40

–60

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 15. Single-Tone 32k FFT with f_IN= 2.3 MHz, f_SAMPLE= 50 MSPS

Figure 18. Single-Tone 32k FFT with f_IN= 120 MHz, f_SAMPLE= 50 MSPS

90

0

AIN = –0.5dBFS

SFDR

SNR = 72.98dB

ENOB = 11.83 BITS

SFDR = 83.8dBc

85

80

–20

–40

–60

75

SNR

70

65

60

–80

–100

–120

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

ENCODE RATE (MSPS)

FREQUENCY (MHz)

Figure 16. Single-Tone 32k FFT with f_IN= 35 MHz, f_SAMPLE= 50 MSPS

Figure 19. SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz, AD9252-50

0

90

AIN = –0.5dBFS

SNR = 72.36dB

ENOB = 11.73 BITS

SFDR = 86.21dBc

–20

85

80

75

70

65

60

SFDR

SNR

–40

–60

–80

–100

–120

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

ENCODE RATE (MSPS)

FREQUENCY (MHz)

Figure 17. Single-Tone 32k FFT with f_IN= 70 MHz, f_SAMPLE= 50 MSPS

Figure 20. SNR/SFDR vs. f_SAMPLE, f_IN= 19.7 MHz, AD9252-50

Rev. E | Page 14 of 52

Data Sheet

AD9252

90

80

70

60

50

40

30

20

10

0

–20

AIN1 AND AIN2 = –7dBFS

SFDR = 83.64dB

IMD2 = 95.57dBc

IMD3 = 84.26dBc

SFDR

–40

–60

80dB REFERENCE

–80

SNR

–100

–120

–60

–50

–40

–30

–20

–10

0

5

10

15

20

25

ANALOG INPUT LEVEL (dBFS)

FREQUENCY (MHz)

Figure 21. SNR/SFDR vs. Analog Input Level, f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

Figure 24. Two-Tone 32k FFT with f_IN1= 70 MHz and

f

_IN2= 71 MHz, f_SAMPLE= 50 MSPS

90

85

80

75

70

65

60

90

80

SFDR

70

60

50

SNR

80dB REFERENCE

40

SNR

30

20

10

1

10

100

1000

–60

–50

–40

–30

–20

–10

0

ANALOG INPUT FREQUENCY (MHz)

ANALOG INPUT LEVEL (dBFS)

Figure 25. SNR/SFDR vs. f_IN, f_SAMPLE= 50 MSPS

Figure 22. SNR/SFDR vs. Analog Input Level, f_IN= 19.7 MHz, f_SAMPLE= 50 MSPS

90

85

80

75

70

65

60

0

AIN1 AND AIN2 = –7dBFS

SFDR = 86.27dB

IMD2 = 97.82dBc

IMD3 = 86.13dBc

–20

SFDR

–40

–60

SINAD

–80

–100

–120

–40

–20

0

20

40

60

80

0

5

10

15

20

25

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 26. SINAD/SFDR vs. Temperature, f_IN= 19.7 MHz, f_SAMPLE= 50 MSPS

Figure 23. Two-Tone 32k FFT with f_IN1= 15 MHz and

_IN2= 16 MHz, f_SAMPLE= 50 MSPS

f

Rev. E | Page 15 of 52

AD9252

Data Sheet

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.047LSB rms

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

2000 4000 6000 8000 10000 12000 14000 16000

CODE

Figure 27. INL, f_IN= 2.3 MHz, f_SAMPLE= 50 MSPS

Figure 30. Input-Referred Noise Histogram, f_SAMPLE= 50 MSPS

1.0

0.8

0

NPR = 62.5dB

NOTCH = 18.0MHz

NOTCH WIDTH = 2.3MHz

–20

0.6

0.4

–40

–60

0.2

0

–0.2

–0.4

–0.6

–0.8

–80

–100

–120

–1.0

0

5

10

15

20

25

2000 4000 6000 8000 10000 12000 14000 16000

CODE

FREQUENCY (MHz)

Figure 28. DNL, f_IN= 2.3 MHz, f_SAMPLE= 50 MSPS

Figure 31. Noise Power Ratio (NPR), f_SAMPLE= 50 MSPS

–30

–35

–40

–45

–50

–55

–60

–65

0

–1

–3dB BANDWIDTH = 325MHz

–2

–3

–4

–5

–6

–7

–8

–9

–10

–11

–70

0

5

10

15

20

25

30

35

40

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 29. CMRR vs. Frequency, f_SAMPLE= 50 MSPS

Figure 32. Full-Power Bandwidth vs. Frequency, f_SAMPLE= 50 MSPS

Rev. E | Page 16 of 52

Data Sheet

AD9252

THEORY OF OPERATION

The AD9252 architecture consists of a pipelined ADC divided

into three sections: a 4-bit first stage followed by eight 1.5-bit

stages and a 3-bit flash. Each stage provides sufficient overlap

to correct for flash errors in the preceding stage. The quantized

outputs from each stage are combined into a final 14-bit result

in the digital correction logic. The pipelined architecture permits

the first stage to operate with a new input sample while the

remaining stages operate with preceding samples. Sampling

occurs on the rising edge of the clock.

front end at high IF frequencies. Either a shunt capacitor or two

single-ended capacitors can be placed on the inputs to provide a

matching passive network. This ultimately creates a low-pass

filter at the input to limit unwanted broadband noise. See the

AN-742 Application Note, Frequency Domain Response of

Switched-Capacitor ADCs; the AN-827 Application Note, A

Resonant Approach to Interfacing Amplifiers to Switched-Capacitor

ADCs; and the Analog Dialogue article “Transformer-Coupled

Front-End for Wideband A/D Converters” (Volume 39, April 2005)

for more information. In general, the precise values depend on

the application.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The analog inputs of the AD9252 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide

this bias externally. Setting the device so that V

_CM= AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 34 and Figure 35.

90

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and data clocks.

SFDR (dBc)

85

ANALOG INPUT CONSIDERATIONS

80

75

The analog input to the AD9252 is a differential switched-

capacitor circuit designed for processing differential input signals.

This circuit can support a wide common-mode range while

maintaining excellent performance. An input common-mode

voltage of midsupply minimizes signal-dependent errors and

provides optimum performance.

SNR (dB)

70

65

60

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

H

ANALOG INPUT COMMON-MODE VOLTAGE (V)

C_PAR

Figure 34. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 2.3 MHz, f_SAMPLE= 50 MSPS

H

VIN + x

C_SAMPLE

90

85

80

75

70

65

60

S

C_SAMPLE

SFDR (dBc)

SNR (dB)

VIN – x

H

C_PAR

H

Figure 33. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 33). When the input

circuit is switched into sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each

input can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low-Q inductors

or ferrite beads can be placed on each leg of the input to reduce

high differential capacitance at the analog inputs and therefore

achieve the maximum bandwidth of the ADC. Such use of low-Q

inductors or ferrite beads is required when driving the converter

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

ANALOG INPUT COMMON-MODE VOLTAGE (V)

Figure 35. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 35 MHz, f_SAMPLE= 50 MSPS

Rev. E | Page 17 of 52

AD9252

Data Sheet

ADT1-1WT

1:1 Z RATIO

For best dynamic performance, the source impedances driving

VIN + x and VIN − x should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference buffer

creates the positive and negative reference voltages, REFT and

REFB, respectively, that define the span of the ADC core. The

output common mode of the reference buffer is set to midsupply,

and the REFT and REFB voltages and span are defined as

C

1

R

VIN + x

ADC

2Vp-p

49.9Ω

C

DIFF

AD9252

R

AVDD

1kΩ

VIN – x

AGND

C

1kΩ

0.1μF

1

C

IS OPTIONAL.

DIFF

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

Figure 36. Differential Transformer-Coupled Configuration

for Baseband Applications

ADT1-1WT

1:1 Z RATIO

2Vp-p

16nH

16nH 0.1μF

33Ω

It can be seen from these equations that the REFT and REFB

voltages are symmetrical about the midsupply voltage and, by

definition, the input span is twice the value of the VREF voltage.

VIN+x

65Ω

ADC

499Ω

16nH

2.2pF

1kΩ

AD9252

VIN–x

33Ω

AVDD

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9252, the largest input span available is 2 V p-p.

1kΩ

0.1μF

Differential Input Configurations

Figure 37. Differential Transformer-Coupled Configuration for IF Applications

There are several ways to drive the AD9252 either actively or

passively; however, optimum performance is achieved by driving

the analog input differentially. For example, using the AD8334

differential driver to drive the AD9252 provides excellent perfor-

mance and a flexible interface to the ADC (see Figure 39) for

baseband applications. This configuration is commonly used

for medical ultrasound systems.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-

sensitive applications. In this configuration, SFDR and distortion

performance degrade due to the large input common-mode swing.

If the application requires a single-ended input configuration,

ensure that the source impedances on each input are well matched

in order to achieve the best possible performance. A full-scale input

of 2 V p-p can still be applied to the ADC’s VIN + x pin while the

VIN − x pin is terminated. Figure 38 details a typical single-

ended input configuration.

For applications where SNR is a key parameter, differential

transformer coupling is the recommended input configuration

(see Figure 36 and Figure 37), because the noise performance of

most amplifiers is not adequate to achieve the true performance

of the AD9252.

AVDD

C

1kΩ

Regardless of the configuration, the value of the shunt capacitor,

C, is dependent on the input frequency and may need to be

reduced or removed.

R

VIN + x

0.1µF

AVDD

1kΩ

2V p-p

49.9Ω

ADC

AD9252

1

C

DIFF

1kΩ

25Ω

R

VIN – x

C

0.1µF

1kΩ

1

C

IS OPTIONAL.

DIFF

Figure 38. Single-Ended Input Configuration

0.1μF

LOP

VIP

0.1μF

187Ω

374Ω

R

VOH

VOL

0.1μF 120nH

INH

VIN + x

1V p-p

AD8334

1.0kΩ

22pF

LNA

ADC

AD9252

VGA

C

1.0kΩ

R

LMD

VIN – x

0.1μF

187Ω

0.1μF

AVDD

0.1μF

10μF

LON

VIN

1kΩ

274Ω

18nF

0.1μF

Figure 39. Differential Input Configuration Using the AD8334

Rev. E | Page 18 of 52

Data Sheet

AD9252

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 43). Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages of up to 3.3 V, making the

selection of the drive logic voltage very flexible.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9252 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional biasing.

Figure 40 shows the preferred method for clocking the AD9252.

The low jitter clock source is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9252 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9252, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLK+

CLK

CMOS DRIVER

CLK

OPTIONAL

100Ω

0.1µF

1

50Ω

CLK+

ADC

AD9252

0.1µF

CLK–

0.1µF

39kΩ

1

50Ω RESISTOR IS OPTIONAL.

®

Mini-Circuits

ADT1-1WT, 1:1Z

Figure 43. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

XFMR

CLK+

AD9510/AD9511/

AD9512/AD9513/

100Ω

ADC

AD9252

CLK–

50Ω

0.1µF

AD9514/AD9515

0.1µF

CLK+

CLK

SCHOTTKY

DIODES:

HSM2812

OPTIONAL

100Ω

0.1µF

1

50Ω

CLK+

CMOS DRIVER

CLK

ADC

AD9252

Figure 40. Transformer-Coupled Differential Clock

0.1µF

CLK–

Another option is to ac-couple a differential PECL signal to the

sample clock input pins as shown in Figure 41. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 family of clock

drivers offers excellent jitter performance.

1

50Ω RESISTOR IS OPTIONAL.

Figure 44. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9252 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9252. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See the Memory Map section for

more details on using this feature.

0.1µF

CLK+

CLK

PECL DRIVER

CLK

CLK+

ADC

AD9252

100Ω

0.1µF

CLK–

1

240Ω

50Ω

1

50Ω RESISTORS ARE OPTIONAL.

Figure 41. Differential PECL Sample Clock

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLK+

CLK–

CLK+

CLK

ADC

AD9252

100Ω

LVDS DRIVER

CLK

0.1µF

CLK–

1

50Ω

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

1

50Ω RESISTORS ARE OPTIONAL.

Figure 42. Differential LVDS Sample Clock

Rev. E | Page 19 of 52

AD9252

Data Sheet

Clock Jitter Considerations

Power Dissipation and Power-Down Mode

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(f_A) due only to aperture jitter (t_J) can be calculated by

As shown in Figure 46, the power dissipated by the AD9252 is

proportional to its sample rate. The digital power dissipation

does not vary much because it is determined primarily by the

DRVDD supply and bias current of the LVDS output drivers.

SNR Degradation = 20 × log 10(1/2 × π × f_A× t_J)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.80

0.75

0.70

0.65

0.60

0.55

0.50

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 45).

AVDD CURRENT

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9252.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

TOTAL POWER

DRVDD CURRENT

10

15

20

25

30

35

40

45

50

ENCODE (MSPS)

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

Figure 46. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

130

RMS CLOCK JITTER REQUIREMENT

120

110

16 BITS

100

90

80

70

60

50

40

30

14 BITS

12 BITS

10 BITS

8 BITS

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

Figure 45. Ideal SNR vs. Input Frequency and Jitter

Rev. E | Page 20 of 52

Data Sheet

AD9252

By asserting the PDWN pin high, the AD9252 is placed into

power-down mode. In this state, the ADC typically dissipates

11 m W. Du r i ng p owe r-down, the LVDS output drivers are placed

into a high impedance state. The AD9252 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

both 1.8 V and 3.3 V tolerant.

recommended that the trace length be no longer than 24 inches

and that the differential output traces be kept close together and

at equal lengths. An example of the FCO and data stream when

the AD9252 is used with traces of proper length and position is

shown in Figure 47.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode: shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 µF and 4.7 µF decoupling

capacitors on REFT and REFB, approximately 1 sec is required

to fully discharge the reference buffer decoupling capacitors and

approximately 375 µs is required to restore full operation.

5.0ns/DIV

CH1 500mV/DIV = FCO

CH2 500mV/DIV = DCO

CH3 500mV/DIV = DATA

There are several other power-down options available when

using the SPI. The user can individually power down each

channel or put the entire device into standby mode. The latter

option allows the user to keep the internal PLL powered when

fast wake-up times (~600 ns) are required. See the Memory

Map section for more details on using these features.

Figure 47. LVDS Output Timing Example in ANSI-644 Mode (Default)

An example of the LVDS output using the ANSI-644 standard

(default) data eye and a time interval error (TIE) jitter histogram

with trace lengths less than 24 inches on standard FR-4 material

is shown in Figure 48. Figure 49 shows an example of the trace

length exceeding 24 inches on standard FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position. It is the user’s

responsibility to determine if the waveforms meet the timing

budget of the design when the trace lengths exceed 24 inches.

Additional SPI options allow the user to further increase the

internal termination (increasing the current) of all eight outputs

in order to drive longer trace lengths (see Figure 50). Even though

this produces sharper rise and fall times on the data edges and

is less prone to bit errors, the power dissipation of the DRVDD

supply increases when this option is used. In addition, notice in

Figure 50 that the histogram has improved.

Digital Outputs and Timing

The AD9252 differential outputs conform to the ANSI-644 LVDS

standard by default upon power-up. This can be changed to a low

power, reduced signal option (similar to the IEEE 1596.3 standard)

via the SDIO/ODM pin or the SPI. This LVDS standard can further

reduce the overall power dissipation of the device by approximately

36 mW. See the SDIO/ODM Pin section or Table 16 in the

Memory Map section for more information. The LVDS driver

current is derived on chip and sets the output current at each

output equal to a nominal 3.5 mA. A 100 Ω differential termination

resistor placed at the LVDS receiver inputs results in a nominal

350 mV swing at the receiver.

The AD9252 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended with a 100 Ω termination resistor

placed as close to the receiver as possible. If there is no far-end

receiver termination or there is poor differential trace routing,

timing errors may result. To avoid such timing errors, it is

In cases that require increased driver strength to the DCO and

FCO outputs because of load mismatch, Register 0x15 allows

the user to increase the drive strength by 2×. To do this, first

set the appropriate bit in Register 0x05. Note that this feature

cannot be used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and

Bit 5 take precedence over this feature. See the Memory Map

section for more details.

Rev. E | Page 21 of 52

AD9252

Data Sheet

500

400

300

EYE: ALL BITS

ULS: 12071/12071

EYE: ALL BITS

ULS: 12072/12072

300

200

100

0

–100

–200

–300

–400

–500

–100

–200

–300

–400

–1.5ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

1.5ns

–1.5ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

1.5ns

90

80

70

60

50

40

30

20

10

80

70

60

50

40

30

20

10

0

–150ps

–100ps

–50ps

0ps

50ps

100ps

150ps

–150ps

–100ps

–50ps

0ps

50ps

100ps

150ps

Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω

Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4

Figure 48. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Less Than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 8.

To change the output data format to twos complement, see the

Memory Map section.

500

EYE: ALL BITS

ULS: 12067/12067

400

300

200

100

Table 8. Digital Output Coding

0

(VIN + x) − (VIN − x),

Code Input Span = 2 V p-p (V) (D13 ... D0)

163±3 +1.00 11 1111 1111 1111

Digital Output Offset Binary

–100

–200

–300

–400

–500

±192

±191

0

0.00

−0.000122

−1.00

10 0000 0000 0000

01 1111 1111 1111

00 0000 0000 0000

–1.5ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

1.5ns

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 14 bits

times the sample clock rate, with a maximum of 700 Mbps

(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion

rate is 10 MSPS. However, if lower sample rates are required for

a specific application, the PLL can be set up via the SPI to allow

encode rates as low as 5 MSPS. See the Memory Map section for

information about enabling this feature.

100

90

80

70

60

50

40

30

20

10

0

–200ps

–100ps

0ps

100ps

200ps

Figure 49. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater Than 24 Inches on Standard FR-4

Rev. E | Page 22 of 52

Data Sheet

AD9252

Two output clocks are provided to assist in capturing data from

the AD9252. The DCO is used to clock the output data and is

equal to seven times the sample clock (CLK) rate. Data is clocked

out of the AD9252 and must be captured on the rising and

falling edges of the DCO that supports double data rate (DDR)

capturing. The FCO is used to signal the start of a new output

byte and is equal to the sample clock rate. See the timing

diagram shown in Figure 2 for more information.

Table 9. Flexible Output Test Modes

Subject

to Data

Format

Output Test

Mode Bit

Sequence

Pattern Name

Off (default)

Digital Output Word 1

Digital Output Word 2

Select

0000

N/A

0001

Midscale short

1000 0000 (±-bit)

Same

Yes

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (14-bit)

0010

0011

0100

+Full-scale short

−Full-scale short

Checkerboard

1111 1111 (±-bit)

Same

Yes

No

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (14-bit)

0000 0000 (±-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (14-bit)

1010 1010 (±-bit)

0101 0101 (±-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (14-bit)

01 0101 0101 (10-bit)

0101 0101 0101 (12-bit)

01 0101 0101 0101 (14-bit)

0101

0110

0111

PN sequence long¹

PN sequence short¹

One-/zero-word toggle

N/A

Yes

No

1111 1111 (±-bit)

0000 0000 (±-bit)

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (14-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (14-bit)

1000

1001

User input

1-/0-bit toggle

Register 0x19 and Register 0x1A

1010 1010 (±-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (14-bit)

Register 0x1B and Register 0x1C

N/A

No

1010

1011

1100

1× sync

0000 1111 (±-bit)

N/A

No

00 0001 1111 (10-bit)

0000 0011 1111 (12-bit)

00 0000 0111 1111 (14-bit)

One bit high

Mixed frequency

1000 0000 (±-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (14-bit)

1010 0011 (±-bit)

10 0110 0011 (10-bit)

1010 0011 0011 (12-bit)

10 1000 0110 0111 (14-bit)

¹All test mode options except PN sequence short and PN sequence long can support ±- to 14-bit word lengths in order to verify data capture to the receiver.

Rev. E | Page 23 of 52

AD9252

Data Sheet

When the SPI is used, the DCO phase can be adjusted in 60°

increments relative to the data edge. This enables the user to

refine system timing margins if required. The default DCO+

and DCO− timing, as shown in Figure 2, is 90° relative to the

output data edge.

SDIO/ODM Pin

The SDIO/ODM pin is for use in applications that do not require

SPI mode operation. This pin can enable a low power, reduced

signal option (similar to the IEEE 1596.3 reduced range link

output standard) if it and the CSB pin are tied to AVDD during

device power-up. This option should only be used when the

digital output trace lengths are less than 2 inches from the LVDS

receiver. When this option is used, the FCO, DCO, and outputs

function normally, but the LVDS signal swing of all channels is

reduced from 350 mV p-p to 200 mV p-p, allowing the user to

further reduce the power on the DRVDD supply.

An 8-, 10-, and 12-bit serial stream can also be initiated from

the SPI. This allows the user to implement different serial stream

to test the device’s compatibility with lower and higher resolution

systems. When changing the resolution to an 8-, 10-, or 12-bit

serial stream, the data stream is shortened. See Figure 3 for a

12-bit example.

When the SPI is used, the data outputs can be inverted from

their nominal state. This is not to be confused with inverting

the serial stream to an LSB-first mode. In default mode, as

shown in Figure 2, the MSB is first in the data output serial

stream. However, this can be inverted so that the LSB is first in

the data output serial stream (see Figure 4).

For applications where this pin is not used, it should be tied low.

In this case, the device pin can be left open, and the 30 kΩ internal

pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.

If applications require this pin to be driven from a 3.3 V logic level,

insert a 1 kΩ resistor in series with this pin to limit the current.

Table 11. Output Driver Mode Pin Settings

There are 12 digital output test pattern options available that

can be initiated through the SPI. This feature is useful when

validating receiver capture and timing. Refer to Table 9 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. Note that some

patterns do not adhere to the data format select option. In

addition, customer user-defined test patterns can be assigned in

the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode

options except PN sequence short and PN sequence long can

support 8- to 14-bit word lengths in order to verify data capture

to the receiver.

Resulting

Output Standard FCO and DCO

Resulting

Selected ODM ODM Voltage

Normal

Operation

AGND

(10 kΩ pull-

down resistor)

ANSI-644

(default)

ANSI-644

(default)

ODM

AVDD

Low power,

reduced signal

option

Low power,

reduced signal

option

SCLK/DTP Pin

The SCLK/DTP pin is for use in applications that do not require

SPI mode operation. This pin can enable a single digital test pattern

if it and the CSB pin are held high during device power-up. When

the SCLK/DTP is tied to AVDD, the ADC channel outputs shift

out the following pattern: 10 0000 0000 0000. The FCO and DCO

function normally while all channels shift out the repeatable test

pattern. This pattern allows the user to perform timing alignment

adjustments among the FCO, DCO, and output data. For normal

operation, this pin should be tied to AGND through a 10 kΩ

resistor. This pin is both 1.8 V and 3.3 V tolerant.

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 2⁹− 1 or 511 bits. A description

of the PN sequence and how it is generated can be found in

Section 5.1 of the ITU-T 0.150 (05/96) standard. The only

difference is that the starting value must be a specific value

instead of all 1s (see Table 10 for the initial values).

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 2²³− 1 or 8,388,607 bits. A

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

only differences are that the starting value must be a specific

value instead of all 1s (see Table 10 for the initial values) and the

AD9252 inverts the bit stream with relation to the ITU standard.

Table 12. Digital Test Pattern Pin Settings

Resulting

D + x and D − x FCO and DCO

Resulting

Selected DTP DTP Voltage

Normal

Operation

AGND

(10 kΩ pull-

down resistor)

Normal

operation

Normal operation

DTP

AVDD

10 0000 0000

0000

Table 10. PN Sequence

Initial

Value

First Three Output Samples

(MSB First)

Sequence

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map section

for information about the options available.

PN Sequence Short

PN Sequence Long

0x0df

0x26e02±

0x37e4, 0x3533, 0x0063

0x191f, 0x35c2, 0x2359

Rev. E | Page 24 of 52

Data Sheet

AD9252

CSB Pin

VIN + x

VIN – x

The CSB pin should be tied to AVDD for applications that do

not require SPI mode operation. By tying CSB high, all SCLK

and SDIO information is ignored. This pin is both 1.8 V and

3.3 V tolerant.

REFT

0.1µF

REFB

+

ADC

CORE

4.7µF

RBIAS Pin

0.1µF

VREF

0.1µF

To set the internal core bias current of the ADC, place a resistor

that is nominally equal to 10.0 kΩ between the RBIAS pin and

ground. The resistor current is derived on chip and sets the

AVDD current of the ADC to a nominal 360 mA at 50 MSPS.

Therefore, it is imperative that at least a 1% tolerance on this

resistor be used to achieve consistent performance.

1µF

0.5V

SELECT

LOGIC

SENSE

Voltage Reference

A stable, accurate 0.5 V voltage reference is built into the

AD9252. This is gained up internally by a factor of 2, setting

VREF to 1.0 V, which results in a full-scale differential input

span of 2 V p-p. VREF is set internally by default; however, the

VREF pin can be driven externally with a 1.0 V reference to

improve accuracy.

Figure 51. Internal Reference Configuration

VIN + x

VIN – x

REFT

0.1µF

REFB

+

ADC

CORE

4.7µF

When applying the decoupling capacitors to the VREF, REFT,

and REFB pins, use ceramic low-ESR capacitors. These capacitors

should be close to the ADC pins and on the same layer of the

PCB as the AD9252. The recommended capacitor values and

configurations for the AD9252 reference pin are shown in

Figure 51.

EXTERNAL

REFERENCE

0.1µF

VREF

1

1µF

0.1µF

0.5V

SELECT

LOGIC

AVDD

SENSE

Table 13. Reference Settings

Resulting

Differential

Span (V p-p)

Selected

Mode

SENSE

Voltage

Resulting

VREF (V)

1

OPTIONAL.

External

AVDD

N/A

2 × external

reference

2.0

Figure 52. External Reference Operation

Reference

Internal,

2 V p-p FSR

5

AGND to 0.2 V

1.0

0

–5

Internal Reference Operation

A comparator within the AD9252 detects the potential at the

SENSE pin and configures the reference. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 51), setting VREF to 1 V.

–10

–15

–20

–25

–30

The REFT and REFB pins establish their input span of the ADC

core from the reference configuration. The analog input full-

scale range of the ADC equals twice the voltage at the reference

pin for either an internal or an external reference configuration.

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

CURRENT LOAD (mA)

If the reference of the AD9252 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 53

depicts how the internal reference voltage is affected by loading.

Figure 53. VREF Accuracy vs. Load

Rev. E | Page 25 of 52

AD9252

Data Sheet

0.02

0

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 54 shows the typical drift characteristics of the

internal reference in 1 V mode.

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

–0.16

–0.18

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. The external

reference is loaded with an equivalent 6 kΩ load. An internal

reference buffer generates the positive and negative full-scale

references, REFT and REFB, for the ADC core. Therefore, the

external reference must be limited to a nominal voltage of 1.0 V.

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 54. Typical VREF Drift

Rev. E | Page 26 of 52

Data Sheet

AD9252

SERIAL PORT INTERFACE (SPI)

Regardless of the mode, if CSB is taken high in the middle of a

byte transfer, the SPI state machine is reset and the device waits

for a new instruction.

The AD9252 serial port interface allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. This may

provide the user with additional flexibility and customization,

depending on the application. Addresses are accessed via the

serial port and can be written to or read from via the port. Memory

is organized into bytes that can be further divided into fields, as

documented in the Memory Map section. Detailed operational

information can be found in the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

In addition to the operation modes, the SPI port configuration

influences how the AD9252 operates. For applications that do

not require a control port, the CSB line can be tied and held high.

This places the remainder of the SPI pins into their secondary

modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin

sections. CSB can also be tied low to enable 2-wire mode. When

CSB is tied low, SCLK and SDIO are the only pins required for

communication. Although the device is synchronized during

power-up, the user should ensure that the serial port remains

synchronized with the CSB line when using this mode. When

operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-

byte transfer be used exclusively. Without an active CSB line,

streaming mode can be entered but not exited.

Three pins define the SPI: the SCLK, SDIO, and CSB pins (see

Table 14). The SCLK pin is used to synchronize the read and

write data presented to the ADC. The SDIO pin is a dual-

purpose pin that allows data to be sent to and read from the

internal ADC memory map registers. The CSB pin is an active

low control that enables or disables the read and write cycles.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the SDIO pin to change from an

input to an output at the appropriate point in the serial frame.

Table 14. Serial Port Pins

Function

SCLK

Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

Serial Data Input/Output. A dual-purpose pin that typically

serves as an input or output, depending on the instruction

sent and the relative position in the timing frame.

Chip Select Bar (Active Low). This control gates the read

and write cycles.

SDIO

CSB

Data can be sent in MSB- or LSB-first mode. MSB-first mode

is the default at power-up and can be changed by adjusting the

configuration register. For more information about this and

other features, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing sequence. During

an instruction phase, a 16-bit instruction is transmitted, followed

by one or more data bytes, which is determined by Bit Field W0

and Bit Field W1. An example of the serial timing and its

definitions can be found in Figure 56 and Table 15.

HARDWARE INTERFACE

The pins described in Table 14 constitute the physical interface

between the user’s programming device and the serial port of

the AD9252. The SCLK and CSB pins function as inputs when

using the SPI. The SDIO pin is bidirectional, functioning as an

input during write phases and as an output during readback.

During normal operation, CSB is used to signal to the device

that SPI commands are to be received and processed. When

CSB is brought low, the device processes SCLK and SDIO to

execute instructions. Normally, CSB remains low until the

communication cycle is complete. However, if connected to a

slow device, CSB can be brought high between bytes, allowing

older microcontrollers enough time to transfer data into shift

registers. CSB can be stalled when transferring one, two, or

three bytes of data.

If multiple SDIO pins share a common connection, care should be

taken to ensure that proper V_OHlevels are met. Assuming the same

load for each AD9252, Figure 55 shows the number of SDIO pins

that can be connected together and the resulting V_OHlevel.

This interface is flexible enough to be controlled by either serial

PROMs or PIC microcontrollers, providing the user with an

alternative method, other than a full SPI controller, to program

the ADC (see the AN-812 Application Note).

When W0 and W1 are set to 11, the device enters streaming

mode and continues to process data, either reading or writing,

until CSB is taken high to end the communication cycle. This

allows complete memory transfers without requiring additional

instructions.

If the user chooses not to use the SPI, these dual-function pins

serve their secondary functions when the CSB is strapped to

AVDD during device power-up. See the Theory of Operation

section for details on which pin-strappable functions are

supported on the SPI pins.

Rev. E | Page 27 of 52

AD9252

Data Sheet

1.800

1.795

1.790

1.785

1.780

1.775

1.770

1.765

1.760

1.755

1.750

1.745

1.740

1.735

1.730

1.725

1.720

1.715

0

10

20

30

40

50

60

70

80

90

100

NUMBER OF SDIO PINS CONNECTED TOGETHER

Figure 55. SDIO Pin Loading

t_DS

t_HI

t_CLK

t_H

t_S

t_DH

t_LO

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

Figure 56. Serial Timing Details

Table 15. Serial Timing Definitions

Parameter

Timing (Minimum, ns)

Description

t_DS

5

2

40

5

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the clock

t_DH

t_CLK

t_S

Setup time between CSB and SCLK

t_H

2

Hold time between CSB and SCLK

t_HI

t_LO

t_{EN_SDIO}

16

10

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 56)

t_{DIS_SDIO}

10

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 56)

Rev. E | Page 28 of 52

Data Sheet

AD9252

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have 0 written to their registers during power-up.

Each row in the memory map register table (Table 16) has eight

address locations. The memory map is divided into three sections:

the chip configuration register map (Address 0x00 to Address 0x02),

the device index and transfer register map (Address 0x04,

Address 0x05, and Address 0xFF), and the ADC functions register

map (Address 0x08 to Address 0x22).

DEFAULT VALUES

When the AD9252 comes out of a reset, critical registers are

preloaded with default values. These values are indicated in

Table 16, where an X refers to an undefined feature.

The leftmost column of the memory map indicates the register

address number; the default value is shown in the second right-

most column. The Bit 7 column is the start of the default

hexadecimal value given. For example, Address 0x09, the clock

register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0,

Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or

0000 0001 in binary. This setting is the default for the duty cycle

stabilizer in the on condition. By writing 0 to Bit 0 of this address

followed by writing 0x01 in Register 0xFF (transfer bit), the duty

cycle stabilizer turns off. It is important to follow each writing

sequence with a transfer bit to update the SPI registers. All

registers, except Register 0x00, Register 0x04, Register 0x05, and

Register 0xFF, are buffered with a master-slave latch and require

writing to the transfer bit. For more information on this and

other functions, consult the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

LOGIC LEVELS

An explanation of various registers follows: “bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Rev. E | Page 29 of 52

AD9252

Data Sheet

Table 16. Memory Map Register¹

Default

Value

(Hex)

Addr.

(MSB)

(LSB)

Bit 0

Notes/

Comments

(Hex) Parameter Name Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

LSB first

1 = on

0

0x1±

The nibbles

should be

00

chip_port_config

0

LSB first

1 = on

Soft

reset

1

Soft

reset

0 = off

(default)

1 = on

0 = off

(default)

1 = on

0 = off

(default)

0 = off

(default)

mirrored so

that LSB- or

MSB-first mode

is set correctly

regardless of

shift mode.

01

02

chip_id

±-bit Chip ID Bits [7:0]

(AD9252 = 0x09), (default)

Read

only

Default is unique

chip ID, different

for each device.

This is a read-

only register.

chip_grade

X

Child ID [6:4]

X

Read

only

Child ID used to

differentiate

(identify device variants of Chip ID)

011 = 50 MSPS

graded devices.

Device Index and Transfer Registers

Data

Channel

E

0x0F

0x00

Bits are set to

04

05

FF

device_index_2

device_index_1

device_update

X

Channel Channel Channel

H

1 = on

(default)

0 = off

determine which

on-chip device

receives the next

write command.

G

F

1 = on

(default) (default) (default)

0 = off

Clock

Data

Channel

A

Bits are set to

Channel Channel Channel Channel Channel

determine which

on-chip device

receives the next

write command.

DCO

1 = on

0 = off

FCO

1 = on

0 = off

D

1 = on

C

B

1 = on

(default) (default) (default) (default)

(default) (default) 0 = off

0 = off

X

SW

Synchronously

transfers data

from the master

shift register to

the slave.

transfer

1 = on

0 = off

(default)

ADC Functions Registers

0±

modes

X

Internal power-down mode

000 = chip run (default)

001 = full power-down

010 = standby

0x00

0x01

Determines

various generic

modes of chip

operation.

011 = reset

09

clock

X

Duty

Turns the

cycle

internal duty

cycle stabilizer

on and off.

stabilizer

1 = on

(default)

0 = off

When this register

is set, the test

data is placed on

the output pins

in place of

0D

test_io

User test mode

00 = off (default)

01 = on, single alternate 1 = on

10 = on, single once

11 = on, alternate once

Reset PN Reset

long gen PN short

0x00

Output test mode—see 5BCMF in the

%JHJUBM 0 VUQVUT BOE 5JNJOH section

0000 = off (default)

0001 = midscale short

0010 = +FS short

gen

0 = off

1 = on

(default) 0 = off

(default)

normal data.

0011 = −FS short

0100 = checkerboard output

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one-/zero-word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

(format determined by output_mode)

Rev. E | Page 30 of 52

Data Sheet

AD9252

Default

Value

(Hex)

Addr.

(MSB)

(LSB)

Bit 0

Notes/

Comments

(Hex) Parameter Name Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

14

output_mode

X

0 = LVDS

ANSI-644

(default)

1 = LVDS

low power,

(IEEE 1596.3

similar)

X

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

01 = twos complement

0x00

Configures the

outputs and the

format of the data.

15

output_adjust

X

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

X

DCO and 0x00

FCO

2× drive

strength

1 = on

Determines

LVDS or other

output properties.

Primarily func-

tions to set the

LVDS span and

common-mode

levels in place of

an external

0 = off

(default)

resistor.

On devices that

utilize global

clock divide,

this register

16

output_phase

X

0011 = output clock phase adjust

(0000 through 1010)

0000 = 0° relative to data edge

0001 = 60° relative to data edge

0010 = 120° relative to data edge

0x03

determines

0011 = 1±0° relative to data edge (default)

0101 = 300° relative to data edge

0110 = 360° relative to data edge

1000 = 4±0° relative to data edge

1001 = 540° relative to data edge

1010 = 600° relative to data edge

1011 to 1111 = 660° relative to data edge

which phase

of the divider

output is used

to supply the

output clock.

Internal latching

is unaffected.

19

1A

1B

1C

21

user_patt1_lsb

user_patt1_msb

user_patt2_lsb

user_patt2_msb

serial_control

B7

B6

B5

B4

B3

B2

B1

B9

B1

B9

B0

B±

B0

B±

0x00

User-defined

pattern, 1 LSB.

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

User-defined

pattern, 1 MSB.

User-defined

pattern, 2 LSB.

B15

B14

X

B13

X

B12

X

B11

B10

User-defined

pattern, 2 MSB.

LSB first

1 = on

0 = off

<10

MSPS,

low

encode

rate

000 = 14 bits (default, normal bit

stream)

001 = ± bits

010 = 10 bits

011 = 12 bits

Serial stream

control. Default

causes MSB first

and the native

bit stream

(default)

mode

1 = on

0 = off

(default)

100 = 14 bits

(global).

Used to power

down individual

sections of a

22

serial_ch_stat

X

Channel

output

reset

1 = on

0 = off

Channel

power-

down

1 = on

0 = off

0x00

converter (local).

(default) (default)

¹X = an undefined feature.

Rev. E | Page 31 of 52

AD9252

Data Sheet

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9252. An

exposed continuous copper plane on the PCB should mate to

the AD9252 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be solder-filled or plugged.

Before starting design and layout of the AD9252 as a system, it

is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9252, it is recommended

that two separate 1.8 V supplies be used: one for analog (AVDD)

and one for digital (DRVDD). If only one supply is available, it

should be routed to the AVDD first and then tapped off and

isolated with a ferrite bead or a filter choke preceded by

decoupling capacitors for the DRVDD. The user can employ

several different decoupling capacitors to cover both high and

low frequencies. These capacitors should be located close to the

point of entry at the PC board level and close to the parts with

minimal trace lengths.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This provides

multiple tie points between the ADC and PCB during the

reflow process, whereas using one continuous plane with no

partitions guarantees only one tie point. See Figure 57 for a PCB

layout example. For detailed information on packaging and the

PCB layout of chip scale packages, see the AN-772 Application

Note, A Design and Manufacturing Guide for the Lead Frame

Chip Scale Package (LFCSP).

A single PC board ground plane should be sufficient when

using the AD9252. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance can be easily achieved.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 57. Typical PCB Layout

Rev. E | Page 32 of 52

Data Sheet

AD9252

EVALUATION BOARD

The AD9252 evaluation board provides all the support cir-

cuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially by using

a transformer (default) or an AD8334 driver. The ADC can also be

driven in a single-ended fashion. Separate power pins are provided

to isolate the DUT from the drive circuitry of the AD8334. Each

input configuration can be selected by changing the connections

of various jumpers (see Figure 62 to Figure 66). Figure 58 shows

the typical bench characterization setup used to evaluate the

ac performance of the AD9252. It is critical that the signal sources

used for the analog input and clock have very low phase noise

(<1 ps rms jitter) to realize the optimum performance of the

converter. Proper filtering of the analog input signal to remove

harmonics and lower the integrated or broadband noise at the

input is also necessary to achieve the specified noise performance.

board individually. Use P702 to connect a different supply for

each section. At least one 1.8 V supply is needed for AVDD_DUT

and DRVDD_DUT; however, it is recommended that separate

supplies be used for both analog and digital signals and that each

supply have a current capability of 1 A. To operate the evaluation

board using the VGA option, a separate 5.0 V analog supply

(AVDD_5 V) is needed. To operate the evaluation board using

the SPI and alternate clock options, a separate 3.3 V analog supply

(AVDD_3.3 V) is needed in addition to the other supplies.

INPUT SIGNALS

When connecting the clock and analog sources to the

evaluation board, use clean signal generators with low phase

noise, such as Rohde & Schwarz SMA or HP8644 signal generators

or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial

cable. Enter the desired frequency and amplitude from the ADC

specifications tables. Typically, most Analog Devices, Inc., evalu-

ation boards can accept approximately 2.8 V p-p or 13 dBm

sine wave input for the clock. When connecting the analog

input source, it is recommended to use a multipole, narrow-band,

band-pass filter with 50 Ω terminations. Good choices of such

band-pass filters are available from TTE, Allen Avionics, and

K&L Microwave, Inc. The filter should be connected directly to

the evaluation board if possible.

See Figure 62 to Figure 72 for the complete schematics and

layout diagrams demonstrating the routing and grounding

techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board has a wall-mountable switching power

supply that provides a 6 V, 2 A maximum output. Connect the

supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to

63 Hz. The other end of the supply is a 2.1 mm inner diameter

jack that connects to the PCB at P701. Once on the PC board,

the 6 V supply is fused and conditioned before connecting to

three low dropout linear regulators that supply the proper bias

to each of the various sections on the board.

OUTPUT SIGNALS

The default setup uses the Analog Devices HSC-ADC-FIFO5-

INTZ to interface with the Analog Devices standard dual-channel

FIFO data capture board (HCS-ADC-EVALCZ). Two of the

eight channels can be evaluated at the same time. For more

information on the channel settings and optional settings of

these boards, visit www.analog.com/FIFO.

When operating the evaluation board in a nondefault condition,

L701 to L704 can be removed to disconnect the switching

power supply. This enables the user to bias each section of the

WALL OUTLET

100V AC TO 240V AC

47Hz TO 63Hz

6V DC

2A MAX

5.0V

1.8V

3.3V

–

+

–

+

–

+

–

+

–

+

SWITCHING

POWER

SUPPLY

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

ROHDE & SCHWARZ,

INTERPOSER

BOARD

HSC-ADC-EVALCZ

FIFO DATA

CAPTURE

SMA,

2V p-p SIGNAL

SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

BOARD

CH A TO CH H

14-BIT

SOFTWARE

AD9252

EVALUATION BOARD

USB

CONNECTION

ROHDE & SCHWARZ,

SMA,

CLK

SERIAL

LVDS

2V p-p SIGNAL

SYNTHESIZER

SPI

Figure 58. Evaluation Board Connection

Rev. E | Page 33 of 52

AD9252

Data Sheet

A differential LVPECL clock can also be used to clock the

ADC input using the AD9515 (U401). Populate R406 and

R407 with 0 Ω resistors, and remove R215 and R216 to

disconnect the default clock path inputs. In addition, populate

C205 and C206 with a 0.1 μF capacitor, and remove C409 and

C410 to disconnect the default clock path outputs. The

AD9515 has many pin-strappable options that are set to a

default mode of operation. Consult the AD9515 data sheet

for more information about these and other options.

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

The following is a list of the default and optional settings or

modes allowed on the AD9252 Rev. A evaluation board.



Power: Connect the switching power supply that is

provided with the evaluation kit between a rated 100 V ac

to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.



AIN: The evaluation board is set up for a transformer-

coupled analog input with an optimum 50 Ω impedance

match of 150 MHz of bandwidth (see Figure 59). For more

bandwidth response, the differential capacitor across the

analog inputs can be changed or removed. The common

mode of the analog inputs is developed from the center

tap of the transformer or AVDD_DUT/2.

In addition, an on-board oscillator is available on the OSC401

and can act as the primary clock source. The setup is quick

and involves installing R403 with a 0 Ω resistor and setting

the enable jumper (J401) to the on position. If the user wishes

to employ a different oscillator, two oscillator footprint options

are available (OSC401) to check the ADC performance.

0



PDWN: To enable the power-down feature, short J301 to

the on position (AVDD) for the PDWN pin.

–1

–3dB CUTOFF = 186MHz

–2

–3

SCLK/DTP: To enable the digital test pattern on the digital

outputs of the ADC, use J304. If J304 is tied to AVDD during

device power-up, Test Pattern 10 0000 0000 0000 is enabled.

See the SCLK/DTP Pin section for details.

–4

–5

–6

–7

–8



SDIO/ODM: To enable the low power, reduced signal option

(similar to the IEEE 1595.3 reduced range link LVDS output

standard), use J303. If J303 is tied to AVDD during device

power-up, it enables the LVDS outputs in a low power,

reduced signal option from the default ANSI-644 standard.

This option changes the signal swing from 350 mV p-p to

200 mV p-p, reducing the power of the DRVDD supply. See

the SDIO/ODM Pin section for more details.

–9

–10

–11

–12

–13

–14

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 59. Evaluation Board Full-Power Bandwidth



VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R317. This causes the ADC to operate in 2.0 V p-p

full-scale range. A separate external reference option using

the ADR510 is also included on the evaluation board.

Populate R312 and R313, and remove C307. Proper use of

the VREF options is noted in the Voltage Reference

section.



CSB: To enable processing of the SPI information on the

SDIO and SCLK pins, tie J302 low in the always enable

mode. To ignore the SDIO and SCLK information, tie J302

to AVDD.

Non-SPI Mode: For users who wish to operate the DUT

without using the SPI, simply remove Jumpers J302, J303,

and J304. This disconnects the CSB, SCLK/DTP, and

SDIO/ODM pins from the control bus, allowing the DUT

to operate in its simplest mode. Each of these pins has

internal termination and will float to its respective level.



RBIAS: RBIAS has a default setting of 10 kΩ (R301) to

ground and is used to set the ADC core bias current.

Clock: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth

1:1 impedance ratio transformer (T401) that adds a very

low amount of jitter to the clock path. The clock input is

50 Ω terminated and ac-coupled to handle single-ended

sine wave types of inputs. The transformer converts the

single-ended input to a differential signal that is clipped

before entering the ADC clock inputs.



D + x, D − x: If an alternative data capture method to the

setup shown in Figure 62 is used, optional receiver

terminations, R318 and R320 to R328, can be installed next

to the high speed backplane connector.

Rev. E | Page 34 of 52

Data Sheet

AD9252

In this example, a 16 MHz, two-pole low-pass filter was applied

to the AD8334 outputs. The following components need to be

removed and/or changed:

ALTERNATIVE ANALOG INPUT DRIVE

CONFIGURATION

The following is a brief description of the alternative analog

input drive configuration using the AD8334 dual VGA. If this

drive option is in use, some components may need to be populated,

in which case all the necessary components are listed in Table 17.

For more details on the AD8334 dual VGA, including how it works

and its optional pin settings, consult the AD8334 data sheet.

•

Remove L507, L508, L511, L512, L515, L516, L519, L520,

L607, L608, L611, L612, L615, L616, L619, and L620 on the

AD8334 analog outputs.

Populate L507, L508, L511, L512, L515, L516, L519, L520,

L607, L608, L611, L612, L615, L616, L619, and L620 with

680 nH inductors.

To configure the analog input to drive the VGA instead of the

default transformer option, the following components need to

be removed and/or changed.

Populate C543, C547, C551, C555, C643, C647, C651, and

C655 with a 68 pF capacitor.

•

Remove R102, R115, R128, R141, R161, R162, R163, R164,

R202, R208, R218, R225, R234, R241, R252, R259, T101,

T102, T103, T104, T201, T202, T203, and T204 in the

default analog input path.

680nH

68pF

680nH

Figure 60. Example Filter Configured for16 MHz, Two-Pole Low-Pass Filter

0

•

Populate R101, R114, R127, R140, R201, R217, R233, and

R251 with 0 Ω resistors in the analog input path.

f_SAMPLE= 50MSPS

AIN = 3.5MHz

AD8334 = MAX GAIN SETTING

–20

Populate R152, R153, R154, R155, R156, R157, R158, R159,

R215, R216, R229, R230, R247, R248, R263, R264, C103,

C105, C110, C112, C117, C119, C124, C126, C203, C205,

C210, C212, C217, C219, C224, and C226 with 10 kΩ

resistors to provide an input common-mode level to the

ADC analog inputs.

–40

–60

–80

•

Populate R105, R113, R118, R124, R131, R137, R151, R160,

R205, R213, R221, R222, R237, R238, R255, and R256 with

0 Ω resistors in the ADC analog input path to connect the

VGA outputs.

–100

–120

0

2.5

5.0

7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0

FREQUENCY (MHz)

•

Remove R515, R520, R527, R532, R615, R620, R627, and

R632 on the AD8334 analog outputs.

Figure 61. AD9252 FFT Example Results Using

16 MHz, Two-Pole Low-Pass Filter Applied to the AD8334 Outputs

(Analog Input Signal = −1.03 dBFS, SNR = 60.2 dBc, SFDR = 66.23 dBc)

Remove R512, R524, R612, and R624 to set the AD8334

mode and AD8334 HILO pin low. Some applications may

require this to be different. Consult the AD8334 data sheet

for more information on these functions.

In this configuration, L505 to L520 and L605 to L620 are populated

with 0 Ω resistors to allow signal connection and use of a filter if

additional requirements are necessary.

Rev. E | Page 35 of 52

AD9252

Data Sheet

0 7 2

0 6 2 9 6 -

Figure 62. Evaluation Board Schematic, DUT Analog Inputs

Rev. E | Page 36 of 52

Data Sheet

AD9252

0 7 3 0 6 2 9 6 -

Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued)

Rev. E | Page 37 of 52

AD9252

Data Sheet

0 7 4 0 6

2

R307

10kΩ

R306

100kΩ

AVDD_DUT

R302

DNP

R305

100kΩ

CW

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

0

VIN+C

VIN−C

AVDD

VIN−D

VIN+D

RBIAS

SENSE

VREF

REFB

REFT

AVDD

VIN+E

VIN−E

AVDD

VIN−F

VIN+F

SLUG

VIN_C

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

CHB

D+B

D−B

CHB

CHC

AVDD_DUT

VIN_D

D+C

D−C

CHC

CHD

GND

R301

10kΩ

VIN_D

D+D

D−D

CHD

FCO

VSENSE_DUT

VREF_DUT

FCO+

FCO−

DCO+

DCO−

D+E

FCO

DCO

AVDD_DUT

VIN_E

CHE

D−E

VIN_E

D+F

CHF

AVDD_DUT

D−F

CHF

CHG

VIN_F

D+G

D−G

CHG

Figure 64. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Rev. E | Page 3± of 52

Data Sheet

AD9252

0 7 5

0

25

16

15

14

13

12

11

10

9

S0

S1

S2

S3

1

2

33

31

1

S4

3

S5

GND

VS

S6

S7

S8

8

S9

32

7

RSET

S10

VREF

6

Figure 65. Evaluation Board Schematic, Clock Circuitry

Rev. E | Page 39 of 52

AD9252

Data Sheet

0 7 6

0

R524

10kΩ

R523

10kΩ

R513

187Ω

C512

10µF

C511

0.1µF

C533

10µF

C534

0.1µF

C535

10µF

C536

0.1µF

C510

10µF

C509

0.1µF

R512

10kΩ

R511

10kΩ

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCM2

VCM1

EN34

NC

VCM3

VCM4

HILO

R504

10kΩ

R505

10kΩ

AVDD_5V

EN12

CLMP12

GAIN12

VPS1

VIN1

CLMP34

GAIN34

VPS4

VG34

VG12

AVDD_5V

VIN4

VIP1

VIP4

LOP1

LON1

COM1X

LMD1

INH1

LOP4

LON4

COM4X

LMD4

INH4

R509

274Ω

C505

0.1µF

COM1

COM2

COM4

COM3

C527

0.018µF

C526

22pF

L504

120nH

0.1µF

C525

R503

274Ω

R508

274Ω

R507

274Ω

C502

0.018µF

C521

0.018µF

C515

0.018µF

C503

22pF

L501

120nH

C520

22pF

C514

22pF

0.1µF

C501

L503

120nH

L502

120nH

0.1µF

C519

0.1µF

C513

AVDD_5V

CW

GND

VG34

VG12

Variable Gain Circuit

(0−1.0V DC)

Variable Gain Circuit

(0−1.0V DC)

VG34

VG12

External

Variable Gain Drive

External

Variable Gain Drive

Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive

Rev. E | Page 40 of 52

Data Sheet

AD9252

0 7 7

0

R613

187Ω

C612

10µF

C611

0.1µF

C633

10µF

C634

0.1µF

C635

10µF

C636

0.1µF

C610

10µF

C609

0.1µF

VCM2

NC

VCM3

VCM4

HILO

49

50

51

52

53

54

55

56

57

58

59

60

61

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCM1

EN34

EN12

10kΩ

R604

R612

10kΩ

R611

10kΩ

R605

10kΩ

AVDD_5V

CLMP12

GAIN12

VPS1

CLMP34

GAIN34

VPS4

VG56

VG78

AVDD_5V

VIN1

VIN4

VIP1

VIP4

LOP1

LOP4

LON1

COM1X

LMD1

INH1

LON4

COM4X

LMD4

INH4

R609

274Ω

C605

0.1µF

62

63

COM1

COM2

COM4

COM3

64

C627

0.018µF

C626

22pF

L604

120nH

0.1µF

C625

R603

274Ω

R608

274Ω

R607

274Ω

C602

0.018µF

C621

0.018µF

C615

0.018µF

C603

22pF

L601

120nH

C620

22pF

C614

22pF

0.1µF

C601

L603

120nH

L602

120nH

0.1µF

C619

0.1µF

C613

AVDD_5V

CW

GND

VG78

VG56

Variable Gain Circuit

(0−1.0V DC)

Variable Gain Circuit

(0−1.0V DC)

VG78

VG56

External

Variable Gain Drive

External

Variable Gain Drive

Figure 67. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)

Rev. E | Page 41 of 52

AD9252

Data Sheet

0 7 8

0

CR702

GREEN

C702

0.1µF

C703

0.1µF

GND

1

R709

0Ω

SDO_CHA

SDI_CHA

R708

R707

R706

0Ω

SCLK_CHA

CSB1_CHA

PICVCC

1

3

5

7

9

2

4

PICVCC

GP1

GP0

6

GP0

MCLR/GP3

8

MCLR/GP3

10

GND

CR701

GND

2

OPTIONAL GREEN

Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry

Rev. E | Page 42 of 52

Data Sheet

AD9252

Figure 69. Evaluation Board Layout, Primary Side

Rev. E | Page 43 of 52

AD9252

Data Sheet

Figure 70. Evaluation Board Layout, Ground Plane

Rev. E | Page 44 of 52

Data Sheet

AD9252

Figure 71. Evaluation Board Layout, Power Plane

Rev. E | Page 45 of 52

AD9252

Data Sheet

Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. E | Page 46 of 52

Data Sheet

AD9252

Table 17. Evaluation Board Bill of Materials (BOM)¹

Qty

per

Reference

Manufacturer

Manufacturer Part Number

Item Board Designator

Device

Package

PCB

402

Value

1

2

1

11±

AD9252LFCSP_REVA PCB

PCB

C101, C102, C107,

C10±, C109, C114,

C115, C116, C121,

C122, C123, C12±,

C201, C202, C207,

C20±, C209, C214,

C215, C216, C221,

C222, C223, C22±,

C301, C302, C304,

C305, C306, C401,

C402, C403, C409,

C410, C411, C412,

C413, C414, C415,

C416, C417, C41±,

C501, C504, C505,

C506, C50±, C509,

C511, C513, C51±,

C519, C522, C523,

C524, C525, C52±,

C529, C530, C532,

C534, C536, C537,

C53±, C601, C604,

C605, C606, C60±,

C609, C611, C613,

C616, C617, C61±,

C619, C622, C623,

C624, C625, C62±,

C629, C630, C632,

C634, C636, C701,

C702, C703, C706,

C70±, C710, C712,

C723, C724, C725,

C726, C727, C730,

C731, C732, C733,

C734, C735, C740,

C741, C742, C743,

C744, C745, C746,

C747, C74±, C749,

C750, C751, C752,

C753

Capacitor

0.1 μF, ceramic, X5R,

10 V, 10% tol

Murata

GRM155R71C104KA±±D

3

4

±

C104, C111, C11±,

C125, C204, C211,

C21±, C225

C510, C512, C533,

C535, C610, C612,

C633, C635

Capacitor

402

±05

2.2 pF, ceramic, COG,

0.25 pF tol, 50 V

Murata

GRM1555C1H2R20CZ01D

GRM219R60J106KE19D

10 μF, 6.3 V ±10%,

ceramic, X5R

5

6

7

1

4

±

C303

Capacitor

603

402

4.7 μF, ceramic, X5R,

6.3 V, 10% tol

1000 pF, ceramic, X7R,

25 V, 10% tol

0.01± μF, ceramic, X7R,

16 V, 10% tol

Murata

AVX

GRM1±±R60J475KE19D

GRM155R71H102KA01D

0402YC1±3KAT2A

C507, C531, C607,

C631

C502, C515, C521,

C527, C602, C615,

C621, C627

Rev. E | Page 47 of 52

AD9252

Data Sheet

Qty

per

Reference

Manufacturer

Manufacturer Part Number

Item Board Designator

Device

Package

Value

±

C503, C514, C520,

C526, C603, C614,

C620, C626

Capacitor

402

22 pF, ceramic, NPO,

5% tol, 50 V

Murata

GRM1555C1H220JZ01D

9

1

9

C704

Capacitor

1206

603

10 μF, tantalum,

16 V, 20% tol

1 μF, ceramic, X5R,

6.3 V, 10% tol

ROHM Co., Ltd. TCA1C106M±R

10

C307, C714, C715,

C716, C717, C719,

C720, C721, C722

C540, C541, C544,

C545, C54±, C549,

C552, C553, C640,

C641, C644, C645,

C64±, C649, C652,

C653

Murata

GRM1±±R61C105KA93D

11

16

Capacitor

±05

0.1 μF, ceramic, X7R,

50 V, 10% tol

GRM21BR71H104KA01L

12

13

4

1

C705, C707, C709,

C711

CR401

Capacitor

Diode

603

10 μF, ceramic, X5R,

6.3 V, 20% tol

30 V, 20 mA, dual

Schottky

Green, 4 V, 5 m candela

3 A, 30 V, SMC

Murata

GRM1±±R60J106ME47D

HSMS-2±12-TR1G

SOT-23

603

Avago

Technologies

Panasonic

Micro

14

15

2

1

CR701, CR702

D702

LED

Diode

LNJ314G±TRA

SK33-TP

DO-

214AB

Commercial Co.

16

17

1±

19

1

D701

Diode

DO-

214AA

5 A, 50 V, SMC

Micro

Commercial Co.

Tyco/Raychem

S2A-TP

1

F701

Fuse

1210

2020

603

6.0 V, 2.2 A trip-current

resettable fuse

10 μH, 5 A, 50 V, 190 Ω

@ 100 MHz

10 Ω, test frequency

100 MHz, 25% tol,

500 mA

NANOSMDC110F-2

DLW5BSN191SQ2L

BLM1±BA100SN1D

1

FER701

Choke coil

Ferrite bead

Murata

24

FB101, FB102,

FB103, FB104,

FB105, FB106,

FB107, FB10±,

FB109, FB110,

FB111, FB112,

FB201, FB202,

FB203, FB204,

FB205, FB206,

FB207, FB20±,

FB209, FB210,

FB211, FB212

Murata

20

21

23

4

6

1

JP501, JP502,

JP601, JP602

J301, J302, J303,

J304, J401, J701

Connector

2-pin

3-pin

10-pin

100 mil header jumper,

2-pin

100 mil header jumper,

3-pin

100 mil header, male,

2 × 5 double row

straight

Samtec

TSW-102-07-G-S

TSW-103-07-G-S

TSW-105-0±-G-D

J702

24

25

±

L701, L702, L703,

L704, L705, L706,

L707, L70±

L501, L502, L503,

L504, L601, L602,

L603, L604

Ferrite bead

Inductor

1210

402

10 μH, bead core 3.2 ×

2.5 × 1.6 SMD, 2 A

Murata

BLM31PG500SN1L

LQG15HNR12J02D

120 nH, test freq

100 MHz, 5% tol,

150 mA

Rev. E | Page 4± of 52

Data Sheet

AD9252

Qty

per

Reference

Manufacturer

Manufacturer Part Number

Item Board Designator

Device

Package

Value

26

32

L505, L506, L507,

L50±, L509, L510,

L511, L512, L513,

L514, L515, L516,

L517, L51±, L519,

L520, L605, L606,

L607, L60±, L609,

L610, L611, L612,

L613, L614, L615,

L616, L617, L61±,

L619, L620

Resistor

±05

0 Ω, 1/± W, 5% tol

NIC

Components

Corp.

NRC04Z0TRF

27

2±

29

1

9

1

OSC401

Oscillator

Connector

SMT

Clock oscillator,

50.00 MHz, 3.3 V,

±5% duty cycle

Side-mount SMA for

0.063" board thickness

Valpey Fisher

VFAC3-BHL-50MHz

142-0701-±51

6469169-1

P101, P103, P105,

P107, P201, P203,

P205, P207, P401

SMA

Johnson

Components

P301

HEADER

1469169-1, right angle

2-pair, 25 mm, header

assembly

Tyco

30

31

1

P701

Connector

Resistor

0.1",

PCMT

402

RAPC722, power

supply connector

10 kΩ, 1/16 W, 5% tol

Switchcraft

RAPC722X

21

R301, R307, R401,

R402, R410, R413,

R504, R505, R511,

R512, R523, R524,

R604, R605, R611,

R612, R623, R624,

R711, R714, R715

NIC

Components

Corp.

NRC04J103TRF

32

1±

R103, R117, R129,

R142, R203, R219,

R235, R253, R317,

R405, R415, R416,

R417, R41±, R706,

R707, R70±, R709

Resistor

402

0 Ω, 1/16 W, 5% tol

NIC

Components

Corp.

NRC04Z0TRF

33

34

35

±

R102, R115, R12±,

R141, R202, R21±,

R234, R252

R104, R116, R130,

R143, R204, R220,

R236, R254

R109, R111, R112,

R123, R125, R126,

R135, R13±, R139,

R14±, R149, R150,

R211, R212, R214,

R22±, R231, R232,

R246, R249, R250,

R262, R265, R266,

R319, R710, R712,

R713

Resistor

402

603

402

64.9 Ω, 1/16 W, 1% tol

0 Ω, 1/10 W, 5% tol

1 kΩ, 1/16 W, 1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC04F64R9TRF

NRC06Z0TRF

±

2±

NRC04F1001TRF

36

16

R10±, R110, R121,

R122, R134, R136,

R146, R147, R209,

R210, R226, R227,

R242, R245, R260,

R261

Resistor

402

33 Ω, 1/16 W, 5% tol

NIC

Components

Corp.

NRC04J330TRF

Rev. E | Page 49 of 52

AD9252

Data Sheet

Qty

per

Reference

Manufacturer

Manufacturer Part Number

Item Board Designator

Device

Package

Value

37

3±

39

±

3

1

R161, R162, R163,

R164, R20±, R225,

R241, R259

Resistor

402

499 Ω, 1/16 W, 1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC04F4990TRF

NRC04F1003TRF

NRC04F4121TRF

R303, R305, R306

Resistor

402

100 kΩ, 1/16 W, 1% tol

4.12 kΩ, 1/16W, 1% tol

R414

40

41

1

R404

R309

Resistor

402

49.9 Ω, 1/16 W, 0.5% tol Susumu

RR0510R-49R9-D

NRC04F4991TRF

4.99 kΩ, 1/16 W, 5% tol

NIC

Components

Corp.

42

43

44

45

5

R310, R501, R535,

R601, R634

Potentiometer 3-lead

10 kΩ, Cermet trimmer

potentiometer, 1±-turn

top adjust, 10%, 1/2 W

470 kΩ, 1/16 W, 5% tol

39 kΩ, 1/16 W, 5% tol

1±7 Ω, 1/16 W, 1% tol

Copal

Electronics

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

CT94EW103

1

R30±

Resistor

402

NRC04J474TRF

NRC04J393TRF

NRC04F1±70TRF

4

R502, R536, R602,

R635

16

R513, R514, R51±,

R519, R525, R526,

R530, R531, R613,

R614, R61±, R619,

R625, R626, R630,

R631

46

47

4±

±

R515, R520, R527,

R532, R615, R620,

R627, R632

R503, R507, R50±,

R509, R603, R607,

R60±, R609

R425, R427, R429,

R431, R433, R435,

R436, R439, R441,

R443, R445

Resistor

402

201

374 Ω, 1/16 W, 1% tol

274 Ω, 1/16 W, 1% tol

0 Ω, 1/20 W, 5% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC04F3740TRF

NRC04F2740TRF

NRC02Z0TRF

±

11

49

50

51

52

53

54

1

2

1

R701

Resistor

Switch

402

603

402

SMD

4.7 kΩ, 1/16 W, 1% tol

261 Ω, 1/16 W, 1% tol

240 Ω, 1/16 W, 5% tol

100 Ω, 1/16 W, 1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC04J472TRF

NRC04F2610TRF

NRC06F261OTRF

NRC04J241TRF

NRC04F1000TRF

EVQPLDA15

R702

R716

R420, R421

R422, R423

S701

NIC

Components

Corp.

Light Touch,

Panasonic

100 GE, 5 mm

Rev. E | Page 50 of 52

Data Sheet

AD9252

Qty

per

Reference

Manufacturer

Manufacturer Part Number

Mini-Circuits ADT1-1WT+

Item Board Designator

Device

Package

Value

55

56

57

9

2

T101, T102, T103,

T104, T201, T202,

T203, T204, T401

Transformer

CD542

ADT1-1WT+,

1:1 impedance ratio

transformer

ADP3339AKC-1.±-RL,

1.5 A, 1.± V LDO

regulator

AD±334ACPZ-REEL,

ultralow noise

U704, U707

IC

SOT-223

CP-64-3

Analog Devices ADP3339AKCZ-1.±-RL

Analog Devices AD±334ACPZ-REEL

U501, U601

precision dual VGA

5±

59

60

1

U706

U705

U301

IC

SOT-223

CP-64-3

ADP3339AKC-5-RL7

ADP3339AKC-3.3-RL

AD9252BCPZ-50, octal,

14-bit, 50 MSPS serial

LVDS 1.± V ADC

Analog Devices ADP3339AKCZ-5-RL7

Analog Devices ADP3339AKCZ-3.3-RL

Analog Devices AD9252BCPZ-50

61

1

U302

IC

SOT-23

ADR510ARTZ, 1.0 V,

precision low noise

shunt voltage

Analog Devices ADR510ARTZ

reference

62

63

64

65

1

U401

U702

U703

U701

IC

LFCSP

CP-32-2

SC70,

MAA06A

SC70,

MAA06A

±-SOIC

AD9515BCPZ, 1.6 GHz

clock distribution IC

NC7WZ07P6X_NL,

UHS dual buffer

NC7WZ16P6X_NL,

UHS dual buffer

Flash prog

Analog Devices AD9515BCPZ

Fairchild

Microchip

NC7WZ07P6X_NL

NC7WZ16P6X_NL

PIC12F629-I/SNG

mem 1k × 14,

RAM size 64 × ±,

20 MHz speed, PIC12F

controller series

¹This BOM is RoHS compliant.

Rev. E | Page 51 of 52

AD9252

Data Sheet

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

7.55

7.50 SQ

7.45

EXPOSED PAD

(BOTTOM VIEW)

8.75

BSC SQ

0.50

0.40

0.30

16

17

33

32

0.22 MIN

TOP VIEW

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-6)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Package

Option

Model¹

Notes

Package Description

AD9252ABCPZ-50

AD9252ABCPZRL7-50

AD9252-50EBZ

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel

Evaluation Board

CP-64-6

2

¹Z = RoHS Compliant Part.

²Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board.

registered trademarks are the property of their respective owners.

D06296-0-12/11(E)

Rev. E | Page 52 of 52


型号：	ADUC7128_15
厂家：	ADI
描述：	Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC 数据分配系统微控制器
文件：	总53页 (文件大小：1804K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUC7128_15 [ADI]

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