ADUM3480ARSZ-RL7 [ADI]
Small, 3.75 kV RMS Quad Digital Isolators (4/0 Channel Directionality);
| 型号： | ADUM3480ARSZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Small, 3.75 kV RMS Quad Digital Isolators (4/0 Channel Directionality) 光电二极管 接口集成电路 |
| 文件： | 总20页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Small, 3.75 kV RMS Quad Digital Isolators
ADuM3480/ADuM3481/ADuM3482
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Up to 25 Mbps data rate (NRZ)
ADuM3480
1
2
20
19
18
17
16
15
14
13
12
11
V
V
DDL2
Low propagation delay: 25 ns typical
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Output default select
20-lead, RoHS-compliant, SSOP package
Safety and regulatory approvals:
UL recognition: 3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DDL1
GND
GND
2
1
IA
IB
IC
ID
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
3
V
V
V
V
V
V
V
V
OA
OB
OC
OD
4
5
6
7
NC
CTRL
2
REG
REG
8
V
V
V
DD1
DD2
DDC2
9
V
DDC1
10
GND
GND
1
2
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM = 560 V peak
Figure 1. ADuM3480
APPLICATIONS
ADuM3481
1
2
20
19
18
17
16
15
14
13
12
11
V
V
DDL2
DDL1
General-purpose multichannel isolation
SPI interface/data converter isolation
Industrial field bus isolation
GND
V
GND
1
2
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
3
V
IA
IB
IC
OA
4
V
V
V
V
V
OB
OC
ID
GENERAL DESCRIPTION
5
The ADuM3480/ADuM3481/ADuM34821 are quad-channel
digital isolators based on the Analog Devices, Inc., iCoupler®
technology. Combining high speed CMOS and monolithic air
core transformer technology, these isolation components provide
outstanding performance characteristics superior to alternatives
such as optocoupler devices and other integrated couplers. With
typical propagation delay reduced to 25 ns, pulse width
distortion is also halved.
6
V
OD
7
CTRL
V
CTRL
1
2
REG
REG
8
V
DD1
DD2
9
V
V
DDC1
DDC2
10
GND
GND
1
2
Figure 2. ADuM3481
ADuM3482
The four channels of the ADuM3480/ADuM3481/ADuM3482
are available in a variety of channel configurations with two data
rate grades up to 25 Mbps (see the Ordering Guide section). All
models use separate core and I/O power supplies. The core
operates between 3.0 V and 5.5 V, whereas the I/O supply can
range from 1.8 V to 5.5 V. If I/O operation is required within
the range of the core supply, the two supplies can be tied together
to allow single-supply operation. When the I/O must interface
with logic levels that are different from the core supply voltage,
the I/O supply operates independently of the core supply over
its wider range. The minimum I/O supply voltage is 1.8 V, which
allows compatibility with low voltage logic. Both core and I/O
supplies are required for proper operation.
1
2
20
19
18
17
16
15
14
13
12
11
V
V
DDL1
DDL2
GND
GND
1
IA
IB
2
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
3
V
V
V
V
V
V
OA
OB
IC
4
5
V
V
OC
OD
6
ID
7
CTRL
V
CTRL
1
2
REG
REG
8
V
DD1
DD2
9
V
V
DDC1
DDC2
10
GND
GND
1
2
Figure 3. ADuM3482
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. A
Document Feedback
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Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM3480/ADuM3481/ADuM3482
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 10
Absolute Maximum Ratings ......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions......................... 12
Typical Performance Characteristics ........................................... 15
Applications Information.............................................................. 17
Supply Voltages........................................................................... 17
Printed Circuit Board Layout ................................................... 17
Propagation Delay Related Parameters ................................... 17
DC Correctness and Magnetic Field Immunity..................... 17
Power Consumption .................................................................. 18
Insulation Lifetime..................................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—1.8 V Operation ............................ 7
Package Characteristics ............................................................... 9
Regulatory Information............................................................... 9
Regulatory Approvals................................................................... 9
Insulation and Safety Related Specifications ............................ 9
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 10
REVISION HISTORY
6/14—Rev. 0 to Rev. A
Changed Safety Certification Status from Pending to Approved
(Throughout) .................................................................................... 1
Changes to Table 12.......................................................................... 9
Changed Highest Allowable Overvoltage from 5300 VPEAK to
4000 VPEAK ........................................................................................ 10
Changes to DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 17
Changes to Ordering Guide .......................................................... 20
7/12—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDDL1 = VDD1 = VDDL2 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDDL1, VDD1 ≤ 5.5 V, 4.5 V ≤ VDDL2, VDD2 ≤ 5.5 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
Table 1.
A Grade
Typ
B Grade
Typ
Parameter
Symbol Min
Max
Min
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
1000
40
ns
Within PWD limit
Data Rate
1
90
6
25
33
3
Mbps
ns
ns
ps/°C
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
tPHL, tPLH
PWD
65
7
25
3
tPSK
50
17
Between any two units
tPSKCD
tPSKOD
19
25
5
7
ns
ns
ns
Opposing Direction
Jitter
2
2
Table 2.
1 Mbps—A, B Grades
25 Mbps—B Grade
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT
ADuM3480
IDD1
2.0
0.11
5.1
0.2
2.8
0.14
4.3
0.18
3.5
0.16
3.5
0.16
2.9
0.4
6.9
0.7
3.0
0.5
5.7
0.6
4.1
0.5
4.7
0.65
8.6
0.2
6.0
2.1
7.9
0.7
6.7
1.6
7.3
1.2
7.3
1.2
12
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDDL1
IDD2
IDDL2
IDD1
IDDL1
IDD2
IDDL2
IDD1
IDDL1
IDD2
0.6
7.5
4.8
10
1.4
7.8
3.2
8.8
2.4
8.8
2.4
CL = 0 pF
CL = 0 pF
CL = 0 pF
CL = 0 pF
CL = 0 pF
ADuM3481
ADuM3482
IDDL2
Rev. A | Page 3 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
Table 3.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High
VIH
VIL
0.7 VDDLx
V
V
Logic Low
0.3 VDDLx
Output Voltages
Logic High
VOH
VOL
II
VDDLx − 0.1
VDDLx − 0.4
5.0
4.8
0.0
0.2
V
V
V
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0V ≤ VIx ≤ VDDLx, 0V ≤ VCTRLx ≤ VDDLx
Logic Low
0.1
0.4
+10
Input Current per Channel
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side
I/O Input
−10
+0.01
µA
IDDI (Q)
0.50
0.027
1.26
0.60
0.05
1.7
mA
mA
mA
mA
IDDIL (Q)
IDDO (Q)
IDDOL (Q)
Regulator Output Side
I/O Output
0.031
0.10
Dynamic Supply Current
Regulator Input Side
I/O Input
Regulator Output Side
I/O Output
IDDI (D)
0.070
0.90
0.010
0.020
mA/Mbps
µA/Mbps
mA/Mbps
mA/Mbps
IDDIL (D)
IDDO (D)
IDDOL (D)
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
tR/tF
|CM|
2.5
35
ns
kV/µs
10% to 90%
VIx = VDDLx, VCM = 1000 V, transient
magnitude = 800 V
25
Refresh Period
tr
1.66
µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 4 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All typical specifications are at TA = 25°C, VDDL1 = VDD1 = VDDL2 = VDD2 = 3.0 V. Minimum/maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDDL1,VDD1 ≤ 3.6 V, 3.0 V ≤ VDDL2, VDD2 ≤ 3.6 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4.
A Grade
Typ
B Grade
Typ
Parameter
Symbol Min
Max
Min
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
1000
40
ns
Within PWD limit
Data Rate
1
99
12
25
38
5
Mbps
ns
ns
ps/°C
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
tPHL, tPLH
PWD
71
2
7
28
3
3
tPSK
58
20
Between any two units
tPSKCD
tPSKOD
20
26
6
9
ns
ns
ns
Opposing Direction
Jitter
4
3
Table 5.
1 Mbps—A, B Grades
25 Mbps—B Grade
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT
ADuM3480
IDD1
1.4
0.08
4.9
0.14
2.3
0.09
4.0
0.12
3.2
0.11
3.2
2.9
0.4
6.7
0.40
3.0
0.4
5.7
0.5
4.2
0.5
4.2
0. 5
8.1
0.13
5.8
1.4
7.5
0.46
6.4
1.1
7.0
0.78
7.0
11
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDDL1
IDD2
IDDL2
IDD1
IDDL1
IDD2
IDDL2
IDD1
IDDL1
IDD2
0.5
7.2
2.5
9.8
1.4
7.5
2.7
8.8
1.7
8.8
1.7
CL = 0 pF
CL = 0 pF
CL = 0 pF
CL = 0 pF
CL = 0 pF
ADuM3481
ADuM3482
IDDL2
0.11
0.78
Rev. A | Page 5 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High
VIH
VIL
0.7 VDDLx
V
V
Logic Low
0.3 VDDLx
Output Voltages
Logic High
VOH
VOL
II
VDDLx − 0.1
VDDLx − 0.4
3.0
2.8
0.0
0.2
V
V
V
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDLx, 0 V ≤ VCTRLx ≤ VDDLx
Logic Low
0.1
0.4
+10
Input Current per Channel
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side
I/O Input
−10
+0.01
µA
IDDI (Q)
0.36
0.019
1.21
0.5
0.050
1.7
mA
mA
mA
mA
IDDIL (Q)
IDDO (Q)
IDDOL (Q)
Regulator Output Side
I/O Output
0.021
0.050
Dynamic Supply Current
Regulator Input Side
I/O Input
Regulator Output Side
I/O Output
IDDI (D)
0.070
0.53
0.010
0.013
mA/Mbps
µA/Mbps
mA/Mbps
mA/Mbps
IDDIL (D)
IDDO (D)
IDDOL (D)
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
tR/tF
|CM|
3
35
ns
kV/µs
10% to 90%
VIx = VDDLx, VCM = 1000 V,
transient magnitude = 800 V
25
Refresh Period
tr
1.66
µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 6 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDDL1 = 1.8 V, VDD1 = 3.0 V, VDDL2 = 1.8 V, VDD2 = 3.0 V. Minimum/maximum specifications
apply over the entire recommended operation range: VDDL1 = 1.8 V, 3.0 V ≤ VDD1 ≤ 3.6 V, VDDL2 = 1.8 V, 3.0 V ≤ VDD2 ≤ 3.6 V,−40°C ≤ TA ≤
+125°C; unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 7.
A Grade
Typ
B Grade
Typ
Parameter
Symbol Min
Max
Min
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
1000
40
ns
Within PWD limit
Data Rate
1
145
32
25
85
30
Mbps Within PWD limit
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
tPHL, tPLH
PWD
86
6
7
43
6
3
ns
ns
50% input to 50% output
|tPLH − tPHL
|
ps/°C
ns
tPSK
93
60
Between any two units
tPSKCD
tPSKOD
40
55
34
37
ns
ns
ns
Opposing Direction
Jitter
4
3
Table 8.
1 Mbps—A, B Grades
25 Mbps—B Grade
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT
ADuM3480
IDD1
1.4
0.04
4.7
0.08
2.3
0.05
3.9
0.07
3.1
0.06
3.1
1.9
0.3
6.5
0.5
2.8
0.35
5.7
0.4
3.8
0.4
4.5
0.40
8.1
0.07
5.7
0.82
7.5
0.25
6.3
0.63
6.9
0.44
6.9
11
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDDL1
IDD2
IDDL2
IDD1
IDDL1
IDD2
IDDL2
IDD1
IDDL1
IDD2
0.4
7.3
1.5
10
0.7
8.0
1.3
8.7
1.1
8.8
1.1
CL = 0 pF
CL = 0 pF
CL = 0 pF
CL = 0 pF
CL = 0 pF
ADuM3481
ADuM3482
IDDL2
0.06
0.44
Rev. A | Page 7 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
Table 9.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High
VIH
VIL
0.7 VDDLx
V
V
Logic Low
0.3 VDDLx
Output Voltages
Logic High
VOH
VOL
II
VDDLx − 0.1
VDDLx − 0.4
1.8
1.6
0.0
0.2
V
V
V
V
IOx = −20 µA, VIx = VIxH
IOx = −2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 2 mA, VIx = VIxL
0V ≤ VIx ≤ VDDLx, 0V ≤ VCTRLx ≤ VDDLx
Logic Low
0.1
0.4
+10
Input Current per Channel
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side
I/O Input
−10
+0.01
µA
IDDI (Q)
0.39
0.010
1.17
0.45
0.025
1.5
mA
mA
mA
mA
IDDIL (Q)
IDDO (Q)
IDDOL (Q)
Regulator Output Side
I/O Output
0.012
0.038
Dynamic Supply Current
Regulator Input Side
I/O Input
Regulator Output Side
I/O Output
IDDI (D)
0.071
0.25
0.010
0.0077
mA/Mbps
µA/Mbps
mA/Mbps
mA/Mbps
IDDIL (D)
IDDO (D)
IDDOL (D)
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
tR/tF
|CM|
3
35
ns
kV/µs
10% to 90%
VIx = VDDLx, VCM = 1000 V,
transient magnitude = 800 V
25
Refresh Period
tr
1.66
µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 8 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Symbol
RI-O
CI-O
Min
Typ Max
1012
2.2
Unit
Ω
pF
Test Conditions/Comments
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
f = 1 MHz
CI
4.0
pF
IC Junction-to-Case Thermal Resistance
θJC
50.5
°C/W
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
1 The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together; Pin 11 to Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM3480/ADuM3481/ADuM3482 are approved by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime
section for the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
REGULATORY APPROVALS
Table 11.
UL
CSA
VDE
Recognized under the UL 1577
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
component recognition program1
Single protection, 3750 V rms
isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (565 V peak)
maximum working voltage
Reinforced insulation, 560 V peak
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM3480/ADuM3481/ADuM3482 is proof tested by applying an insulation test voltage of ≥4500 V rms for 1 second (current
leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, each of the ADuM348x is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 second (partial discharge
detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 12.
Parameter
Symbol
Value
3750
>5.1
Unit
V rms
mm
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air, in the plane of the PCB
Measured from input terminals to output terminals,
shortest distance path along body
Distance through insulation
L(I01)
L(I02)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
>5.1
mm
0.017 min mm
Tracking Resistance (Comparative Tracking Index) CTI
Isolation Group
>400
II
V
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. A | Page 9 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 13.
Description
Test Conditions/Comments
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
560
1050
VPEAK
VPEAK
VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = Vpd(m)
1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Vpd(m)
Vpd(m)
840
672
VPEAK
VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Withstand Isolation Voltage
VIOTM
VISO
4000
3750
VPEAK
VRMS
1 minute withstand rating
Surge Isolation Voltage
Safety Limiting Values
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 4)
VIOSM
6000
VPEAK
Case Temperature
Total Power Dissipation
Insulation Resistance at TS
TS
IS1
RS
150
2.47
>109
°C
W
Ω
VIO = 500 V
3.0
2.5
2.0
1.5
1.0
0.5
0
RECOMMENDED OPERATING CONDITIONS
Table 14.
Parameter
Symbol
TA
VDDL1, VDDL2
VDD1, VDD2
Min Max
Unit
Operating Temperature
Supply Voltages1
−40 +125 °C
1.8
3.0
5.5
5.5
1.0
V
V
ms
Input Signal Rise and Fall
Times
1 See the DC Correctness and Magnetic Field Immunity section for information
on immunity to external magnetic fields.
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. A | Page 10 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 16. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
Applicable
Table 15.
Parameter
Rating
Parameter
Max
Unit
Certification
Supply Voltages (VDD1, VDD2, VDDL1
,
−0.5 V to +7.0 V
AC Voltage, Bipolar
Waveform
AC Voltage, Unipolar
Waveform
565
V peak
All certifications
V
DDL2, VDDC1, VDDC2
Input Voltages (VIA, VIB, VIC, VID, VCTRL1
VCTRL2
)
,
−0.5 V to VDDI + 0.5 V
848
V peak
)
Output Voltages (VOA, VOB, VOC, VOD)
Average Output Current per Pin1
Common-Mode Transients2
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
−100 kV/μs to +100 kV/μs
−65°C to +150°C
DC Voltage
848
V peak
1 Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
Storage Temperature (TST) Range
ESD CAUTION
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
1 See Figure 4 for maximum rated current values for various temperatures.
2 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 11 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
20
19
18
17
16
15
14
13
12
11
V
V
DDL1
DDL2
2
GND *
GND *
2
1
3
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
4
ADuM3480
TOP VIEW
5
(Not to Scale)
6
7
NC
CTRL
2
8
V
V
V
DD1
DD2
DDC2
9
V
DDC1
10
GND *
GND *
2
1
NOTES
1. NC = NO CONNECTION. THIS PIN IS NOT
CONNECTED INTERNALLY AND CAN BE LEFT
FLOATING OR CONNECTED TO V
OR GND .
DD1
1
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO PCB SIDE 1 GROUND IS
RECOMMENDED. PIN 11 AND PIN 19 ARE
INTERNALLY CONNECTED. CONNECTING BOTH
TO PCB SIDE 2 GROUND IS RECOMMENDED.
Figure 5. ADuM3480 Pin Configuration
Table 17. ADuM3480 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDDL1
1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1
.
2
GND1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
3
4
5
6
7
8
9
VIA
VIB
VIC
VID
NC
VDD1
VDDC1
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
No Connection. This pin is not connected internally and can be left floating or connected to VDD1 or GND1.
3.0 V to 5.5 V Supply Voltage for Isolator Side 1.
Output Pin of an Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
10
11
12
GND1
GND2
VDDC2
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
Output Pin of an Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
13
14
15
16
17
18
19
VDD2
CTRL2
VOD
VOC
VOB
3.0 V to 5.5 V Supply Voltage for Isolator Side 2.
Select Side 2 Output Default Level. Low = default output low. High = default output high.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
VOA
GND2
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
20
VDDL2
1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2
.
Rev. A | Page 12 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
1
2
20
19
18
17
16
15
14
13
12
11
V
V
DDL1
DDL2
GND *
GND *
1
2
3
V
V
V
V
V
V
V
IA
IB
IC
OA
OB
OC
ID
4
ADuM3481
TOP VIEW
5
(Not to Scale)
6
V
OD
7
CTRL
CTRL
2
1
8
V
V
DD1
DD2
DDC2
9
V
V
DDC1
10
GND *
GND *
2
1
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO PCB SIDE 1 GROUND IS
RECOMMENDED. PIN 11 AND PIN 19 ARE
INTERNALLY CONNECTED. CONNECTING BOTH
TO PCB SIDE 2 GROUND IS RECOMMENDED.
Figure 6. ADuM3481 Pin Configuration
Table 18. ADuM3481 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDDL1
1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1
.
2
GND1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
3
4
5
6
7
8
9
VIA
VIB
VIC
VOD
CTRL1
VDD1
VDDC1
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Select Side 1 Output Default Level. Low = default output low. High = default output high.
3.0 V to 5.5 V Supply Voltage for Isolator Side 1.
Output Pin of an Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
10
11
12
GND1
GND2
VDDC2
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
Output Pin of an Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
13
14
15
16
17
18
19
VDD2
CTRL2
VID
VOC
VOB
3.0 V to 5.5 V Supply Voltage for Isolator Side 2.
Select Side 2 Output Default Level. Low = default output low. High = default output high.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
VOA
GND2
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
20
VDDL2
1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2
.
Rev. A | Page 13 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
1
2
20
19
18
17
16
15
14
13
12
11
V
V
DDL2
DDL1
GND *
GND *
2
1
3
V
V
V
V
V
V
IA
IB
OA
OB
IC
4
ADuM3482
TOP VIEW
5
V
OC
OD
(Not to Scale)
6
V
ID
7
CTRL
CTRL
2
1
8
V
V
V
DD1
DD2
DDC2
9
V
DDC1
10
GND *
GND *
2
1
*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO PCB SIDE 1 GROUND IS
RECOMMENDED. PIN 11 AND PIN 19 ARE
INTERNALLY CONNECTED. CONNECTING BOTH
TO PCB SIDE 2 GROUND IS RECOMMENDED.
Figure 7. ADuM3482 Pin Configuration
Table 19. ADuM3482 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDDL1
1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1
.
2
GND1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
3
4
5
6
7
8
9
VIA
VIB
VOC
VOD
CTRL1
VDD1
VDDC1
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Select Side 1 Output Default Level. Low = default output low. High = default output high.
3.0 V to 5.5 V Supply Voltage for Isolator Side 1.
Output Pin of Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not
use this pin to power external circuits.
10
11
12
GND1
GND2
VDDC2
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
Output Pin of Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not
use this pin to power external circuits.
13
14
15
16
17
18
19
VDD2
CTRL2
VID
VIC
VOB
3.0 V to 5.5 V Supply Voltage for Isolator Side 2.
Select Side 2 Output Default Level. Low = default output low. High = default output high.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
VOA
GND2
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
20
VDDL2
1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2
.
Rev. A | Page 14 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 3.3V/V
= 1.8V
DD
DDL
2.0
V
= 3.3V/V
= 3.3V
DD
DDL
1.5
V
= 5V/V
= 1.8V
DD
DDL
V
= 5V/V
= 5V
DD
DDL
1.0
0.5
0
0
5
10
15
20
25
0
5
10
15
20
25
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical VDDI = 5 V Supply Current per Input Channel vs. Data Rate
for 5 V and 1.8 V I/O Operation
Figure 11. Typical VDDO = 3.3 V Supply Current per Output Channel vs. Data
Rate for 3.3 V and 1.8 V I/O Operation
2.5
2.0
1.5
0.06
0.05
0.04
V
= 5V
DDL
0.03
0.02
0.01
0
V
= 3.3V/V
= 1.8V
DD
DDL
V
= 3.3V
= 1.8V
DDL
DDL
1.0
0.5
0
V
V
= 3.3V/V
= 3.3V
10
DD
DDL
0
5
15
20
25
0
5
10
15
20
25
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 9. Typical VDDI = 3.3 V Supply Current per Input Channel vs. Data Rate
for 3.3 V, and 1.8 V I/O Operation
Figure 12. Typical VDDIL Input Supply Current vs. Data Rate for 5 V, 3.3 V, and
1.8 V Operation
1.6
0.6
0.5
0.4
V
= 5V/V
= 1.8V
DD
DDL
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 5V/V
= 5V
DD
DDL
V
= 5V
DDL
0.3
0.2
0.1
0
V
= 3.3V
DDL
V
= 1.8V
DDL
0
5
10
15
20
25
0
5
10
15
20
25
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 10. Typical VDDO = 5 V Supply Current per Output Channel vs. Data
Rate for 5 V and 1.8 V I/O Operation
Figure 13. Typical VDDOL Output Supply Current vs. Data Rate
for 5 V, 3.3 V, and 1.8 V, CL = 0 pF Operation
Rev. A | Page 15 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
1.6
1.4
1.2
V
= 5V
DDL
1.0
0.8
0.6
0.4
0.2
0
V
= 3.3V
DDL
V
= 1.8V
DDL
0
5
10
15
20
25
DATA RATE (Mbps)
Figure 14. Typical VDDOL Output Supply Current vs. Data Rate
for 5 V, 3.3 V, and 1.8 V, CL = 15 pF Operation
Rev. A | Page 16 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
APPLICATIONS INFORMATION
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to follow this design guideline can allow voltage differentials
between pins that exceed the absolute maximum ratings of the
device during high voltage transients, which can lead to latch-up or
permanent damage.
SUPPLY VOLTAGES
The ADuM3480/ADuM3481/ADuM3482 devices are built
around a fixed voltage internal data transfer core. The core
voltage is 2.7 V, which is generated by regulating the VDD1 and
V
DD2 voltages with an internal LDO. To ensure proper headroom
for the LDO, the VDD1 and VDD2 inputs must be in the 3.0 V to 5.5 V
range. Additional pins, VDDC1 and VDDC2, are provided for direct
bypass of the LDO output, ensuring clean stable core operation.
Bypass capacitors to ground of between 0.01 μF and 0.1 μF are
required for each of these supply or dedicated bypass pins.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high to low transition may
differ from the propagation delay time of a low to high transition.
The ADuM3480/ADuM3481/ADuM3482 provide independent
supplies for the I/O buffers, VDDL1 and VDDL2, which have wider
operating ranges than that required for the core. This allows the
I/O supply voltage to range between 1.8 V and 5.5 V. The VDDLx
supplies must also be bypassed with between 0.01 μF and 0.1 μF
capacitors.
INPUT (V
)
50%
Ix
tPLH
tPHL
Having independent power supplies for the I/O and core allows
several power configurations depending on the I/O voltage
required and the available power supply rails. If one power
supply is available, the VDDx and VDDLx pins can be connected
together and operate between 3.0 V and 5.5 V. If lower I/O
supply voltage is required, to interface with low voltage logic,
two supply rails are required. For example, if the I/O is 1.8 V
logic, the VDDLx pin can be connected to a 1.8 V supply rail. The
core supply voltage for VDDx requires an input of between 3.0 V and
5.5 V, so an available 3.3 V or 5 V supply rail can be used. The I/O
and core supply voltage on each side are independent and different
configurations can be used on each side of the device.
OUTPUT (V
)
50%
Ox
Figure 16. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel to channel matching refers to the maximum amount of
time that the propagation delay differs between channels within
a single ADuM3480/ADuM3481/ADuM3482 component.
Propagation delay skew refers to the maximum amount of time
that the propagation delay differs between multiple ADuM3480/
ADuM3481/ADuM3482 components operating under the same
conditions.
PRINTED CIRCUIT BOARD LAYOUT
The ADuM3480/ADuM3481/ADuM3482 digital isolator requires
no external interface circuitry for the logic interfaces. Power supply
bypassing to the local ground is required at all four power supply
pins, VDD1, VDDL1, VDD2, and VDDL2, as well as at the two internal
regulator bypass pins: VDDC1 and VDDC2 (see Figure 15). Placement
of the recommended bypass capacitors is shown in Figure 15. The
capacitor value should be between 0.01 μF and 0.1 μF. The total lead
length between both ends of the capacitor and the input power
supply pin should not exceed 20 mm.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1.7 μs, the current
dc state is sent to the output to ensure dc correctness at the output.
If the decoder receives no pulses for more than about 5 μs, the
input side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 17,
Table 18, or Table 19) by the watchdog timer circuit.
V
GND
V
DDL2
DDL1
GND
1
IA
IB
2
V
V
V
V
V
V
OA
OB
V
V
/V
/V
IC OC
OC IC
/V
/V
OD ID
ID OD
CTRL
CTRL
2
1
V
V
V
DD1
DD2
V
DDC1
DDC2
GND
GND
2
1
Figure 15. Recommended Printed Circuit Board (PCB) Layout
Rev. A | Page 17 of 20
ADuM3480/ADuM3481/ADuM3482
Data Sheet
The limitation on the magnetic field immunity of the device is set
by the condition in which induced voltage in the receiving coil
of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines such conditions.
The ADuM3480/ADuM3481/ADuM3482 are examined in a
3 V operating condition because it represents the most
susceptible mode of operation of these products.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3480/ADuM3481/ADuM3482 transformers. Figure 18
expresses these allowable current magnitudes as a function of
frequency for selected distances. The ADuM3480/ADuM3481/
ADuM3482 are very insensitive to external fields. Only extremely
large, high frequency currents that are very close to the component
are a concern. For the 1 MHz example noted, a 1.2 kA current would
need to be placed 5 mm away from the ADuM3480/ADuM3481/
ADuM3482 to affect component operation.
The pulses at the transformer output have an amplitude of
greater than 1.5 V. The decoder has a sensing threshold of
approximately = 1.0 V, thereby establishing a 0.5 V margin
within which induced voltages can be tolerated. The voltage
induced across the receiving coil is given by
1000
DISTANCE = 1m
100
2
V = (−dβ / dt)∑πrn ; n = 1, 2, …, N
where:
10
β is the magnetic flux density.
DISTANCE = 100mm
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
1
Given the geometry of the receiving coil in the ADuM3480/
ADuM3481/ADuM3482 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 17.
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
100
Figure 18. Maximum Allowable Current for Various Current to ADuM3480
Spacings
10
1
Note that at combinations of strong magnetic field and high
frequency, or any loops formed by PCB traces, can induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Take care to avoid PCB structures that
form loops.
0.1
POWER CONSUMPTION
The supply current at a given channel of the ADuM3480/
ADuM3481/ADuM3482 isolator is a function of the supply
voltage, the data rate of the channel, and the output load of the
channel.
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Calculating IDD1 or IDD2
Figure 17. Maximum Allowable External Magnetic Flux Density
For each input channel, assuming worst case I/O voltage, the
supply current is given by
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces a voltage
of 0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. If such
an event occurs, with the worst-case polarity, during a transmitted
pulse, it reduces the received pulse from >1.0 V to 0.75 V. This is
still well above the 0.5 V sensing threshold of the decoder.
I
DDI = IDDI (Q)
RD ≤ 2.5 × RR
RD > 2.5 × RR
IDDI = IDDI (D) × (RD−RR) + IDDI (Q)
For each output channel, the supply current is given by
DDO = IDDO (D) × RD + IDDO (Q)
I
Rev. A | Page 18 of 20
Data Sheet
ADuM3480/ADuM3481/ADuM3482
Calculating IDDL1 or IDDL2
Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 16 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working voltages.
In many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
For each input channel, the supply current is given by
IDDIL = IDDIL (D) × RD + IDDIL (Q)
For each output channel, the supply current is given by
CL ×VDDOL ×10−3
IDDOL
=
IDDOL (D)
+
RD + IDDOL (Q)
2
where:
CL is the output load capacitance (pF).
DDOL is the output supply voltage (V).
The insulation lifetime of the
ADuM3480/ADuM3481/ADuM3482 depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 19,
Figure 20,and Figure 21 illustrate these different isolation
voltage waveforms.
V
RD is the input logic signal data rate (Mbps); it is twice the input
frequency, expressed in units of MHz.
RR is the input stage refresh rate (Mbps) = 1/tr (µs)
I
DDI (Q), IDDIL (Q), IDDO (Q), IDDOL (Q) are the specified input and output
quiescent supply currents (mA).
DDI (D), IDDIL (D), IDDO (D), and IDDOL(D) are the input and output
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
I
dynamic supply currents per channel (mA/Mbps).
As inputs and outputs can be present on each side of the device,
the calculations refer to the current drawn from the local supply.
For example, if an output is on Side 2 of a part, the IDDOL current
is drawn from the VDDL2 pin of the part. The IDDL1 and IDDL2 currents
are dependent on VDDL1 and VDDL2, the data rate, and the capacitive
load. It is nearly independent of the value of the core supplies.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 16 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms to
either the unipolar ac or dc voltage case. Treat any cross-insulation
voltage waveform that does not conform to Figure 19, Figure 20,
or Figure 21 as a bipolar ac waveform, and limit its peak voltage
to the 50-year lifetime voltage value listed in Table 16.
To calculate the total IDD1, IDDL1, IDD2, and IDDL2 supply current, the
supply currents for each input and output channel corresponding to
VDD1, VDDL1, VDD2, and VDDL2 are calculated and totaled, or read from
Figure 8 through Figure 14.
The input current for the regulated core power supplies is
nearly independent of the I/O voltage, and scales with data rate.
The IDDI current is not linear down to dc, but goes to a minimum
value between about 2.5 × RR and dc. This is due to the refresh
circuit establishing a minimum data rate; the values in Figure 8 and
Figure 9 and the quiescent currents in Table 3, Table 6, and Table 9
approximate the current in this region. VDDI, VDDO, VDDIL, and
Note that the voltage presented in Figure 20 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The limiting
value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE
0V
V
DDOL represent the voltages on the core and I/O power supply
Figure 19. Bipolar AC Waveform
RATED PEAK VOLTAGE
pins for the input and output of a given channel. I represents an
input, O is an output, and L denotes an I/O supply.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation depends on the characteristics of the voltage waveform
applied across the insulation. In addition to the testing performed
by the regulatory agencies, Analog Devices carries out an extensive
set of evaluations to determine the lifetime of the insulation
structure within the ADuM3480/ADuM3481/ADuM3482.
0V
Figure 20. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 21. DC Waveform
Analog Devices performs accelerated life testing using voltage
levels that are higher than the rated continuous working voltage.
Rev. A | Page 19 of 20
ADuM3480/ADuM3481/ADuM3482
OUTLINE DIMENSIONS
Data Sheet
7.50
7.20
6.90
11
20
5.60
5.30
5.00
8.20
7.80
7.40
1
10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
0.05 MIN
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
SEATING
PLANE
COPLANARITY
0.65 BSC
0.10
COMPLIANT TO JEDEC STANDARDS MO-150-AE
Figure 22. 20-Lead Standard Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
No. of Inputs, No. of Inputs, Maximum Max Prop
Temperature
Range
Package
Model1
VDD1 Side
VDD2 Side
Data Rate
Delay, 5 V
Package Description
Option
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
ADuM3480ARSZ
ADuM3480ARSZ-RL7
ADuM3480BRSZ
ADuM3480BRSZ-RL7
ADuM3481ARSZ
ADuM3481ARSZ-RL7
ADuM3481BRSZ
ADuM3481BRSZ-RL7
EVAL-ADuM3481EBZ
ADuM3482ARSZ
ADuM3482ARSZ-RL7
ADuM3482BRSZ
4
4
4
4
3
3
3
3
0
0
0
0
1
1
1
1
1 Mbps
1 Mbps
25 Mbps
25 Mbps
1 Mbps
1 Mbps
25 Mbps
25 Mbps
90 ns
90 ns
33 ns
33 ns
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
20-Lead SSOP
20-Lead SSOP, 7” Reel
20-Lead SSOP
20-Lead SSOP, 7” Reel
20-Lead SSOP
20-Lead SSOP, 7” Reel
20-Lead SSOP
20-Lead SSOP, 7” Reel
Evaluation Board
20-Lead SSOP
20-Lead SSOP, 7” Reel
20-Lead SSOP
90 ns
90 ns
33 ns
33 ns
2
2
2
2
2
2
2
2
1 Mbps
1 Mbps
25 Mbps
25 Mbps
90 ns
90 ns
33 ns
33 ns
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
RS-20
RS-20
RS-20
RS-20
ADuM3482BRSZ-RL7
1 Z = RoHS Compliant Part.
20-Lead SSOP, 7” Reel
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10459-0-6/14(A)
Rev. A | Page 20 of 20
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