ADUM5241 [ADI]

Dual-Channel Isolators with Integrated DC/DC Converter, 50 mW; 双通道隔离器,集成DC / DC转换器, 50毫瓦
ADUM5241
型号: ADUM5241
厂家: ADI    ADI
描述:

Dual-Channel Isolators with Integrated DC/DC Converter, 50 mW
双通道隔离器,集成DC / DC转换器, 50毫瓦

转换器
文件: 总10页 (文件大小:142K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Dual-Channel Isolators with  
Integrated DC/DC Converter, 50 mW  
ADuM5240/ADuM5241/ADuM5242  
GENERAL DESCRIPTION  
Preliminary Technical Data  
FEATURES  
Integrated isolated DC/DC converter  
Regulated 5V/10 mA output  
The ADuM524x1 are dual-channel digital isolators having an  
integrated DC/DC converter. Based on Analog Devices’  
iCoupler® technology, the DC/DC converter provides up to  
50 mW of regulated, isolated power at +5V. This eliminates the  
need for a separate isolated DC/DC converter in low-power  
isolated designs. Analog Devices’ chip-scale transformer  
iCoupler® technology is used both for the isolation of the logic  
signals as well as for the DC/DC converter. The result is a small  
form-factor total-isolation solution.  
Dual dc-to-10 Mbps (NRZ) signal isolation channels  
Narrow body SOIC 8-lead package  
High temperature operation: 105°C  
Precise timing characteristics:  
3 ns maximum pulse-width distortion  
3 ns maximum channel-to-channel matching  
70 ns maximum propagation delay  
High common-mode transient immunity: > 25 kV/μs  
Safety and regulatory approvals (pending)  
UL recognition  
ADuM524x units may be used in combination or with other  
iCoupler products to achieve greater channel counts.  
2500 V rms for 1 minute per UL 1577  
CSA component acceptance notice #5A  
VDE certificate of conformity  
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01  
DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000  
VIORM = 425 V peak  
The ADuM524x isolators provide two independent isolation  
channels in a variety of channel configurations and data rates  
(see Ordering Guide) operating off a 5V input supply.  
1 Protected by U.S. Patents 5,952,849 6,873,065 and 7,075,329 Other patents  
pending.  
FUNCTIONAL BLOCK DIAGRAM  
rect.  
osc.  
rect.  
osc.  
rect.  
osc.  
1
2
1
2
1
2
8
7
8
7
8
7
VDD  
VIA  
VISO  
VOA  
VOB  
VDD  
VOA  
VISO  
VIA  
VDD  
VOA  
VISO  
VIA  
ENCODE  
DECODE  
DECODE  
DECODE  
ENCODE  
ENCODE  
ENCODE  
ENCODE  
DECODE  
DECODE  
DECODE  
ENCODE  
3
4
3
4
3
4
6
5
6
5
6
5
VIB  
VOB  
VIB  
VOB  
VIB  
GND  
GNDISO  
GND  
GND  
GNDISO  
GNDISO  
Figure 1. ADuM5240 Functional Block  
Diagram  
Figure 2. ADuM5241 Functional Block  
Diagram  
Figure 3. ADuM5242 Functional Block  
Diagram  
Rev. PrN  
November 17, 2006  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  
ADuM5240/ADuM5241/ADuM5242  
Preliminary Technical Data  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS1  
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range,  
unless otherwise noted. All typical specifications are at TA = 25°C, VDD = 5.0 V, VISO = 5.0 V.  
Table 1.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
With DC/DC Converter Enabled:  
DC to 2 Mbps Data Rate:  
Setpoint  
Maximum Output Current  
Input Supply Current2  
At Maximum Output Current  
With No Output Current  
10 Mbps Data Rate:  
Setpoint  
Logic signal freq. ≤ 1 MHz  
VISO  
IISO(max)  
5.0  
10  
5.5  
V
mA  
IDD(max)  
IDD(0)  
125  
95  
mA  
mA  
IISO = 10 mA, Logic signal freq. ≤ 1 MHz  
IISO= 0  
Logic signal freq. = 5 MHz  
VISO  
4.5  
5.5  
V
Maximum Output Current  
ADuM5240  
ADuM5241  
IISO(max, 10)  
8.5  
7.0  
5.7  
mA  
mA  
mA  
ADum5242  
Input Supply Current3  
At Maximum Output Current  
With No Output Current  
With DC/DC Converter Disabled:  
DC to 2 Mbps  
IDD(max)  
IDD(0)  
125  
100  
mA  
mA  
IISO(max, 10), Logic signal freq. = 5 MHz  
IISO = 0, Logic signal freq. = 5 MHz  
IDD(2)  
Logic signal freq.≤1 MHz  
2
Input Supply Current, VDD  
ADuM5240  
ADuM5241  
ADuM5242  
3.3  
2.7  
2.2  
mA  
mA  
mA  
2
Input Supply Current, VISO  
ADuM5240  
ADuM5241  
ADum5242  
10 Mbps  
1.6  
3.1  
2.5  
mA  
mA  
mA  
IDD(10)  
IISO=0, Logic signal freq.≤5 MHz  
2
Input Supply Current, VDD  
ADuM5240  
ADuM5241  
ADum5242  
6.1  
5.0  
4.0  
mA  
mA  
mA  
2
Input Supply Current, VISO  
ADuM5240  
ADuM5241  
ADuM5242  
3.8  
5.0  
6.2  
4.5  
mA  
mA  
mA  
V
Enable Threshold4  
VENABLE  
Disable Threshold4  
Input Currents  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VDISABLE  
IIA, IIB  
VIH  
VIL  
VOAH, VOBH  
4.0  
−10  
4.5  
+10  
0.7 VISO  
V
μA  
V
V
V
+0.01  
0.3 VISO  
VDD, − 0.1 5.0  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
VDD, − 0.5 4.8  
V
V
V
Logic Low Output Voltages  
VOAL, VOBL  
0.0  
0.0  
0.1  
0.4  
Rev. PrN | Page 2 of 10  
Preliminary Technical Data  
ADuM5240/ADuM5241/ADuM5242  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
AC SPECIFICATIONS  
Minimum Pulse Width5  
Maximum Data Rate6  
PW  
100  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
25  
Propagation Delay7  
tPHL, tPLH  
PWD  
tPSK  
70  
3
45  
3
7
Pulse-Width Distortion, |tPLH − tPHL  
Propagation Delay Skew8  
Channel-to-Channel Matching,  
Codirectional Channels9  
|
tPSKCD  
ns  
Channel-to-Channel Matching,  
tPSKCD  
15  
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels10  
Ripple11  
200  
50  
50  
2.5  
35  
mVP-P  
ns  
ns  
ns  
kV/μs  
Enable Time12  
TENABLE  
TDISABLE  
tR/tF  
Disable Time12  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
at Logic High Output  
Common-Mode Transient Immunity  
at Logic Low Output  
Refresh Frequency  
CL = 15 pF, CMOS signal levels  
VIx = VDD, VISO, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, V = 1000 V,  
transient magnitude = 800 V  
|CMH|  
25  
25  
|CML|  
fr  
35  
kV/μs  
MHz  
1.0  
1 All voltages are relative to their respective ground.  
2 Supply current values are specified with no load present on the digital outputs.  
3 Supply current values are specified with no load present on the digital outputs.  
4 Enable/disable threshold is the voltage at which the internal DC/DC converter is enabled/disabled.  
5 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.  
6 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.  
7 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
8 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output  
load within the recommended operating conditions.  
9 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.  
10 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.  
11 Ripple occurs at frequency corresponding to the input signal data rate or the refresh frequency for data rates below 1Mbps.  
12 Enable time is the duration from when input supply voltage rises above the enable threshold to when the internal DC/DC converter starts charging an external load.  
Disable time is the duration from when the input supply voltage drops below the disable threshold to when the internal DC/DC converter stops charging an external  
load  
PACKAGE CHARACTERISTICS  
Table 2.  
Parameter  
Symbol  
RI-O  
CI-O  
Min  
Typ  
1012  
1.0  
Max  
Unit  
Ω
pF  
Test Conditions  
Resistance (Input-Output)  
Capacitance (Input-Output)  
Input Capacitance  
f = 1 MHz  
CI  
4.0  
pF  
IC Junction-to-Air Thermal Resistance  
θJA  
150  
°C/W  
Rev. PrN | Page 3 of 10  
ADuM5240/ADuM5241/ADuM5242  
Preliminary Technical Data  
REGULATORY INFORMATION  
The ADuM5240/5241/5242 will be approved by the following organizations upon product release:  
Table 3.  
UL (pending)  
CSA (pending)  
VDE (pending)  
Recognized under 1577 Component  
Recognition Program1  
Approved under CSA Component  
Acceptance Notice #5A  
Certified according to  
DIN EN 60747-5-2 (VDE 0884 Part 2):2003-012  
Basic insulation, 2500 V rms isolation  
rating  
Basic insulation per CSA 60950-1-03  
and IEC 60950-1, 300 V rms (425 V  
peak) maximum working voltage  
Basic insulation,300 V rms (425 V peak) maximum  
working voltage  
File E214100  
File 205078  
File 2471900-4880-0001  
1 In accordance with UL1577, each ADuM524x is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).  
2 In accordance with DIN EN 60747-5-2, each ADuM524x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection  
limit = 5 pC).  
INSULATION AND SAFETY-RELATED SPECIFICATIONS  
Table 4.  
Parameter  
Symbol Value  
Unit  
V rms  
mm  
Conditions  
Rated Dielectric Insulation Voltage  
Minimum External Air Gap (Clearance)  
2500  
1 minute duration  
Measured from input terminals to output terminals, shortest  
distance through air  
L(I01)  
4.90 min  
Minimum External Tracking (Creepage) L(I02)  
4.01 min  
0.017 min  
>175  
mm  
mm  
V
Measured from input terminals to output terminals, shortest  
distance path along body  
Insulation distance through insulation  
Minimum Internal Gap (Internal  
Clearance)  
Tracking Resistance (Comparative  
Tracking Index)  
CTI  
DIN IEC 112/VDE 0303 Part 1  
Isolation Group  
IIIa  
Material Group (DIN VDE 0110, 1/89, Table 1)  
Rev. PrN | Page 4 of 10  
Preliminary Technical Data  
ADuM5240/ADuM5241/ADuM5242  
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS  
Table 5.  
Description  
Symbol Characteristic Unit  
Installation Classification per DIN VDE 0110  
For Rated Mains Voltage ≤ 150 V rms  
I−IV  
For Rated Mains Voltage ≤ 300 V rms  
I−III  
Climatic Classification  
40/105/21  
2
425  
797  
Pollution Degree (DIN VDE 0110, Table 1)  
Maximum Working Insulation Voltage  
Input to Output Test Voltage, Method b1  
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC  
Input to Output Test Voltage, Method a  
After Environmental Tests Subgroup 1  
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC  
After Input and/or Safety Test Subgroup 2/3  
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC  
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)  
VIORM  
VPR  
V peak  
V peak  
VPR  
680  
V peak  
510  
4000  
V peak  
V peak  
VTR  
Safety-Limiting Values (maximum value allowed in the event of a failure; also see the thermal  
derating curve, Figure 4)  
Case Temperature  
Side 1 Current  
Side 2 Current  
TS  
IS1  
IS2  
RS  
150  
160  
170  
>109  
°C  
mA  
mA  
Ω
Insulation Resistance at TS, VIO = 500 V  
Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 425 V peak working voltage.  
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.  
[Figure to be added]  
RECOMMENDED OPERATING CONDITIONS  
Table 6.  
Parameter  
Figure 4. Thermal Derating Curve, Dependence of Safety  
Limiting Values on Case Temperature, per DIN EN 60747-5-  
2
Symbol Min Max Unit  
Operating Temperature  
Supply Voltages1  
TA  
−40 +105 °C  
VDD, DC/DC Conv. Enabled  
VDD, DC/DC Conv. Disabled  
VISO, DC/DC Conv. Disabled  
Input Signal Rise and Fall Times  
Input Supply Slew Rate  
VDD  
VDD  
VISO  
4.5  
2.7  
2.7  
5.5  
4.0  
5.5  
1.0  
10  
V
V
V
ms  
V/ms  
1 All voltages are relative to their respective ground.  
Rev. PrN | Page 5 of 10  
ADuM5240/ADuM5241/ADuM5242  
Preliminary Technical Data  
ABSOLUTE MAXIMUM RATINGS  
Ambient temperature = 25°C, unless otherwise noted.  
Table 7.  
Parameter  
Symbol  
Min  
−55  
−40  
−0.5  
−0.5  
−0.5  
Max  
Unit  
°C  
°C  
V
V
Storage Temperature  
Ambient Operating Temperature  
Supply Voltages1  
Input Voltage1  
Output Voltage1  
Average Output Current, per Pin2  
Common-Mode Transients3  
TST  
TA  
VDD, VISO  
VIA, VIB  
VOA, VOB  
IO  
150  
105  
7.0  
VDD/ISO + 0.5  
VDD/ISO + 0.5  
V
mA  
kV/μs  
−100  
+100  
1 All voltages are relative to their respective ground.  
2 See Figure 4 for maximum rated current values for various temperatures.  
3 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or  
permanent damage.  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;  
Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is  
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on  
the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Table 8. Truth Table, ADuM5240  
VDD State  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
DC/DC  
Converter  
VISO State  
VIA  
Input  
VIB  
Input  
VOA  
Output  
VOB  
Output  
Enabled  
Enabled  
Enabled  
Enabled  
Disabled  
Disabled  
Disabled  
Disabled  
Disabled  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Externally)  
Powered  
(Externally)  
Powered  
(Externally)  
Powered  
(Externally)  
H
H
H
H
L
L
L
L
H
L
L
H
L
L
H
H
L
H
H
L
H
L
H
L
H
L
L
H
L
L
H
H
Unpowered  
Powered  
X
X
X
X
Z
L
Z
L
Unpowered Disabled  
(Externally)  
Unpowered Disabled  
Unpowered  
X
X
Z
Z
Rev. PrN | Page 6 of 10  
Preliminary Technical Data  
ADuM5240/ADuM5241/ADuM5242  
Table 9. Truth Table, ADuM5241  
VDD State  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
DC/DC  
Converter  
VISO State  
VIA  
Input  
VIB  
Input  
VOA  
Output  
VOB  
Output  
Enabled  
Enabled  
Enabled  
Enabled  
Disabled  
Disabled  
Disabled  
Disabled  
Disabled  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Externally)  
Powered  
(Externally)  
Powered  
(Externally)  
Powered  
(Externally)  
H
H
H
H
L
L
L
L
H
L
L
H
L
L
H
H
L
H
H
L
H
L
H
L
H
L
L
H
L
L
H
H
Unpowered  
Powered  
X
X
X
X
L
Z
Z
L
Unpowered Disabled  
(Externally)  
Unpowered Disabled  
Unpowered  
X
X
Z
Z
Table 10. Truth Table, ADuM5242  
VDD State  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
DC/DC  
Converter  
VISO State  
VIA  
Input  
VIB  
Input  
VOA  
Output  
VOB  
Output  
Enabled  
Enabled  
Enabled  
Enabled  
Disabled  
Disabled  
Disabled  
Disabled  
Disabled  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Internally)  
Powered  
(Externally)  
Powered  
(Externally)  
Powered  
(Externally)  
Powered  
(Externally)  
H
H
H
H
L
L
L
L
H
L
L
H
L
L
H
H
L
H
H
L
H
L
H
L
H
L
L
H
L
L
H
H
Unpowered  
Powered  
X
X
X
X
L
Z
L
Z
Unpowered Disabled  
(Externally)  
Unpowered Disabled  
Unpowered  
X
X
Z
Z
Rev. PrN | Page 7 of 10  
ADuM5240/ADuM5241/ADuM5242  
Preliminary Technical Data  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VDD  
VISO  
VDD  
VOA  
VOB  
VISO  
VIA  
VDD  
VIA  
VIB  
VISO  
VOA  
VOB  
ADuM5240  
TOP VIEW  
(Not to Scale)  
VOA  
VIB  
ADuM5241  
TOP VIEW  
(Not to Scale)  
VIA  
ADuM5242  
TOP VIEW  
(Not to Scale)  
VOB  
VIB  
GND  
GNDISO  
GND  
GNDISO  
GND  
GNDISO  
Figure 5. ADuM5240 Pin  
Configuration  
Figure 6. ADuM5241 Pin  
Configuration  
Figure 7. ADuM5242 Pin  
Configuration  
Table 11. ADuM5240 Pin Function Descriptions  
Table 13. ADuM5242 Pin Function Descriptions  
Pin  
No.  
Pin  
No.  
Mnemonic Function  
Mnemonic Function  
1
VDD1  
Supply Voltage for Isolator Side 1,  
4.5 V to 5.5 V (DC/DC Enabled), 2.7 V to 4.0  
V (DC/DC Disabled)  
1
VDD1  
Supply Voltage for Isolator Side 1,  
4.5 V to 5.5 V (DC/DC Enabled), 2.7 V to 4.0  
V (DC/DC Disabled)  
2
3
4
VIA  
VIB  
GND  
Logic Input A.  
Logic Input B.  
Ground. Ground reference for Isolator  
Side 1.  
2
3
4
VOA  
VOB  
GND  
Logic Output A.  
Logic Output B.  
Ground. Ground reference for Isolator  
Side 1.  
5
GNDISO  
Isolated Ground. Ground reference for  
Isolator Side 2.  
5
GNDISO  
Isolated Ground. Ground reference for  
Isolator Side 2.  
6
7
8
VOB  
VOA  
VISO  
Logic Output B.  
Logic Output A.  
Isolated Supply Voltage for Isolator Side 2,  
5.0 V to 5.5 V Output (DC/DC Enabled), 4.5  
V to 5.5 V Input (DC/DC Disabled)  
6
7
8
VIB  
VIA  
VISO  
Logic Input B.  
Logic Input A.  
Isolated Supply Voltage for Isolator Side 2,  
5.0 V to 5.5 V Output (DC/DC Enabled), 4.5  
V to 5.5 V Input (DC/DC Disabled)  
Table 12. ADuM5241 Pin Function Descriptions  
Pin  
No.  
Mnemonic Function  
1
VDD1  
Supply Voltage for Isolator Side 1,  
4.5 V to 5.5 V (DC/DC Enabled), 2.7 V to 4.0  
V (DC/DC Disabled)  
2
3
4
VOA  
VIB  
GND  
Logic Output A.  
Logic Input B.  
Ground. Ground reference for Isolator  
Side 1.  
5
GNDISO  
Isolated Ground. Ground reference for  
Isolator Side 2.  
6
7
8
VOB  
VIA  
VISO  
Logic Output B.  
Logic Input A.  
Isolated Supply Voltage for Isolator Side 2,  
5.0 V to 5.5 V Output (DC/DC Enabled), 4.5  
V to 5.5 V Input (DC/DC Disabled)  
Rev. PrN | Page 8 of 10  
Preliminary Technical Data  
ADuM5240/ADuM5241/ADuM5242  
APPLICATION INFORMATION  
When these guidelines are followed, pre-production samples  
may be used for prototype and evaluation. As mentioned above  
this issue will be corrected in final silicon and the ADuM524x  
will operate at specified load and temperature conditions.  
DC/DC CONVERTER  
The ADuM524x can be operated with the internal DC/DC  
enabled or disabled. With the internal DC/DC converter  
enabled, the Pin 8 isolated supply provides output power as well  
as power to the parts isolated-side circuitry. Since the power  
consumed by the ADuM524x is a function of the input signals’  
data rate, the available isolated output power is determined by  
the data rate at which the parts data channels are operating.  
Table 14. Special Usage Conditions for Pre-production  
Devices  
Max Temperature by Load Capacitance1  
10nF  
105°C  
105°C  
80°C  
100nF  
The ADuM524xs internal DC/DC converter state is controlled  
by the input VDD voltage as defined in Table 6. In normal  
operating mode, VDD is set between 4.5 V and 5.5 V and the  
internal DC/DC converter is enabled. When/if it is desired to  
disable the DC/DC converter, VDD is lowered to a value between  
2.7 V and 4.0 V. In this mode, the VISO supply is supplied by the  
user and the ADuM524xs signal channels continue to operate  
normally.  
ADuM5240  
ADuM5241  
ADuM5242  
Not Recommended  
65°C  
80°C  
1 Value of load capacitor C3 in Figure 8  
PC BOARD LAYOUT  
The ADuM524x digital isolators require no external interface  
circuitry for the logic interfaces. Power supply bypassing is  
strongly recommended at the input and output supply pins as  
shown in Figure 8. For the ADuM5240 and ADuM5241, a  
bypass capacitance (C1) of 44 μF is required at the VDD input to  
ensure proper power-up. For all models bypass capacitance is  
recommended with C2=0.1 μF on the non-isolated side and  
C3=10 nF on the isolated side. Due to high inductance  
associated with larger capacitors such as C1, it is recommended  
that both C1 and C2 be used on the ADuM5240 and  
GUIDELINES FOR PRE-PRODUCTION SAMPLES  
Pre production samples meet all data sheet specifications;  
however, a limitation in the internal circuitry of the ADuM524x  
prevents proper start-up under all load conditions. This  
limitation will be corrected in the final product.  
At certain temperature and load conditions the ADuM524x will  
not regulate its VISO output to the 5.25V target voltage at  
converter start-up. The output stabilizes at just under 4V with  
no external load or as low as 3V with an external load. If the  
converter starts successfully, the output voltage will continue to  
regulate properly even as temperature and load conditions  
change.  
ADuM5241. The bypass capacitors should be placed as close as  
possible to the ADuM524x device.  
In cases where EMI is a concern, inductance should be added  
between the system supply and ground and the ADuM524x  
supply and ground as shown in Figure 8. Inductance can be  
added in the form of discrete inductors or ferrite beads, and its  
recommended the value correspond to an impedance between  
50Ω and 100Ω at approximately 300MHz.  
The start-up issue is affected by several circuit and  
environmental conditions: slew rate applied to VDD1, ambient  
temperature, and VISO capacitive load. The recommendations in  
the PC board layout section address the VDD1 slew rate  
dependence in most cases. Good results have been obtained  
when the system power supply slews at ~0.5V/μS. Faster slew  
rates can be tolerated but should be verified over temperature.  
Table 14 contains guidelines for the maximum reliable start-up  
temperature for two common values of load capacitance.  
The VISO start-up issue is strongly temperature dependant. The  
ADuM542x dissipates between 40 and 63mW under normal  
operation, causing the internal temperature of the device to be  
higher than ambient during normal operation. A “warm start”  
after the device has reached its equilibrium temperature is the  
worst case condition and will give the highest probability of  
incorrect regulation of output voltage. The guidelines in Table  
14 are based on “warm start” at full load. Cold start will be  
successful at higher ambient temperatures.  
Figure 8. Recommended Application Circuit. C1 may be  
omitted for ADuM5242, and L1 and L2 should be included  
where EMI is a concern.  
Rev. PrN | Page 9 of 10  
ADuM5240/ADuM5241/ADuM5242  
OUTLINE DIMENSIONS  
Preliminary Technical Data  
5.00 (0.1968)  
4.80 (0.1890)  
8
1
5
4
6.20 (0.2440)  
5.80 (0.2284)  
4.00 (0.1574)  
3.80 (0.1497)  
1.27 (0.0500)  
BSC  
0.50 (0.0196)  
0.25 (0.0099)  
× 45°  
1.75 (0.0688)  
1.35 (0.0532)  
0.25 (0.0098)  
0.10 (0.0040)  
8°  
0.51 (0.0201)  
0.31 (0.0122)  
0° 1.27 (0.0500)  
COPLANARITY  
0.10  
0.25 (0.0098)  
0.17 (0.0067)  
SEATING  
PLANE  
0.40 (0.0157)  
COMPLIANT TO JEDEC STANDARDS MS-012AA  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN  
Figure 9. 8-Lead Standard Small Outline Package [SOIC]—Narrow Body  
(R-8)  
Dimensions shown in millimeters (inches)  
ORDERING GUIDE  
Number  
of Inputs,  
VDD1 Side  
Number  
of Inputs,  
VDD2 Side  
Maximum  
Data Rate  
(Mbps)  
Temperature  
Range (°C)  
Package  
Model  
Option1  
R-8  
ADuM5240BRZ2,3  
ADuM5241BRZ2, 3  
ADuM5242BRZ2, 3  
2
1
0
0
1
2
10  
10  
10  
−40 to +105  
−40 to +105  
−40 to +105  
R-8  
R-8  
1 R-8 = 8-lead narrow body SOIC.  
2 Tape and reel are available. The addition of an “-RL7” suffix designates a 7” (1,000 units) tape and reel option.  
3 Z = Pb-free part.  
Rev. PrN | Page 10 of 10  
PR06014-0-11/06(PrN)  

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