DAC8412AT_技术文档

Quad, 12-Bit DAC

Voltage Output with Readback

Data Sheet

DAC8412/DAC8413

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

REFH

LOGIC

DD

+5 V to 15 V operation

Unipolar or bipolar operation

True voltage output

Double-buffered inputs

Reset to minimum (DAC8413) or center scale (DAC8412)

Fast bus access time

12

I/O

PORT

DATA

I/O

INPUT

REG A

OUTPUT

REG A

V

DAC A

DAC B

DAC C

DAC D

OUTA

OUTB

DGND

INPUT

REG B

OUTPUT

REG B

V

A0

A1

INPUT

REG C

OUTPUT

REG C

V

CONTROL

LOGIC

OUTC

Readback

R/W

CS

INPUT

REG D

OUTPUT

REG D

OUTD

APPLICATIONS

RESET

LDAC

Automatic test equipment

Digitally controlled calibration

Servo controls

V

REFL

SS

Figure 1.

Process control equipment

GENERAL DESCRIPTION

They can be operated from a wide variety of supply and reference

voltages with supplies ranging from single +5 V to 15 V, and

references from +2.5 V to 10 V. Power dissipation is less than

330 mW with 15 V supplies and only 60 mW with a +5 V supply.

The DAC8412/DAC8413 are quad, 12-bit voltage output

DACs with readback capability. Built using a complementary

BiCMOS process, these monolithic DACs offer the user very

high package density.

For MIL-STD-883 applications, contact your local Analog

Devices, Inc. sales office for the DAC8412/DAC8413/883 data

sheet, which specifies operation over the −55°C to +125°C

temperature range. All 883 parts are also available on Standard

Military Drawings 5962-91 76401MXA through 76404M3A.

0.500

Output voltage swing is set by the two reference inputs V_REFH

and V_REFL. By setting the V_REFLinput to 0 V and V_REFHto a

positive voltage, the DAC provides a unipolar positive output

range. A similar configuration with V_REFHat 0 V and V_REFLat a

negative voltage provides a unipolar negative output range.

Bipolar outputs are configured by connecting both V_REFHand

V

_REFLto nonzero voltages. This method of setting output voltage

0.375

0.250

0.125

+125°C

range has advantages over other bipolar offsetting methods

because it is not dependent on internal and external resistors

with different temperature coefficients.

+25°C

Digital controls allow the user to load or read back data from any

DAC, load any DAC, and transfer data to all DACs at one time.

0

–0.125

–0.250

–0.375

–0.500

–55°C

RESET

An active low

loads all DAC output registers to midscale

V

T

= +15V

= –15V

DD

SS

for the DAC8412 and zero scale for the DAC8413.

= +10V

= –10V

REFH

REFL

The DAC8412/DAC8413 are available in 28-lead plastic DIP,

28-lead cerami c DI P, 28-lead PLCC, and 28-lead LCC packages.

= –55°C, +25°C, +125°C

A

0

512

1024 1536 2046 2548 2560

DIGITAL INPUT CODE (Decimal)

3072 4096

Figure 2. INL vs. Code Over Temperature

Rev. G

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

DAC8412/DAC8413

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Introduction................................................................................ 14

DACs............................................................................................ 14

Glitch............................................................................................ 14

Reference Inputs......................................................................... 14

Digital I/O ................................................................................... 14

Coding ......................................................................................... 14

Supplies........................................................................................ 15

Amplifiers.................................................................................... 15

Reference Configurations.......................................................... 16

Single +5 V Supply Operation.................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

aRevision History ............................................................................. 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 14

REVISION HISTORY

4/13—Rev. F to Rev. G

Changed Reference Low Input Current from 0 mA (min),

2 mA (typ), 2.75 mA (max) to −2.75 mA (min), −2 mA (typ),

0 mA (max); Table 1......................................................................... 3

Changes to Reference Configurations Section ........................... 17

9/09—Rev. E to Rev. F

Updated Figure Numbering..............................................Universal

Removed Figure 7............................................................................. 6

Changes to Ordering Guide .......................................................... 20

6/07—Rev. D to Rev. E

Updated Format..................................................................Universal

Added CERDIP Package....................................................Universal

Changes to Specifications Section.................................................. 3

Changes to Absolute Maximum Ratings Section......................... 7

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide .......................................................... 20

3/00—Rev. C to Rev. D

Rev. G | Page 2 of 20

Data Sheet

DAC8412/DAC8413

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= +15.0 V, V_SS= −15.0 V, V_LOGIC= +5.0 V, V_REFH= +10.0 V, V_REFL= −10.0 V,−40°C ≤ T_A≤ +85°C, unless otherwise noted.¹

Table 1.

Parameter

Symbol

Conditions

Min

Typ

0.25

Max

Unit

ACCURACY

Integral Nonlinearity Error

INL

E grade

F grade

0.5

1

LSB

Differential Nonlinearity Error

Min-Scale Error

Full-Scale Error

DNL

V_ZSE

V_FSE

Monotonic over temperature

R_L= 2 kΩ

−1

LSB

2

Min-Scale Temperature Coefficient

Full-Scale Temperature Coefficient

Linearity Matching

TCV_ZSE

TCV_FSE

R_L= 2 kΩ

Adjacent DAC Matching

15

20

1

ppm/°C

LSB

REFERENCE

Positive Reference Input Voltage Range²

Negative Reference Input Voltage Range²

Reference High Input Current

Reference Low Input Current

Large Signal Bandwidth

AMPLIFIER CHARACTERISTICS

Output Current

V_REFL+ 2.5

−10

−2.75

V_DD− 2.5

V_REFH− 2.5

+2.75

V

mA

kHz

I_REFH

I_REFL

BW

+1.5

−2

160

−2.75

0

−3 dB, V_REFH= 0 V to 10 V p-p

I_OUT

t_S

SR

R_L= 2 kΩ, C_L= 100 pF

To 0.01%, 10 V step, R_L= 1 kΩ

10% to 90%

–5

+5

mA

μs

V/μs

dB

Settling Time

Slew Rate

Analog Crosstalk

10

2.2

72

LOGIC CHARACTERISTICS

Logic Input High Voltage

Logic Input Low Voltage

Logic Output High Voltage

Logic Output Low Voltage

Logic Input Current

V_INH

V_INL

V_OH

V_OL

I_IN

T_A= 25°C

I_OH= 0.4 mA

I_OL= −1.6 mA

2.4

V

0.8

0.4

1

μA

Input Capacitance

C_IN

8

5

pF

nV-sec

Digital Feedthrough³

LOGIC TIMING CHARACTERISTICS^{3, 4}

Chip Select Write Pulse Width

Write Setup

V_REFH= 2.5 V, V_REFL= 0 V

t_WCS

t_WS

t_WH

t_AS

t_AH

t_LS

80

0

70

30

20

0

170

140

130

0

ns

t_WCS= 80 ns

Write Hold

Address Setup

Address Hold

Load Setup

Load Hold

Write Data Setup

Write Data Hold

Load Data Pulse Width

Reset Pulse Width

Chip Select Read Pulse Width

Read Data Hold

Read Data Setup

Data to High-Z

Chip Select to Data

t_LH

t_WDS

t_WDH

t_LDW

t_RESET

t_RCS

t_RDH

t_RDS

t_DZ

t_WCS= 80 ns

t_RCS= 130 ns

C_L= 10 pF

0

200

160

t_CSD

C_L= 100 pF

Rev. G | Page 3 of 20

DAC8412/DAC8413

Data Sheet

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY CHARACTERISTICS

Power Supply Sensitivity

Positive Supply Current

Negative Supply Current

Power Dissipation

PSS

I_DD

I_SS

14.25 V ≤ V_DD≤ 15.75 V

V_REFH= 2.5 V

150

12

ppm/V

mA

8.5

−6.5

−10

P_DISS

330

mW

¹All supplies can be varied 5%, and operation is guaranteed. Device is tested with nominal supplies.

²Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

³All parameters are guaranteed by design.

⁴All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

V_DD= V_LOGIC= +5.0 V 5%, V_SS= 0.0 V, V_REFH= +2.5 V, V_REFL= 0.0 V, V_SS= –5.0 V 5%, V_REFL= −2.5 V, −40°C ≤ T_A≤ +85°C,

unless otherwise noted.¹

Table 2.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

ACCURACY

Integral Nonlinearity Error

INL

E grade

F grade

V_SS= 0.0 V, E grade²

V_SS= 0.0 V, F grade²

Monotonic over temperature

V_SS= −5.0 V

V_SS= 0.0 V

0.5

1

2

4

LSB

Differential Nonlinearity Error

Min-Scale Error

Full-Scale Error

Min-Scale Error

Full-Scale Error

DNL

V_ZSE

V_FSE

V_ZSE

V_FSE

–1

4

8

LSB

Min-Scale Temperature Coefficient

Full-Scale Temperature Coefficient

Linearity Matching

TCV_ZSE

TCV_FSE

100

1

ppm/°C

LSB

Adjacent DAC matching

REFERENCE

Positive Reference Input Voltage Range³

Negative Reference Input Voltage Range

V_REFL+ 2.5

0

–2.5

V_DD− 2.5

V_REFH− 2.5

+1.0

V

mA

kHz

V_SS= 0.0 V

V_SS= −5.0 V

Code 0x000

−3 dB, V_REFH= 0 V to 2.5 V p-p

Reference High Input Current

Large Signal Bandwidth

AMPLIFIER CHARACTERISTICS

Output Current

Settling Time

Slew Rate

I_REFH

BW

–1.0

450

I_OUT

t_S

SR

R_L= 2 kΩ, C_L= 100 pF

To 0.01%, 2.5 V step, R_L= 1 kΩ

10% to 90%

–1.25

+1.25

mA

μs

V/μs

7

2.2

LOGIC CHARACTERISTICS

Logic Input High Voltage

Logic Input Low Voltage

Logic Output High Voltage

Logic Output Low Voltage

Logic Input Current

Input Capacitance

V_INH

V_INL

V_OH

V_OL

I_IN

T_A= 25°C

I_OH= 0.4 mA

I_OL= −1.6 mA

2.4

V

μA

pF

0.8

0.45

1

C_IN

8

LOGIC TIMING CHARACTERISTICS^{4, 5}

Chip Select Write Pulse Width

Write Setup

Write Hold

Address Setup

Address Hold

Load Setup

Load Hold

t_WCS

t_WS

t_WH

t_AS

t_AH

t_LS

150

0

ns

t_WCS= 150 ns

70

50

t_LH

Rev. G | Page 4 of 20

Data Sheet

DAC8412/DAC8413

Parameter

Symbol

t_WDS

t_WDH

t_LDW

t_RESET

t_RCS

t_RDH

t_RDS

t_DZ

t_CSD

Conditions

t_WCS= 150 ns

Min

20

0

180

150

170

20

Typ

Max

Units

ns

Write Data Setup

Write Data Hold

Load Data Pulse Width

Reset Pulse Width

Chip Select Read Pulse Width

Read Data Hold

t_RCS= 170 ns

C_L= 10 pF

Read Data Setup

Data to High-Z

0

200

320

Chip Select to Data

SUPPLY CHARACTERISTICS

Power Supply Sensitivity

Positive Supply Current

Negative Supply Current

Power Dissipation

C_L= 100 pF

ns

PSS

I_DD

I_SS

100

7

ppm/V

mA

mW

12

V_SS= −5.0 V

V_SS= 0 V

V_SS= −5.0 V

−10

P_DISS

60

110

¹All supplies can be varied 5ꢀ% and operation is guaranteed. Device is tested with V_DD= 4.75 V.

²For single-supply operation only (V_REFL= 0.0 V% V_SS= 0.0 V). Due to internal offset errors% INL and DNL are measured beginning at 0x005.

³Operation is guaranteed over this reference range% but linearity is neither tested nor guaranteed.

⁴All parameters are guaranteed by design.

⁵All input control signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of 5 V) and timed from a voltage level of 1.6 V.

t_WCS

CS

t_WS

t_WH

R/W

t_AH

t_AS

t_RDS

A0/A1

CS

t_RDH

t_RCS

t_LH

t_LDW

t_LS

R/W

LDAC

DATA IN

RESET

t_AH

t_AS

t_WDS

t_WDH

A0/A1

t_DZ

HIGH-Z

t_RESET

DATA

OUT

DATA VALID

t_CSD

Figure 3. Data Output (Read Timing)

Figure 4. Data Write (Input and Output Registers) Timing

Rev. G | Page 5 of 20

DAC8412/DAC8413

Data Sheet

80ns

CS

t_WH

t_WS

R/W

t_AS

ADDRESS

ONE

ADDRESS

TWO

ADDRESS

THREE

ADDRESS

FOUR

ADDRESS

ONE

ADDRESS

TWO

ADDRESS

THREE

ADDRESS

FOUR

ADDRESS

LDAC

ADDRESS

t_LSt_LH

t_LH

t_LS

LDAC

t_LDW

t_WDS

t_WDH

t

t_WDH

WDS

DATA1

VALID

DATA2

VALID

DATA3

VALID

DATA4

VALID

DATA IN

DATA1

VALID

DATA3

VALID

DATA4

VALID

DATA2

VALID

DATA IN

Figure 5. Single-Buffer Mode

Figure 6. Double-Buffer Mode

Rev. G | Page 6 of 20

Data Sheet

DAC8412/DAC8413

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

T_A= +25°C, unless otherwise noted.

θ_JAis specified for the worst-case mounting conditions, that is, a

device in socket.

Table 3.

Parameter

Rating

Table 4. Thermal Resistance

Package Type

V_SSto V_DD

V_SSto V_LOGIC

V_LOGICto DGND

V_SSto V_REFL

V_REFHto V_DD

V_REFHto V_REFL

Current into Any V_SSpin

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature Range

EP, FP, FPC

−0.3 V, +33.0 V

−0.3 V, +7.0 V

−0.3 V, +V_SS− 2.0 V

+2.0 V, +33.0 V

+2.0 V, V_SS− V_DD

15 mA

θ_JAθ_JCUnit

48 22 °C/W

70 28 °C/W

63 25 °C/W

28-Lead Plastic DIP (PDIP)

28-Terminal Ceramic Leadless Chip Carrier (LLC)

28-Lead Plastic Leaded Chip Carrier (PLLC)

28-Lead Ceramic Dual In-Line Package (CERDIP) 51

9

°C/W

−0.3 V, V_LOGIC+ 0.3 V

−0.3 V, +7.0 V

ESD CAUTION

−40°C to +85°C

−55°C to +125°C

150°C

−65°C to +150°C

1000 mW

AT, BT, BTC

Junction Temperature

Storage Temperature Range

Power Dissipation Package

Lead Temperature

Soldering

JEDEC Industry Standard

J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. G | Page 7 of 20

DAC8412/DAC8413

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

6

7

8

9

28

27

26

25

24

V

REFH

OUTB

OUTA

REFL

OUTC

OUTD

DD

V

4

3

2

1

28 27 26

4

3

2

1

28 27 26

V

SS

PIN 1

INDENTFIER

5

6

25

24

23

22

21

20

DGND

RESET

LDAC

V

5

6

25

24

23

22

21

20

19

DGND

RESET

LDAC

V

DD

DGND

RESET

LDAC

LOGIC

DAC8412/

DAC8413

LOGIC

23 CS

DAC8412/

DAC8413

7

CS

7

CS

A0

22 A0

TOP VIEW

DAC8412/

DAC8413

TOP VIEW

8

DB0 (LSB)

DB1

A0

(Not to Scale)

DB0 (LSB)

DB1

21 A1

8

DB0 (LSB)

DB1

TOP VIEW

9

A1

20 R/W

19 DB11 (MSB)

18 DB10

17 DB9

16 DB8

15 DB7

(Not to Scale)

9

A1

(Not to Scale)

10

11

DB2

R/W

DB2 10

DB3 11

DB4 12

DB5 13

DB6 14

10

DB2

R/W

DB3

DB11 (MSB)

DB3 11

19 DB11 (MSB)

12 13 14 15 16 17 18

Figure 7. PDIP/CERDIP

Figure 8. PLCC

Figure 9. LCC

Table 5. Pin Function Descriptions

Pin Number Mnemonic Description

1

2

3

4

V_REFH

V_OUTB

V_OUTA

V_SS

High-Side DAC Reference Input.

DAC B Output.

DAC A Output.

Lower Rail Power Supply.

Digital Ground.

5

DGND

RESET

LDAC

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

R/W

A1

6

Reset Input and Output Registers to all 0s, Enabled at Active Low.

7

Load Data to DAC, Enabled at Active Low.

Data Bit 0, LSB.

Data Bit 1.

Data Bit 2.

Data Bit 3.

Data Bit 4.

Data Bit 5.

Data Bit 6.

Data Bit 7.

Data Bit 8.

Data Bit 9.

Data Bit 10.

Data Bit 11, MSB.

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with V_LOGICconnected to 5 V.

Address Bit 1.

Address Bit 0.

A0

CS

Chip Select, Enabled at Active Low.

Voltage Supply for Readback Function. Can be open circuit if not used.

Upper Rail Power Supply.

DAC D Output.

DAC C Output.

V_LOGIC

V_DD

V_OUTD

V_OUTC

V_REFL

Low-Side DAC Reference Input.

Rev. G | Page 8 of 20

Data Sheet

DAC8412/DAC8413

TYPICAL PERFORMANCE CHARACTERISTICS

V

= +15V

= –15V

DD

SS

V

= 5V

= 0V

DD

SS

2

1

= –10V

REFL

= 25°C

= 0V

REFL

= 25°C

T

A

1

T

A

0

–1

–2

–1

1

2

3

6

7

8

9

10

11

12

V

REFH

(V)

V

(V)

REFH

Figure 13. DNL vs. V_REFH

Figure 10. DNL vs. V_REFH

1

0.3

0.2

0.1

0

V

= 5V

= 0V

DD

SS

V

= +15V

= –15V

DD

SS

–1

= 0V

REFL

= 25°C

= 0V

REFL

T

A

T

= 25°C

A

1

2

3

6

8

10

12

V

(V)

V

(V)

REFH

Figure 14. INL vs.V_REFH

Figure 11. INL vs. V_REFH

0.4

0.2

0

0.3

0.1

V

= +15V

= –15V

X+3σ

DD

SS

= +10V

= –10V

REFH

REFL

X

–0.1

–0.3

X–3σ

X+3σ

–0.2

V

= +15V

= –15V

DD

SS

X

–0.4

–0.6

–0.5

–0.7

= +10V

= –10V

REFH

REFL

X–3σ

0

200

400

600

800

1000

0

200

400

600

800

1000

T = HOURS OF OPERATION AT 125°C

Figure 12. Full-Scale Error vs. Time Accelerated by Burn-in

Figure 15. Zero-Scale Error vs. Time Accelerated by Burn-In

Rev. G | Page 9 of 20

DAC8412/DAC8413

Data Sheet

0.2

1.00

0.75

0.50

0.25

V

= +15V

= –15V

V

T

= 5V

= 0V

DD

SS

DD

SS

= +10V

= –10V

= 2.5V

REFH

REFL

REFH

= 25°C

A

0

–0.2

0

–0.25

–0.50

–0.75

–1.00

DAC A

DAC D

DAC B

DAC C

–0.4

–0.6

–75

0

75

150

0

512

1024

1536

2048

2560

3072 3584

4096

TEMPERATURE (°C)

DIGITAL INPUT CODE (Decimal)

Figure 16. Full-Scale Error vs. Temperature

Figure 19. Channel-to-Channel Matching (V_SUPPLY= +5 V/GND)

0.2

13

V

= +15V

= –15V

V

= +15V

= –15V

DD

SS

DD

SS

= +10V

= –10V

REFH

REFL

0

–0.2

–0.4

–0.6

10

DAC A

DAC D

DAC C

7

DAC B

4

–75

0

75

150

7

3

1

5

9

13

TEMPERATURE (°C)

V

(V)

REFH

Figure 17. Zero-Scale Error vs. Temperature

Figure 20. I_DDvs. V_REFH(All DACs High)

0.37500

0.26125

0.18750

0.08375

0.500

0.375

0.250

0.125

V

= 10V

= 0V

= 25°C

REFH

REFL

T

A

0

–0.09375

–0.18750

–0.23125

–0.37500

0

–0.125

–0.250

–0.375

–0.500

V

= +15V

= –15V

DD

SS

= +10V

= –10V

REFH

REFL

T

= –55°C, +25°C, +125°C

A

0

512

1024

1536

2048

2560

3072 3584

4096

0

512

1024

1536

2048

2560

3072

3584

4096

DIGITAL INPUT CODE (Decimal)

Figure 18. Channel-to-Channel Matching (V_SUPPLY

= 15 V)

Figure 21. INL vs. Code

Rev. G | Page 10 of 20

Data Sheet

DAC8412/DAC8413

10V

1V/DIV

EA

1V/DIV

EA

V

T

= +15V

= –15V

V

T

= +15V

= –15V

DD

SS

DD

SS

= +10V

= –10V

TRIG'D

= +10V

= –10V

TRIG'D

REFH

REFL

REFH

REFL

= 25°C

A

0V

–580ns

0V

–580ns

1µs/DIV

9.42µs

1µs/DIV

9.42µs

Figure 22. Positive Slew Rate

Figure 25. Negative Slew Rate

15.5mV

2.0

1.5

1.0

V

= +15V

= –15V

DD

SS

V

= +15V

= –15V

DD

SS

0

INPUT

–5V

= +10V

= –10V

REFH

REFL

= +10V

= –10V

REFH

REFL

T

= 25°C

A

T

= 25°C

A

2mV/DIV

5V/DIV

0.5

TRIG'D

0

–4.5mV

–1.96µs

–0.5

2µs/DIV

18.04µs

0

511

1023

1535

2047

2559

3071

3583

4095

DIGITAL INPUT CODE (Decimal)

Figure 26. I_VREFHvs. Code

Figure 23. Settling Time (Negative)

32.5mV

1.0

V

= +15V

= –15V

DD

SS

5V

INPUT

0

= +10V

= –10V

0.8

0.6

0.4

0.2

0

REFH

REFL

T

= 25°C

A

5mV/DIV

5V/DIV

1 LSB ERROR BAND

TRIG'D

V

= +15V

= –15V

DD

SS

= +10V

REFH

= –10V

REFL

T

= 25°C

A

–0.2

0.01

–17.5mV

–1.96µs

0.1

1

10

100

2µs/DIV

18.04µs

LOAD RESISTANCE (kΩ)

Figure 27. INL vs. Load Resistance

Figure 24. Settling Time (Positive)

Rev. G | Page 11 of 20

DAC8412/DAC8413

Data Sheet

12

100

80

60

40

20

0

V

= +15V

= –15V

DD

SS

+PSRR

= +10V

= –10V

10

8

REFH

REFL

T

= 25°C

A

–PSRR

6

+PSRR:

V

= +15V ±1Vp

= –15V

DD

SS

4

–PSRR:

V

= +15V

= –15V ±1V

DD

2

SS

= +10V

REFH

ALL DATA 0

0

0.01

0.1

1

10

100

10

100

1k

10k

100k

1M

10k

25

LOAD RESISTANCE (kΩ)

FREQUENCY (Hz)

Figure 28. Output Swing vs. Load Resistance

Figure 31. PSRR vs. Frequency

10

V

= +15V

= –15V

DD

SS

= +10V

= –10V

REFH

REFL

1

0.10

0

T

= 25°C

A

–10

–30

–50

–70

V

= +15V

= –15V

DD

SS

0.01

= 0 ±100mV

= –10V

REFH

REFL

DATA BITS = +5V

200mV p-p

0.001

0

10

100

1k

10k

100k

1M

10M

1

10

100

1k

FREQUENCY (Hz)

NOISE FREQUENCY (Hz)

Figure 32. Noise Density vs. Noise Frequency

Figure 29. Small Signal Response

10

6

40

30

V

T

= +15V

= –15V

= +10V

= –10V

DD

SS

I

DD

REFH

REFL

+I

SC

20

= 25°C

DATA = 0x000

V

= +15V

= –15V

A

DD

SS

10

2

0

–2

–6

–10

–20

–30

–40

I

SS

–I

SC

–10

–75

0

75

150

–25 –20 –15 –10

–5

0

5

10

15

20

TEMPERATURE (°C)

V

(V)

OUT

Figure 30. Power Supply Current vs. Temperature

Figure 33. I_OUTvs. V_OUT

Rev. G | Page 12 of 20

Data Sheet

DAC8412/DAC8413

10µs

CH1 MEAN

66.19µV

4µs

1V

GLITCH AT DAC OUTPUT

1

2

1

V

= +15V

= –15V

DD

SS

= +10V

= –10V

REFH

REFL

DEGLITCHER OUTPUT

T

= 25°C

A

1V

20µV/DIV

M 200µs

A

CH1

12.9mV

CH2

1.86V

Figure 34. Broadband Noise

Figure 36. Glitch and Deglitched Results

25

V

= +15V

= 0V

+I

SC

DD

SS

20

15

= +10V

REFH

= 0V

REFL

T

= 25°C

A

10

5

DATA = 0x800

0

–5

–10

–15

–20

–25

–I

SC

–6

–4

–2

0

2

4

6

V

(V)

OUT

Figure 35. I_OUTvs. V_OUT

Rev. G | Page 13 of 20

DAC8412/DAC8413

Data Sheet

THEORY OF OPERATION

INTRODUCTION

REFERENCE INPUTS

All four DACs share common reference high (V_REFH) and reference

low (V_REFL) inputs. The voltages applied to these reference inputs set

the output high and low voltage limits of all four of the DACs.

Each reference input has voltage restrictions with respect to the

other reference and to the power supplies. The V_REFLcan be set at

any voltage between V_SSand V_REFH− 2.5 V, and V_REFHcan be set to

any value between +V_DD− 2.5 V and V_REFL+ 2.5 V. Note that

because of these restrictions, the DAC8412 references cannot be

inverted (that is, V_REFLcannot be greater than V_REFH).

The DAC8412/DAC8413 are quad, voltage output, 12-bit parallel

input DACs featuring a 12-bit data bus with readback capability.

The only differences between the DAC8412/DAC8413 are the

reset functions. The DAC8412 resets to midscale (Code 0x800),

and the DAC8413 resets to minimum scale (Code 0x000).

The ability to operate from a single 5 V supply is a unique

feature of these DACs.

Operation of the DAC8412/DAC8413 can be viewed by

dividing the system into three separate functional groups: the

digital I/O and logic, the digital-to-analog converters, and the

output amplifiers.

It is important to note that the DAC8412 V_REFHinput both sinks

and sources current. In addition, the input current of both V_REFH

and V_REFLare code-dependent. Many references have limited

current-sinking capability and must be buffered with an

amplifier to drive V_REFH. The V_REFLhas no such special

requirements.

DACS

Each DAC is a voltage switched, high impedance (R = 50 kΩ),

R-2R ladder configuration. Each 2R resistor is driven by a pair

of switches that connect the resistor to either V_REFHor V_REFL

.

It is recommended that the reference inputs be bypassed with

0.2 μF capacitors when operating with 10 V references. This

limits the reference bandwidth.

GLITCH

Worst-case glitch occurs at the transition between Half-Scale

Digital Code 1000 0000 0000 to half-scale minus 1 LSB, 0111

1111 1111. It can be measured at about 2 V μs (see Figure 36).

For demanding applications such as waveform generation or

precision instrumentation control, a deglitcher circuit can be

implemented with a standard sample-and-hold circuit (see

DIGITAL I/O

See Table 6 for the digital control logic truth table. Digital I/O

consists of a 12-bit bidirectional data bus, two registers select

W

RESET

CS

inputs, A0 and A1, a R/ input, a

LDAC

input, a chip select ( ),

and a load DAC (

) input. Control of the DACs and bus

CS

Figure 37). When

is enabled by synchronizing the hold

direction is determined by these inputs as shown in Table 6. Digital

data bits are labeled with the MSB defined as Data Bit 11 and the

LSB as Data Bit 0. All digital pins are TTL/CMOS compatible.

period to be longer than the glitch tradition, the output voltage

can be smoothed with minimum disturbance. A quad

sample-and-hold amplifier, SMP04, has been used to illustrate

the deglitching result (see Figure 36).

See Figure 38 for a simplified I/O logic diagram. The register

select inputs A0 and A1 select individual DAC registers A

(Binary Code 00) through D (Binary Code 11). Decoding of the

DACOUT

1

CS

registers is enabled by the

input. When

is high, no

S/H

decoding takes place, and neither the writing nor the reading of

the input registers is enabled. The loading of the second bank of

LDAC

registers is controlled by the asynchronous

input. By

DACOUT

LDAC CS

taking

low while

is enabled, all output registers can

be updated simultaneously. Note that the t_LDWrequired pulse

width for updating all DACs is a minimum of 170 ns.

CS

W

CS

The R/ input, when enabled by , controls the writing to

and reading from the input register.

S/H

H

S

H

S

DACOUT

1

CODING

Both DAC8412/DAC8413 use binary coding. The output

voltage can be calculated by

Figure 37. Data Output (Read Timing)

(V_REFHV_REFL) N

V_OUT V_REFL

4096

where N is the digital code in decimal.

Rev. G | Page 14 of 20

Data Sheet

DAC8412/DAC8413

V

_LOGICis the digital output supply voltage for the readback

RESET

function. It is normally connected to +5 V. This pin is a logic

reference input only. It does not supply current to the device. If

the readback function is not being used, V_LOGICcan be left open-

circuit. While V_LOGICdoes not supply current to the DAC8412, it

does supply currents to the digital outputs when readback is used.

RESET

The

function can be used either at power-up or at any

RESET

time during DAC operation. The

function is independent

CS

of . This pin is active low and sets the DAC output registers

to either center code for the DAC8412, or zero code for the

DAC8413. The reset-to-center code is most useful when the

DAC is configured for bipolar references and an output of 0 V

after reset is desired.

AMPLIFIERS

Unlike many voltage output DACs, the DAC8412 features buffered

voltage outputs. Each output is capable of both sourcing and

sinking 5 mA at 10 V, eliminating the need for external

amplifiers when driving 500 pF or smaller capacitive load in

most applications. These amplifiers are short-circuit protected.

SUPPLIES

Supplies required are V_SS, V_DD, and V_LOGIC. The V_SSsupply can

be set between −15 V and 0 V. V_DDis the positive supply; its

operating range is between 5 V and 15 V.

Table 6. DAC8412/DAC8413 Logic Table

R/

W

CS

RS

H

L

LDAC

A1

L

H

L

A0

L

H

L

H

L

H

L

H

L

H

L

H

X

Input Register

Write

Read

Output Register

Mode

DAC

A

B

C

D

A

B

C

D

A

B

C

D

All

L

H

X

L

H

X

H

L

H

L

Write

Hold

Transparent

Write input

Read input

L

H

L

Read

Hold

H

X

Update all output registers

Hold

H

X

Hold

All registers reset to midscale/zero-scale¹

All registers latched to midscale/zero-scale¹

¹DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.

Rev. G | Page 15 of 20

DAC8412/DAC8413

Data Sheet

V

SS

REFH

DD

RDDACA

WRDB0

WRDB1

WRDB2

WRDB3

WRDB4

WRDB5

WRDB6

WRDB7

WRDB8

WRDB9

WRDB10

WRDB11

CS

DAC A

DAC B

DAC C

DAC D

V

OUTA

WRDACA

RDDACB

A0

A1

V

OUTB

WRDACB

INPUT

REGISTER

OUTPUT

REGISTER

RDDACC

V

OUTC

WRDACC

RDDACD

WRDACD

R/W

V

OUTD

DB11..DB0

V

REFL

V

LOGIC

LDAC

RESET

READOUTBAR

READBACKDATAIN_DB10

READOUT

READBACKDATAIN_DB11

READBACK

DATAOUT_DB11

DGND

Figure 38. Simplified I/O Logic Diagram

+15V

Careful attention to grounding is important for accurate

operation of the DAC8412. This is not because the DAC8412 is

more sensitive than other 12-bit DACs, but because with four

outputs and two references, there is greater potential for ground

loops. Because the DAC8412 has no analog ground, the ground

must be specified with respect to the reference.

39kΩ

+15V

V

DD

6.2Ω

V

BALANCE

REFH

100kΩ

0.2µF

AD688 FOR ±10V

AD588 FOR ±5V

DAC8412

OR

DAC8413

0.1µF

//10µF

REFERENCE CONFIGURATIONS

GAIN

100kΩ

Output voltage ranges can be configured as either unipolar or

bipolar, and within these choices, a wide variety of options

exists. The unipolar configuration can be either positive or

negative voltage output, and the bipolar configuration can be

either symmetrical or nonsymmetrical.

6.2Ω

V

REFL

0.2µF

V

SS

1µF

–15V

±5 OR ±10V OPERATION

+15V

Figure 40. Symmetrical Bipolar Operation

+15V

+

Figure 40 (symmetrical bipolar operation) shows the DAC8412

configured for 10 ꢀ operation. See the AD688 data sheet for a

full explanation of reference operation. Adjustments may not be

required for many applications since the AD688 is a very high

accuracy reference. However, if additional adjustments are

required, adjust the DAC8412 full scale first. Begin by loading

the digital full-scale code (0xFFF), and then adjust the gain

adjust potentiometer to attain a DAC output voltage of 9.9976 ꢀ.

Then, adjust the balance adjust to set the center-scale output

voltage to 0.000 ꢀ.

V

REFH

V

INPUT

DD

OP400

OUTPUT

TRIM

0.2µF

DAC8412

OR

DAC8413

REF10

0.1µF

//10µF

10kΩ

V

REFL

V

SS

+10V OPERATION

–15V

Figure 39. Unipolar +10 V Operation

Rev. G | Page 16 of 20

Data Sheet

DAC8412/DAC8413

The 0.2 μF bypass capacitors shown at the reference inputs in

Figure 40 should be used whenever ±±0 ꢀ references are used.

Applications with single references or references to ±5 ꢀ may

not require the 0.2 μF bypassing. The 6.2 Ω resistor in series

with the output of the reference amplifier keeps the amplifier

from oscillating with the capacitive load. This 6.2 Ω resistor has

been found to be large enough to stabilize this circuit. Larger

resistor values are acceptable, provided that the drop across the

resistor does not exceed ꢀ_BE. Assuming a minimum ꢀ_BEof 0.6 ꢀ

and a maximum current of 2.75 mA, then the resistor should be

under 200 Ω for the loading of a single DAC84±2.

Figure 4± shows the DAC84±2 configured for –±0 ꢀ to 0 ꢀ

operation. A –±0 ꢀ full-scale output voltage reference is

connected directly to ꢀ_REFLfor the reference voltage.

SINGLE +5 V SUPPLY OPERATION

For operation with a 5 ꢀ supply, the reference voltage should be

set between ±.0 ꢀ and 2.5 ꢀ for optimum linearity. Figure 42

shows a REF43 used to supply a 2.5 ꢀ reference voltage. The

headroom of the reference and DAC are both sufficient to support

a 5 ꢀ supply with ±5% tolerance. ꢀ_DDand ꢀ_LOGICshould be

connected to the same supply. Separate bypassing to each pin

should also be used.

Using two separate references is not recommended. Having two

references can cause different drifts with time and temperature;

whereas with a single reference, most drifts track.

5V

10µF

0.01µF

Unipolar positive full-scale operation can usually be set with a

reference with the correct output voltage. This is preferable to

using a reference and dividing down to the required value. For a

±0 ꢀ full-scale output, the circuit can be configured as shown in

Figure 4±. In this configuration, the full-scale value is set first by

adjusting the ±0 kΩ resistor for a full-scale output of 9.9976 ꢀ.

10kΩ

INPUT

V

DD

V

OUTPUT

REFH

REF43

0.2µF

DAC8412

OR

DAC8413

0.1µF

//10µF

TRIM

10kΩ

GND

V

REFL

V

SS

ZERO TO 2.5V OPERATION

SINGLE 5V SUPPLY

V

TRIM

REFH

V

DD

Figure 42. +5 V Single-Supply Operation

OUTPUT

0.2µF

GND VOLTAGE

REFERENCE

DAC8412

OR

0.1µF

//10µF

DAC8413

V

REFL

0.01µF

10µF

V

SS

ZERO TO –10V OPERATION

–15V

Figure 41. Unipolar –10 V Operation

Rev. G | Page 17 of 20

DAC8412/DAC8413

Data Sheet

OUTLINE DIMENSIONS

0.300 (7.62)

REF

0.100 (2.54)

0.064 (1.63)

0.075

(1.91)

REF

0.020 (0.51)

MIN

19

25

0.028 (0.71)

0.022 (0.56)

18

26

28

0.05 (1.27)

0.458

BOTTON

VIEW

0.458 (11.63)

0.442 (11.23)

(11.63)

MAX

SQ

1

SQ

0.15 (3.81)

REF

0.075 (1.91)

REF

12

4

11

5

0.095 (2.41)

0.075 (1.90)

0.055 (1.40)

0.045 (1.14)

0.088 (2.24)

0.054 (1.37)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 43. 28-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-28-1)

Dimensions shown in inches and (millimeters)

1.565 (39.75)

1.380 (35.05)

28

1

15

0.580 (14.73)

0.485 (12.31)

14

0.625 (15.88)

0.600 (15.24)

0.100 (2.54)

BSC

0.195 (4.95)

0.125 (3.17)

0.250 (6.35)

MAX

0.015 (0.38)

GAUGE

PLANE

0.015

(0.38)

MIN

0.200 (5.08)

0.115 (2.92)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.700 (17.78)

MAX

0.022 (0.56)

0.014 (0.36)

0.005 (0.13)

MIN

0.070 (1.78)

0.050 (1.27)

COMPLIANT TO JEDEC STANDARDS MS-011

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.

Figure 44. 28-Lead Plastic Dual In-Line Package [PDIP]

Wide Body

(N-28-2)

Dimensions shown in inches and (millimeters)

Rev. G | Page 18 of 20

Data Sheet

DAC8412/DAC8413

0.180 (4.57)

0.165 (4.19)

0.048 (1.22)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.020 (0.51)

MIN

4

5

26

25

0.048 (1.22)

0.042 (1.07)

0.021 (0.53)

0.013 (0.33)

PIN 1

IDENTIFIER

BOTTOM

VIEW

(PINS UP)

0.050

(1.27)

BSC

0.430 (10.92)

0.390 (9.91)

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

11

12

19

18

0.045 (1.14)

0.025 (0.64)

R

0.456 (11.582)

0.450 (11.430)

SQ

0.120 (3.04)

0.090 (2.29)

0.495 (12.57)

SQ

0.485 (12.32)

COMPLIANT TO JEDEC STANDARDS MO-047-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 45. 28-Lead Plastic Leaded Chip Carrier [PLCC]

(P-28)

Dimensions shown in inches and (millimeters)

0.100 (2.54)

MAX

0.005 (0.13)

MIN

28

15

14

0.610 (15.49)

0.500 (12.70)

1

PIN 1

0.620 (15.75)

0.590 (14.99)

0.015 (0.38)

MIN

0.225(5.72)

MAX

1.490 (37.85) MAX

0.150 (3.81)

MIN

0.018 (0.46)

0.008 (0.20)

15°

0°

0.200 (5.08)

0.125 (3.18)

0.100

(2.54)

BSC

SEATING

PLANE

0.070 (1.78)

0.030 (0.76)

0.026 (0.66)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 46. 28-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-28-2)

Dimensions shown in inches and (millimeters)

Rev. G | Page 19 of 20

DAC8412/DAC8413

Data Sheet

ORDERING GUIDE

Model¹

Notes Temperature Range

INL

Package Description

Package Option

Q-28-2

E-28-1

N-28-2

P-28

DAC8412AT/883C

DAC8412BT/883C

DAC8412BTC/883C

DAC8412EP

DAC8412EPZ

DAC8412FP

−55°C to +125°C

−40°C to +85°C

−55°C to +125°C

−40°C to +85°C

0.75 28-Lead Ceramic Dual In-Line Package [CERDIP]

1.5

0.5

1

28-Lead Ceramic Dual In-Line Package [CERDIP]

28-Terminal Ceramic Leadless Chip Carrier [LCC]

28-Lead Plastic Dual In-Line Package [PDIP]

28-Lead Plastic Leaded Chip Carrier [PLCC]

28-Lead Plastic Dual In-Line Package [PDIP]

2

DAC8412FPC

DAC8412FPC-REEL

DAC8412FPCZ

DAC8412FPCZ-REEL

DAC8412FPZ

P-28

1

N-28-2

Q-28-2

E-28-1

N-28-2

P-28

N-28-2

DAC8413AT/883C

DAC8413BT/883C

DAC8413BTC/883C

DAC8413EP

DAC8413EPZ

DAC8413FP

0.75 28-Lead Ceramic Dual In-Line Package [CERDIP]

1.5

0.5

1

28-Lead Ceramic Dual In-Line Package [CERDIP]

28-Terminal Ceramic Leadless Chip Carrier [LCC]

28-Lead Plastic Dual In-Line Package [PDIP]

28-Lead Plastic Leaded Chip Carrier [PLCC]

28-Lead Plastic Dual In-Line Package [PDIP]

2

DAC8413FPC

DAC8413FPC-REEL

DAC8413FPCZ

DAC8413FPC-REEL

DAC8413FPZ

1

¹Z = RoHS Compliant Part.

²If burn-in is required, these models are available in CERDIP. Contact sales.

registered trademarks are the property of their respective owners.

D00274-0-4/13(G)

Rev. G | Page 20 of 20


型号：	DAC8412AT
厂家：	ADI
描述：	Quad, 12-Bit DAC Voltage Output with Readback 四通道，12位DAC电压输出，回读
文件：	总20页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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