ACT-F128K32N-090F5C [AEROFLEX]

ACT-F128K32 High Speed 4 Megabit FLASH Multichip Module; ACT- F128K32高速4兆位闪存多芯片模块
ACT-F128K32N-090F5C
型号: ACT-F128K32N-090F5C
厂家: AEROFLEX CIRCUIT TECHNOLOGY    AEROFLEX CIRCUIT TECHNOLOGY
描述:

ACT-F128K32 High Speed 4 Megabit FLASH Multichip Module
ACT- F128K32高速4兆位闪存多芯片模块

闪存
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中文:  中文翻译
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ACT–F128K32 High Speed  
4 Megabit FLASH Multichip Module  
CIRCUIT TECHNOLOGY  
www.aeroflex.com  
Features  
4 Low Power 128K x 8 FLASH Die in One MCM  
MIL-PRF-38534 Compliant MCMs Available  
Industry Standard Pinouts  
Package  
Organized as 128K x 32  
Packaging – Hermetic Ceramic  
User Configurable to 256K x 16 or 512K x 8  
Upgradable to 512K x 32 in same Package Style  
Access Times of 60, 70, 90, 120 and 150ns  
+5V Programing, 5V ±10% Supply  
100,000 Erase/Program Cycles Typical, 0°C to +70°C  
Low Standby Current  
68 Lead, .88" x .88" x .160" Single-Cavity Small  
Outline gull wing, Aeroflex code# "F5" (Drops into  
the 68 Lead JEDEC .99"SQ CQFJ footprint)  
66 Pin, 1.08" x 1.08" x .160" PGA Type, No  
Shoulder, Aeroflex code# "P3"  
66 Pin, 1.08" x 1.08" x .185" PGA Type, With  
Shoulder, Aeroflex code# "P7"  
TTL Compatible Inputs and CMOS Outputs  
Embedded Erase and Program Algorithms  
Page Program Operation and Internal Program  
Control Time  
Commercial, Industrial and Military Temperature  
Ranges  
Sector Architecture (Each Die)  
8 Equal size sectors of 64K bytes each  
Any Combination of Sectors can be erased with  
one command sequence  
Supports Full Chip Erase  
DESC SMD# 5962–94716 Released (P3,P7,F5)  
General Description  
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)  
The ACT–F128K32 is a high  
speed, 4 megabit CMOS flash  
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4  
multichip  
module  
(MCM)  
OE  
A0–A16  
designed for full temperature  
range military, space, or high  
reliability applications.  
128Kx8  
128Kx8  
128Kx8  
128Kx8  
The MCM can be organized  
as a 128K x 32 bits, 256K x 16  
bits or 512K x 8 bits device and  
is input TTL and output CMOS  
8
8
8
8
I/O0-7  
I/O8-15  
I/O16-23  
I/O24-31  
compatible.  
The  
command  
register is written by bringing  
WE to a logic low level (VIL),  
while CE is low and OE is at  
logic high level (VIH). Reading is  
accomplished by chip Enable  
(CE) and Output Enable (OE)  
being logically active, see  
Figure 9. Access time grades of  
60ns, 70ns, 90ns, 120ns and  
150ns maximum are standard.  
Pin Description  
I/O0-31  
Data I/O  
A0–16 Address Inputs  
WE1-4 Write Enables  
CE1-4 Chip Enables  
OE Output Enable  
VCC Power Supply  
GND  
Ground  
The  
ACT–F128K32  
is  
packaged in a hermetically  
NC Not Connected  
eroflex Circuit Technology - Advanced Multichip Modules © SCD1667 REV A 4/28/98  
General Description, Cont’d,  
sealed co-fired ceramic 66 pin, 1.08" sq  
PGA or a 68 lead, .88" sq Ceramic Gull  
Wing CQFP package for operation over the  
temperature range of -55°C to +125°C and  
military environment.  
second. Erase is accomplished by  
executing the erase command sequence.  
This will invoke the Embedded Erase  
Algorithm which is an internal algorithm  
that automatically preprograms the array, (if  
it is not already programmed before)  
executing the erase operation. During  
erase, the device automatically times the  
erase pulse widths and verifies proper cell  
margin.  
Each flash memory die is organized as  
128KX8 bits and is designed to be  
programmed in-system with the standard  
system 5.0V Vcc supply. A 12.0V VPP is  
not required for write or erase operations.  
The MCM can also be reprogrammed with  
standard EPROM programmers (with the  
proper socket).  
Each die in the module or any individual  
sector of the die is typically erased and  
verified in 1.3 seconds (if already  
completely preprogrammed).  
The standard ACT-F128K32 offers  
access times between 60ns and 150ns,  
Each die also features a sector erase  
architecture. The sector mode allows for  
allowing  
operation  
of  
high-speed  
microprocessors without wait states. To 16K byte blocks of memory to be erased  
eliminate bus contention, the device has  
separate chip enable (CE) and write enable  
(WE). The ACT-F128K32 is command set  
compatible with JEDEC standard 1 Mbit  
EEPROMs. Commands are written to the  
and reprogrammed without affecting other  
blocks. The ACT-F128K32 is erased when  
shipped from the factory.  
The device features single 5.0V power  
supply operation for both read and write  
command  
register  
using  
standard  
functions.  
lnternally  
generated  
and  
microprocessor write timings. Register  
contents serve as input to an internal  
state-machine which controls the erase and  
programming circuitry. Write cycles also  
internally latch addresses and data needed  
for the programming and erase operations.  
regulated voltages are provided for the  
program and erase operations. A low VCC  
detector  
automatically  
inhibits  
write  
operations on the loss of power. The end of  
program or erase is detected by Data  
Polling of D7 or by the Toggle Bit feature on  
D6. Once the end of a program or erase  
cycle has been completed,-+ the device  
internally resets to the read mode.  
Reading data out of the device is similar  
to reading from 12.0V Flash or EPROM  
devices. The ACT-F128K32 is programmed  
by executing the program command  
sequence. This will invoke the Embedded  
Program Algorithm which is an internal  
algorithm that automatically times the  
program pulse widths and verifies proper  
cell margin. Typically, each sector can be  
programmed and verified in less than 0.3  
All bits of each die, or all bits within a  
sector of  
a
die, are erased via  
Fowler-Nordhiem tunneling. Bytes are  
programmed one byte at a time by hot  
electron injection.  
DESC Standard Military Drawing (SMD)  
numbers are released.  
2
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z
Absolute Maximum Ratings  
Parameter  
Symbol  
TC  
Range  
-55 to +125  
-65 to +150  
-2.0 to +7.0  
-2.0 to +7.0  
300  
Units  
°C  
Case Operating Temperature  
Storage Temperature Range  
Supply Voltage Range  
TSTG  
VCC  
°C  
V
VG  
V
Signal Voltage Range (Any Pin Except A9) Note 1  
Maximum Lead Temperature (10 seconds)  
Data Retention  
°C  
10  
Years  
100,000 Minimum  
-2.0 to +14.0  
Endurance (Write/Erase cycles)  
A9 Voltage for sector protect, Note 2  
VID  
V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0v for periods of up  
to 20ns. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to  
VCC + 2.0V for periods up to 20 ns.  
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns.  
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.  
Normal Operating Conditions  
Symbol Parameter  
Minimum  
+4.5  
Maximum  
Units  
V
VCC  
VIH  
VIL  
TC  
+5.5  
Power Supply Voltage  
Input High Voltage  
+2.0  
V
+ 0.5  
V
CC  
+0.8  
-0.5  
V
Input Low Voltage  
-55  
+125  
12.5  
°C  
V
Operating Temperature (Military)  
A9 Voltage for sector protect  
VID  
11.5  
Capacitance  
(VIN= 0V, f = 1MHz, TC = 25°C)  
Symbol Parameter  
Maximum  
Units  
CAD  
50  
50  
pF  
pF  
A0 – A16 Capacitance  
OE Capacitance  
COE  
CWE  
Write Enable Capacitance  
CQFP(F5) Package  
20  
20  
20  
20  
pF  
pF  
pF  
pF  
PGA(P3,P7) Package  
Chip Enable Capacitance  
I/O0 – I/O31 Capacitance  
CCE  
CI/O  
Parameters Guaranteed but not tested  
DC Characteristics – CMOS Compatible  
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C, unless otherwise indicated)  
Speeds 60, 70, 90, 120 & 150ns  
Parameter  
Sym  
Conditions  
Minimum  
Maximum  
10  
Units  
µA  
µA  
mA  
mA  
mA  
mA  
V
ILI  
Input Leakage Current  
VCC = 5.5V, ViN = GND to VCC  
VCC = 5.5V, ViN = GND to VCC  
CE = VIL, OE = VIH, f = 5MHz  
CE = VIL, OE = VIH  
ILOX32  
ICC1  
ICC2  
ICC3  
ICC4  
VOL  
10  
Output Leakage Current  
140  
Active Operating Supply Current for Read (1)  
Active Operating Supply Current for Program or Erase(2)  
Standby Supply Current  
200  
6.5  
VCC = 5.5V, CE = VIH, f = 5MHz  
VCC = 5.5V, CE = VIH  
0.6  
Static Supply Current (4)  
0.45  
Output Low Voltage  
IOL = +8.0 mA, VCC = 4.5V  
IOH = –2.5 mA, VCC = 4.5V  
IOH = –100 µA, VCC = 4.5V  
VOH1  
VOH2  
VLKO  
0.85 x VCC  
VCC – 0.4  
3.2  
V
Output High Voltage  
V
Output High Voltage (4)  
V
Low Power Supply Lock-Out Voltage (4)  
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency  
component typically is less than 2 mA/MHz, with OE at VIN.  
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.  
Note 3. DC Test conditions: VIL = 0.3V, VIH = VCC - 0.3V, unless otherwise indicated  
Note 4. Parameter Guaranteed but not tested.  
3
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Characteristics – Read Only Operations  
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)  
Symbol –60  
JEDEC Stand’d Min Max Min Max Min Max Min Max  
–70  
–90  
–120  
–150  
Min Max  
150  
Parameter  
Units  
tAVAV  
tAVQV  
tELQV  
tGLQV  
tEHQZ  
tGHQZ  
tAXQX  
tRC  
tACC  
tCE  
60  
70  
90  
120  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
60  
60  
30  
20  
20  
70  
70  
35  
20  
20  
90  
90  
40  
25  
25  
120  
120  
50  
150  
Address Access Time  
150  
Chip Enable Access Time  
tOE  
tDF  
55  
Output Enable to Output Valid  
30  
35  
Chip Enable to Output High Z (1)  
Output Enable High to Output High Z (1)  
Output Hold from Address, CE or OE Change, whichever is first  
Note 1. Guaranteed by design, but not tested  
tDF  
30  
35  
tOH  
0
0
0
0
0
AC Characteristics – Write/Erase/Program Operations, WE Controlled  
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)  
Symbol –60  
–70  
–90  
–120  
–150  
Parameter  
Units  
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max  
tAVAC  
tELWL  
tWLWH  
tAVWL  
tWC  
tCE  
60  
0
70  
0
90  
0
120  
0
150  
0
ns  
ns  
Write Cycle Time  
Chip Enable Setup Time  
Write Enable Pulse Width  
Address Setup Time  
tWP  
tAS  
30  
0
35  
0
45  
0
50  
0
50  
0
ns  
ns  
tDVWH  
tWHDX  
tWLAX  
tDS  
30  
0
30  
0
45  
0
50  
0
50  
0
ns  
Data Setup Time  
tDH  
tAH  
tCH  
tWPH  
ns  
Data Hold Time  
45  
0
45  
0
45  
0
50  
0
50  
0
ns  
Address Hold Time  
tWHEH  
tWHWL  
tWHWH1  
tWHWH2  
tWHWH3  
ns  
Chip Enable Hold Time (1)  
Write Enable Pulse Width High  
Duration of Byte Programming Operation  
Sector Erase Time  
20  
20  
20  
20  
20  
ns  
14 TYP 14 TYP 14 TYP 14 TYP 14 TYP  
µs  
60  
60  
60  
60  
60  
Sec  
Sec  
µs  
120  
120  
120  
120  
120  
Chip Erase Time  
tGHWL  
0
0
0
0
0
Read Recovery Time before Write (1)  
Vcc Setup Time (1)  
tVCE  
50  
50  
50  
50  
50  
µs  
12.5  
12.5  
12.5  
12.5  
12.5  
Sec  
ns  
Chip Programming Time  
Output Enable Setup Time (1)  
Output Enable Hold Time (1)  
Note 1. Guaranteed by design, but not tested  
tOES  
tOEH  
0
0
0
0
0
10  
10  
10  
10  
10  
ns  
AC Characteristics – Write/Erase/Program Operations, CE Controlled  
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)  
Symbol –60  
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max  
–70  
–90  
–120  
–150  
Parameter  
Units  
tAVAC  
tWLEL  
tELEH  
tWC  
tWS  
tCP  
60  
0
70  
0
90  
0
120  
0
150  
0
ns  
ns  
Write Cycle Time  
Write Enable Setup Time  
Chip Enable Pulse Width  
Address Setup Time  
35  
0
35  
0
45  
0
50  
0
55  
0
ns  
tAVEL  
tAS  
ns  
tDVEH  
tDS  
30  
0
30  
0
45  
0
50  
0
55  
0
ns  
Data Setup Time  
tEHDX  
tDH  
tAH  
tWH  
tCPH  
ns  
Data Hold Time  
tELAX  
45  
0
45  
0
45  
0
50  
0
55  
0
ns  
Address Hold Time  
tEHWH  
tEHEL  
ns  
Write Enable Hold Time (1)  
Write Select Pulse Width High  
Duration of Byte Programming  
Sector Erase Time  
20  
20  
20  
20  
20  
ns  
tWHWH1  
tWHWH2  
tWHWH3  
14 TYP 14 TYP 14 TYP 14 TYP 14 TYP  
µs  
60  
60  
60  
60  
60  
Sec  
Sec  
ns  
120  
120  
120  
120  
120  
Chip Erase Time  
tGHEL  
0
0
0
0
0
Read Recovery Time (1)  
Chip Programming Time  
Note 1. Guaranteed by design, but not tested  
12.5  
12.5  
12.5  
12.5  
12.5  
Sec  
4
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current consumed is typically less than 400 µA; and a  
TTL standby mode (CE is held VIH) is approximately 1  
mA. In the standby mode the outputs are in a high  
impedance state, independent of the OE input.  
Device Operation  
The ACT-F128K32 MCM is composed of four, one  
megabit flash EEPROMs. The following description is for  
the individual flash EEPROM device, is applicable to  
each of the four memory chips inside the MCM. Chip 1 is  
distinguished by CE1 and I/O1-7, Chip 2 by CE2 and  
I/08-15, Chip 3 by CE3 and I/016-23, and Chip 4 by CE4 and  
I/024-31.  
If the device is deselected during erasure or  
programming, the device will draw active current until the  
operation is completed.  
WRITE  
Programming of the ACT-F128K32 is accomplished by  
executing the program command sequence.  
The  
Device erasure and programming are accomplished via  
the command register. The contents of the register serve  
as input to the internal state machine. The state machine  
outputs dictate the function of the device.  
program algorithm, which is an internal algorithm,  
automatically times the program pulse widths and verifies  
proper cell status. Sectors can be programed and  
verified in less than 0.3 second. Erase is accomplished  
by executing the erase command sequence. The erase  
algorithm, which is internal, automatically preprograms  
the array if it is not already programed before executing  
The command register itself does not occupy an  
addressable memory location. The register is a latch  
used to store the command, along with address and data  
information needed to execute the command. The  
command register is written by bringing WE to a logic low  
level (VIL), while CE is low and OE is at VIH. Addresses  
are latched on the falling edge of WE or CE, whichever  
happens later. Data is latched on the rising edge of the  
the erase operation.  
During erase, the device  
automatically times the erase pulse widths and verifies  
proper cell status. The entire memory is typically erased  
and verified in 3 seconds (if pre-programmed). The  
sector mode allows for 16K byte blocks of memory to be  
erased and reprogrammed without affecting other blocks.  
WE or CE whichever occurs first.  
Standard  
microprocessor write timings are used. Refer to AC  
Program Characteristics and Waveforms, Figures 3,  
8 and 13.  
Bus Operation  
READ  
Command Definitions  
The ACT-F128K32 has two control functions, both of  
which must be logically active, to obtain data at the  
outputs. Chip Enable (CE) is the power control and  
should be used for device selection. Output-Enable (OE)  
is the output control and should be used to gate data to  
the output pins of the chip selected. Figure 7 illustrates  
AC read timing waveforms.  
Device operations are selected by writing specific  
address and data sequences into the command register.  
Table 3 defines these register command sequences.  
READ/RESET COMMAND  
The read or reset operation is initiated by writing the  
read/reset command sequence into the command  
register. Microprocessor read cycles retrieve array data  
from the memory. The device remains enabled for reads  
until the command register contents are altered.  
OUTPUT DISABLE  
With Output-Enable at a logic high level (VIH), output from  
the device is disabled. Output pins are placed in a high  
impedance state.  
The device will automatically power-up in the read/reset  
state. In this case, a command sequence is not required  
to read data. Standard microprocessor read cycles will  
STANDBY MODE  
The ACT-F128K32 has two standby modes, a CMOS  
standby mode (CE input held at Vcc + 0.5V), where the  
retrieve array data.  
power-up in the read/reset state. In this case, a command  
sequence is not required to read data. Standard  
The device will automatically  
Microprocessor read cycles will retrieve array data. This  
Table 1 – Bus Operations  
Table 2 – Sector Addresses Table  
Operation  
READ  
CE OE WE A0 A1 A9  
I/O  
A16 A15 A14  
Address Range  
00000h – 03FFFh  
04000h – 07FFFh  
08000h – 0BFFFh  
0C000h – 0FFFFh  
10000h – 13FFFh  
14000h – 17FFFh  
18000h – 1BFFFh  
1C000h – 1FFFFh  
L
H
L
L
X
H
H
H
X
H
L
A0 A1 A9 DOUT  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
HIGH Z  
HIGH Z  
DIN  
STANDBY  
OUTPUT DISABLE  
WRITE  
L
A0 A1 A9  
ENABLE SECTOR  
PROTECT  
L
L
VID  
L
L
X
L
X
H
VID  
X
VERIFY SECTOR  
PROTECT  
H
VID Code  
5
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Table 3 — Commands Definitions  
Bus  
Write  
Fourth Bus  
Read/Write  
First Bus Write Second Bus Write Third Bus Write  
Cycle Cycle Cycle  
Fifth Bus Write Sixth Bus Write  
Cycle Cycle  
Command  
Sequence  
Cycle  
Cycle  
Req’d Addr  
Data  
AAH  
AAH  
AAH  
AAH  
Addr  
Data  
55H  
55H  
55H  
55H  
Addr  
Data  
F0H  
A0H  
80H  
80H  
Addr  
Data  
RD  
Addr  
Data  
Addr  
Data  
Read/Reset  
Byte Program  
Chip Erase  
4
6
6
6
5555H  
5555H  
5555H  
5555H  
2AAAH  
2AAAH  
2AAAH  
2AAAH  
5555H  
5555H  
5555H  
5555H  
RA  
PA  
PD  
5555H  
5555H  
AAH  
AAH  
2AAAH 55H  
2AAAH 55H  
5555H 10H  
SA 30H  
Sector Erase  
NOTES:  
1. Address bit A15 = X = Don't Care. Write Sequences may be initiated with A15 in either state.  
2. Address bit A16 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).  
3. RA = Address of the memory location to be read  
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.  
SA = Address of the sector to be erased. The combination of A16, A15, A14 will uniquely select any sector.  
4. RD = Data read from location RA during read Operation.  
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.  
default value ensures that no spurious alteration of the  
memory content occurs during the power transition.  
CHIP ERASE  
Chip erase is a six bus cycle operation. There are two  
'unlock' write cycles. These are followed by writing the  
“set-up” command. Two more “unlock” write cycles are  
then followed by the chip erase command.  
Refer to the AC Read Characteristics and Figure 7 for the  
specific timing parameters.  
BYTE PROGRAMING  
Chip erase does not require the user to program the  
device prior to erase. Upon executing the Embedded  
Erase Algorithm command sequence (Figure 4) the  
device will automatically program and verify the entire  
memory for an all zero data pattem prior to electrical  
erase. The erase is performed concurrently on all sectors  
at the same time . The system is not required to provide  
any controls or timings during these operations. Note:  
Post Erase data state is all "1"s.  
The device is programmed on a byte-byte basis.  
Programming is a four bus cycle operation. There are  
two "unlock" write cycles. These are followed by the  
program set-up command and data write cycles.  
Addresses are latched on the falling edge of CE or WE,  
whichever occurs later, while the data is latched on the  
rising edge of CE or WE whichever occurs first. The  
rising edge of CE or WE (whichever happens first) begins  
programming using the Embedded Program Algorithm.  
Upon executing the program algorithm command  
sequence the system is not required to provide further  
controls or timings. The device will automatically provide  
adequate internally generated program pulses and verify  
the programmed cell.  
The automatic erase begins on the rising edge of the last  
WE pulse in the command sequence and terminates  
when the data on D7 is "1" (see Write Operation Status  
section - Table 3) at which time the device retums to read  
mode. See Figures 4 and 9.  
The automatic programming operation is completed  
when the data on D7 (also used as Data Polling) is  
equivalent to data written to this bit at which time the  
device returns to the read mode and addresses are no  
longer latched. Therefore, the device requires that a valid  
address be supplied by the system at this particular  
instance of time for Data Polling operations. Data Polling  
must be performed at the memory location which is being  
programmed.  
SECTOR ERASE  
Sector erase is a six bus cycle operation. There are two  
"unlock" write cycles. These are followed by writing the  
"setup" command. Two more "unlock" write cycles are  
then followed by the sector erase command. The sector  
address (any address location within the desired sector)  
is latched on the falling edge of WE, while the command  
(30H) is latched on the rising edge of WE. After a  
time-out of 80µs from the rising edge of the last sector  
erase command, the sector erase operation will begin.  
Any commands written to the chip during the Embedded  
Program Algorithm will be ignored.  
Multiple sectors may be erased concurrently by writing  
the six bus cycle operations as described above. This  
sequence is followed with writes of the sector erase  
command to addresses in other sectors desired to be  
concurrently erased. The time between writes must be  
less than 80µs otherwise that command will not be  
accepted and erasure will start. It is recommended that  
processor interrupts be disabled during this time to  
Programming is allowed in any sequence and across  
sector boundaries. Beware that a data "0" cannot be  
programmed back to a “1". Attempting to do so may  
cause the device to exceed programming time limits (D5  
= 1) or result in an apparent success, according to the  
data polling algorithm, but a read from reset/read mode  
will show that the data is still “0". Only erase operations  
can convert “0"s to “1"s.  
guarantee this condition.  
The interrupts can be  
Figure 3 illustrates the programming algorithm using  
typical command strings and bus operations.  
re-enabled after the last Sector Erase command is  
written. A time-out of 80µs from the rising edge of the  
last WE will initiate the execution of the Sector Erase  
command(s). If another falling edge of the WE occurs  
6
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
within the 80µs time-out window the timer is reset.  
(Monitor D3 to determine if the sector erase timer window  
is still open, see section D3, Sector Erase Timer.) Any  
commarid other than Sector Erase during this period will  
reset the device to read mode, ignoring the previous  
command string. In that case, restart the erase on those  
sectors and allow them to complete.  
LOGICAL INHIBIT  
Writing is inhibited by holding anyone of OE = VIL, CE =  
VIH or WE = VIH. To initiate a write cycle CE and WE  
must be logical zero while OE is a logical one.  
POWER-UP WRITE INHIBIT  
Loading the sector erase buffer may be done in any  
sequence and with any number of sectors (0 to 7).  
Power-up of the device with WE = CE = VIL and OE = VIH  
will not accept commands on the rising edge of WE. The  
internal state machine is automatically reset to the read  
mode on power-up.  
Sector erase does not require the user to program the  
device prior to erase. The device automatically programs  
all memory locations in the sector(s) to be erased prior to  
electrical erase. When erasing a sector or sectors the  
remaining unselected sectors are not affected. The  
system is not required to provide any controls or timings  
during these operations. Post Erase data state is all "1"s.  
Write Operation Status  
D7  
DATA POLLING  
The ACT-F128K32 features Data Polling as a method to  
indicate to the host that the internal algorithms are in  
progress or completed.  
The automatic sector erase begins after the 80µs time  
out from the rising edge of the WE pulse for the last  
sector erase command pulse and terminates when the  
data on D7, Data Polling, is “1" (see Write Operatlon  
Status secton) at which time the device returns to read  
mode. Data Polling must be performed at an address  
within any of the sectors being erased.  
During the program algorithm, an attempt to read the  
device will produce compliment data of the data last  
written to D7. Upon completion of the programming  
algorithm an attempt to read the device will produce the  
true data last written to D7. Data Polling is valid after the  
rising edge of the fourth WE pulse in the four write pulse  
sequence.  
Figure 4 illustrates the Embedded Erase Algorithm.  
Data Protection  
The ACT-F128K32 is designed to offer protection against  
accidental erasure or programming caused by spurious  
system level singles that may exist during power  
transitions. During power up the device automatically  
resets the internal state machine in the read mode. Also,  
with its control register architecture, alteration of the  
memory content only occurs after successful completion  
of specific multi-bus cycle command sequences.  
During the erase algorithm, D7 will be "0" until the erase  
operation is completed. Upon completion data at D7 is  
"1". For chip erase, the Data Polling is valid after the  
rising edge of the sixth WE pulse in the six write pulse  
sequence. For sector erase, the Data Polling is Valid  
after the last rising edge of the sector erase WE pulse.  
The Data Polling feature is only active during the  
programming algorithm, erase algorithm, or sector erase  
time-out.  
The device also incorporates several features to prevent  
inadvertent write cycles resulting from Vcc power-up and  
power-down transitions or system noise.  
See Figures 6 and 10 for the Data Polling specifications.  
LOW Vcc WRITE INHIBIT  
D6  
To avoid initiation of a write cycle during Vcc power-up  
and power-down, a write cycle is locked out for VCC less  
than 3.2V (typically 3.7V). If VCC < VLKO, the command  
register is disabled and all internal program/erase circuits  
are disabled. Under this condition the device will reset to  
read mode. Subsequent writes will be ignored until the  
TOGGLE BIT  
The ACT-F128K32 also features the "Toggle Bit" as a  
method to indicate to the host system that algorithms are  
in progress or completed.  
During a program or erase algorithm cycle, successive  
attempts to read data from the device will result in D6  
toggling between one and zero. Once the program or  
erase algorithm cycle is completed, D6 Will stop toggling  
and valid data will be read on successive attempts.  
During programming the Toggle Bit is valid after the rising  
edge of the fourth WE pulse in the four write pulse  
sequence. For chip erase the Toggle Bit is valid after the  
rising edge of the sixth WE pulse in the six write pulse  
sequence. For Sector erase, the Toggle Bit is valid after  
the last rising edge of the sector erase WE pulse. The  
Toggle Bit is active during the sector time out.  
Vcc level is greater than VLKO.  
It is the users  
responsibility to ensure that the control pins are logically  
correct to prevent unintentional writes when Vcc is above  
3.2V.  
WRITE PULSE GLITCH PROTECTION  
Noise pulses of less than 5ns (typical) on OE, CE or WE  
will not initiate a write cycle.  
See Figure 1 and 5.  
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Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Table 4 — Hardware Sequence Flags  
Status  
D7  
D6  
D5 D4 D3  
D2 – D0  
D7 Toggle  
0
0
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
Auto-Programming  
Programming in Auto Erase  
Erase in Auto Erase  
Auto-Programming  
Programming in Auto Erase  
Erase in Auto Erase  
In Progress  
Reserved for  
future use  
0
0
Toggle  
Toggle  
D7 Toggle  
T0 Toggle  
Reserved for  
future use  
Exceeding Time Limits  
0
Toggle  
D5  
Sector Protection  
Algorithims  
EXCEEDED TIMING LIMITS  
D5 will indicate if the program or erase time has  
exceeded the specified limits. Under these conditions  
D5 will produce a "1". The Program or erase cycle was  
not successfully completed. Data Polling is the only  
operation function of the device under this condition.  
The CE circuit will partially power down the device under  
these conditions by approximately 8 mA per chip. The  
OE and WE pins will control the output disable functions  
as shown in Table 1. To reset the device, write the reset  
command sequence to the device. This allows the  
system to continue to use the other active sectors in the  
device.  
SECTOR PROTECTION  
The ACT-F128K32 features hardware sector protection  
which will disable both program and erase operations to  
an individual sector or any group of sectors. To activate  
this mode, the programming equipment must force VID  
on control pin OE and address pin A9. The sector  
addresses should be set using higher address lines A16,  
A15, and A14. The protection mechanism begins on the  
falling edge of the WE pulse and is terminated with the  
rising edge of the same.  
It is also possible to verify if a sector is protected during  
the sector protection operation. This is done by setting  
CE = OE = VIL and WE = VIH (A9 remains high at VID).  
Reading the device at address location XXX2H, where  
the higher order addresses (A16, A15 and A14) define a  
particular sector, will produce 01H at data outputs D0 -  
D7, for a protected sector.  
D4 - HARDWARE SEQUENCE FLAG  
If the device has exceeded the specified erase or  
program time and D5 is "1", then D4 Will indicate which  
step in the algorithm the device exceeded the limits. A  
"0" in D4 indicates in programming, a "1" indicates an  
erase. (See Table 4)  
SECTOR UNPROTECT  
D3  
The ACT-F128K32 also features a sector unprotect  
mode, so that a protected sector may be unprotected to  
incorporate any changes in the code. All sectors should  
be protected prior to unprotecting any sector.  
SECTOR ERASE TIMER  
After the completion of the initial sector erase command  
sequence the sector erase time-out will begin. D3 will  
remain low until the time-out is complete. Data Polling  
and Toggle Bit are valid after the initial sector erase  
command sequence.  
To activate this mode, the programming equipment must  
force VID on control pins OE, CE, and address pin A9.  
The address pins A6, A7, and A12 should be set to VIH,  
and A6 = VIL. The unprotection mechanism begins on  
the falling edge of the WE pulse and is terminated with  
the rising edge of the same.  
If Data Polling or the Toggle Bit indicates the device has  
been written with a valid erase command, D3 may be  
used to determine if the sector erase timer window is still  
open. If D3 is high ("1") the internally controlled erase  
cycle has begun; attempts to write subsequent  
commands to the device will be ignored until the erase  
operation is completed as indicated by Data Polling or  
Toggle Bit. If D3 is low ("0"), the device will accept  
additional sector erase commands. To ensure the  
command has been accepted, the software should check  
the status of D3 prior to and following each subsequent  
sector erase command. If D3 were high on the second  
status check, the command may not have been  
accepted.  
It is also possible to determine if a sector is unprotected  
in the system by writing the autoselect command.  
Performing a read operation at address location XXX2H,  
where the higher order addresses (A16, A15, and A14)  
define a particular sector address, will produce 00H at  
data outputs (D0-D7) for an unprotected sector.  
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Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 1  
AC Waveforms for Toggle Bit During Embedded Algorithm Operations  
CE  
tOEH  
WE  
tOES  
OE  
Data  
D0-D7  
D6  
D0-D7  
Valid  
D6=Toggle  
D6=Toggle  
Stop Toggle  
tOE  
Figure 2  
AC Test Circuit  
Current Source  
IOL  
Parameter  
Typical  
Units  
V
Input Pulse Level  
0 – 3.0  
5
Input Rise and Fall  
ns  
Input and Output Timing Reference  
Output Lead Capacitance  
1.5  
V
VZ ~ 1.5 V (Bipolar Supply)  
To Device Under Test  
50  
pF  
CL =  
50 pF  
IOH  
Current Source  
Notes:  
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance  
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical  
resistance load circuit. 6) ATE Tester includes jig capacitance.  
9
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 3  
Programming Algorithm  
Bus  
Operations  
Command  
Sequence  
Comments  
Standby  
Write  
Program  
Valid Address/Data Sequence  
Read  
Data Polling to Verify Programming  
Compare Data Output to Data Expected  
Standby  
Start  
Write Program Command Sequence  
(See Below)  
Data Poll Device  
No  
Increment  
Address  
Last Address  
?
Yes  
Programming Complete  
Program Command Sequence (Address/Command):  
5555H/AAH  
2AAAH/55H  
5555H/A0H  
Programming Address/Program Data  
10  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 4  
Erase Algorithm  
Bus  
Operations  
Command  
Sequence  
Comments  
Standby  
Write  
Erase  
Read  
Data Polling to Verify Erasure  
Compare Output to FFH  
Standby  
Start  
Write Erase Command Sequence  
(See Below)  
Data Poll or Toggle Bit  
Successfully Completed  
Erasure Completed  
Chip Erase Command Sequence  
Individual Sector/Multiple Sector  
Erase Command Sequence  
(Address/Command)  
(Address/Command)  
5555H/AAH  
5555H/AAH  
2AAAH/55H  
5555H/80H  
5555H/AAH  
2AAAH/55H  
5555H/10H  
2AAAH/55H  
5555H/80H  
5555H/AAH  
2AAAH/55H  
Sector Address/30H  
Sector Address/30H  
Sector Address/30H  
Additional Sector  
Erase Commands  
are Optional  
Note 1. To Ensure the command has been accepted, the system software should check the  
status of D3 prior to and following each subsequent sector erase command. If D3 were high on  
the second status check, the command may not have been accepted.  
11  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 5  
Figure 6  
Toggle Bit Algorithm  
Data Polling Algorithm  
Start  
Start  
VA = Byte Address for Programming  
VA = Byte Address for Programming  
= Any of the Sector Addresses  
within the sector being erased  
during sector erase operation  
= Any of the Sector Addresses  
within the sector being erased  
during sector erase operation  
Read Byte  
D0-D7  
Address = VA  
Read Byte  
D0-D7  
Address = VA  
= XXXXH during Chip Erase  
= XXXXH during Chip Erase  
Yes  
No  
D7 = Data  
?
D6 = Toggle  
?
No  
Yes  
No  
No  
D5 = 1  
?
D5 = 1  
?
Yes  
Yes  
Read Byte  
D0-D7  
Address = VA  
Read Byte  
D0-D7  
Address = VA  
D6 =  
Toggle?  
(Note 1)  
D7 =  
Toggle?  
(Note 1)  
Yes  
No  
Pass  
Pass  
No  
Yes  
Fail  
Fail  
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at  
the same time as D5 changes to "1".  
Note 1. D7 is rechecked even if D5 = "1" because D7 may change  
simultaneously with D5.  
12  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 7  
AC Waveforms for Read Operations  
tRC  
Addresses  
CE  
Addresses Stable  
tACC  
tDF  
OE  
tOE  
WE  
tCE  
tOH  
High Z  
High Z  
Outputs  
Output Valid  
Figure 8  
Write/Erase/Program  
Operation, WE Controlled  
Data Polling  
Addresses  
5555H  
PA  
PA  
tRC  
tWC  
tAH  
tAS  
CE  
OE  
tGHWL  
tWP  
tWHWH1  
tWPH  
WE  
tCE  
tDF  
tOE  
tDH  
AOH  
PD  
D7  
DOUT  
Data  
5.0V  
tDS  
tOH  
tCE  
Notes:  
1. PA is the address of the memory location to be programmed.  
2. PD is the data to be programmed at byte address.  
3. D7 is the 0utput of the complement of the data written to the deviced.  
4. Dout is the output of the data written to the device.  
5. Figure indicates last two bus cycles of four bus cycle sequence.  
13  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 9  
AC Waveforms Chip/Sector  
Erase Operations  
Data Polling  
5555H  
tAH  
5555H  
2AAAH  
5555H  
2AAAH  
SA  
Addresses  
tAS  
CE  
OE  
WE  
tGHWL  
tWP  
tWPH  
tDH  
tCE  
AAH  
55H  
80H  
AAH  
55H  
10H/30H  
Data  
VCC  
tDS  
tVCE  
Notes:  
1. SA is the sector address for sector erase.  
Figure 10  
AC Waveforms for Data Polling  
During Embedded Algorithm Operations  
tCH  
CE  
tDF  
tOE  
OE  
tOEH  
tCE  
WE  
tOH  
*
High Z  
D7=  
D7  
D7  
Valid Data  
tWHWH1 or 2  
D0–D6  
Valid Data  
D0-D6  
D0–D6=Invalid  
tOE  
* D7=Valid Data (The device has completed the Embedded operation).  
14  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 11  
Sector Protection Algorithm  
Start  
Set Up Sector Address  
(A16, A15, A14)  
PLSCNT = 1  
OE = VID  
A9 = VID, CE = VIL  
Activate WE Pulse  
Time Out 100µs  
Increment  
PLSCNT  
Power Down OE  
WE = VIH  
CE = OE = VIH  
A9 Should Remain VID  
Read From Sector  
Address = SA, A0 = 0, A1 = 1, A6 = 0  
No  
No  
Data = 01H  
PLSCNT = 25  
?
?
Yes  
Yes  
Device Failure  
Protect  
Yes  
Another  
Sector?  
No  
Remove VID from A9  
Write Reset Command  
Sector Protection  
Complete  
15  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 12  
Sector Unprotect Algorithm  
Start  
Set VCC = 5.0 V  
Protect All Sectors  
PLSCNT = 1  
Set Up Sector Address  
Unprotected Mode  
(A12 = A7 = VIH, A6 = VIL)  
Set VCC = 5.0 V  
Set  
OE = CE = A9 = VID  
Activate WE Pulse  
Time Out 10ms  
Increment  
PLSCNT  
Set OE = CE = VIL  
Remove VID from A9  
Set VCC = 4.25 V  
Write Autoselect  
Command Sequence  
Setup Sector Address SA0  
Set A1 = 1, A0 = 0  
Read Data  
From Device  
No  
Increment  
No  
Write Reset  
Command  
Data = 00H  
?
PLSCNT = 1000  
?
Sector Address  
Yes  
Yes  
Device Failure  
Sector  
No  
Address = SA7  
?
Yes  
Set VCC = 5.0 V  
Notes:  
SA0 = Sector Address for initial sector  
SA7 = Sector Address for last sector  
Please refer to Table 2  
Write Reset Command  
Sector Unprotect  
Completed  
16  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Figure 13  
Write/Erase/Program Operation, CE Controlled  
Data Polling  
5555H  
PA  
PA  
Addresses  
tWC  
tAS  
tAH  
WE  
OE  
tGHEL  
tCP  
tWHWH1  
CE  
tCPH  
tDH  
tWS  
AOH  
PD  
D7  
DOUT  
Data  
5.0V  
tDS  
Notes:  
1. PA is the address of the memory location to be programmed.  
2. PD is the data to be programmed at byte address.  
3. D7 is the 0utput of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles of four bus cycle sequence.  
17  
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SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Pin Numbers & Functions  
66 Pins — PGA  
Pin#  
1
Function  
I/O8  
I/O9  
I/O10  
A14  
Pin#  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
Function  
A15  
Pin#  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
Function  
I/O25  
I/O26  
A7  
Pin#  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
Function  
WE3  
CE3  
2
Vcc  
3
CE1  
NC  
GND  
I/O19  
I/O31  
I/O30  
I/O29  
I/O28  
A1  
4
A12  
5
A16  
I/O3  
NC  
6
A11  
I/O15  
I/O14  
I/O13  
I/O12  
OE  
A13  
7
A0  
A8  
8
NC  
I/O16  
I/O17  
I/O18  
VCC  
9
I/O0  
I/O1  
I/O2  
WE2  
CE2  
GND  
I/O11  
A10  
10  
11  
12  
13  
14  
15  
16  
17  
A2  
NC  
A3  
WE1  
I/O7  
CE4  
WE4  
I/O27  
A4  
I/O23  
I/O22  
I/O21  
I/O20  
I/O6  
I/O5  
I/O4  
A5  
A9  
I/O24  
A6  
"P3" — 1.08" SQ PGA Type (without shoulder) Package  
"P7" — 1.08" SQ PGA Type (with shoulder) Package  
Bottom View (P7 & P3)  
Side View  
(P7)  
Side View  
(P3)  
1.085 SQ  
MAX  
.185  
1.000  
MAX  
Pin 1  
.600  
.025  
.035  
Pin 56  
.050  
.100  
1.030  
1.040  
1.030  
1.040  
.100  
1.000  
.020  
.016  
.020  
.016  
Pin 66  
Pin 11  
.180  
TYP  
.100  
.180  
TYP  
.160  
MAX  
All dimensions in inches  
18  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
Pin Numbers & Functions  
68 Pins — CQFP Package  
Pin#  
1
Function  
GND  
CE3  
A5  
Pin#  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
Function  
GND  
I/O8  
Pin#  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
Function  
OE  
Pin#  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
Function  
GND  
I/O23  
I/O22  
I/O21  
I/O20  
I/O19  
I/O18  
I/O17  
I/O16  
VCC  
2
CE2  
3
I/O9  
NC  
4
A4  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
VCC  
WE2  
WE3  
WE4  
NC  
5
A3  
6
A2  
7
A1  
8
A0  
NC  
9
NC  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
I/O31  
I/O30  
I/O29  
I/O28  
I/O27  
I/O26  
I/O25  
I/O24  
A11  
A10  
A12  
A9  
A13  
A8  
A14  
A7  
A15  
A6  
A16  
WE1  
CE4  
CE1  
"F5" — Single-Cavity CQFP  
Top View  
Side View  
0.990 SQ  
±.010  
0.880 SQ  
0.160  
MAX  
±.010  
Pin 9  
Pin 61  
Pin 10  
Pin 60  
0.010  
REF  
0.015  
±.010  
0.946  
±.010  
.010 R  
3°-3°  
0.040  
0.010  
±.005  
Detail “A”  
0.050  
TYP  
Pin 26  
Pin 27  
Pin 44  
Pin 43  
See Detail “A”  
0.800 REF  
All dimensions in inches  
19  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  
C I R C U I T T E C H N O L O G Y  
Ordering Information  
Model Number  
DESC Drawing Number  
5962-9471605HZX*  
5962-9471604HZC  
5962-9471603HZC  
5962–9471602HZC  
5962–9471601HZC  
5962-9471605H8X*  
5962-9471604H8C  
5962-9471603H8C  
5962–9471602H8C  
5962–9471601H8C  
5962-9471605HNX*  
5962-9471604HNC  
5962-9471603HNC  
5962–9471602HNC  
5962–9471601HNC  
Speed  
Package  
PGA  
ACT–F128K32N–060P3Q  
ACT–F128K32N–070P3Q  
ACT–F128K32N–090P3Q  
ACT–F128K32N–120P3Q  
ACT–F128K32N–150P3Q  
ACT–F128K32N–060P7Q  
ACT–F128K32N–070P7Q  
ACT–F128K32N–090P7Q  
ACT–F128K32N–120P7Q  
ACT–F128K32N–150P7Q  
ACT–F128K32N–060F5Q  
ACT–F128K32N–070F5Q  
ACT–F128K32N–090F5Q  
ACT–F128K32N–120F5Q  
ACT–F128K32N–150F5Q  
* Pending  
60 ns  
70 ns  
90 ns  
120 ns  
150 ns  
60 ns  
70 ns  
90 ns  
120 ns  
150 ns  
60 ns  
70 ns  
90 ns  
120 ns  
150 ns  
PGA  
PGA  
PGA  
PGA  
PGA  
PGA  
PGA  
PGA  
PGA  
CQFP  
CQFP  
CQFP  
CQFP  
CQFP  
Part Number Breakdown  
ACT– F 128K 32 N– 060 F5 Q  
Aeroflex Circuit  
Technology  
Screening  
Memory Type  
C = Commercial Temp, 0°C to +70°C  
I = Industrial Temp, -40°C to +85°C  
T = Military Temp, -55°C to +125°C  
M = Military Temp, -55°C to +125°C, Screened *  
Q = MIL-STD-883 Compliant/SMD if applicable  
F = FLASH EEPROM  
Memory Depth  
Memory Width, Bits  
Package Type & Size  
Options  
Surface Mount Packages  
F5 = .88"SQ 68 Lead  
Single-Cavity CQFP  
Thru-Hole Packages  
P3 = 1.075"SQ PGA 66 Pins W/O Shoulder  
P7 = 1.075"SQ PGA 66 Pins With Shoulder  
N = None  
Memory Speed, ns  
*
Screened to the individual test methods of MIL-STD-883  
Specification subject to change without notice  
Aeroflex Circuit Technology  
Telephone: (516) 694-6700  
FAX: (516) 694-6715  
Toll Free Inquiries: 1-(800) 843-1553  
35 South Service Road  
Plainview New York 11830  
20  
Aeroflex Circuit Technology  
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700  

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