ACT-SF41632N-39P5C [AEROFLEX]

ACT-SF41632 High Speed 128Kx32 SRAM / 512Kx32 Flash Multichip Module; ACT- SF41632高速128Kx32 SRAM /闪存512Kx32多芯片模块
ACT-SF41632N-39P5C
型号: ACT-SF41632N-39P5C
厂家: AEROFLEX CIRCUIT TECHNOLOGY    AEROFLEX CIRCUIT TECHNOLOGY
描述:

ACT-SF41632 High Speed 128Kx32 SRAM / 512Kx32 Flash Multichip Module
ACT- SF41632高速128Kx32 SRAM /闪存512Kx32多芯片模块

闪存 静态存储器
文件: 总11页 (文件大小:186K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ACT-SF41632 High Speed  
128Kx32 SRAM / 512Kx32 Flash  
Multichip Module  
CIRCUIT TECHNOLOGY  
www.aeroflex.com  
FEATURES  
4 – 128K x 8 SRAMs & 4 – 512K x 8 Flash Die in  
FLASH MEMORY FEATURES  
One MCM  
Sector Architecture (Each Die)  
8 Equal Sectors of 64K bytes each  
Any combination of sectors can be erased with  
one command sequence.  
Access Times of 25ns, 35ns (SRAM) and  
60ns, 70ns, 90ns (Flash)  
Organized as 128K x 32 of SRAM and 512K x 32  
+5V Programing, +5V Supply  
of Flash Memory with Common Data Bus  
Embedded Erase and Program Algorithms  
Hardware and Software Write Protection  
Page Program Operation and Internal Program  
Control Time.  
10,000 Erase/Program Cycles  
Low Power CMOS  
Input and Output TTL Compatible Design  
MIL-PRF-38534 Compliant MCMs Available  
Decoupling Capacitors and Multiple Grounds for  
Low Noise  
Commercial, Industrial and Military Temperature  
Ranges  
Industry Standard Pinouts  
TTL Compatible Inputs and Outputs  
Packaging – Hermetic Ceramic  
ISO  
66–Lead, PGA-Type, 1.385"SQ x 0.245"max,  
Aeroflex code# "P1,P5 with/without shoulders)"  
68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x  
.20"max (.18 max thickness available, contact  
factory for details) (Drops into the 68 Lead  
JEDEC .99"SQ CQFJ footprint)  
1
900  
I
Block Diagram – PGA Type Package(P1 & P5) & CQFP(F2)  
FWE4 SWE4  
PIN DESCRIPTION  
FWE1 SWE1  
FWE3 SWE3  
FWE2 SWE2  
I/O0-31  
A0–18  
Data I/O  
OE  
A0–A18  
SCE  
Address Inputs  
FWE1-4 Flash Write Enables  
SWE1-4 SRAM Write Enables  
FCE  
FCE  
SCE  
OE  
Flash Chip Enable  
SRAM Chip Enable  
Output Enable  
Not Connected  
Power Supply  
Ground  
512K X 8 FLASH  
512K X 8 FLASH  
512K X 8 FLASH  
512K X 8 FLASH  
128K X 8 SRAM  
128K X 8 SRAM  
128K X 8 SRAM  
128K X 8 SRAM  
NC  
VCC  
GND  
I/O0-7  
I/O8-15  
I/O16-23  
I/O24-31  
eroflex Circuit Technology - Advanced Multichip Modules © SCD3851 REV A 5/21/98  
Absolute Maximum Ratings  
Symbol  
TC  
Rating  
Range  
-55 to +125  
-65 to +150  
-0.5 to +7  
300  
Units  
°C  
Case Operating Temperature  
TSTG  
VG  
°C  
Storage Temperature  
V
Maximum Signal Voltage to Ground  
Maximum Lead Temperature (10 seconds)  
TL  
°C  
Parameter  
Flash Data Retention  
10 Years  
10,000  
Flash Endurance (Write/Erase Cycles)  
Normal Operating Conditions  
Symbol  
VCC  
Parameter  
Minimum  
Maximum  
Units  
+4.5  
+2.2  
-0.5  
+5.5  
V
V
V
Power Supply Voltage  
Input High Voltage  
Input Low Voltage  
VIH  
V
CC + 0.3  
+0.8  
VIL  
Capacitance  
(VIN = 0V, f = 1MHz, TA = 25°C)  
Symbol Parameter  
Maximum  
Units  
pF  
CAD  
COE  
80  
80  
30  
50  
30  
A0 A18 Capacitance  
pF  
OE Capacitance  
CWE1-4  
CCE  
pF  
F/S Write Enable Capacitance  
F/S Chip Enable Capacitance  
I/O0 – I/O31 Capacitance  
pF  
CI/O  
pF  
This parameter is guaranteed by design but not tested  
DC Characteristics  
(VCC = 5.0V, VSS = 0V, Tc = -55°C to +125°C)  
Parameter  
Sym  
Conditions  
Min  
Max Units  
ILI  
10  
µA  
Input Leakage Current  
VCC = Max, VIN = 0 to VCC  
FCE = SCE = VIH, OE = VIH,  
VOUT = 0 to VCC  
ILO  
ICCx32  
ISB  
10  
µA  
Output Leakage Current  
SRAM Operating Supply Current x 32  
Mode  
SCE = VIL, OE = VIH, f = 5MHz, VCC  
Max, FCE = VIH  
=
500 mA  
FCE = SCE = VIH, OE = VIH, f = 5MHz,  
VCC = Max  
80  
mA  
Standby Current  
VOL  
VOH  
ICC1  
0.4  
V
V
SRAM Output Low Voltage  
IOL = 8 mA, VCC = Min, FCE = VIH  
IOH = -4.0 mA, , VCC = Min, FCE = VIH  
FCE = VIL, OE = VIH, SCE = VIH  
2.4  
SRAM Output High Voltage  
260 mA  
Flash Vcc Active Current for Read (1)  
Flash Vcc Active Current for Program  
or Erase (2)  
ICC2  
300 mA  
FCE = VIL, OE = VIH, SCE = VIH  
VOL  
VOH1  
VLKO  
0.45  
4.2  
V
V
V
Flash Output Low Voltage  
Flash Output High Voltage  
Flash Low Vcc Lock Out Voltage  
IOL = 12 mA, VCC = Min, SCE = VIH  
IOH = -2.5 mA, , VCC = Min, SCE = VIH  
0.85 x VCC  
3.2  
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The  
frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or  
erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V  
2
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
SRAM AC Characteristics  
(VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C)  
Read Cycle  
Parameter  
–025  
–035  
Min Max  
35  
Symbol  
Units  
Min Max  
25  
tRC  
tAA  
tACE  
tOH  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
25  
25  
35  
Address Access Time  
35  
Chip Select Access Time  
0
0
Output Hold from Address Change  
Output Enable to Output Valid  
Chip Select to Output in Low Z *  
Output Enable to Output in Low Z *  
Chip Deselect to Output in High Z *  
Output Disable to Output in High Z *  
* Parameters guaranteed by design but not tested  
tOE  
15  
20  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
3
0
3
0
12  
12  
20  
20  
Write Cycle  
Parameter  
–025  
–035  
Min Max  
35  
Symbol  
Units  
Min Max  
tWC  
tCW  
tAW  
tDW  
tWP  
tAS  
25  
20  
20  
15  
20  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write Cycle Time  
25  
25  
20  
25  
0
Chip Select to End of Write  
Address Valid to End of Write  
Data Valid to End of Write  
Write Pulse Width  
Address Setup Time  
tOW  
tWHZ  
tDH  
0
0
Output Active from End of Write *  
Write to Output in High Z *  
Data Hold from Write Time  
Address Hold Time  
10  
20  
0
0
tAH  
0
0
* Parameters guaranteed by design but not tested  
SRAM Truth Table  
Mode  
Standby  
Read  
SCE  
OE  
SWE  
Data I/O  
Power  
H
L
L
L
X
X
H
H
L
High Z  
Data Out  
High Z  
Standby  
Active  
Active  
Active  
L
Output Disable  
Write  
H
X
Data In  
3
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
Timing Diagrams — SRAM  
Read Cycle Timing Diagrams  
Write Cycle Timing Diagrams  
Write Cycle (SWE Controlled, OE = VIH)  
Read Cycle 1 (SCE = OE = VIL, SWE = VIH)  
tWC  
tRC  
A0-18  
A0-18  
tAA  
tAW  
tCW  
tAH  
tOH  
DI/O  
SCE  
Previous Data Valid  
Data Valid  
tAS  
tWP  
SWE  
tOW  
tDH  
tWHZ  
tDW  
SEE NOTE  
DI/O  
Data Valid  
Read Cycle 2 (SWE = VIH)  
tRC  
Write Cycle (SCE Controlled, OE = VIH )  
A0-18  
tWC  
tAA  
A0-18  
tAH  
tAW  
SCE  
tAS  
tACE  
tCW  
tWP  
tCHZ  
SEE NOTE  
SCE  
tCLZ  
SEE NOTE  
OE  
tOHZ  
tOE  
SWE  
SEE NOTE  
tOLZ  
SEE NOTE  
tDW  
tDH  
DI/O  
Data Valid  
High Z  
DI/O  
Data Valid  
Note: Guaranteed by design, but not tested.  
DON’T CARE  
UNDEFINED  
AC Test Circuit  
Current Source  
IOL  
AC Test Conditions  
Parameter  
Typical  
0 – 3.0  
5
Units  
Input Pulse Level  
Input Rise and Fall  
V
ns  
V
VZ ~ 1.5 V (Bipolar Supply)  
To Device Under Test  
CL = 50 pF  
Input and Output Timing Reference Level  
1.5  
IOH  
Current Source  
Notes:  
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance  
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance  
load circuit. 6) ATE Tester includes jig capacitance.  
4
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
Flash AC Characteristics – Read Only Operations  
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)  
Symbol  
–60  
–70  
–90  
Parameter  
Units  
JEDEC Stand’d Min Max Min Max Min Max  
tAVAV  
tAVQV  
tELQV  
tGLQV  
tEHQZ  
tGHQZ  
tAXQX  
tRC  
tACC  
tCE  
tOE  
tDF  
60  
70  
90  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
60  
60  
30  
20  
20  
70  
70  
35  
20  
20  
90  
90  
35  
20  
20  
Address Access Time  
Chip Enable Access Time  
Output Enable to Output Valid  
Chip Enable to Output High Z (1)  
Output Enable High to Output High Z(1)  
Output Hold from Address, CE or OE Change, Whichever is First  
Note 1. Guaranteed by design, but not tested  
tDF  
tOH  
0
0
0
Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled  
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)  
Symbol  
–60  
–70  
–90  
Parameter  
Units  
JEDEC Stand’d Min Max Min Max Min Max  
tAVAC  
tELWL  
tWC  
tCE  
60  
0
70  
0
90  
0
ns  
ns  
Write Cycle Time  
Chip Enable Setup Time  
Write Enable Pulse Width  
Address Setup Time  
tWLWH  
tAVWL  
tDVWH  
tWHDX  
tWLAX  
tWHWL  
tWHWH1  
tWHWH2  
tWP  
tAS  
40  
0
45  
0
45  
0
ns  
ns  
tDS  
40  
0
45  
0
45  
0
ns  
Data Setup Time  
tDH  
tAH  
tWPH  
ns  
Data Hold Time  
45  
20  
45  
20  
45  
20  
ns  
Address Hold Time  
ns  
Write Enable Pulse Width High  
Duration of Byte Programming Operation  
Sector Erase Time  
14 TYP 14 TYP 14 TYP  
µs  
30  
30  
30  
Sec  
µs  
tGHWL  
0
0
0
Read Recovery Time before Write  
Vcc Setup Time  
tVCE  
50  
50  
50  
µs  
50  
10  
50  
10  
50  
10  
Sec  
ns  
Chip Programming Time  
Chip Enable Hold Time  
Chip Erase Time  
1
tOEH  
tWHWH3  
120  
120  
120  
Sec  
1. Toggle and Data Polling only.  
Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled  
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)  
Symbol  
–60  
–70  
–90  
Parameter  
Units  
JEDEC Stand’d Min Max Min Max Min Max  
tAVAC  
tWLEL  
tELEH  
tWC  
tWS  
tCP  
60  
0
70  
0
90  
0
ns  
ns  
Write Cycle Time  
Write Enable Setup Time  
Chip Enable Pulse Width  
Address Setup Time  
Data Setup Time  
40  
0
45  
0
45  
0
ns  
tAVEL  
tAS  
ns  
tDVEH  
tEHDX  
tELAX  
tDS  
40  
0
45  
0
45  
0
ns  
tDH  
tAH  
tCPH  
ns  
Data Hold Time  
45  
20  
45  
20  
45  
20  
ns  
Address Hold Time  
tEHEL  
ns  
Chip Enable Pulse Width High  
Duration of Byte Programming  
Sector Erase Time  
tWHWH1  
tWHWH2  
14 TYP 14 TYP 14 TYP  
µs  
30  
30  
30  
Sec  
ns  
tGHEL  
0
0
0
Read Recovery Time  
Chip Programming Time  
Chip Erase Time  
50  
50  
50  
Sec  
Sec  
tWHWH3  
120  
120  
120  
5
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
AC Waveforms for Flash Memory Read Operations  
tRC  
Addresses  
FCE  
Addresses Stable  
tACC  
tDF  
OE  
tOE  
FWE  
tCE  
tOH  
High Z  
High Z  
Outputs  
Output Valid  
Write/Erase/Program  
Operation for Flash Memory, FWE Controlled  
Data Polling  
Addresses  
5555H  
PA  
PA  
tRC  
tWC  
tAH  
tAS  
FCE  
OE  
tGHWL  
tWP  
tWHWH1  
tWPH  
FWE  
tCE  
tDF  
tOH  
tOE  
tDH  
AOH  
PD  
D7  
DOUT  
Data  
5.0V  
tDS  
tCE  
Notes:  
1. PA is the address of the memory location to be programmed.  
2. PD is the data to be programmed at byte address.  
3. D7 is the 0utput of the complement of the data written to the deviced.  
4. Dout is the output of the data written to the device.  
5. Figure indicates last two bus cycles of four bus cycle sequence.  
6
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
AC Waveforms Chip/Sector  
Erase Operations for Flash Memory  
Data Polling  
5555H  
tAH  
5555H  
2AAAH  
5555H  
2AAAH  
SA  
Addresses  
tAS  
FCE  
OE  
tGHWL  
tWP  
FWE  
tWPH  
tDH  
tCE  
AAH  
55H  
80H  
AAH  
55H  
10H/30H  
Data  
VCC  
tDS  
tVCE  
Notes:  
1. SA is the sector address for sector erase.  
AC Waveforms for Data Polling  
During Embedded Algorithm Operations for Flash Memory  
tCH  
FCE  
tDF  
tOE  
OE  
tOEH  
tCE  
FWE  
tOH  
*
High Z  
DQ7=  
Valid Data  
DQ7  
DQ7  
tWHWH1 or 2  
DQ0–DQ6  
Valid Data  
DQ0-DQ6  
DQ0–DQ6=Invalid  
tOE  
* DQ7=Valid Data (The device has completed the Embedded operation).  
7
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
Write/Erase/Program Operation for Flash Memory, FCE Controlled  
Data Polling  
5555H  
PA  
PA  
Addresses  
tWC  
tAS  
tAH  
FCE  
OE  
tGHWL  
tCP  
tWHWH1  
FWE  
tCPH  
tWS  
tDH  
AOH  
PD  
D7  
DOUT  
Data  
5.0V  
tDS  
Notes:  
1. PA is the address of the memory location to be programmed.  
2. PD is the data to be programmed at byte address.  
3. D7 is the 0utput of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles of four bus cycle sequence.  
8
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
Pin Numbers & Functions  
66 Pins — PGA-Type  
Pin #  
1
Function  
I/O8  
I/O9  
I/O10  
A14  
Pin #  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
Function  
A15  
Pin #  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
Function  
I/O25  
I/O26  
A7  
Pin #  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
Function  
FWE3  
SWE3  
GND  
I/O19  
I/O31  
I/O30  
I/O29  
I/O28  
A1  
2
Vcc  
3
FCE  
SCE  
I/O3  
4
A12  
5
A16  
SWE1  
A13  
6
A11  
I/O15  
I/O14  
I/O13  
I/O12  
OE  
7
A0  
A8  
8
A18  
I/O16  
I/O17  
I/O18  
VCC  
9
I/O0  
I/O1  
I/O2  
FWE2  
SWE2  
GND  
I/O11  
A10  
10  
11  
12  
13  
14  
15  
16  
17  
A2  
A17  
A3  
FWE1  
I/O7  
SWE4  
FWE4  
I/O27  
A4  
I/O23  
I/O22  
I/O21  
I/O20  
I/O6  
I/O5  
I/O4  
A5  
A9  
I/O24  
A6  
"P1" — 1.385" SQ PGA Type Package Standard (with shoulders on Pins 1, 11, 56 & 66)  
"P5" — 1.385" SQ PGA Type Special Order Package (without shoulders)  
Bottom View (P1 & P5)  
Side View  
(P5)  
Side View  
(P1)  
1.400 SQ  
MAX  
1.000  
TYP  
.600  
TYP  
.245  
MAX  
Pin 1  
.220  
MAX  
.025  
.035  
Pin 56  
1.000  
TYP  
.100  
TYP  
.100 TYP  
.020  
.016  
.020  
.016  
Pin 66  
Pin 11  
.145  
MIN  
.165  
MIN  
.100 TYP  
All dimensions in inches  
9
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
Pin Numbers & Functions  
68 Pins — Dual-Cavity CQFP  
Pin #  
1
Function  
GND  
SWE3  
A5  
Pin #  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
Function  
GND  
I/O8  
Pin #  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
Function  
OE  
Pin #  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
Function  
GND  
FI/O23  
FI/O22  
FI/O21  
FI/O20  
FI/O19  
FI/O18  
FI/O17  
FI/O16  
VCC  
2
SWE2  
A17  
3
I/O9  
4
A4  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
Vcc  
FWE2  
FWE3  
FWE4  
A18  
5
A3  
6
A2  
7
A1  
8
A0  
SCE  
9
NC  
SWE1  
FI/O31  
FI/O30  
FI/O29  
FI/O28  
FI/O27  
FI/O26  
FI/O25  
FI/O24  
10  
11  
12  
13  
14  
15  
16  
17  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
A11  
A10  
A12  
A9  
A13  
A8  
A14  
A7  
A15  
A6  
A16  
FWE1  
SWE4  
FCE  
Package Outline — Dual-Cavity CQFP "F2"  
Top View  
.990 SQ  
±.010  
.890 SQ  
MAX  
Pin 9  
Pin 61  
*.200 MAX  
.010 REF  
Pin 10  
Pin 60  
.015  
±.002  
.010 ±.002  
.010 R  
REF  
+3°/-3°  
.010 ±.005  
.040  
±.005  
.050  
TYP  
Detail “A”  
Pin 26  
Pin 27  
Pin 44  
Pin 43  
See Detail “A”  
.800 REF  
*.180 MAX available, call factory for details  
All dimensions in inches  
10  
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  
C I R C U I T T E C H N O L O G Y  
Ordering Information  
Model Number  
DESC Part Number  
Speed  
Package  
1.385"sq PGA-Type  
1.385"sq PGA-Type  
1.385"sq PGA-Type  
.88"sq CQFP  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
25(S) / 60(F) ns  
35(S) / 70(F) ns  
35(S) / 90(F) ns  
25(S) / 60(F) ns  
35(S) / 70(F) ns  
35(S) / 90(F) ns  
ACT-SF41632N–26P1X  
ACT-SF41632N–37P1X  
ACT-SF41632N–39P1X  
ACT-SF41632N–26F2X  
ACT-SF41632N–37F2X  
ACT-SF41632N–39F2X  
.88"sq CQFP  
.88"sq CQFP  
Note: (S) = Speed for SRAM, (F) = Speed for FLASH  
Part Number Breakdown  
ACT– SF 416 32 N– 26 P1 M  
Aeroflex Circuit  
Technology  
Memory Type  
Screening  
SF = SRAM Flash Combo Module  
C = Commercial Temp, 0°C to +70°C  
I = Industrial Temp, -40°C to +85°C  
T = Military Temp, -55°C to +125°C  
M = Military Temp, -55°C to +125°C Screened *  
Q = MIL-PRF-38534 Compliant/SMD  
Memory Depth, Locations  
4 = 4M SRAM, 16 = 16M Flash  
Memory Width, Bits  
Package Types & Sizes  
Surface Mount Packages  
Pinout Options  
N = None  
F2 = 0.88"SQ 68 Leads Dual-Cavity CQFP  
Thru-Hole Packages  
P1 = 1.385"SQ PGA 66 Pins W/Shoulder  
P5 = 1.385"SQ PGA 66 Pins WO/Shoulder  
Memory Speed (Code)  
26 = 25ns SRAM & 60ns FLASH  
37 = 35ns SRAM & 70ns FLASH  
39 = 35ns SRAM & 90ns FLASH  
*
Screened to the individual test methods of MIL-STD-883  
Specifications subject to change without notice.  
Telephone: (516) 694-6700  
FAX: (516) 694-6715  
Toll Free Inquiries: 1-(800) 843-1553  
Aeroflex Circuit Technology  
35 South Service Road  
Plainview New York 11830  
11  
Aeroflex Circuit Technology  
SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700  

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