首页 |元器件品牌

GR712RC-MS-CG240 [AEROFLEX]

Dual-Core LEON3-FT SPARC V8 Processor; 双核LEON3 -FT SPARC V8处理器
GR712RC-MS-CG240
型号： GR712RC-MS-CG240
厂家： AEROFLEX CIRCUIT TECHNOLOGY    AEROFLEX CIRCUIT TECHNOLOGY
描述：

Dual-Core LEON3-FT SPARC V8 Processor
双核LEON3 -FT SPARC V8处理器
文件： 总48页 (文件大小：838K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Dual-Core LEON3-FT SPARC V8 Processor  
GR712RC  
Data Sheet  
GAISLER  
Features  
Description  
•
Dual-core SPARC V8 integer unit, each with  
7-stage pipeline, 8 register windows, 4x4 KiB multi-  
way instruction cache, 4x4 KiB multi-way data cache,  
branch prediction, hardware multiplier and divider,  
power-down mode, hardware watchpoints, single-  
vector trapping, SPARC reference memory  
management unit, etc.  
The GR712RC is an implementation of the  
dual-core LEON3FT SPARC V8 processor using  
TM  
RadSafe technology. The fault tolerant design  
of the processor in combination with the  
radiation tolerant technology  
provides total immunity  
to radiation effects.  
•
•
Two high-performance double precision IEEE-754  
floating point units  
EDAC protected (8-bit BCH and 16-bit Reed-  
Solomon) interface to multiple 8/32-bits  
PROM/SRAM/SDRAM memory banks  
Advanced on-chip debug support unit  
192 KiB EDAC protected on-chip memory  
Multiple SpaceWire links with RMAP target  
Redundant 1553 BC/RT/MT interfaces  
Redundant CAN 2.0 interfaces  
Specification  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CQFP240 package  
Total Ionizing Dose (TID) up to 300 krad(Si)  
Proven Single-Event Latch-Up (SEL) immunity  
Proven Single-Event Upset (SEU) tolerance  
1.8V & 3.3V supply  
15 mW/MHz processor core power consumption  
100 MHz system frequency  
200 Mbps SpaceWire links  
10 Mbps CCSDS Telecommand link  
50 Mbps CCSDS Telemetry link  
10/100 Ethernet MAC with RMII interface  
2
SPI, I C, ASCS16 (STR), SLINK interfaces  
CCSDS/ECSS Telemetry and Telecommand  
UARTs, Timers & Watchdog, GPIO ports,  
Interrupt controllers, Status registers, JTAG, etc.  
Configurable I/O switch matrix  
•
Applications  
GR712RC is an advanced system-on-chip, targeting high reliability rad-hard space,  
aeronautics and military applications.  
It incorporates a dual-core LEON3-FT SPARC V8 processor and is implemented  
TM  
using Ramon Chips’ RadSafe library on Tower Semiconductors’ standard  
180 nm CMOS technology.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
2
GR712RC-DS  
Table of contents  
1
Introduction..............................................................................................................................3  
1.1  
1.2  
1.3  
1.4  
1.5  
Overview .................................................................................................................................................3  
Key features.............................................................................................................................................3  
Signal overview .......................................................................................................................................5  
Signal description....................................................................................................................................6  
I/O switch matrix overview .....................................................................................................................7  
2
3
Electrical characteristics ........................................................................................................18  
2.1  
2.2  
2.3  
2.4  
Absolute maximum ratings ...................................................................................................................18  
Recommended operating conditions .....................................................................................................18  
DC electrical performance characteristics.............................................................................................19  
AC electrical performance characteristics.............................................................................................21  
Mechanical description ..........................................................................................................37  
3.1  
3.2  
3.3  
Package..................................................................................................................................................37  
Pin assignment.......................................................................................................................................37  
Mechanical package drawings...............................................................................................................43  
4
5
6
7
Reference documents.............................................................................................................45  
Screening, qualification, and quality control .........................................................................46  
Ordering information .............................................................................................................46  
Change record ........................................................................................................................47  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
3
GR712RC-DS  
1
Introduction  
Overview  
1.1  
GR712RC is a dual-core LEON3-FT SPARC V8 processor, with advanced interface protocols, dedi-  
cated for high reliability Rad-Hard aerospace applications.  
The GR712RC is fabricated at Tower Semiconductors Ltd., using standard 180 nm CMOS technol-  
TM  
ogy. It employs radiation-hard-by-design methods from Aeroflex Gaisler and the RadSafe technol-  
ogy from Ramon Chips Ltd., enabling superior radiation hardness together with excellent low-power  
performance.  
The LEON3-FT processors provide hardware support for cache coherency, processor enumeration  
and interrupt steering. Each processor core includes a SPARC Reference Memory Management Unit  
(SRMMU) and an IEEE-754 compliant double-precision FPU for floating-point operations. It can be  
utilized in symmetric or asymmetric multiprocessing mode.  
The GR712RC architecture is centered around the AMBA Advanced High-speed Bus (AHB), to  
which the two LEON3-FT processors and other high-bandwidth units are connected. Low-bandwidth  
units are connected to the AMBA Advanced Peripheral Bus (APB) which is accessed through an  
AHB to APB bridge.  
GR712RC is provided in a 240-pin, 0.5 mm pitch high-reliability ceramic quad flat package (CQFP).  
This document is complemented by the GR712RC Dual-Core LEON3-FT SPARC V8 Processor -  
User's Manual from Aeroflex Gaisler [UM], which provides information related to software integra-  
tion and development.  
1.2  
Key features  
•
•
•
Technology: 180 nm standard CMOS, Tower Semiconductors Ltd.  
Library: 180 nm RadSafe™, Ramon Chips Ltd.  
Package:  
• 240 pin CQFP, 0.5 mm pitch, 32 mm * 32 mm, hermetically sealed,  
delivered with flat pins and insulating lead-frame for customer trim and fold  
• Core voltage 1.8V +/- 0.15V, I/O voltage 3.3V +/- 0.3V  
• -55ºC to +125ºC temperature range  
Radiation tolerance:  
•
•
• TID: 300 krad (Si)  
2
• SEL: > 118 MeV-cm /mg  
• SEU: proven tolerance with hardened flip-flops and error correction on all on-chip memories  
• Error detection and correction on external memories  
Maximum system clock frequency of 100 MHz (depending on external memory choice)  
• Optional 2x internal system frequency multiplication by an all-digital DLL  
• Optional 2x or 4x internal SpaceWire frequency multiplication by an all-digital DLL  
• Clock-gating for each major core  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
4
GR712RC-DS  
•
Two LEON3-FT SPARC V8 compliant 32-bit processors, each with:  
• SPARC reference memory management unit (SRMMU) with 32 TLB entries  
• High-performance double-precision IEEE-754 floating point co-processor (GRFPU)  
• 16 KiB multi-way instruction cache and 16 KiB multi-way data cache  
Internal on-chip high speed AMBA (AHB) bus  
•
•
•
•
•
•
•
Instruction trace and AMBA (AHB) trace buffers for debugging  
Timer unit with four 32-bit timers including watchdog  
Secondary timer unit with four 32-bit timers  
Primary and secondary interrupt controller for 31 interrupts  
On-chip 192 KiB memory block with EDAC  
External memory support:  
• Bus width: 8 bits, or 32 bit data plus 8/16 bits for EDAC checkbits, 24 bit address  
• 8 bit BCH EDAC for SRAM and PROM, 16 bit Reed-Solomon EDAC for SDRAM  
• Memory types: SRAM, SDRAM, PROM / EEPROM / NOR-FLASH and I/O address space  
• Programmable wait-states:  
• SRAM read/write cycle 2 - 5 clock cycles  
• PROM / EEPROM / NOR-FLASH read cycle 2 - 32 clock periods  
• One idle clock period between accesses to SRAM and PROM  
Debug Support Unit (DSU) accessed via JTAG and SpaceWire RMAP targets  
Two SpaceWire ports with RMAP targets, maximum 200 Mbps full-duplex data rate  
Configurable I/O selection matrix, connecting a subset of available I/O units to 67 shared pins:  
• Four SpaceWire ports, maximum 200 Mbps full-duplex data rate  
• Redundant MIL-STD-1553B BRM (BC/RT/BM) interface  
• Two CAN 2.0B bus controllers  
•
•
•
• Six UART ports, with 8-byte FIFO  
• Ethernet MAC with RMII 10/100 Mbps port  
• SPI master serial port  
• I2C master serial port  
• ASCS16 (STR) serial port  
• SLINK 6 MHz serial port  
• CCSDS / ECSS Telecommand decoder (five input channels), maximum 10 Mbps input rate  
• CCSDS / ECSS Telemetry encoder, maximum 50 Mbps output rate  
• 26 input and 38 input/output general purpose ports  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
5
GR712RC-DS  
1.3  
Signal overview  
INCLK  
RESETN  
DLLBPN  
ERRORN  
WDOGN  
Clock & Reset  
Error & Watchdog  
TESTEN  
SCANEN  
Test  
TCK  
TMS  
TDI  
TDO  
JTAG  
DATA[31:0]  
CB[7:0]  
BRDYN  
ADDRESS[23:0]  
RAMSN[1:0]  
RAMOEN  
RAMWEN  
ROMSN[1:0]  
IOSN  
Memory interface  
BEXCN  
OEN  
READ  
WRITEN  
SDCLK  
SPWCLK  
SPW_RXD[1:0]  
SPW_RXS[1:0]  
SpaceWire Links  
SPW_TXD[1:0]  
SPW_TXS[1:0]  
SWMX[66:0]  
I/O Matrix  
Figure 1. Signal overview  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
6
GR712RC-DS  
1.4  
Signal description  
The external signals are described in table 1.  
Table 1. External signals  
Name  
Usage  
Direction  
In  
Polarity  
-
INCLK  
Main system clock  
DLL bypass  
DLLBPN  
RESETN  
SCANEN  
TESTEN  
ERRORN  
WDOGN  
TCK  
In  
Low  
Low  
High  
High  
Low  
Low  
-
System reset  
In  
Scan enable (tie to ground)  
Test enable (tie to ground)  
Processor error mode  
Watchdog output  
In  
In  
Out-Tri  
Out-Tri  
In  
JTAG Test Clock  
TMS  
JTAG Test Mode  
In  
High  
-
TDI  
JTAG Test Data Input  
JTAG Test Data Output  
Memory address  
In  
TDO  
Out  
Out  
In/Out  
In/Out  
Out  
Out  
Out  
Out  
Out  
Out  
-
ADDRESS[23:0]  
DATA[31:0]  
CB[7:0]  
RAMSN[1:0]  
RAMOEN  
RAMWEN  
OEN  
-
Memory data bus  
-
Memory checkbits  
SRAM chip selects  
SRAM output enable  
SRAM write enable strobe  
PROM, I/O output enable  
PROM, I/O write strobe  
-
Low  
Low  
Low  
Low  
Low  
High  
WRITEN  
READ  
SRAM, PROM I/O read indicator 1)  
I/O area chip select  
IOSN  
Out  
Out  
In  
Low  
Low  
Low  
Low  
-
ROMSN[1:0]  
BRDYN  
PROM chip selects  
Bus ready  
BEXCN  
Bus exception  
In  
SDCLK  
SDRAM clock  
Out  
In  
SPWCLK  
SpaceWire receiver and transmitter clock  
SpaceWire Data input  
SpaceWire Strobe input  
SpaceWire Data output  
SpaceWire Strobe output  
I/O switch matrix  
-
SPW_RXD[1:0]  
SPW_RXS[1:0]  
SPW_TXD[1:0]  
SPW_TXS[1:0]  
SWMX[66:0]  
Note 1:  
In  
High  
High  
High  
High  
-
In  
Out  
Out  
In/Out  
The READ signal may also change value during SDRAM accesses.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
7
GR712RC-DS  
1.5  
I/O switch matrix overview  
The I/O switch matrix provides access to several I/O units. When an interface is not activated, its pins  
automatically become general purpose I/O. After reset, all I/O switch matrix pins are defined as I/O  
until programmed otherwise. Note that some pins are input only, some are output only, and the rest are  
both input and output, as described in table 3. The enabling of the I/O units is described in [UM].  
Figure 2 shows how the various I/O units are connected to the I/O switch matrix.  
Table 2 shows examples of possible configurations using the I/O switch matrix. Note that two  
SpaceWire interfaces are always available outside the I/O switch matrix.  
Table 3 shows a listing of all pins in the I/O switch matrix, indicating the priority amongst them.  
Table 4 shows a listing of pin utilization per I/O unit.  
Table 5 shows a listing of pins in the I/O switch matrix grouped per function (GPIO is not listed).  
Table 6 shows a complete listing of conflicts between I/O units (GPIO is not listed).  
TMS, TCK  
TDI, TDO  
INCLK, SPWCLK  
DLLBPN, RESETN  
TESTEN  
SCANEN  
ERRORN  
WDOGN  
TIMERS  
JTAG  
DSU  
LEON3FT LEON3FT 192K RAM CANMUX CLKGATE GPREG IRQ  
STAT  
AMBA  
TM  
1553  
SLINK  
I2C  
UART  
UART  
GPIO  
SPW  
SPW  
SPW  
GPIO  
SPW  
U
UART  
SPW  
U
UART  
MCTRL SDRAM  
TC  
CAN  
ETH  
SPI  
ASCS  
SWMX[66:0]  
SPW_TXD/S[1:0]  
SPW_RXD/S[1:0]  
ADDRESS[23:0]  
DATA[31:0], CB[7:0]  
CTRL, SDCLK  
Figure 2. Architectural block diagram showing connections to the I/O switch matrix  
Table 2. Example of possible configurations using the I/O switch matrix. Note that other configurations are also possible.  
Interface type  
Example configuration  
CF0  
CF1  
CF2  
CF3  
CF4  
CF5  
SDRAM with or without Reed-Solomon  
1
4
4
1
6
2
1
6
2
1
6
4
1
1
6
3
1
UART  
6
6
SpaceWire  
Ethernet  
MIL-STD-1553B BC/RT/BM  
1
1
1
I2C  
1
1
1
1
1
1
1
SPI  
SLINK  
1
1
ASCS16  
CCSDS/ECSS TC & TM  
1
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
8
GR712RC-DS  
Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest  
priority for each pin listed first.  
Pin no.  
Pin name  
SWMX[0]  
SWMX[1]  
SWMX[2]  
SWMX[3]  
Pin function  
UART_TX[0]  
UART_RX[0]  
UART_TX[1]  
UART_RX[1]  
GPIO[0]  
Polarity  
Reset value  
Dir.  
Out  
In  
Description  
4
3
2
1
-
-
-
-
-
-
-
-
High  
UART Transmit 0  
UART Receive 0  
High  
Out  
In  
UART Transmit 1  
UART Receive 1  
In  
GPIO 1 Register, bit 0 (input only)  
UART Transmit 2  
GPIO 1 Register, bit 1  
240  
SWMX[4]  
UART_TX[2]  
GPIO[1]  
High-Z  
High-Z  
Out  
In/Out  
In  
MCFG3[8]  
At reset, bit 8 in MCFG3 register in the mem-  
ory controller is set from this input.  
239  
238  
SWMX[5]  
SWMX[6]  
UART_RX[2]  
GPIO[2]  
-
-
-
-
-
In  
UART Receive 2  
In  
GPIO 1 Register, bit 2 (input only)  
UART Transmit 3  
UART_TX[3]  
GPIO[3]  
High-Z  
High-Z  
Out  
In/Out  
In  
GPIO 1 Register, bit 3  
MCFG1[9]  
At reset, bit 9 in MCFG1 register in the mem-  
ory controller is set from this input  
233  
232  
SWMX[7]  
SWMX[8]  
UART_RX[3]  
GPIO[4]  
-
In  
UART Receive 3  
-
In  
GPIO 1 Register, bit 4 (input only)  
UART Transmit 4  
UART_TX[4]  
TMDO  
-
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
In  
-
Telemetry Data Out  
GPIO[5]  
-
GPIO 1 Register, bit 5  
231  
230  
229  
228  
227  
226  
SWMX[9]  
SWMX[10]  
SWMX[11]  
SWMX[12]  
SWMX[13]  
SWMX[14]  
UART_RX[4]  
TMCLKI  
-
UART Receive 4  
Rising  
In  
Telemetry Clock Input  
GPIO 1 Register, bit 6 (input only)  
UART Transmit 5  
GPIO[6]  
-
In  
UART_TX[5]  
TMCLKO  
GPIO[7]  
-
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
In  
-
Telemetry Clock Output  
GPIO 1 Register, bit 7  
-
UART_RX[5]  
TCACT[0]  
GPIO[8]  
-
UART Receive 5  
High  
In  
Telecommand Active 0  
GPIO 1 Register, bit 8 (input only)  
SpaceWire Transmit Strobe 4  
SDRAM Select 0  
-
In  
SPW_TXS[4]  
SDCSN[0]  
GPIO[9]  
High  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
Out  
Out  
In/Out  
In  
Low  
-
GPIO 1 Register, bit 9  
SPW_TXD[4]  
SDCSN[1]  
GPIO[10]  
High  
SpaceWire Transmit Data 4  
SDRAM Select 1  
Low  
-
GPIO 1 Register, bit 10  
SpaceWire Receive Strobe 4  
Telecommand Clock 0  
ASCS DAS A - Slave data in  
GPIO 1 Register, bit 11 (input only)  
SpaceWire Receive Data 4  
Telecommand Data 0  
SPW_RXS[4]  
TCCLK[0]  
A16DASA  
GPIO[11]  
High  
Rising  
In  
-
In  
-
In  
225  
220  
SWMX[15]  
SWMX[16]  
SPW_RXD[4]  
TCD[0]  
High  
In  
-
In  
A16DASB  
GPIO[12]  
-
In  
ASCS DAS B - Slave data in  
GPIO 1 Register, bit 12 (input only)  
SpaceWire Transmit Strobe 2  
CAN Transmit A  
-
In  
SPW_TXS[2]  
CANTXA  
GPIO[13]  
High  
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
-
-
GPIO 1 Register, bit 13  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
9
GR712RC-DS  
Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest  
priority for each pin listed first.  
Pin no.  
Pin name  
Pin function  
SPW_TXD[2]  
CANTXB  
Polarity  
Reset value  
High-Z  
Dir.  
Out  
Out  
In/Out  
In  
Description  
219  
SWMX[17]  
High  
SpaceWire Transmit Data 2  
CAN Transmit B  
-
High-Z  
GPIO[14]  
-
High-Z  
GPIO 1 Register, bit 14  
218  
217  
203  
202  
SWMX[18]  
SWMX[19]  
SWMX[20]  
SWMX[21]  
SPW_RXS[2]  
CANRXA  
High  
SpaceWire Receive Strobe 2  
CAN Receive A  
-
In  
GPIO[15]  
-
In  
GPIO 1 Register, bit 15 (input only)  
SpaceWire Receive Data 2  
CAN Receive B  
SPW_RXD[2]  
CANRXB  
High  
-
In  
In  
GPIO[16]  
-
In  
GPIO 1 Register, bit 16 (input only)  
SpaceWire Transmit Strobe 3  
SLINK SYNC  
SPW_TXS[3]  
SLSYNC  
High  
High  
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
Out  
Out  
In/Out  
In  
GPIO[17]  
GPIO 1 Register, bit 17  
SPW_TXD[3]  
A16ETR  
High  
High  
-
SpaceWire Transmit Data 3  
ASCS ETR - Synchronization signal  
GPIO 1 Register, bit 18  
GPIO[18]  
201  
200  
197  
SWMX[22]  
SWMX[23]  
SWMX[24]  
SPW_RXS[3]]  
GPIO[19]  
High  
-
SpaceWire Receive Strobe 3  
GPIO 1 Register, bit 19 (input only)  
SpaceWire Receive Data 3  
GPIO 1 Register, bit 20 (input only)  
SpaceWire Transmit Data 5  
In  
SPW_RXD[3]  
GPIO[20]  
High  
-
In  
In  
SPW_TXD[5]  
SDDQM[0]  
High  
High  
High-Z  
High-Z  
Out  
Out  
SDRAM Data Mask 0, corresponds to  
DATA[7:0]  
GPIO[21]  
-
High-Z  
High-Z  
High-Z  
In/Out  
Out  
GPIO 1 Register, bit 21  
196  
SWMX[25]  
SPW_TXS[5]  
SDDQM[1]  
High  
High  
SpaceWire Transmit Strobe 5  
Out  
SDRAM Data Mask 1, corresponds to  
DATA[15:8]  
GPIO[22]  
SPW_RXS[5]  
TCRFAVL[0]  
GPIO[23]  
SPW_RXD[5]  
TCCLK[1]  
GPIO[24]  
1553RXENA  
-
-
High-Z  
In/Out  
In  
GPIO 1 Register, bit 22  
193  
192  
191  
SWMX[26]  
SWMX[27]  
SWMX[28]  
High  
High  
-
SpaceWire Receive Strobe 5  
Telecommand RF Available 0  
GPIO 1 Register, bit 23 (input only)  
SpaceWire Receive Data 5  
Telecommand Clock 1  
In  
In  
High  
Rising  
-
In  
In  
In  
GPIO 1 Register, bit 24 (input only)  
MIL-STD-1553B Receive Enable A  
Proprietary, enabled by CAN  
Ethernet Transmit Data 0  
High  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
In/Out  
Out  
Out  
Out  
In/Out  
In  
RMTXD[0]  
GPIO[25]  
1553TXA  
-
-
-
GPIO 1 Register, bit 25  
190  
189  
SWMX[29]  
SWMX[30]  
High  
MIL-STD-1553B Transmit Positive A  
Proprietary, enabled by CAN  
Ethernet Transmit Data 1  
RMTXD[1]  
GPIO[26]  
1553RXA  
TCD[1]  
-
-
GPIO 1 Register, bit 26  
High  
MIL-STD-1553B Receive Positive A  
Telecommand Data 1  
-
-
-
In  
RMRXD[0]  
GPIO[27]  
In  
Ethernet Receive Data 0  
In  
GPIO 1 Register, bit 27 (input only)  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
10  
GR712RC-DS  
Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest  
priority for each pin listed first.  
Pin no.  
Pin name  
Pin function  
1553RXNA  
TCACT[1]  
RMRXD[1]  
GPIO[28]  
1553TXNA  
-
Polarity  
Reset value  
Dir.  
In  
Description  
188  
SWMX[31]  
Low  
High  
-
MIL-STD-1553B Receive Negative A  
Telecommand Active 1  
In  
In  
Ethernet Receive Data 1  
-
In  
GPIO 1 Register, bit 28 (input only)  
MIL-STD-1553B Transmit Negative A  
Proprietary, enabled by CAN  
Ethernet Transmit Enable  
185  
SWMX[32]  
Low  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
In/Out  
Out  
Out  
In/Out  
In  
RMTXEN  
GPIO[29]  
1553TXINHA  
-
High  
-
GPIO 1 Register, bit 29  
184  
183  
SWMX[33]  
SWMX[34]  
High  
MIL-STD-1553B Transmit Inhibit A  
Proprietary, enabled by CAN  
GPIO 1 Register, bit 30  
GPIO[30]  
1553RXB  
TCRFAVL[1]  
RMCRSDV  
GPIO[31]  
1553RXNB  
TCCLK[2]  
RMINTN  
GPIO[32]  
1553RXENB  
A16MCS  
RMMDIO  
GPIO[33]  
1553TXB  
A16HS  
-
High  
High  
High  
-
MIL-STD-1553B Receive Positive B  
Telecommand RF Available 1  
Ethernet Carrier Sense / Data Valid  
GPIO 1 Register, bit 31 (input only)  
MIL-STD-1553B Receive Negative B  
Telecommand Clock 2  
In  
In  
In  
182  
179  
178  
SWMX[35]  
SWMX[36]  
SWMX[37]  
Low  
Rising  
Low  
-
In  
In  
In  
Ethernet Management Interrupt  
GPIO 2 Register, bit 0 (input only)  
MIL-STD-1553B Receive Enable B  
ASCS MCS - TM start/stop signal  
Ethernet Media Interface Data  
GPIO 2 Register, bit 1  
In  
High  
High  
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
In/Out  
Out  
Out  
Out  
In/Out  
In  
-
High  
High  
-
MIL-STD-1553B Transmit Positive B  
ASCS HS - TM/TC serial clock  
Ethernet Media Interface Clock  
GPIO 2 Register, bit 2  
RMMDC  
GPIO[34]  
-
SpaceWire clock  
divisor registers  
-
At reset, bits 8 and 0 in the clock divisor reg-  
ister of the SpaceWire interfaces are set from  
this input  
177  
SWMX[38]  
1553CK  
-
In  
MIL-STD-1553B Clock  
TCD[2]  
-
In  
Telecommand Data 2  
RMRFCLK  
GPIO[35]  
TCACT[2]  
GPIO[36]  
1553TXNB  
A16DCS  
GPIO[37]  
-
In  
Ethernet Reference Clock  
GPIO 2 Register, bit 3 (input only)  
Telecommand Active 2  
-
In  
176  
175  
SWMX[39]  
SWMX[40]  
High  
In  
-
In  
GPIO 2 Register, bit 4 (input only)  
MIL-STD-1553B Transmit Negative B  
ASCS DCS - Slave data out  
GPIO 2 Register, bit 5  
Low  
High-Z  
High-Z  
High-Z  
Out  
Out  
In/Out  
In  
-
-
-
SpaceWire clock  
divisor registers  
At reset, bits 9 and 1 in the clock divisor reg-  
ister of the SpaceWire interfaces are set from  
this input  
174  
SWMX[41]  
1553TXINHB  
A16MAS  
High  
High  
-
High-Z  
High-Z  
High-Z  
Out  
MIL-STD-1553B Transmit Inhibit B  
ASCS MAS - TM start/stop signal  
GPIO 2 Register, bit 6  
Out  
GPIO[38]  
In/Out  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
11  
GR712RC-DS  
Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest  
priority for each pin listed first.  
Pin no.  
Pin name  
Pin function  
TCRFAVL[2]  
GPIO[39]  
-
Polarity  
Reset value  
Dir.  
In  
Description  
173  
SWMX[42]  
High  
-
Telecommand RF Available 2  
GPIO 2 Register, bit 7 (input only)  
Proprietary, enabled by CAN  
GPIO 2 Register, bit 8  
In  
172  
SWMX[43]  
High-Z  
High-Z  
Out  
In/Out  
In  
GPIO[40]  
-
-
SpaceWire clock  
divisor registers  
At reset, bits 10 and 2 in the clock divisor reg-  
ister of the SpaceWire interfaces are set from  
this input  
169  
166  
SWMX[44]  
SWMX[45]  
SPICLK  
SLO  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
SPI Clock  
-
Out  
SLINK Data Out  
GPIO 2 Register, bit 9  
SPI Master Out Slave In  
SLINK Clock  
GPIO[41]  
SPIMOSI  
SLCLK  
GPIO[42]  
-
In/Out  
Out  
-
High  
Out  
-
-
In/Out  
In  
GPIO 2 Register, bit 10  
SpaceWire clock  
divisor registers  
At reset, bits 11 and 3 in the clock divisor reg-  
ister of the SpaceWire interfaces are set from  
this input  
165  
164  
163  
162  
161  
160  
SWMX[46]  
SWMX[47]  
SWMX[48]  
SWMX[49]  
SWMX[50]  
SWMX[51]  
TCCLK[3]  
GPIO[43]  
TCD[3]  
Rising  
In  
Telecommand Clock 3  
-
In  
GPIO 2 Register, bit 11 (input only)  
Telecommand Data 3  
-
In  
GPIO[44]  
SDCASN  
GPIO[45]  
SDRASN  
GPIO[46]  
TCACT[3]  
GPIO[47]  
SPIMISO  
TCRFAVL[3]  
SLI  
-
In  
GPIO 2 Register, bit 12 (input only)  
SDRAM Column Address Strobe  
GPIO 2 Register, bit 13  
Low  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
In/Out  
Out  
In/Out  
In  
-
Low  
SDRAM Row Address Strobe  
GPIO 2 Register, bit 14  
-
High  
-
Telecommand Active 3  
In  
GPIO 2 Register, bit 15 (input only)  
SPI Master In Slave Out  
In  
High  
In  
Telecommand RF Available 3  
SLINK Data In  
-
In  
GPIO[48]  
SDWEN  
-
In  
GPIO 2 Register, bit 16 (input only)  
SDRAM Write Enable  
157  
155  
SWMX[52]  
SWMX[53]  
Low  
-
High-Z  
High-Z  
High-Z  
Out  
In/Out  
Out  
GPIO[49]  
SDDQM[2]  
GPIO 2 Register, bit 17  
High  
SDRAM Data Mask 2, corresponds to  
DATA[23:16]  
GPIO[50]  
-
High-Z  
High-Z  
In/Out  
Out  
GPIO 2 Register, bit 18  
154  
SWMX[54]  
SDDQM[3]  
High  
SDRAM Data Mask 3, corresponds to  
DATA[31:24]  
GPIO[51]  
TCACT[4]  
GPIO[52]  
TCRFAVL[4]  
GPIO[53]  
I2CSDA  
-
High-Z  
In/Out  
In  
GPIO 2 Register, bit 19  
Telecommand Active 4  
GPIO 2 Register, bit 20 (input only)  
Telecommand RF Available 4  
GPIO 2 Register, bit 21 (input only)  
I2C Serial Data  
153  
144  
143  
SWMX[55]  
SWMX[56]  
SWMX[57]  
High  
-
In  
High  
-
In  
In  
High-Z  
High-Z  
In/Out  
In/Out  
In  
GPIO[54]  
TCCLK[4]  
I2CSCL  
-
GPIO 2 Register, bit 22  
Telecommand Clock 4  
I2C Serial Clock  
Rising  
142  
SWMX[58]  
High-Z  
High-Z  
In/Out  
In/Out  
In  
GPIO[55]  
TCD[4]  
-
-
GPIO 2 Register, bit 23  
Telecommand Data 4  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
12  
GR712RC-DS  
Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest  
priority for each pin listed first.  
Pin no.  
Pin name  
Pin function  
CB[8]  
Polarity  
Reset value  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dir.  
Description  
140  
SWMX[59]  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
Reed-Solomon Check Bit 8  
GPIO 2 Register, bit 24  
Reed-Solomon Check Bit 9  
GPIO 2 Register, bit 25  
Reed-Solomon Check Bit 10  
GPIO 2 Register, bit 26  
Reed-Solomon Check Bit 11  
GPIO 2 Register, bit 27  
Reed-Solomon Check Bit 12  
GPIO 2 Register, bit 28  
Reed-Solomon Check Bit 13  
GPIO 2 Register, bit 29  
Reed-Solomon Check Bit 14  
GPIO 2 Register, bit 30  
Reed-Solomon Check Bit 15  
GPIO 2 Register, bit 31  
GPIO[56]  
CB[9]  
137  
136  
135  
132  
129  
128  
127  
SWMX[60]  
SWMX[61]  
SWMX[62]  
SWMX[63]  
SWMX[64]  
SWMX[65]  
SWMX[66]  
GPIO[57]  
CB[10]  
GPIO[58]  
CB[11]  
GPIO[59]  
CB[12]  
GPIO[60]  
CB[13]  
GPIO[61]  
CB[14]  
GPIO[62]  
CB[15]  
GPIO[63]  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
13  
GR712RC-DS  
Table 4. I/O switch matrix pin utilization per interface type  
Interface type  
Pin function  
Direction  
Total  
In  
Out  
In/Out  
SDRAM  
SDDQM[3:0], SDCASN, SDRASN, SDWEN, SDCSN[1:0]  
CB[15:8]  
9
9
SDRAM Reed-Solomon  
GPIO  
8
8
GPIO[...]  
26  
6
38  
64  
12  
16  
10  
UART  
UART_TX[5:0], UART_RX[5:0]  
6
8
4
SpaceWire  
Ethernet  
SPW_RXD[5:2], SPW_RXS[5:2], SPW_TXD[5:2], SPW_TXS[5:2]  
RMTXD[1:0], RMTXEN, RMMDIO, RMMDC  
RMRFCLK, RMRXD[0:1], RMCRSDV, RMINTN  
CANTXA, CANRXA, CANTXB, CANRXB  
8
5
1
CAN  
4
5
4
8
8
MIL-STD-1553B BC/RT/BM 1553RXA, 1553RXNA, 1553RXENA, 1553TXA, 1553TXNA, 1553TXINHA  
13  
1553RXB, 1553RXNB, 1553RXENB, 1553TXB, 1553TXNB, 1553TXINHB  
1553CK  
I2C  
I2CSDA, I2CSCL  
2
2
SPI  
SPICLK, SPIMOSI, SPIMISO  
1
2
3
5
3
SLINK  
SLI, SLO, SLSYNC, SLCLK  
1
4
ASCS16  
A16DASA, A16DASB, A16MCS, A16HS, A16DCS, A16MAS, A16ETR  
TCACT[4:0], TCD[4:0], TCCLK[4:0], TCRFAV[4:0]  
TMDO, TMCLKO, TMCLKI  
2
7
CCSDS/ECSS TC  
CCSDS/ECSS TM  
20  
1
20  
3
2
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
14  
GR712RC-DS  
Table 5. I/O switch matrix pins listed per function, including supporting signals outside the I/O switch matrix.  
Pin no.  
157  
Pin name  
Pin function  
SDWEN  
Polarity  
Low  
Reset value  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dir.  
Out  
Out  
Out  
Out  
Out  
Out  
Description  
SWMX[52]  
SWMX[48]  
SWMX[49]  
SWMX[12]  
SWMX[13]  
SWMX[24]  
SDRAM Write Enable  
SDRAM Column Address Strobe  
SDRAM Row Address Strobe  
SDRAM Select 0  
163  
SDCASN  
SDRASN  
SDCSN[0]  
SDCSN[1]  
SDDQM[0]  
Low  
162  
Low  
228  
Low  
227  
Low  
SDRAM Select 1  
197  
High  
SDRAM Data Mask 0, corresponds to  
DATA[7:0]  
196  
155  
154  
SWMX[25]  
SWMX[53]  
SWMX[54]  
SDDQM[1]  
SDDQM[2]  
SDDQM[3]  
High  
High  
High  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
SDRAM Data Mask 1, corresponds to  
DATA[15:8]  
SDRAM Data Mask 2, corresponds to  
DATA[23:16]  
SDRAM Data Mask 3, corresponds to  
DATA[31:24]  
140  
137  
136  
135  
132  
129  
128  
127  
SWMX[59]  
SWMX[60]  
SWMX[61]  
SWMX[62]  
SWMX[63]  
SWMX[64]  
SWMX[65]  
SWMX[66]  
ADDRESS[16:2]  
DATA[31:0]  
CB[7:0]  
CB[8]  
-
-
-
-
-
-
-
-
-
-
-
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Low  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
Out  
Check Bit 8, Reed-Solomon  
Check Bit 9, Reed-Solomon  
Check Bit 10, Reed-Solomon  
Check Bit 11, Reed-Solomon  
Check Bit 12, Reed-Solomon  
Check Bit 13, Reed-Solomon  
Check Bit 14, Reed-Solomon  
Check Bit 15, Reed-Solomon  
Memory address  
CB[9]  
CB[10]  
CB[11]  
CB[12]  
CB[13]  
CB[14]  
CB[15]  
ADDRESS[16:2]  
DATA[31:0]  
CB[7:0]  
MCFG3[8]  
High-Z  
High-Z  
In/Out  
In/Out  
In  
Memory data bus  
Memory checkbits  
240  
238  
SWMX[4]  
At reset, bit 8 in MCFG3 register in the  
memory controller is set from this input.  
SWMX[6]  
MCFG1[9]  
-
In  
At reset, bit 9 in MCFG1 register in the  
memory controller is set from this input  
4
SWMX[0]  
UART_TX[0]  
UART_RX[0]  
UART_TX[1]  
UART_RX[1]  
UART_TX[2]  
UART_RX[2]  
UART_TX[3]  
UART_RX[3]  
UART_TX[4]  
UART_RX[4]  
UART_TX[5]  
UART_RX[5]  
SPW_RXD[0]  
SPW_RXS[0]  
SPW_TXD[0]  
SPW_TXS[0]  
SPW_RXD[1]  
SPW_RXS[1]  
SPW_TXD[1]  
SPW_TXS[1]  
SPW_RXD[2]  
-
High  
Out  
In  
UART Transmit 0  
3
SWMX[1]  
-
UART Receive 0  
2
SWMX[2]  
-
High  
Out  
In  
UART Transmit 1  
1
SWMX[3]  
-
UART Receive 1  
240  
239  
238  
233  
232  
231  
230  
229  
213  
214  
215  
216  
204  
205  
206  
209  
217  
SWMX[4]  
-
High-Z  
High-Z  
High-Z  
High-Z  
Out  
In  
UART Transmit 2  
SWMX[5]  
-
UART Receive 2  
SWMX[6]  
-
Out  
In  
UART Transmit 3  
SWMX[7]  
-
UART Receive 3  
SWMX[8]  
-
Out  
In  
UART Transmit 4  
SWMX[9]  
-
UART Receive 4  
SWMX[10]  
SWMX[11]  
SPW_RXD[0]  
SPW_RXS[0]  
SPW_TXD[0]  
SPW_TXS[0]  
SPW_RXD[1]  
SPW_RXS[1]  
SPW_TXD[1]  
SPW_TXS[1]  
SWMX[19]  
-
Out  
In  
UART Transmit 5  
-
UART Receive 5  
High  
High  
High  
High  
High  
High  
High  
High  
High  
In  
SpaceWire Receive Data 0  
SpaceWire Receive Strobe 0  
SpaceWire Transmit Data 0  
SpaceWire Transmit Strobe 0  
SpaceWire Receive Data 1  
SpaceWire Receive Strobe 1  
SpaceWire Transmit Data 1  
SpaceWire Transmit Strobe 1  
SpaceWire Receive Data 2  
In  
Low  
Low  
Out  
Out  
In  
In  
Low  
Low  
Out  
Out  
In  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
15  
GR712RC-DS  
Table 5. I/O switch matrix pins listed per function, including supporting signals outside the I/O switch matrix.  
Pin no.  
218  
219  
220  
200  
201  
202  
203  
225  
226  
227  
228  
192  
193  
197  
196  
178  
175  
172  
166  
185  
191  
190  
189  
188  
183  
182  
179  
178  
177  
220  
218  
219  
217  
191  
190  
185  
184  
172  
177  
184  
190  
185  
191  
189  
188  
174  
178  
Pin name  
Pin function  
SPW_RXS[2]  
SPW_TXD[2]  
SPW_TXS[2]  
SPW_RXD[3]  
SPW_RXS[3]  
SPW_TXD[3]  
SPW_TXS[3]  
SPW_RXD[4]  
SPW_RXS[4]  
SPW_TXD[4]  
SPW_TXS[4]  
SPW_RXD[5]  
SPW_RXS[5]  
SPW_TXD[5]  
SPW_TXS[5]  
Polarity  
Reset value  
Dir.  
In  
Description  
SWMX[18]  
SWMX[17]  
SWMX[16]  
SWMX[23]  
SWMX[22]  
SWMX[21]  
SWMX[20]  
SWMX[15]  
SWMX[14]  
SWMX[13]  
SWMX[12]  
SWMX[27]  
SWMX[26]  
SWMX[24]  
SWMX[25]  
SWMX[37]  
SWMX[40]  
SWMX[43]  
SWMX[45]  
SWMX[32]  
SWMX[28]  
SWMX[29]  
SWMX[30]  
SWMX[31]  
SWMX[34]  
SWMX[35]  
SWMX[36]  
SWMX[37]  
SWMX[38]  
SWMX[16]  
SWMX[18]  
SWMX[17]  
SWMX[19]  
SWMX[28]  
SWMX[29]  
SWMX[32]  
SWMX[33]  
SWMX[43]  
SWMX[38]  
SWMX[33]  
SWMX[29]  
SWMX[32]  
SWMX[28]  
SWMX[30]  
SWMX[31]  
SWMX[41]  
SWMX[37]  
High  
SpaceWire Receive Strobe 2  
SpaceWire Transmit Data 2  
SpaceWire Transmit Strobe 2  
SpaceWire Receive Data 3  
High  
High-Z  
High-Z  
Out  
Out  
In  
High  
High  
High  
In  
SpaceWire Receive Strobe 3  
SpaceWire Transmit Data 3  
SpaceWire Transmit Strobe 3  
SpaceWire Receive Data 4  
High  
High-Z  
High-Z  
Out  
Out  
In  
High  
High  
High  
In  
SpaceWire Receive Strobe 4  
SpaceWire Transmit Data 4  
SpaceWire Transmit Strobe 4  
SpaceWire Receive Data 5  
High  
High-Z  
High-Z  
Out  
Out  
In  
High  
High  
High  
In  
SpaceWire Receive Strobe 5  
SpaceWire Transmit Data 5  
SpaceWire Transmit Strobe 5  
At reset, bits 8 & 0 are set from this input  
At reset, bits 9 & 1 are set from this input  
At reset, bits 10 & 2 are set from this input  
At reset, bits 11 & 3 are set from this input  
Ethernet Transmit Enable  
High  
High-Z  
High-Z  
Out  
Out  
In  
High  
SpaceWire clock  
divisor registers  
values at reset, all  
other bits are zero.  
-
-
In  
-
In  
-
In  
RMTXEN  
RMTXD[0]  
RMTXD[1]  
RMRXD[0]  
RMRXD[1]  
RMCRSDV  
RMINTN  
RMMDIO  
RMMDC  
RMRFCLK  
CANTXA  
CANRXA  
CANTXB  
CANRXB  
-
High  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
In  
-
Ethernet Transmit Data 0  
-
Ethernet Transmit Data 1  
-
Ethernet Receive Data 0  
-
In  
Ethernet Receive Data 1  
High  
In  
Ethernet Carrier Sense / Data Valid  
Ethernet Management Interrupt  
Ethernet Media Interface Data  
Ethernet Media Interface Clock  
Ethernet Reference Clock  
Low  
In  
-
-
-
-
-
-
-
High-Z  
High-Z  
In/Out  
Out  
In  
High-Z  
High-Z  
Out  
In  
CAN Transmit A  
CAN Receive A  
Out  
In  
CAN Transmit B  
CAN Receive B  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
Out  
Out  
In  
Proprietary, enabled by CAN  
Proprietary, enabled by CAN  
Proprietary, enabled by CAN  
Proprietary, enabled by CAN  
Proprietary, enabled by CAN  
MIL-STD-1553B Clock  
-
-
-
-
1553CK  
-
1553TXINHA  
1553TXA  
1553TXNA  
1553RXENA  
1553RXA  
1553RXNA  
1553TXINHB  
1553TXB  
High  
High  
Low  
High  
High  
Low  
High  
High  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
Out  
In  
MIL-STD-1553B Transmit Inhibit A  
MIL-STD-1553B Transmit Positive A  
MIL-STD-1553B Transmit Negative A  
MIL-STD-1553B Receive Enable A  
MIL-STD-1553B Receive Positive A  
MIL-STD-1553B Receive Negative A  
MIL-STD-1553B Transmit Inhibit B  
MIL-STD-1553B Transmit Positive B  
In  
High-Z  
High-Z  
Out  
Out  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
16  
GR712RC-DS  
Table 5. I/O switch matrix pins listed per function, including supporting signals outside the I/O switch matrix.  
Pin no.  
175  
179  
183  
182  
143  
142  
169  
166  
160  
203  
166  
160  
169  
226  
225  
202  
175  
174  
179  
178  
229  
226  
225  
193  
188  
192  
189  
183  
176  
182  
177  
173  
161  
165  
164  
160  
153  
143  
142  
144  
231  
230  
232  
Pin name  
Pin function  
1553TXNB  
1553RXENB  
1553RXB  
1553RXNB  
I2CSDA  
Polarity  
Low  
Reset value  
High-Z  
Dir.  
Out  
Out  
In  
Description  
SWMX[40]  
SWMX[36]  
SWMX[34]  
SWMX[35]  
SWMX[57]  
SWMX[58]  
SWMX[44]  
SWMX[45]  
SWMX[51]  
SWMX[20]  
SWMX[45]  
SWMX[51]  
SWMX[44]  
SWMX[14]  
SWMX[15]  
SWMX[21]  
SWMX[40]  
SWMX[41]  
SWMX[36]  
SWMX[37]  
SWMX[11]  
SWMX[14]  
SWMX[15]  
SWMX[26]  
SWMX[31]  
SWMX[27]  
SWMX[30]  
SWMX[34]  
SWMX[39]  
SWMX[35]  
SWMX[38]  
SWMX[42]  
SWMX[50]  
SWMX[46]  
SWMX[47]  
SWMX[51]  
SWMX[55]  
SWMX[57]  
SWMX[58]  
SWMX[56]  
SWMX[9]  
MIL-STD-1553B Transmit Negative B  
MIL-STD-1553B Receive Enable B  
MIL-STD-1553B Receive Positive B  
MIL-STD-1553B Receive Negative B  
I2C Serial Data  
High  
High-Z  
High  
Low  
In  
High-Z  
High-Z  
High-Z  
High-Z  
In/Out  
In/Out  
Out  
Out  
In  
I2CSCL  
I2C Serial Clock  
SPICLK  
SPI Clock  
SPIMOSI  
SPIMISO  
SLSYNC  
SLCLK  
-
SPI Master Out Slave In  
SPI Master In Slave Out  
SLINK SYNC  
High  
High  
-
High-Z  
High-Z  
Out  
Out  
In  
SLINK Clock  
SLI  
SLINK Data In  
SLO  
-
High-Z  
Out  
In  
SLINK Data Out  
A16DASA  
A16DASB  
A16ETR  
-
ASCS DAS A - Slave data in  
ASCS DAS B - Slave data in  
ASCS ETR - Synchronization signal  
ASCS DCS - Slave data out  
ASCS MAS - TM start/stop signal  
ASCS MCS - TC start/stop signal  
ASCS HS - TM/TC serial clock  
Telecommand Active 0  
Telecommand Clock 0  
Telecommand Data 0  
-
In  
High  
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Out  
Out  
Out  
Out  
Out  
In  
A16DCS  
A16MAS  
A16MCS  
A16HS  
High  
High  
High  
High  
Rising  
-
TCACT[0]  
TCCLK[0]  
TCD[0]  
In  
In  
TCRFAVL[0]  
TCACT[1]  
TCCLK[1]  
TCD[1]  
High  
High  
Rising  
-
In  
Telecommand RF Available 0  
Telecommand Active 1  
Telecommand Clock 1  
Telecommand Data 1  
In  
In  
In  
TCRFAVL[1]  
TCACT[2]  
TCCLK[2]  
TCD[2]  
High  
High  
Rising  
-
In  
Telecommand RF Available 1  
Telecommand Active 2  
Telecommand Clock 2  
Telecommand Data 2  
In  
In  
In  
TCRFAVL[2]  
TCACT[3]  
TCCLK[3]  
TCD[3]  
High  
High  
Rising  
-
In  
Telecommand RF Available 2  
Telecommand Active 3  
Telecommand Clock 3  
Telecommand Data 3  
In  
In  
In  
TCRFAVL[3]  
TCACT[4]  
TCCLK[4]  
TCD[4]  
High  
High  
Rising  
-
In  
Telecommand RF Available 3  
Telecommand Active 4  
Telecommand Clock 4  
Telecommand Data 4  
In  
In  
In  
TCRFAVL[4]  
TMCLKI  
TMCLKO  
TMDO  
High  
Rising  
-
In  
Telecommand RF Available 4  
Telemetry Clock Input  
Telemetry Clock Output  
Telemetry Data Out  
In  
SWMX[10]  
SWMX[8]  
High-Z  
High-Z  
Out  
Out  
-
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
17  
GR712RC-DS  
Table 6. Conflicting interfaces in the I/O switch matrix are marked with an X, with duplicates shown in bold typeface.  
SDRAM (with RS)  
UART 0  
-
X
X
-
UART 1  
-
UART 2  
-
UART 3  
-
UART 4  
-
X
X
UART 5  
-
X
SpaceWire 0  
SpaceWire 1  
SpaceWire 2  
SpaceWire 3  
SpaceWire 4  
SpaceWire 5  
Ethernet  
-
-
-
X
X
X
-
X
X
X
-
X
X
-
X
-
X
X
X
X
CAN  
X
X
X
X
-
MIL-STD-1553B  
I2C  
-
X
X
X
-
X
SPI  
-
X
X
X
SLINK  
X
X
-
ASCS  
X
X
X
-
X
CCSDS TC 0  
CCSDS TC 1  
CCSDS TC 2  
CCSDS TC 3  
CCSDS TC 4  
CCSDS TM  
X
X
X
X
X
-
X
X
X
X
-
-
X
X
-
X
-
X
-
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
18  
GR712RC-DS  
2
Electrical characteristics  
2.1  
Absolute maximum ratings  
These values specify the stress that might apply to the device without causing it permanent damage.  
Table 7. Absolute maximum ratings 1)  
Symbol  
Parameter  
Rating  
Units  
Min.  
Max.  
VDDIO  
VDD  
VIN  
DC Supply Voltage for I/O  
DC Supply Voltage for Core  
Input Voltage  
-0.3  
4.2  
V
V
-0.3  
-0.3  
-65  
-55  
2.4  
VDDIO + 0.3  
+150  
+125  
+250  
+150  
4
V
Tstor  
Tcase  
Tsolder  
Tj  
Storage Temperature  
˚C  
Operating Case Temperature  
Lead Temperature (Soldering 10 sec.)  
Junction Temperature  
˚C  
˚C  
˚C  
ΘJC (ceramic) Thermal Resistance, Junction to Case  
˚C/W  
W
PD  
Power Dissipation  
6.25  
Note 1:  
Extended operation at the maximum levels may degrade the performance and affect the reliability of the  
device.  
2.2  
Recommended operating conditions  
Table 8. Recommended operating conditions  
Symbol  
Parameter  
Rating  
Units  
Min.  
Typ.  
Max.  
VDDIO  
VDD  
DC Supply Voltage for I/O  
DC Supply Voltage for Core  
Input Voltage  
3.0  
3.3  
3.6  
V
V
1.65  
0
1.8  
1.95  
VDDIO  
+125  
VIN  
V
Tcase  
Operating Case Temperature  
-55  
0.4  
˚C  
Slew rate of all inputs 1)  
SLIN  
Note 1:  
V/ns  
Applies only to the range 0.8 V and 2.0 V.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
19  
GR712RC-DS  
2.3  
DC electrical performance characteristics  
Table 9. DC characteristics (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Symbol Parameter  
Condition  
Rating  
Typ.  
Units  
Min.  
Max.  
Output High Voltage 1)  
IOH = -4 mA 2)  
IOH = -6 mA 3)  
VOH  
2.4  
V
V
VOL  
Output Low Voltage  
0.5  
IOL = 4 mA 2)  
IOL = 6 mA 3)  
VIH  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
2.0  
V
V
VIL  
0.8  
10  
10  
IILEAK  
-10  
-10  
uA  
uA  
IOLEAK Output Leakage Current  
outputs at  
tri-state  
120 5)  
IOS  
Short-circuit Output Current  
VO = VDDIO  
,
mA  
VDDIO = 3.6 V  
-120 5)  
VO = 0 V,  
VDDIO = 3.6 V  
IDDS  
IDD  
Core Static Current  
Core Supply Current  
FCLK = 0 MHz  
1
mA  
A
10  
2.0 5)  
2
FCLK = 100 MHz  
0.9  
0.2  
I/O Static Current 4)  
IDDIOS  
FCLK = 0 MHz  
VDDIO = 3.6 V  
mA  
I/O Supply Current 6)  
I/O Pad Capacitance 5)  
IDDIO  
CI/O  
mA  
pF  
15  
Note 1: Except open-drain outputs ERRORN, WDOGN, I2CSCL and I2CSDA.  
Note 2: All outputs defined with a maximum load of 50 pF.  
Note 3: All outputs defined with a maximum load of 100 pF.  
Note 4: All inputs at 0 V or VDDIO. No resistive load.  
Note 5: Supplied as a design limit. Parameter not measured during production test.  
Note 6: The dynamic power consumption of the I/O supply can be calculated as a function of the average frequency and  
2
the capacitive load of each output i: sum of [FI/O * CLOAD (i) * (VDDIO)  
]
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
20  
GR712RC-DS  
Table 10. Detailed core power consumption (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Test condition  
Rating  
Units  
1)  
Typ.  
Max.  
Static, no clocks or toggling signals  
30  
4
50  
6
mW  
Standby, all cores clock gated  
mW/MHz  
mW/MHz  
mW/MHz  
mW/MHz  
mW/MHz  
mW/MHz  
mW/MHz  
1 processor core active at 50%, remaining IP cores clock gated  
1 processor core active at 100%, remaining IP cores clock gated  
2 processor cores active at 100%, remaining IP cores clock gated  
1 SpaceWire link active @ 100 Mbit/s  
7
10  
15  
24  
1.5  
1.5  
1
10  
15  
1
2 CAN interfaces active 100% @ 1 Mbit/s  
1
Telemetry encoder active @ 10 Mbit/s  
0.5  
Note 1: Supplied as a design limit. Parameter not measured during production test.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
21  
GR712RC-DS  
2.4  
AC electrical performance characteristics  
All measured AC parameters have been tested with a 50 pF - 70 pF capacitive load on the outputs.  
Transition time measurements have been tested at a voltage level of 1.4 V. Equivalent load chart is  
provided in the product specification [PS.]  
2.4.1 Clock  
The timing waveforms and timing parameters are shown in figure 3 and are defined in table 11.  
TINCLK  
INCLK  
Figure 3. Timing waveforms  
Table 11. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference  
INCLK  
Min  
10  
Max  
-
Unit  
ns  
TINCLK  
input clock period without DLL  
input clock frequency without DLL 2)  
input clock high phase without DLL 5)  
input clock low phase without DLL 5)  
input clock period with DLL 1)  
input clock frequency with DLL 1) 2)  
input frequency duty cycle with DLL  
input clock high phase with DLL 5)  
input clock low phase with DLL 5)  
FINCLK  
INCLK  
INCLK  
INCLK  
INCLK  
INCLK  
INCLK  
INCLK  
INCLK  
-
-
100  
MHz  
ns  
TINCLK_HIGH  
TINCLK_LOW  
TINCLK  
4.5  
4.5  
20  
ns  
22 3)  
50  
ns  
46 3)  
35  
FINCLK  
MHz  
%
DCINCLK  
TINCLK_HIGH  
TINCLK_LOW  
TCLK  
65  
7
ns  
7
ns  
4) 5) 6)  
10  
-
-
ns  
internal system clock period  
internal system clock frequency 2) 4) 5) 6)  
FCLK  
-
100  
MHz  
Note 1:  
Note 2:  
For the system clock, the DLL provides a times 2 multiplication of the input frequency.  
TINCLK = 1/FINCLK, TCLK = 1/FCLK  
Note 3:  
Note 4:  
Parameter not measured during production test.  
Applies to the system clock only (i.e. processor and AMBA clock) only. SpaceWire clocks are dis-  
cussed in section 2.4.9.  
Note 5:  
The maximum internal system clock frequency is specified by the parameters TCLK and FCLK.  
The parameters TINCLK and FINCLK specify the what the clock input pin and the DLL can support,  
and not what the internal logic can support.  
Note 6:  
The internal system clock frequency is limited by the timing of the memory interface towards external  
synchronous memory components.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
22  
GR712RC-DS  
2.4.2 Reset and initialization  
The timing waveforms and timing parameters are shown in figure 4 and are defined in table 12.  
INCLK  
RESETN  
tRSTGEN0  
Figure 4. Timing waveforms  
Table 12. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge Min  
10  
Max  
-
Unit  
tRSTGEN0  
asserted period  
-
TINCLK periods  
Note 1:  
Note 2:  
The RESETN input is re-synchronized internally.  
VDD must reach at least minimum operating voltage for tRESTGEN0 before RESETN is de-asserted.  
If DLL is used, the internal reset is released 2048 TINCLK periods after RESETN is de-asserted  
After power-up all flip-flops, on-chip memory and DLL are in an unknown state before reset.  
Note 3:  
Note 4:  
2.4.3 LEON3 - High-performance SPARC V8 32-bit Processor  
The timing waveforms and timing parameters are shown in figure 5 and are defined in table 13.  
INCLK  
tLEON0  
tLEON1  
ERRORN  
Figure 5. Timing waveforms  
Table 13. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
2 1)  
Max  
23 2)  
50 1)  
Unit  
ns  
tLEON0  
clock to output delay  
rising INCLK edge  
tLEON1  
clock to output tri-state  
rising INCLK edge  
ns  
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
Parameter measured during production test without DLL enabled.  
For correct operation, the signal should be pulled-up externally with 1- 10 kOhm. GR712RC does  
not include any internal pull-up resistors.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
23  
GR712RC-DS  
2.4.4 Fault tolerant memory controller  
The timing waveforms and timing parameters are shown in figure 6 and are defined in table 14.  
SDCLK  
tFTMCTRL0  
ADDRESS[23:0]  
tFTMCTRL1  
tFTMCTRL2  
tFTMCTRL2  
tFTMCTRL1  
tFTMCTRL2  
tFTMTRL2  
RAMSN[1:0]  
ROMSN[1:0]  
RAMWEN, WRITEN  
READ  
tFTMCTRL3, FTMCTRL4  
t
DATA[31:0], CB[7:0]  
(output)  
tFTMCTRL5  
SDCLK  
ADDRESS[23:0]  
RAMSN[1:0]  
ROMSN[1:0]  
tFTMCTRL6  
tFTMCTRL6  
RAMOEN, OEN  
READ  
tFTMCTRL7  
tFTMCTRL8  
DATA[31:0], CB[7:0]  
(input)  
tFTMCTRL10  
tFTMCTRL9  
BRDYN, BEXCN  
Figure 6. Timing waveforms - SRAM (0 wait state) access, PROM (0 wait state) access  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
24  
GR712RC-DS  
The timing waveforms and timing parameters are shown in figure 7 and are defined in table 14.  
SDCLK  
tFTMCTRL0  
ADDRESS[23:0]  
tFTMCTRL1  
tFTMCTRL2  
tFTMCTRL1  
tFTMCTRL2  
tFTMCTRL2  
IOSN  
RAMWEN, WRITEN  
READ  
tFTMCTRL2  
tFTMCTRL3, FTMCTRL4  
t
DATA[31:0]  
(output)  
tFTMCTRL5  
SDCLK  
ADDRESS[23:0]  
IOSN  
tFTMCTRL6  
tFTMCTRL6  
OEN  
READ  
tFTMCTRL8  
tFTMCTRL7  
DATA[31:0]  
(input)  
tFTMCTRL10  
tFTMCTRL9  
BRDYN, BEXCN  
Figure 7. Timing waveforms - I/O accesses  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
25  
GR712RC-DS  
Table 14. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge 2)  
Min  
0 1)  
0 1)  
Max  
Unit  
address clock to output delay 3)  
tFTMCTRL0  
rising SDCLK edge  
7.5  
ns  
tFTMCTRL1  
clock to RAMSN[1:0] and  
ROMSN[1:0]output delay 3)  
rising SDCLK edge  
7.5  
ns  
clock to IOSN output delay 3)  
clock to output delay  
0 1)  
0 1)  
0 1)  
0 1)  
0 1)  
tFTMCTRL1  
tFTMCTRL2  
tFTMCTRL3  
tFTMCTRL4  
tFTMCTRL5  
tFTMCTRL6  
tFTMCTRL7  
tFTMCTRL8  
tFTMCTRL9  
tFTMCTRL10  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
8.5  
8.5  
6.5  
6.5  
ns  
ns  
ns  
ns  
clock to data output delay  
clock to data non-tri-state delay  
clock to data tri-state delay 4)  
clock to output delay  
6.5 1)  
8.5  
ns  
ns  
0 1)  
6.9  
data input to clock setup  
data input from clock hold  
input to clock setup  
-
-
-
-
ns  
ns  
ns  
ns  
-0.5 1)  
6.9  
-0.5 1)  
input from clock hold  
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
The specified timing is valid for the default programmable internal clock delay of value 0.  
The ADDRESS[23:0] and RAMSN[1:0] signals change in the same clock cycle, which might not be  
compatible with all SRAM types. Check your SRAM documentation for compatibility.  
Note 4:  
GR712RC does not provide internal pull-up resistors on the DATA[31:0] and CB[15:0] buses. In the  
case of prolonged periods of idle bus activity in a board design, i.e. high impedance state, it is  
advised to add external pull-up resistors.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
26  
GR712RC-DS  
The timing waveforms and timing parameters are shown in figure 8 and are defined in table 15.  
SDCLK  
tFTMCTRL11  
SDCASN, SDRASN  
SDWEN, SDCSN[1:0]  
SDDQM[3:0]  
write  
nop  
read  
nop  
nop  
term  
nop  
nop  
nop  
tFTMCTRL11  
ADDRESS[16:2]  
tFTMCTRL12  
tFTMCTRL14  
tFTMCTRL13  
DATA[31:0], CB[15:0]  
tFTMCTRL15  
Figure 8. Timing waveforms - SDRAM accesses  
Table 15. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge 2)  
Min  
1 1)  
Max  
Unit  
tFTMCTRL11  
clock to output delay  
rising SDCLK edge  
6
ns  
1 1)  
tFTMCTRL12  
tFTMCTRL13  
tFTMCTRL14  
tFTMCTRL15  
clock to data output delay  
data clock to data tri-state delay  
data input to clock setup  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
rising SDCLK edge  
6.5  
ns  
ns  
ns  
ns  
1 1)  
6.9  
6.5 1)  
-
-0.5 1)  
data input from clock hold  
-
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
The specified timing is valid for the default programmable internal clock delay of value 0.  
The maximum operating frequency of the GR712RC may be limited due to the timing performance  
of external SDRAM devices.  
The timing waveforms and timing parameters are shown in figure 9 and are defined in table 16.  
TSDCLK0, TSDCLK51  
INCLK  
SDCLK  
Figure 9. Timing waveforms  
Table 16. Timing parameters (VDD = 1.65 V, VDDIO = 3.0 V, Tcase = +125˚C) 1)  
Name  
Parameter  
Reference  
Min  
7
Max  
10  
Unit  
ns  
TSDCLK0  
clock to output delay, delay value 0  
rising INCLK edge  
TSDCLK51  
Note 1:  
clock to output delay, delay value 51  
rising INCLK edge  
25  
ns  
16  
Production test performed at fixed voltage and temperature.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
27  
GR712RC-DS  
2.4.5 JTAG Debug Interface  
The timing waveforms and timing parameters are shown in figure 10 and are defined in table 17.  
tAHBJTAG0  
tAHBJTAG1  
TCK  
tAHBJTAG2  
TDI, TMS  
TDO  
tAHBJTAG4  
tAHBJTAG3  
Figure 10. Timing waveforms  
Table 17. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
tAHBJTAG0  
clock period  
-
100  
-
ns  
tAHBJTAG1  
tAHBJTAG2  
tAHBJTAG3  
tAHBJTAG4  
clock low/high period  
-
40  
-
ns  
ns  
ns  
ns  
10 1)  
10 1)  
0 1)  
data input to clock setup  
data input from clock hold  
clock to data output delay  
rising TCK edge  
rising TCK edge  
falling TCK edge  
-
-
21  
Note 1:  
Note 2:  
Parameter not measured during production test.  
For correct operation, all JTAG signals should be pulled-up externally with 1 - 10 kOhm. This is in  
line with the TAP specification where TMS and TDI implementation should be such that if an exter-  
nal signal fails (e.g. open circuit) then the behavior of TMS and TDI should be equivalent to a logi-  
cal 1 input. GR712RC does not include any internal pull-up resistors.  
2.4.6 General Purpose Timer Unit  
The timing waveforms and timing parameters are shown in figure 11 and are defined in table 18.  
INCLK  
tGPTIMER0  
tGPTIMER1  
WDOGN  
Figure 11. Timing waveforms  
Table 18. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
23 2)  
50 1)  
Unit  
2 1)  
tGPTIMER0  
clock to output delay  
rising INCLK edge  
ns  
tGPTIMER1  
clock to output tri-state  
rising INCLK edge  
ns  
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
Parameter measured during production test without DLL enabled.  
For correct operation, the signal should be pulled-up externally with 1 - 10 kOhm. GR712RC does  
not include any internal pull-up resistors.  
Note 4:  
WDOGN output is undefined during internal reset when DLL is used to generate the internal system  
clock frequency. See section 2.4.2 for detailed timing information on the reset behavior.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
28  
GR712RC-DS  
2.4.7 General Purpose Input Output Port  
The timing waveforms and timing parameters are shown in figure 12 and are defined in table 19.  
INCLK  
GPIO[...]  
tGRGPIO0  
tGRGPIO0  
(output)  
tGRGPIO1  
tGRGPIO2  
GPIO[...]  
(output)  
GPIO[...]  
tGRGPIO3  
tGRGPIO4  
(input)  
Figure 12. Timing waveforms  
Table 19. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
2 1)  
Max  
21 2)  
21 1)  
Unit  
tGRGPIO0  
clock to output delay  
rising INCLK edge  
ns  
2 1)  
tGRGPIO1  
tGRGPIO2  
tGRGPIO3  
tGRGPIO4  
clock to non-tri-state delay  
clock to tri-state delay  
input to clock hold  
rising INCLK edge  
rising INCLK edge  
rising INCLK edge  
rising INCLK edge  
ns  
ns  
50 1)  
-
ns 3)  
ns 3)  
-
-
input to clock setup  
-
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
Parameter measured during production test without DLL enabled.  
The GPIO[...] inputs are re-synchronized to the internal system clock with a TCLK period.  
2.4.8 UART Serial Interface  
The timing waveforms and timing parameters are shown in figure 13 and are defined in table 20.  
INCLK  
UART_TX[5:0]  
UART_RX[5:0]  
tAPBUART0  
tAPBUART0  
tAPBUART1  
tAPBUART2  
Figure 13. Timing waveforms  
Table 20. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
2 1)  
-
21 2)  
-
tAPBUART0  
clock to output delay  
rising INCLK edge  
ns  
ns 3)  
ns 3)  
tAPBUART1  
tAPBUART2  
input to clock hold  
input to clock setup  
rising INCLK edge  
rising INCLK edge  
-
-
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
Parameter measured during production test without DLL enabled.  
The UART_RX[5:0] inputs are re-synchronized to the internal system clock with a TCLK period.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
29  
GR712RC-DS  
2.4.9 SpaceWire Interface  
The timing waveforms and timing parameters are shown in figure 14 and are defined in table 21.  
TSPWCLK  
SPWCLK  
tSPW2  
tSPW2  
SPW_TXD[5:0]  
SPW_TXS[5:0]  
tSPW2  
tSPW3  
SPW_TXD[5:0]  
SPW_TXS[5:0]  
tSPW4, SPW6  
t
tSPW4, SPW6  
t
SPW_RXD[5:0]  
SPW_RXS[5:0]  
tSPW4, SPW6  
t
tSPW5  
SPW_RXD[5:0]  
SPW_RXS[5:0]  
Figure 14. Timing waveforms  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
30  
GR712RC-DS  
Table 21. Timing parameters transmitter (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
input clock period without DLL 5)  
input clock frequency without DLL 2)  
input frequency duty cycle without DLL 5)  
input clock period with DLL x2 1) 6)  
10 4)  
-
TSPWCLK  
SPWCLK  
-
ns  
100 4)  
55  
FSPWCLK  
DCSPWCLK  
TSPWCLK  
FSPWCLK  
TSPWCLK  
FSPWCLK  
DCSPWCLK  
TSPW  
SPWCLK  
MHz  
%
SPWCLK  
45  
20  
22 4)  
50  
SPWCLK  
ns  
1) 2)  
45 4)  
20  
SPWCLK  
MHz  
ns  
input clock frequency with DLL x2  
input clock period with DLL x4 1) 6)  
22 4)  
50  
SPWCLK  
input clock frequency with DLL x4 1) 2)  
input frequency duty cycle with DLL  
45 4)  
SPWCLK  
MHz  
%
35 4)  
5
65 4)  
SPWCLK  
internal transmitter clock period 6)  
500 4)  
200  
-
-
-
-
-
-
-
ns  
internal transmitter clock frequency 2) 6)  
output data bit period  
2 4)  
FSPW  
MHz  
ns  
5 4)  
-
500 4)  
500 4)  
500 4)  
tSPW2  
tSPW3  
data & strobe output skew & jitter  
input data bit period  
ps  
5 4)  
-
tSPW4  
ns  
800 4)  
-
tSPW5  
data & strobe input skew, jitter & hold  
ps  
data & strobe edge separation 5)  
2500 4)  
tSPW6  
ps  
Note 1:  
For the internal SpaceWire clock, the DLL provides a times 2 or 4 multiplication of the input fre-  
quency.  
Note 2:  
TSPWCLK = 1/FSPWCLK, TSPW = 1/FSPW  
Note 3:  
Note 4:  
Note 5:  
N/A  
Parameter not measured during production test.  
Minimum internal edge separation equals half the internal transmitter clock period. Minimum tSPW6 is  
specified at minimum TSPW with 50% duty cycle. External edge separation should not be less than the  
sum of tSPW5 + tSPW6  
.
Note 6:  
Note 7:  
The maximum SpaceWire clock frequency is specified by the parameters TSPW and FSPW  
.
The parameters TSPWCLK and FSPWCLK specify the what the clock input pin and the DLL can support,  
and not what the internal logic can support.  
The parameters tSPWn are only valid between signals belonging to one SpaceWire link.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
31  
GR712RC-DS  
2.4.10 Ethernet Media Access Controller (MAC)  
The timing waveforms and timing parameters are shown in figure 15 and are defined in table 22.  
RMRFCLK  
RMTXD[1:0], RMTXEN  
tGRETH0  
tGRETH0  
RMRXD[1:0]  
tGRETH1  
tGRETH2  
Figure 15. Timing waveforms  
Table 22. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
-
Unit  
ns  
20 4)  
tGRETHREF Ethernet reference clock period  
any RMRFCLK edge  
2 1)  
2
tGRETH0  
tGRETH1  
tGRETH2  
transmitter clock to output delay rising RMRFCLK edge  
15  
-
ns  
ns  
ns  
input to receiver clock hold  
input to receiver clock setup  
rising RMRFCLK edge  
rising RMRFCLK edge  
4
-
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
The RMINTN, RMMDIO and RMCRSDV inputs are re-synchronized internally.  
The RMMDIO and RMMDC outputs are low speed signals without any timing relationship with the  
RMRFCLK clock.  
Note 4:  
According to Ethernet standard the reference clock RMRFCLK frequency must be 50 MHz +/- 50 ppm.  
2.4.11 CAN Interface  
The timing waveforms and timing parameters are shown in figure 16 and are defined in table 23.  
INCLK  
tCAN_OC0  
CANTX[A:B]  
tCAN_OC2  
CANRX[A:B]  
tCAN_OC1  
Figure 16. Timing waveforms  
Table 23. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
ns  
clock to data output delay  
data input to clock setup  
rising INCLK edge  
rising INCLK edge  
2 1)  
-
21 1)  
-
tCAN_OC0  
tCAN_OC1  
ns 3)  
ns 3)  
tCAN_OC2  
data input from clock hold  
rising INCLK edge  
-
-
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
Parameter measured during production test without DLL enabled.  
The CANRX[A:B] input is re-synchronized to the internal system clock with a TCLK period.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
32  
GR712RC-DS  
2.4.12 Obsolete  
Proprietary function not supported.  
2.4.13 MIL-STD-1553B BC/RT/BM  
The timing waveforms and timing parameters are shown in figure 17 and are defined in table 24.  
1553CK  
t1553BRM0  
1553TXA/TXAN  
1553TXB/TXBN  
1553TXINHA, 1553TXINHB  
1553RXENA, 1553RXENB  
t1553BRM2  
1553RXA/RXAN  
1553RXB/RXBN  
t1553BRM1  
Figure 17. Timing waveforms  
Table 24. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
ns  
clock to data output delay  
data input to clock setup  
rising 1553CK edge 2 1)  
21 1)  
-
t1553BRM0  
t1553BRM1  
t1553BRM2  
t1553BRM3  
ns 2)  
ns 2)  
MHz 3)  
rising 1553CK edge  
rising 1553CK edge  
1553CK  
-
-
data input from clock hold  
clock frequency  
-
16, 20, 24  
Note 1:  
Note 2:  
Note 3:  
Parameter not measured during production test.  
The 1553RXA, 1553RXAN, 1553RXB and 1553RXBN inputs are re-synchronized internally.  
The core frequency must be lower than the internal system frequency: t1553BRM3 < FCLK  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
33  
GR712RC-DS  
2.4.14 I2C-master  
The timing waveforms and timing parameters are shown in figure 18 and are defined in table 25.  
I2CSCL  
(input/output)  
tI2C1  
tI2C0  
tI2C3  
I2CSDA  
(output)  
I2CSDA  
(input)  
tI2C2  
Figure 18. Timing waveforms  
Table 25. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
scaler 1)  
-
tI2C0  
data output valid before clock  
rising I2CSCL edge  
-
TCLK periods  
scaler 1)  
2 2)  
tI2C1  
data output valid after clock  
data input setup to clock  
data input hold from clock  
falling I2CSCL edge  
rising I2CSCL edge  
falling I2CSCL edge  
TCLK periods  
TCLK periods  
TCLK periods  
tI2C2  
-
-
0 2)  
tI2C3  
Note 1:  
The core’s I2C bus functional timing depends on the core’s scaler value and the internal system clock  
TCLK period. When the scaler is set for the core to operate in Fast- or Standard-Mode, the timing charac-  
teristics in the I2C-bus specification apply. The maximum TCLK period for proper operation is 50 ns.  
The I2CSCL and I2CSDA inputs are re-synchronized to the internal system clock with a TCLK period.  
I2CSCL and I2CSDA are open-drain outputs, driving a logical 0 level or tri-state.  
Note 2:  
Note 3:  
Note 4:  
For correct operation, the signals should be pulled-up externally with 10 kOhm. GR712RC does not  
include any internal pull-up resistors.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
34  
GR712RC-DS  
2.4.15 SPI controller  
The timing waveforms and timing parameters are shown in figure 19 and are defined in table 26.  
SPICLK  
SPIMOSI  
SPIMISO  
tSPICTRL0  
tSPICTRL0  
tSPICTRL1  
tSPICTRL2  
Figure 19. Timing waveforms  
Table 26. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
-15 2)  
0 2)  
Max  
Unit  
ns 1)  
ns 3)  
ns 3)  
15 2)  
-
tSPICTRL0  
clock to output delay  
driving SPICLK edge  
tSPICTRL1  
tSPICTRL2  
Note 1:  
input to clock hold  
input to clock setup  
sampling SPICLK edge  
sampling SPICLK edge  
20 2)  
-
The driving and sampling edges of the interface are programmable, and always opposite to each  
other.  
Note 2:  
Note 3:  
Parameter not measured during production test.  
The SPIMISO input is re-synchronized to the internal system clock with a TCLK period.  
2.4.16 SLINK Serial Bus Based Real-Time Network Master  
The timing waveforms and timing parameters are shown in figure 20 and are defined in table 27.  
SLCLK  
SLO, SLSYNC  
tSLINK0  
tSLINK0  
(output)  
SLI  
tSLINK1  
tSLINK2  
(input)  
Figure 20. Timing waveforms  
Table 27. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
TCLK periods 1)  
TCLK periods  
TCLK periods  
tSLINK0  
clock to output delay  
rising SLCLK edge  
1
-
tSLINK1  
tSLINK2  
Note 1:  
input to clock hold  
input to clock setup  
rising SLCLK edge  
rising SLCLK edge  
0
2
-
-
Output timing depends on the ODEL setting in the core’s control register. Outputs will transition  
(ODEL+1)*(system clock period) ns after SLCLK rising edge.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
35  
GR712RC-DS  
2.4.17 ASCS controller  
The timing waveforms and timing parameters are shown in figure 21 and are defined in table 28.  
tASCS1  
tASCS3  
A16MCS, A16MAS  
A16DCS  
tASCS4  
tASCS5  
tASCS2  
tASCS6  
tASCS0  
A16HS  
tASCS7  
A16DASA, A16DASB  
Figure 21. Timing waveforms  
Table 28. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
TCLK periods 1)  
tASCS0  
clock period  
rising A16HS edge  
2
-
TCLK periods 1)  
TCLK periods 1)  
TCLK periods 1)  
TCLK periods 1)  
tASCS1  
tASCS2  
tASCS3  
tASCS4  
tASCS5  
qualifier de-asserted width  
qualifier asserted to clock  
clock to qualifier de-asserted  
output data to clock setup  
output data after clock hold  
-
20  
8
-
-
-
-
-
rising A16HS edge  
falling A16HS edge  
rising A16HS edge  
rising A16HS edge  
2
1
TCLK periods 1)  
TCLK periods  
TCLK periods  
1
tASCS6  
tASCS7  
Note 1:  
input data to clock setup  
input data after clock hold  
rising A16HS edge  
rising A16HS edge  
2
2
-
-
The timing of the interface is programmable and is dependable on the tASCS0 clock period.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
36  
GR712RC-DS  
2.4.18 CCSDS / ECSS Telecommand Decoder  
The timing waveforms and timing parameters are shown in figure 22 and are defined in table 29.  
TCCLK[4:0]  
tGRTC0  
TCACT[4:0]  
TCD[4:0]  
tGRTC1  
tGRTC2  
TCRFAVL[4:0]  
tGRTC3  
tGRTC4  
Figure 22. Timing waveforms  
Table 29. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
tGRTC0  
bit period  
rising TCCLK edge  
7
-
TCLK periods  
tGRTC1  
tGRTC2  
tGRTC3  
tGRTC4  
Note 1:  
data/active input to clock hold  
data/active input to clock setup  
RF available input to clock hold  
RF available input to clock setup  
rising TCCLK edge  
rising TCCLK edge  
rising INCLK edge  
rising INCLK edge  
3
3
-
-
-
-
-
TCLK periods  
TCLK periods  
ns 1)  
ns 1)  
-
The TCRFAVL[4:0] inputs are re-synchronized to the internal system clock with a TCLK period.  
2.4.19 CCSDS / ECSS Telemetry Encoder  
The timing waveforms and timing parameters are shown in figure 23 and are defined in table 30.  
TMCLKO  
TMDO  
tGRTM0  
tGRTM0  
TCACT[4:0], TCRFAVL[4:0]  
tGRTM1  
tGRTM2  
Figure 23. Timing waveforms  
Table 30. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)  
Name  
Parameter  
Reference edge  
Min  
Max  
Unit  
ns 1)  
ns 2)  
-15 3)  
-
15 3)  
-
tGRTM0  
clock to output delay  
any TMCLKO edge  
tGRTM1  
tGRTM2  
tGRTM3  
tGRTM4  
Note 1:  
input to clock hold  
input to clock setup  
input to output delay  
TMCLKI clock period  
rising INCLK edge  
rising INCLK edge  
TMCLKI to TMCLKO  
-
ns 2)  
ns  
-
-
0 3)  
23 3)  
20 3)  
ns  
The TMDO signal is output simultaneously with the programmable TMCLKO clock edge. The oppo-  
site clock edge should be used for sampling TMDO.  
Note 2:  
Note 3:  
The TCACT[4:0] and TCRFAVL[4:0] inputs are re-synchronized to the TCLK period.  
Parameter not measured during production test.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
37  
GR712RC-DS  
3
Mechanical description  
3.1  
Package  
Ceramic hermetically sealed CQFP-240L package with 0.5 mm lead pitch, with gold plated leads.  
See drawing in section 3.3.  
All devices are marked on top lid with GR712RC. For space class marking see the product specifica-  
tion [PS].  
Lead trimming and forming are performed by customer prior to assembly on printed circuit board.  
3.2  
Pin assignment  
The pin assignment in table 31 shows the implementation characteristics of each signal, indicating  
how each pin has been configured in terms of maximum load, polarity and reset value.  
Table 31. Pin assignment  
Pin no.  
Pin name  
SWMX[3]  
SWMX[2]  
SWMX[1]  
SWMX[0]  
CB[6]  
Dir.  
In  
Max load [pF]  
Polarity Reset value  
Note  
1
2
3
4
5
6
7
-
I/O Switch Matrix 3  
I/O Switch Matrix 2  
I/O Switch Matrix 1  
I/O Switch Matrix 0  
Check Bit 6  
Out  
In  
50  
-
-
-
-
High  
Out  
In/Out  
50  
50  
High  
High-Z  
VDDIO  
I/O Supply Voltage  
I/O Supply Ground  
GNDIO 2)  
CB[5]  
8
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
50  
50  
50  
50  
50  
-
-
-
-
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Check Bit 5  
9
CB[4]  
Check Bit 4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
CB[3]  
Check Bit 3  
CB[2]  
Check Bit 2  
CB[1]  
Check Bit 1  
VDD  
Core Supply Voltage  
Core Supply Ground  
Check Bit 0  
GND  
CB[0]  
In/Out  
In/Out  
In/Out  
50  
50  
50  
-
-
-
High-Z  
High-Z  
High-Z  
DATA[31]  
DATA[30]  
VDDIO  
GNDIO  
DATA[29]  
DATA[28]  
DATA[27]  
DATA[26]  
DATA[25]  
DATA[24]  
DATA[23]  
DATA[22]  
VDDIO  
GNDIO  
VDD  
Data Bit 31  
Data Bit 30  
I/O Supply Voltage  
I/O Supply Ground  
Data Bit 29  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
50  
50  
50  
50  
50  
50  
50  
50  
-
-
-
-
-
-
-
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Data Bit 28  
Data Bit 27  
Data Bit 26  
Data Bit 25  
Data Bit 24  
Data Bit 23  
Data Bit 22  
I/O Supply Voltage  
I/O Supply Ground  
Core Supply Voltage  
Core Supply Ground  
GND  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
38  
GR712RC-DS  
Table 31. Pin assignment  
Pin no.  
32  
Pin name  
DATA[21]  
Dir.  
Max load [pF]  
Polarity Reset value  
Note  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
50  
50  
50  
50  
50  
50  
-
-
-
-
-
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Data Bit 21  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
DATA[20]  
DATA[19]  
DATA[18]  
DATA[17]  
DATA[16]  
VDDIO  
Data Bit 20  
Data Bit 19  
Data Bit 18  
Data Bit 17  
Data Bit 16  
I/O Supply Voltage  
I/O Supply Ground  
Data Bit 15  
GNDIO  
DATA[15]  
DATA[14]  
DATA[13]  
DATA[12]  
DATA[11]  
DATA[10]  
DATA[9]  
VDD  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
50  
50  
50  
50  
50  
50  
50  
-
-
-
-
-
-
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Data Bit 14  
Data Bit 13  
Data Bit 12  
Data Bit 11  
Data Bit 10  
Data Bit 9  
Core Supply Voltage  
Core Supply Ground  
Data Bit 8  
GND  
DATA[8]  
VDDIO  
In/Out  
50  
-
High-Z  
I/O Supply Voltage  
I/O Supply Ground  
Data Bit 7  
GNDIO  
DATA[7]  
DATA[6]  
DATA[5]  
DATA[4]  
DATA[3]  
DATA[2]  
DATA[1]  
DATA[0]  
VDDIO  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
In/Out  
50  
50  
50  
50  
50  
50  
50  
50  
-
-
-
-
-
-
-
-
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Data Bit 6  
Data Bit 5  
Data Bit 4  
Data Bit 3  
Data Bit 2  
Data Bit 1  
Data Bit 0  
I/O Supply Voltage  
I/O Supply Ground  
Address Bit 0  
Address Bit 1  
Address Bit 2  
Address Bit 3  
Core Supply Voltage  
Core Supply Ground  
Address Bit 4  
I/O Supply Voltage  
I/O Supply Ground  
Address Bit 5  
Address Bit 6  
Address Bit 7  
Address Bit 8  
I/O Supply Voltage  
I/O Supply Ground  
Address Bit 9  
Core Supply Voltage  
GNDIO  
ADDRESS[0]  
ADDRESS[1]  
ADDRESS[2]  
ADDRESS[3]  
VDD  
Out  
Out  
Out  
Out  
50  
-
-
-
-
Low  
Low  
Low  
Low  
50  
100  
100  
GND  
ADDRESS[4]  
VDDIO  
Out  
100  
-
Low  
GNDIO  
ADDRESS[5]  
ADDRESS[6]  
ADDRESS[7]  
ADDRESS[8]  
VDDIO  
Out  
Out  
Out  
Out  
100  
100  
100  
100  
-
-
-
-
Low  
Low  
Low  
Low  
GNDIO  
ADDRESS[9]  
VDD  
Out  
100  
-
Low  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
39  
GR712RC-DS  
Table 31. Pin assignment  
Pin no.  
79  
Pin name  
GND  
Dir.  
Max load [pF]  
Polarity Reset value  
Note  
Core Supply Ground  
Address Bit 10  
80  
ADDRESS[10]  
ADDRESS[11]  
ADDRESS[12]  
VDDIO  
Out  
Out  
Out  
100  
100  
100  
-
-
-
Low  
Low  
Low  
81  
Address Bit 11  
82  
Address Bit 12  
83  
I/O Supply Voltage  
I/O Supply Ground  
Address Bit 23  
84  
GNDIO  
85  
ADDRESS[23]  
ADDRESS[13]  
ADDRESS[22]  
ADDRESS[21]  
ADDRESS[14]  
VDD  
Out  
Out  
Out  
Out  
Out  
50  
-
-
-
-
-
Low  
Low  
Low  
Low  
Low  
86  
100  
50  
Address Bit 13  
87  
Address Bit 22  
88  
50  
Address Bit 21  
89  
100  
Address Bit 14  
90  
Core Supply Voltage  
Core Supply Ground  
Address Bit 20  
91  
GND  
92  
ADDRESS[20]  
VDDIO  
Out  
50  
-
Low  
93  
I/O Supply Voltage  
I/O Supply Ground  
Address Bit 19  
94  
GNDIO  
95  
ADDRESS[19]  
ADDRESS[15]  
ADDRESS[18]  
ADDRESS[16]  
ADDRESS[17]  
SCANEN  
ROMSN[0]  
VDD  
Out  
Out  
Out  
Out  
Out  
In  
50  
-
Low  
Low  
Low  
Low  
Low  
96  
100  
50  
-
Address Bit 15  
97  
-
Address Bit 18  
98  
100  
50  
-
Address Bit 16  
99  
-
Address Bit 17  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
High  
Low  
Scan enable (tie to ground)  
PROM Select 0  
Out  
50  
High  
Core Supply Voltage  
Core Supply Ground  
I/O Supply Voltage  
I/O Supply Ground  
PROM Select 1  
GND  
VDDIO  
GNDIO  
ROMSN[1]  
WRITEN  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
In  
50  
50  
50  
50  
50  
50  
50  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
High  
High  
High  
High  
High  
High  
High  
Write Strobe for PROM, I/O  
I/O Select  
IOSN  
RAMSN[0]  
RAMSN[1]  
RAMOEN  
RAMWEN  
BRDYN  
SRAM Select 0  
SRAM Select 1  
SRAM Output Enable  
SRAM Write Enable  
Bus Ready  
VDD  
Core Supply Voltage  
Core Supply Ground  
I/O Supply Voltage  
I/O Supply Ground  
Bus Exception  
GND  
VDDIO  
GNDIO  
BEXCN  
In  
Low  
Low  
WDOGN  
Out  
50  
50  
High-Z  
High  
Watchdog Indicator (output is driven active low, else it  
is in tri-state and therefore requires external pull-up)  
120  
121  
122  
123  
124  
READ  
TDI  
Out  
In  
High  
SRAM, PROM, I/O read indicator  
Jtag Test Data In  
-
TCK  
TMS  
TDO  
In  
-
Jtag Test Clock  
In  
High  
-
Jtag Test Mode Select  
Jtag Test Data Out  
Out  
50  
Low  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
40  
GR712RC-DS  
Table 31. Pin assignment  
Pin no.  
125  
Pin name  
TESTEN  
Dir.  
Max load [pF]  
Polarity Reset value  
Note  
In  
High  
Test Enable (tie to ground)  
Output Enable for PROM, I/O  
I/O Switch Matrix 66  
I/O Switch Matrix 65  
I/O Switch Matrix 64  
I/O Supply Voltage  
I/O Supply Ground  
I/O Switch Matrix 63  
Core Supply Voltage  
Core Supply Ground  
I/O Switch Matrix 62  
I/O Switch Matrix 61  
I/O Switch Matrix 60  
I/O Supply Voltage  
I/O Supply Ground  
I/O Switch Matrix 59  
Check Bit 7  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
OEN  
Out  
Low  
High  
SWMX[66]  
SWMX[65]  
SWMX[64]  
VDDIO  
In/Out  
In/Out  
In/Out  
50  
50  
50  
-
-
-
High-Z  
High-Z  
High-Z  
GNDIO  
SWMX[63]  
VDD  
In/Out  
50  
-
High-Z  
GND  
SWMX[62]  
SWMX[61]  
SWMX[60]  
VDDIO  
In/Out  
In/Out  
In/Out  
50  
50  
50  
-
-
-
High-Z  
High-Z  
High-Z  
GNDIO  
SWMX[59]  
CB[7]  
In/Out  
In/Out  
In/Out  
In/Out  
In  
50  
50  
50  
50  
-
High-Z  
High-Z  
High-Z  
High-Z  
-
SWMX[58]  
SWMX[57]  
SWMX[56]  
RESETN  
ERRORN  
-
I/O Switch Matrix 58  
I/O Switch Matrix 57  
I/O Switch Matrix 56  
System Reset  
-
-
In  
Low  
Low  
Out  
50  
High-Z  
Processor Error Mode (output is driven active low, else  
it is in tri-state and therefore requires external pull-up)  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
DLLBPN  
INCLK  
In  
In  
Low  
-
DLL Bypass  
Input Clock  
VDDIO  
I/O Supply Voltage  
Core Supply Voltage  
Core Supply Ground  
I/O Supply Ground  
I/O Switch Matrix 55  
I/O Switch Matrix 54  
I/O Switch Matrix 53  
SDRAM Clock  
VDD  
GND  
GNDIO  
SWMX[55]  
SWMX[54]  
SWMX[53]  
SDCLK  
In  
-
-
-
-
-
In/Out  
In/Out  
Out  
100  
100  
100  
100  
High-Z  
High-Z  
-
SWMX[52]  
VDDIO  
In/Out  
High-Z  
I/O Switch Matrix 52  
I/O Supply Voltage  
I/O Supply Ground  
I/O Switch Matrix 51  
I/O Switch Matrix 50  
I/O Switch Matrix 49  
I/O Switch Matrix 48  
I/O Switch Matrix 47  
I/O Switch Matrix 46  
GNDIO  
SWMX[51]  
SWMX[50]  
SWMX[49]  
SWMX[48]  
SWMX[47]  
SWMX[46]  
SWMX[45]  
In  
-
-
-
-
-
-
-
In  
In/Out  
In/Out  
In  
100  
100  
High-Z  
High-Z  
In  
I/O Switch Matrix 45 1)  
Core Supply Voltage  
Core Supply Ground  
I/O Switch Matrix 44  
I/O Supply Voltage  
In/Out  
50  
50  
High-Z  
High-Z  
167  
168  
169  
170  
VDD  
GND  
SWMX[44]  
VDDIO  
In/Out  
-
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
41  
GR712RC-DS  
Table 31. Pin assignment  
Pin no.  
171  
Pin name  
GNDIO  
Dir.  
Max load [pF]  
Polarity Reset value  
Note  
I/O Supply Ground  
I/O Switch Matrix 43 1)  
I/O Switch Matrix 42  
I/O Switch Matrix 41  
172  
SWMX[43]  
In/Out  
50  
-
High-Z  
173  
174  
175  
SWMX[42]  
SWMX[41]  
SWMX[40]  
In  
-
-
-
In/Out  
In/Out  
50  
50  
High-Z  
High-Z  
I/O Switch Matrix 40 1)  
I/O Switch Matrix 39  
I/O Switch Matrix 38  
176  
177  
178  
SWMX[39]  
SWMX[38]  
SWMX[37]  
In  
-
-
-
In  
I/O Switch Matrix 37 1)  
I/O Switch Matrix 36  
I/O Supply Voltage  
In/Out  
50  
50  
High-Z  
High-Z  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
SWMX[36]  
VDDIO  
In/Out  
-
GNDIO  
I/O Supply Ground  
SWMX[35]  
SWMX[34]  
SWMX[33]  
SWMX[32]  
VDD  
In  
-
-
-
-
I/O Switch Matrix 35  
I/O Switch Matrix 34  
I/O Switch Matrix 33  
I/O Switch Matrix 32  
Core Supply Voltage  
Core Supply Ground  
I/O Switch Matrix 31  
I/O Switch Matrix 30  
I/O Switch Matrix 29  
I/O Switch Matrix 28  
I/O Switch Matrix 27  
I/O Switch Matrix 26  
I/O Supply Voltage  
In  
In/Out  
In/Out  
50  
50  
High-Z  
High-Z  
GND  
SWMX[31]  
SWMX[30]  
SWMX[29]  
SWMX[28]  
SWMX[27]  
SWMX[26]  
VDDIO  
In  
-
-
-
-
-
-
In  
In/Out  
In/Out  
In  
50  
50  
High-Z  
High-Z  
In  
GNDIO  
I/O Supply Ground  
SWMX[25]  
SWMX[24]  
VDD  
In/Out  
In/Out  
100  
100  
-
-
High-Z  
High-Z  
I/O Switch Matrix 25  
I/O Switch Matrix 24  
Core Supply Voltage  
Core Supply Ground  
I/O Switch Matrix 23  
I/O Switch Matrix 22  
I/O Switch Matrix 21  
I/O Switch Matrix 20  
SpaceWire Receive Data 1  
SpaceWire Receive Strobe 1  
SpaceWire Transmit Data 1  
I/O Supply Voltage  
GND  
SWMX[23]  
SWMX[22]  
SWMX[21]  
SWMX[20]  
SPW_RXD[1]  
SPW_RXS[1]  
SPW_TXD[1]  
VDDIO  
In  
-
-
-
-
-
-
-
In  
In/Out  
In/Out  
100  
100  
High-Z  
High-Z  
Out  
Out  
100  
100  
Low  
Low  
GNDIO  
I/O Supply Ground  
SPW_TXS[1]  
VDD  
-
SpaceWire Transmit Strobe 1  
Core Supply Voltage  
Core Supply Ground  
GND  
SPWCLK  
SPW_RXD[0]  
SPW_RXS[0]  
SPW_TXD[0]  
SPW_TXS[0]  
SWMX[19]  
In  
-
-
-
-
-
-
SpaceWire Receiver and Transmitter Clock  
SpaceWire Receive Data 0  
In  
In  
SpaceWire Receive Strobe 0  
SpaceWire Transmit Data 0  
SpaceWire Transmit Strobe 0  
I/O Switch Matrix 19  
Out  
Out  
In  
100  
100  
50  
Low  
Low  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
42  
GR712RC-DS  
Table 31. Pin assignment  
Pin no.  
218  
Pin name  
SWMX[18]  
Dir.  
Max load [pF]  
Polarity Reset value  
Note  
In  
-
I/O Switch Matrix 18  
I/O Switch Matrix 17  
I/O Switch Matrix 16  
I/O Supply Voltage  
Core Supply Voltage  
Core Supply Ground  
I/O Supply Ground  
I/O Switch Matrix 15  
I/O Switch Matrix 14  
I/O Switch Matrix 13  
I/O Switch Matrix 12  
I/O Switch Matrix 11  
I/O Switch Matrix 10  
I/O Switch Matrix 09  
I/O Switch Matrix 08  
I/O Switch Matrix 07  
Core Supply Voltage  
Core Supply Ground  
I/O Supply Voltage  
I/O Supply Ground  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
SWMX[17]  
SWMX[16]  
VDDIO  
In/Out  
In/Out  
100  
100  
-
-
High-Z  
High-Z  
VDD  
GND  
GNDIO  
SWMX[15]  
SWMX[14]  
SWMX[13]  
SWMX[12]  
SWMX[11]  
SWMX[10]  
SWMX[9]  
SWMX[8]  
SWMX[7]  
VDD  
In  
-
-
-
-
-
-
-
-
-
In  
In/Out  
In/Out  
In  
100  
100  
High-Z  
High-Z  
In/Out  
In  
50  
50  
High-Z  
High-Z  
In/Out  
In  
GND  
VDDIO  
GNDIO  
I/O Switch Matrix 06 1)  
I/O Switch Matrix 05  
SWMX[6]  
In/Out  
50  
50  
-
High-Z  
High-Z  
239  
240  
SWMX[5]  
SWMX[4]  
In  
-
-
I/O Switch Matrix 04 1)  
In/Out  
Note 1:  
Note 2:  
See tables 3 and 5 for detailed description of behavior at reset.  
GNDIO is connected internally to GND.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
43  
GR712RC-DS  
3.3  
Mechanical package drawings  
GND  
GND  
V
V
DD  
DD  
GND  
GND  
V
V
DDIO  
DDIO  
Figure 24. Top view  
Table 32. Dimensions  
Millimeters  
Min.  
---  
Max.  
3.50  
A
Total height  
A1  
Body height  
---  
2.75  
A2  
0.10  
0.15  
0.10  
74.80  
55.44  
31.75  
0.40  
b
Lead width  
Lead height  
0.25  
c
0.20  
D/E  
D1/E1  
D2/E2  
D3/E3  
D4/E4  
e
75.40  
56.56  
32.25  
29.50 BSC  
21.00 TYP  
0.50 BSC  
16.50 TYP  
Lead pitch  
L1  
Note 1: The seal ring is electrically connected to GND.  
Note 2: Package weight is 16 1 grams, including the lead-frame.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
44  
GR712RC-DS  
Figure 25. Capacitor pads on top of package (mm)  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
45  
GR712RC-DS  
4
Reference documents  
[UM]  
GR712RC Dual-Core LEON3-FT SPARC V8 Processor - User's Manual, Aeroflex  
Gaisler, www.aeroflex.com/gaisler  
[PS]  
Product Specification GR712RC, GR712RC-PS, Aeroflex Gaisler  
[SPARC]  
The SPARC Architecture Manual, Version 8, Revision SAV080SI9308, SPARC  
International Inc.  
[SPW]  
ECSS - Space Engineering, SpaceWire - Links, Nodes, Routers and Networks,  
ECSS-E-ST-50-12C, 31 July 2008  
[RMAPID] ECSS - Space Engineering, SpaceWire Protocol Identification, ECSS-E-ST-50-51C,  
February 2010  
[RMAP]  
ECSS - Space Engineering, Remote Memory Access Protocol, ECSS-E-ST-50-52C,  
February 2010  
[1553BRM] Core1553BRM Product Handbook, 50200040-0/11-04, November 2004, Actel Corpo-  
ration  
Core1553BRM MIL-STD-1553 BC, RT, and MT, 51700052-4/12.05, v 5.0,  
December 2005, Actel Corporation  
Core1553BRM User's Guide, 50200023-0/06.04, June 2004, Actel Corporation  
Core1553BRM v2.16 Release Notes, 51300019-8/6.06, June 2006, Actel Corporation  
[MIL883]  
Test Method Standard, Microcircuits, revision H, 26 February 2010, MIL-STD-883H  
[MIL38535] Integrated Circuits (Microcircuits) Manufacturing, General Specification For, revision  
J, 28 December 2010, MIL-PRF-38535J  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
46  
GR712RC-DS  
5
Screening, qualification, and quality control  
GR712RC is provided as a high reliability product for space, for which space level screening and  
qualifications tests are performed in accordance to the product specification [PS].  
A Certificate of Compliance is delivered with space grade parts.  
A procurement specification is provided for space grade parts.  
GR712RC is also provided in prototype grade in military or commercial temperature range.  
6
Ordering information  
Ordering information is provided in table 33 and a legend is provided in table 34.  
Table 33. Ordering information, available models  
Product  
Description  
GR712RC-MS-CG240  
GR712RC-MP-CG240  
GR712RC-CP-CG240  
Flight model  
Electrical qualification model  
Engineering model (prototype)  
Table 34. Ordering legend  
Designator  
Option  
Description  
Product  
GR712RC  
Dual-core LEON3-FT SPARC V8 Processor  
-55˚C to +125˚C (Military range)  
-40˚C to +85˚C (Industrial range)  
0˚C to +70˚C (Commercial range)  
Space grade  
Temperature Range  
M
I
C
Screening Level  
S
P
Prototype grade  
Package Type  
Lead Finish  
Lead Count  
C
Ceramic Quad Flat Pack (CQFP)  
Gold  
G
240  
Number of leads  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
47  
GR712RC-DS  
7
Change record  
Change record information is provided in table 35.  
Table 35. Change record  
Issue  
2.0  
Date  
Sections  
Note  
2013 February 1.2  
Key features updated  
1.4  
2.1  
2.2  
2.3  
2.4  
Signal descriptions clarified  
Absolute maximum ratings updated  
Recommended operating conditions updated  
DC parameters updated  
AC parameter test conditions clarified  
2.4.1, 2.4.3, 2.4.4, 2.4.5, 2.4.6, Updated timing  
2.4.7, 2.4.8, 2.4.9, 2.4.10,  
2.4.11, 2.4.13, 2.4.15, 2.4.19  
1.5, 2.4.12  
Obsolete proprietary function removed  
Package marking clarified  
3.1  
3.2  
3.3  
4
GNDIO connection to GND clarified  
Weight information added  
Reference to product specification added  
1.5  
2012 May  
1.5  
The following conflicts added to table:  
CCSDS TC 0 vs. Proprietary  
CCSDS TC 0 vs. ASCS  
CCSDS TC 1 vs. Proprietary  
CCSDS TC 1 vs. Ethernet  
CCSDS TC 2 vs. Ethernet  
Proprietary vs. SpaceWire 2  
1.4  
1.3  
2012 January 2.4.5  
TCK edges in JTAG waveform & timing parameters corrected  
2011 March  
1.2, 2  
4, 5  
Timing parameters redefined  
Qualification level specified  
Table 6  
Conflict between SLINK and CCSDS TC 3 clarified  
1.2  
1.1  
2011 August  
2.3  
Added detailed core power consumption  
2011 February Tables 3 and 5  
Tables 3, 4 and 19, figure 19  
Table 31  
SDDQM signals marked as active high  
GPIO1/GPIO2 names changed to GPIO  
Reference added regarding behavior at reset  
1.0  
2011 February All  
New document layout  
All pin descriptions, reset values etc. updated  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  
AEROFLEX GAISLER  
48  
GR712RC-DS  
Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable.  
However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements of patents  
or other rights of third parties which may result from its use.  
No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB.  
Aeroflex Gaisler AB  
Kungsgatan 12  
411 19 Göteborg  
Sweden  
tel +46 31 7758650  
fax +46 31 421407  
sales@gaisler.com  
www.aeroflex.com/gaisler  
GAISLER  
Copyright © 2013 Aeroflex Gaisler AB.  
All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither  
implicit nor explicit.  
Copyright Aeroflex Gaisler AB  
February 2013, Issue 2.0  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明