FW802BF-09-DB [AGERE]
Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device; 低功耗PHY 1394A -2000双电缆收发器/仲裁器设备
| 型号： | FW802BF-09-DB |
| 厂家： | 
AGERE SYSTEMS |
| 描述： | Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| 文件： | 总26页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
January 2005
™
™
FW802BF Low-Power PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Supports PHY pinging and remote PHY access
packets.
Distinguishing Features
Compliant with IEEE® Standard 1394a-2000,
IEEE Standard for a High Performance Serial
Bus Amendment 1.
Fully supports suspend/resume.
Supports PHY-link interface initialization and reset.
Supports 1394a-2000 register set.
Low power consumption during powerdown or
microlow-power sleep mode.
Supports LPS/link-on as a part of PHY-link inter-
face.
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
Supports provisions of IEEE 1394-1995 Standard
for a High Performance Serial Bus.
Fully interoperable with FireWire® and i.LINK
While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port.
®
implementations of IEEE 1394-1995.
Reports cable power fail interrupt when voltage at
CPS ball falls below 7.5 V.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Provides separate cable bias and driver termination
voltage supply for each port.
Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies.
Other Features
Interoperable with 1394 link-layer controllers using
5 V supplies.
48-ball VTFSBGAC package.
Single 3.3 V supply operation.
1394a-2000 compliant common mode noise filter
on incoming TPBIAS.
Powerdown features to conserve energy in battery-
powered applications include the following:
— Device powerdown ball.
— Link interface disable using LPS.
— Inactive ports power down.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide a 50 MHz
link-layer controller clock as well as transmit/receive
data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
— Automatic microlow-power sleep mode during
suspend.
Multiple separate package signals provided for ana-
log and digital supplies and grounds.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
Description
Features
The Agere Systems FW802BF device provides the
analog physical layer functions needed to imple-
ment a two-port node in a cable-based IEEE 1394-
1995 and IEEE 1394a-2000 network.
Provides two fully compliant cable ports at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Fully supports 1394 Open HCI requirements.
Each cable port incorporates two differential line
transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determin-
ing connection status, for initialization and
arbitration, and for packet reception and transmis-
sion. The PHY is designed to interface with a link-
layer controller (LLC).
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by con-
catenation.
Supports connection debounce.
Supports multispeed packet concatenation.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Table of Contents
Contents
Page
Distinguishing Features ............................................................................................................................................1
Features ...................................................................................................................................................................1
Other Features .........................................................................................................................................................1
Description ................................................................................................................................................................1
Ball Information ........................................................................................................................................................ 6
Signal Information .....................................................................................................................................................7
Application Information ...........................................................................................................................................11
Crystal Selection Considerations ............................................................................................................................12
Load Capacitance ............................................................................................................................................13
Adjustment to Crystal Loading .........................................................................................................................13
Crystal/Board Layout .......................................................................................................................................13
Absolute Maximum Ratings ....................................................................................................................................14
Electrical Characteristics ........................................................................................................................................15
Timing Characteristics ............................................................................................................................................18
Timing Waveforms ..................................................................................................................................................19
Internal Register Configuration ...............................................................................................................................20
Outline Diagrams ....................................................................................................................................................25
48-Ball TFSBGAC ............................................................................................................................................25
Ordering Information ...............................................................................................................................................25
List of Figures
Figures
Page
Figure 1. Block Diagram........................................................................................................................................... 5
Figure 2. FW802BF Ball Diagram (48-Ball TFSBGAC) Top View............................................................................ 6
Figure 3. Typical External Component Connections .............................................................................................. 11
Figure 4. Typical Port Termination Network .......................................................................................................... 12
Figure 5. Crystal Circuitry....................................................................................................................................... 13
Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ............................................................. 19
Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms....................................................................... 19
List of Tables
Tables
Page
Table 1. FW802BF (48-Ball TFSBGAC) Ball Coordination Table ............................................................................6
Table 2. Signal Descriptions..................................................................................................................................... 7
Table 3. Absolute Maximum Ratings ......................................................................................................................14
Table 4. Analog Characteristics ..............................................................................................................................15
Table 5. Driver Characteristics ...............................................................................................................................16
Table 6. Device Characteristics ..............................................................................................................................17
Table 7. Switching Characteristics .........................................................................................................................18
Table 8. Clock Characteristics ...............................................................................................................................18
Table 9. PHY Register Map for the Cable Environment ........................................................................................20
Table 10. PHY Register Fields for the Cable Environment ....................................................................................20
Table 11. PHY Register Page 0: Port Status Page ............................................................................................... 22
Table 12. . PHY Register Port Status Page Fields ................................................................................................23
Table 13. PHY Register Page 1: Vendor Identification Page ...............................................................................24
Table 14. PHY Register Vendor Identification Page Fields ...................................................................................24
2
Agere Systems Inc.
Data Sheet
January 2005
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
tion to set the speed of the next packet transmission.
In addition, the TPB channel monitors the incoming
cable common-mode voltage for the presence of the
remotely supplied twisted-pair bias voltage. This moni-
tor is called bias-detect.
Description (continued)
The PHY requires either an external 24.576 MHz crys-
tal or crystal oscillator. The internal oscillator drives an
internal phase-locked loop (PLL) that generates the
required 393.216 MHz reference signal. The 393.216
MHz reference signal is internally divided to provide
the 49.152 MHz, 98.304 MHz, and 196.608 MHz clock
signals that control transmission of the outbound
encoded strobe and data information. The 49.152 MHz
clock signal is also supplied to the associated LLC for
synchronization of the two chips and is used for resyn-
chronization of the received data. The powerdown
function, when enabled by the PD signal high, stops
operation of the PLL and disables all circuitry except
the cable-not-active (CNA) signal circuitry.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
This monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS con-
nect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY provides a 1.86 V nominal bias voltage for
driver load termination. When seen through a cable by
a remote receiver, this bias voltage indicates the pres-
ence of an active connection. The value of this bias
voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33 µF.
The PHY supports an isolation barrier between itself
and its LLC. When ISON is tied high, the link interface
outputs behave normally. When ISON is tied low, inter-
nal differentiating logic is enabled, and the outputs
become short pulses that can be coupled through a
capacitor or transformer as described in the
IEEE 1394-1995 Annex J. To operate with bus-keeper
isolation, the ISON ball of the FW802BF must be tied
high.
The transmitter circuitry, the receiver circuitry, and the
twisted-pair bias voltage circuity are all disabled with a
powerdown condition. The powerdown condition
occurs when the PD input is high. The port transmitter
circuitry, the receiver circuitry, and the TPBIAS output
are also disabled when the port is disabled, sus-
pended, or disconnected.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in syn-
chronization with the 49.152 MHz system clock. These
bits are combined serially, encoded, and transmitted at
98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as
the outbound data-strobe information stream. During
transmission, the encoded data information is transmit-
ted differentially on the TPA and TPB cable pair(s).
The line drivers in the PHY operate in a high-imped-
ance current mode and are designed to work with
external 112 Ω line-termination resistor networks. One
network is provided at each end of each twisted-pair
cable. Each network is composed of a pair of series-
connected 56 Ω resistors. The midpoint of the pair of
resistors that is directly connected to the twisted-pair A
(TPA) signals is connected to the TPBIAS voltage sig-
nal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair B (TPB) signals is cou-
pled to ground through a parallel RC network with
recommended resistor and capacitor values of 5 kΩ
and 220 pF, respectively. The value of the external
resistors are specified to meet the IEEE 1394 stan-
dard specifications when connected in parallel with the
internal receiver circuits.
During packet reception, the TPA and TPB transmit-
ters of the receiving cable port are disabled and the
receivers for that port are enabled. The encoded data
information is received on the TPA and TPB cable
pair. The received data-strobe information is decoded
to recover the receive clock signal and the serial data
bits. The serial data bits are split into two (for S100),
four (for S200), or eight (for S400) parallel streams,
resynchronized to the local system clock, and sent to
the associated LLC. The received data is also trans-
mitted (repeated) out of the other active (connected)
cable ports.
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states dur-
ing initialization and arbitration. The outputs of these
comparators are used by the internal logic to deter-
mine the arbitration status. The TPA channel monitors
the incoming cable common-mode voltage. The value
of this common-mode voltage is used during arbitra-
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ ± 1%.
Agere Systems Inc.
3
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
without normal termination. When a port does not have
a cable connected, internal connect-detect circuitry will
keep the port in a disconnected state.
Description (continued)
The FW802BF supports suspend/resume as defined in
the IEEE 1394a-2000 specification. The suspend
mechanism allows an FW802BF port to be put into a
suspended state. In this state, a port is unable to
transmit or receive data packets, however, it remains
capable of detecting connection status changes and
detecting incoming TPBias. When all ports of the
FW802BF are suspended, all circuits except the bias
voltage reference generator, and bias detection cir-
cuits are powered down, resulting in significant power
savings. The use of suspend/resume is recommended.
Note: All gap counts on all nodes of a 1394 bus must
be identical. The software accomplishes this by
issuing PHY configuration packets (see Section
4.3.4.3 of the IEEE 1394a-2000 standard) or by
issuing two bus resets, which resets the gap
counts to the maximum level (3Fh).
The link power status (LPS) signal works with the
C_LKON signal to manage the LLC power usage of
the node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is inac-
tive for more than 1.2 ms and less than 25 ms, the
PHY/link interface is reset. If LPS is inactive for greater
than 25 ms, the PHY will disable the PHY/link inter-
face to save power. FW802BF continues its repeater
function even when the PHY/link interface is disabled.
If the PHY then receives a link-on packet, the C_LKON
signal is activated to output a 6.114 MHz signal that
can be used by the LLC to power itself up. Once the
LLC is powered up, the LPS signal communicates this
to the PHY and the PHY/link interface is enabled. The
C_LKON signal is turned off when LPS is active or
when a bus reset occurs, provided the interrupt that
caused C_LKON is not present.
As an input, the C_LKON signal indicates whether a
node is a contender for bus manager. When the
C_LKON signal is asserted, it means the node is a
contender for bus manager. When the signal is not
asserted, it means that the node is not a contender.
The C bit corresponds to bit 20 in the self-ID packet
(see Section 4.3.4.1 of the IEEE 1394a-2000 standard
for additional details).
The power-class (Pwr_class) bits of the self-ID packet
have a default value of 0, i.e., power-class 000. These
bits can be read and modified through the LLC using
Figure 5B-1 (PHY Register Map) and Section 4.3.4.1
of the IEEE 1394a-2000 standard. See Table 9 of this
document for the address space of the Pwr_class
register.
When the PHY/link interface is in the disabled state,
the FW802BF will automatically enter a low-power
mode if all ports are inactive (disconnected, disabled,
or suspended). In this low-power mode, the FW802BF
disables its PLL and also disables parts of its
A powerdown signal (PD) is provided to allow a power-
down mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. The internal logic in FW802BF is reset as
long as the powerdown signal is asserted. A cable sta-
tus signal (CNA) provides a high output when none of
the twisted-pair cable ports are receiving incoming
bias voltage. This output is not debounced. The CNA
output can be used to determine when to power the
PHY down or up. In the powerdown mode, all circuitry
is disabled except the CNA circuitry. It should be noted
that when the device is powered down, it does not act
in a repeater mode.
reference circuitry depending on the state of the ports
(some reference circuitry must remain active in order
to detect incoming TP bias). The lowest power
consumption (the microlow-power sleep mode) is
attained when all ports are either disconnected or
disabled with the ports interrupt enable bit (see Table
12) cleared. The FW802BF will exit the low-power
mode when the LPS input is asserted high or when a
port event occurs that requires the FW802BF to
become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias or
disconnection is detected on a suspended port, a new
connection is detected on a nondisabled port, etc.).
When the FW802BF is in the low-power mode, the
SYSCLK output will become active (and the PHY/link
interface will be initialized and become operative)
within 3 ms after LPS is asserted high.
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY trans-
mitter and receiver circuitry is designed to present a
high impedance to the cable in order to not load the
TPBIAS signal voltage on the other end of the cable.
Whenever the TBA±/TPB± signals are wired to a con-
nector, they must be terminated using the normal
termination network (See Figure 4.). This is required
for reliable operation. For those applications, when
one of the FW802BF’s ports is not wired to a connec-
tor, those unused ports may be left unconnected
Two of the FW802BF’s signals are used to set up
various test conditions used only during the device
manufacturing process. These signals (SE and SM)
should be connected to VSS for normal operation.
4
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Description (continued)
CPS
LPS
RECEIVED
DATA
DECODER/
RETIMER
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
R[0]
R[1]
ISON
CNA
SYSCLK
LREQ
CTL[0]
LINK
INTERFACE
I/O
CTL[1]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
TPA[0]
TPAN[0]
ARBITRATION
AND
TPBIAS[0]
CONTROL
STATE
MACHINE
LOGIC
CABLE PORT 0
TPB[0]
TPBN[0]
C_LKON
SE
SM
PD
TPA[1]
TPAN[1]
CABLE PORT 1
TPBIAS[1]
TPB[1]
TPBN[1]
TRANSMIT
DATA
ENCODER
RESETN
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
XI
XO
CLOCK
GENERATOR
5-5459.f (F) r.3
Figure 1. Block Diagram
Agere Systems Inc.
5
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Ball Information
A1 BALL PAD CORNER
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
1
2
3
4
5
6
7
8
Note: Refer to the outline drawing on page 25 for a bottom view.
5-8117
Figure 2. FW802BF Ball Diagram (48-Ball TFSBGAC) Top View
Table 1. FW802BF (48-Ball TFSBGAC) Ball Coordination Table
Ball
Number
Ball
Number
Ball
Number
Ball
Number
Ball Name
Ball Name
Ball Name
Ball Name
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
CTL[0]
LREQ
SYSCLK
XO
B5
B6
B7
B8
C1
C2
C7
C8
D1
D2
D7
D8
VDD
R[1]
E1
E2
E7
E8
F1
F2
F7
F8
G1
G2
G3
G4
D[5]
D[3]
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
VSS
VSS
VSSA
SE
VDDA
TPAN[0]
CNA
TPA[1]
D[1]
TPBN[1]
D[7]
XI
VSS
D[0]
D[4]
VDD
R[0]
VDDA
VSSA
TPA[0]
LPS
PD
TPBIAS[1]
CTL[1]
RESETN
VSSPLL
VDDPLL
TPAN[1]
D[2]
ISON
CPS
VDD
D[6]
SM
TPBIAS[0]
TPB[1]
VSS
TPB[0]
TPBN[0]
C_LKON
6
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Signal Information
Table 2. Signal Descriptions
Ball
Signal*
Number
Type
Name/Description
G4
C_LKON
I/O
Bus Manager Capable Input and Link-On Output. On hardware reset
(RESETN), this ball is used to set the default value of the contender status
indicated during self-ID. The bit value programming is done by tying the
signal through a 10 kΩ resistor to VDD (high, bus manager capable) or to
GND (low, not bus manager capable). Using either the pull-up or pull-
down resistor allows the link-on output to override the input value when
necessary.
After hardware reset, this ball is set as an output. If the LPS is inactive,
C_LKON indicates one of the following events by asserting a 6.114 MHz
signal.
1. FW802BF receives a link-on packet addressed to this node.
2. Port_event register bit is 1.
3. Any of the Timeout, Pwr_fail, or Loop register bits are 1 and the
Watchdog register bit is also 1.
4. Once activated, the C_LKON output will continue active until the LPS
becomes active. The PHY also deasserts the C_LKON output when a
1394 bus reset occurs, if the C_LKON is active due solely to the recep-
tion of a link-on packet.
Note: If an interrupt condition exists which would otherwise cause the
C_LKON output to be activated if the LPS were inactive, the
C_LKON output will be activated when the LPS subsequently
becomes inactive.
H1
H5
CNA
CPS
O
I
Cable-Not-Active Output. CNA is asserted high when none of the PHY
ports are receiving an incoming bias voltage. This circuit remains active
during the powerdown mode.
Cable Power Status. CPS is normally connected to the cable power
through a 400 kΩ resistor. This circuit drives an internal comparator that
detects the presence of cable power. This information is maintained in one
internal register and is available to the LLC by way of a register read (see
Table 9, address register 00002, bit 7/PS). In applications that do not sink
or source 1394 power (VP), this ball can be tied to ground.
Note: When this ball is grounded, the Pwr_fail bit in PHY register 01012 will
be set.
A1
B1
CTL[0]
I/O
I/O
Control I/O. The CTLn signals are bidirectional communications control
signals between the PHY and the LLC. These signals control the passage
of information between the two devices. Bus-keeper circuitry is built into
these terminals.
CTL[1]
D[0:7]
C1, C2, D1,
E1, E2, F1,
F2, G2
Data I/O. The Dn signals are bidirectional and pass data between the PHY
and the LLC. Bus-keeper circuitry is built into these terminals.
* Active-low signals are indicated by “N” at the end of signal names, within this document.
Agere Systems Inc.
7
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Signal Information (continued)
Table 2. Signal Descriptions (continued)
Ball
Number
Signal*
Type
Name/Description
H4
ISON
I
Link Interface Isolation Disable Input (Active-Low). ISON controls the
operation of an internal pulse differentiating function used on the
PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.
When ISON is asserted low, the isolation barrier is implemented between
PHY and its LLC (as described in Annex J of IEEE 1394-1995).
ISON is normally tied high to disable isolation differentiation. Bus-keepers
are enabled when ISON is high (inactive) on CTLn, Dn, and LREQ. When
ISON is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note, 1394 Isolation (AP05-014CMPR), for more information.
G1
LPS
I
Link Power Status. LPS is connected to either the VDD supplying the LLC
or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2 µs and less than 25 µs, the PHY-link interface is reset. If LPS is
inactive for greater than 25 µs, the PHY will disable the PHY/link interface
to save power. FW802BF continues its repeater function.
A2
H3
LREQ
PD
I
I
Link Request. LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
Powerdown. When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW802BF logic
is kept in the reset state as long as PD is asserted. The PD terminal is
provided for backward compatibility. It is recommended that the FW802BF
be allowed to manage its own power consumption using suspend/resume
in conjunction with LPS. C_LKON features are defined in the IEEE 1394a-
2000 specification.
B4
B3
A7
VDDPLL
VSSPLL
R[0]
—
—
I
Power for PLL Circuit. VDDPLL supplies power to the PLL circuitry
portion of the device.
Ground for PLL Circuit. VSSPLL is tied to a low-impedance ground
plane.
Current Setting Resistor. An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the
IEEE 1394-1995 standard requirements for output voltage limits.
B6
B2
R[1]
RESETN
I
Reset (Active-Low). When RESETN is asserted low (active), a 1394 bus
reset condition is set on the active cable ports and the FW802BF is reset
to the reset start state. To guarantee that the PHY will reset, this ball must
be held low for at least 2 ms. An internal pull-up resistor connected to VDD
is provided so that only an external delay capacitor (0.1 µF) and resistor
(510 kΩ) in parallel, are required to connect this ball to ground. This
circuitry will ensure that the capacitor will be discharged when PHY power
is removed. The input is a standard logic buffer and can also be driven by
an open-drain logic output buffer. Do not leave this ball unconnected.
E7
SE
I
Test Mode Control. SE is used during Agere’s manufacturing test and
should be tied to VSS for normal operation.
* Active-low signals are indicated by “N” at the end of signal names, within this document.
8
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Signal Information (continued)
Table 2. Signal Descriptions (continued)
Ball
Number
Signal*
Type
Name/Description
H6
SM
I
Test Mode Control. SM is used during Agere’s manufacturing test and
should be tied to VSS for normal operation.
A3
SYSCLK
O
System Clock. SYSCLK provides a 49.152 MHz clock signal, which is syn-
chronized with the data transfers to the LLC.
F8
TPA[0]
Analog I/O Port0, Port Cable Pair A. TPA0± is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential
signal balls should be kept as short as possible and matched to the external
load resistors and to the cable connector. When the FW802BF’s 1394 port
pins are not wired to a connector, the unused port pins may be left uncon-
nected. Internal connect-detect circuitry will keep the port in a disconnected
state.
G8
TPAN[0]
B8
C8
TPA[1]
Analog I/O Port1, Port Cable Pair A. TPA1± is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential
signal balls should be kept as short as possible and matched to the exter-
nal load resistors and to the cable connector. When the FW802BF’s 1394
port pins are not wired to a connector, the unused port pins may be left
unconnected. Internal connect-detect circuitry will keep the port in a discon-
nected state.
TPAN[1]
H7
H8
TPB[0]
Analog I/O Port0, Port Cable Pair B. TPB0± is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential
signal balls should be kept as short as possible and matched to the external
load resistors and to the cable connector. When the FW802BF’s 1394 port
pins are not wired to a connector, the unused port pins may be left uncon-
nected. Internal connect-detect circuitry will keep the port in a disconnected
state.
TPBN[0]
D8
E8
TPB[1]
Analog I/O Port1, Port Cable Pair B. TPB1± is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential
signal balls should be kept as short as possible and matched to the external
load resistors and to the cable connector. When the FW802BF’s 1394 port
pins are not wired to a connector, the unused port pins may be left uncon-
nected. Internal connect-detect circuitry will keep the port in a disconnected
state.
TPBN[1]
D7
A8
TPBIAS[0] Analog I/O Portn, Twisted-Pair Bias. (Where n refers to the port number) TPBIAS
provides the 1.86 V nominal bias voltage needed for proper operation of the
TPBIAS[1]
twisted-pair cable drivers and receivers and for sending a valid cable con-
nection signal to the remote nodes. When the FW802BF’s 1394 port pins are
not wired to a connector, the unused port pins may be left unconnected. Inter-
nal connect-detect circuitry will keep the port in a disconnected state.
B5, D2, H2
VDD
—
Digital Power. VDD supplies power to the digital portion of the device.
* Active-low signals are indicated by “N” at the end of signal names, within this document.
Agere Systems Inc.
9
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Signal Information (continued)
Table 2. Signal Descriptions (continued)
Ball
Number
Signal*
Type
Name/Description
C7, G7
VDDA
—
Analog Circuit Power. VDDA supplies power to the analog portion of the
device.
A6, G3, G5,
G6
VSS
VSSA
XI
—
—
—
Digital Ground. All VSS signals should be tied to the low-impedance
ground plane.
B7, F7
Analog Circuit Ground. All VSSA signals should be tied together to a low-
impedance ground plane.
A5
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant
fundamental mode crystal. Although, when a 24.576 MHz clock source is
used, it can be connected to XI with XO left unconnected. The optimum val-
ues for the external load capacitors and resistor are dependent on the
specifications of the crystal used. It is necessary to add an external series
resistor (RL) to the XO pin (see Figures 3 and 5). For more details, refer to
the Crystal Selection Considerations section in this data sheet. Note that it is
very important to place the crystal as close as possible to the XO and XI pins,
i.e., within 0.5 in./1.27 cm.
A4
XO
* Active-low signals are indicated by “N” at the end of signal names, within this document.
10
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Application Information
CL
CL
0.1 µF
510 k
Ω
RL
A1 BALL
PAD CORNER
CTL[0]
XO
R[0]
TPBIAS[1]
TPA[1]
SYSCL
XI
VSS
R[1]
LREQ
VSSPLL
VDD
VSSA
VDDA
CTL[1
D[1]
RESET
D[0]
VDDPLL
PORT 1*
PORT 0*
TPAN[1]
LLC
LLC
D[2]
TPBIAS[0] TPB[1]
VDD
D[3]
AGERE FW802BF
LLC
LLC
LLC
D[5]
SE
TPBN[1]
D[4]
D[6]
VDD
D[7]
VSS
TPA[0]
LCC PULSE
OR VDD
VSS
PD
TPAN[0]
TPBN[0]
VSS
CPS
VSS
SM
VDDA
TPB[0]
LPS
C_LKON
ISON
PORT 0*
CNA
* See Figure 4 for typical port termination network.
Figure 3. Typical External Component Connections
Agere Systems Inc.
11
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Application Information (continued)
TPBIAS[1]
A8
TPBIAS[1]
TPA[1]
B8
C8
D8
E8
D7
F8
TPAN[1]
TPB[1]
USE SAME PORT TERMINATION NETWORK AS ILLUSTRATED BELOW.
TPBN[1]
0.33 µF
TPBIAS[0]
56 Ω
TPA[0]
56 Ω
G8
H7
TPAN[0]
TPB[0]
5
6
IEEE 1394-1995 STANDARD
CONNECTOR
TPBN[0]
3
1
4
H8
56 Ω
56 Ω
5 kΩ
220 pF
2
VP
VG
CABLE
POWER
5-6930 (F)
Figure 4. Typical Port Termination Network
Crystal Selection Considerations
The FW802BF is designed to use an external 24.576 MHz parallel resonant fundamental mode crystal connected
between the XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394a-2000
standard requires that FW802BF have less than ±100 ppm total variation from the nominal data rate, which is
directly influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or
less frequency tolerance be used.
The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error intro-
duced by board and device variations. Trade offs between frequency tolerance and stability may be made as long
as the total frequency variation is less than ±100 ppm.
12
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Crystal Selection Considerations (continued)
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also
capacitances from the FW802BF board traces and capacitances of the other FW802BF connected components.
The values for load capacitors (CA and CB) should be calculated using this formula:
CA = CB = (CL – Cstray) × 2
CA
XI
RL
CB
XO
A
Where:
CL = load capacitance specified by the crystal manufacturer.
Cstray = capacitance of the board and the FW802BF, typically 2 pF—3 pF.
RL = load resistance; the value of RL is dependent on the specific crystal used. Please refer to your crystal manufacturer’s data sheet
and application notes to determine an appropriate value.
Figure 5. Crystal Circuitry
Adjustment to Crystal Loading
The resistor (RL) in Figure 5 is recommended for fine-tuning the crystal circuit. The value for this resistor is depen-
dent on the specific crystal used. Please refer to your crystal manufacturer’s data sheet and application notes to
determine an appropriate value for RL. A more precise value for this resistor can be obtained by placing different
values of RL on a production board and using an oscilloscope to view the resultant clock waveform at node A for
each resistor value. The desired waveform should have the following characteristics: the waveform should be sinu-
soidal, with an amplitude as large as possible, but not greater than 3.3 V or less than 0 volts.
Crystal/Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW802BF PLL. The crystal and two load capacitors (CA + CB) should be considered as a
unit during layout. They should be placed as close as possible to one another, while minimizing the loop area cre-
ated by the combination of the three components. Minimizing the loop area minimizes the effect of the resonant
current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as
close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the
XI and XO signals.
1394 Application Support Contact Information
E-mail: support1394@agere.com
Agere Systems Inc.
13
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Supply Voltage Range
Symbol
Min
Max
Unit
VDD
VI
3.0
–0.5
–0.5
0
3.6
VDD + 0.5
VDD + 0.5
70
V
V
Input Voltage Range*
Output Voltage Range at Any Output
Operating Free Air Temperature
Storage Temperature Range
VO
TA
V
°C
°C
Tstg
–65
150
* Except for 5 V tolerant I/O (CTL0, CTL1, D0—D7, and LREQ) where VI max = 5.5 V.
14
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Electrical Characteristics
Table 4. Analog Characteristics
Parameter
Test Conditions
Symbol
Min Typ Max Unit
Supply Voltage
Source power node
VDD—SP
VID—100
VID—200
VID—400
VID—ARB
VCM
3.0
142
3.3
—
—
—
—
—
3.6
260
V
Differential Input Voltage
Cable inputs, 100 Mbits/s operation
Cable inputs, 200 Mbits/s operation
Cable inputs, 400 Mbits/s operation
Cable inputs, during arbitration
mV
mV
mV
mV
V
132
260
100
260
168
265
Common-mode Voltage
Source Power Mode
TPB cable inputs,
speed signaling off
1.165
2.515
TPB cable inputs,
S100 speed signaling on
VCM—SP—100
VCM—SP—200
VCM—SP—400
VCM
1.165
0.935
0.532
1.165
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.515
2.515
2.515
2.015
2.015
2.015
2.015
1.08
V
V
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
V
Common-mode Voltage
Nonsource Power Mode*
TPB cable inputs,
speed signaling off
V
TPB cable inputs,
S100 speed signaling on
VCM—NSP—100 1.165
VCM—NSP—200 0.935
VCM—NSP—400 0.532
V
TPB cable inputs,
S200 speed signaling on
V
TPB cable inputs,
S400 speed signaling on
V
Receive Input Jitter
Receive Input Skew
TPA, TPB cable inputs,
100 Mbits/s operation
—
—
—
—
—
—
—
—
89
ns
ns
TPA, TPB cable inputs,
200 Mbits/s operation
0.5
TPA, TPB cable inputs,
400 Mbits/s operation
—
0.315 ns
Between TPA and TPB cable inputs,
100 Mbits/s operation
—
0.8
0.55
0.5
ns
ns
Between TPA and TPB cable inputs,
200 Mbits/s operation
—
Between TPA and TPB cable inputs,
400 Mbits/s operation
—
ns
Positive Arbitration
Comparator Input
Threshold Voltage
—
VTH+
168
mV
Negative Arbitration
Comparator Input
Threshold Voltage
—
VTH−
–168
—
–89
mV
Speed Signal Input
Threshold Voltage
200 Mbits/s
400 Mbits/s
VTH—S200
VTH—S400
IO
45
266
–5
—
—
—
—
—
139
445
2.5
mV
mV
mA
V
Output Current
TPBIAS outputs
At rated I/O current
—
TPBIAS Output Voltage
VO
1.665
—
2.015
76
Current Source for
ICD
µA
Connect Detect Circuit
* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).
Agere Systems Inc.
15
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Electrical Characteristics (continued)
Table 5. Driver Characteristics
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Differential Output Voltage
56 Ω load
VOD
VOFF
IDIFF
172
—
—
—
—
265
20
mV
mV
mA
Off-state Common-mode Voltage
Drivers disabled
Driver Differential Current,
TPA, TPAN, TPB, TPBN
Driver enabled,
speed signaling off*
−1.05
1.05
Common-mode Speed Signaling
Current, TPB, TPBN
200 Mbits/s speed
signaling enabled
ISP
ISP
−2.53
−8.1
—
—
−4.84
−12.4
mA
mA
†
400 Mbits/s speed
†
signaling enabled
* Limits are defined as the algebraic sum of TPA and TPAN driver currents. Limits also apply to TPB and TPBN as the algebraic sum of driver
currents.
† Limits are defined as the absolute limit of each of TPB and TPBN driver currents.
16
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Electrical Characteristics (continued)
Table 6. Device Characteristics
Parameter
Supply Current:
Test Conditions
Symbol
Min
Typ
Max
Unit
VDD = 3.3 V
One Port Active
All Ports Active
No Ports Active, (Microlow-
power Sleep Mode) LPS = 0
PD = 1
IDD
IDD
IDD
—
—
—
54
74
50
—
—
—
mA
mA
µA
IDD
VOH
VOL
VIH
VIL
II
—
VDD – 0.4
—
50
—
—
—
—
—
—
—
µA
V
High-level Output Voltage
Low-level Output Voltage
High-level Input Voltage
Low-level Input Voltage
IOH max, VDD = min
IOL min, VDD = max
CMOS inputs
0.4
V
0.7 VDD
—
—
V
CMOS inputs
0.2 VDD
32
V
Pull-up Current,
RESETN Input
VI = 0 V
11
µA
Powerup Reset Time,
RESETN Input
VI = 0 V
—
—
2
—
—
—
—
—
1.4
16
12
ms
V
Rising Input Threshold Voltage
RESETN Input
VIRST
1.1
–16
–12
Output Current
SYSCLK
Control, data
IOL/IOH
@ TTL
mA
mA
IOL/IOH
@ CMOS
CNA
IOL/IOH
IOL/IOH
II
–16
–2
—
—
—
16
2
mA
mA
µA
C_LKON
Input Current,
LREQ, LPS, PD, SE, SM,
PC[0:2] Inputs
VI = VDD or 0 V
—
°±1
Off-state Output Current,
CTL[0:1], D[0:7], C_LKON I/Os
VO = VDD or 0 V
IOZ
VTH
VIT+
VIT−
—
—
7.5
—
—
—
—
—
—
—
°±5
8.5
µA
V
Power Status Input Threshold
Voltage, CPS Input
400 kΩ resistor
Rising Input Threshold Voltage*,
LREQ, CTLn, Dn
—
VDD/2 + 0.3
VDD/2 – 0.8
250
VDD/2 + 0.8
VDD/2 – 0.3
550
V
Falling Input Threshold Voltage*,
LREQ, CTLn, Dn
—
V
Bus Holding Current,
LREQ, CTLn, Dn
VI = 1/2(VDD)
µA
V
Rising Input Threshold Voltage
LPS
—
—
VLIH
VLIL
—
0.24 VDD + 1
—
Falling Input Threshold Voltage
LPS
0.24 VDD + 0.2
V
* Device is capable of both differentiated and undifferentiated operation.
Agere Systems Inc.
17
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Timing Characteristics
Table 7. Switching Characteristics
Symbol
Parameter
Jitter, Transmit
Measured
Test Conditions Min
Typ Max Unit
—
—
TPA, TPB
—
—
—
—
—
—
0.15
ns
ns
Transmit Skew
Between
±0.1
TPA and TPB
tr
tf
Rise Time, Transmit (TPA/TPB)
Fall Time, Transmit (TPA/TPB)
10% to 90%
90% to 10%
50% to 50%
50% to 50%
50% to 50%
RI = 56 Ω,
CI = 10 pF
—
—
6
—
—
—
—
—
1.2
1.2
—
—
6
ns
ns
ns
ns
ns
RI = 56 Ω,
CI = 10 pF
tsu
th
td
Setup Time,
Dn, CTLn, LREQ↑↓ to SYSCLK↑
See Figure 6.
See Figure 6.
See Figure 7.
Hold Time,
Dn, CTLn, LREQ↑↓ from SYSCLK↑
0
Delay Time,
1
SYSCLK↑ to Dn, CTLn↑↓
Table 8. Clock Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
MHz
External Clock Source Frequency
f
24.5735
24.5760
24.5785
18
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Timing Waveforms
SYSCLK
th
tsu
Dn, CTLn, LREQ
5-6017.a (F)
Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms
SYSCLK
td
Dn, CTLn
5-6018.a (F)
Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms
Agere Systems Inc.
19
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Internal Register Configuration
The PHY register map is shown below in Table 9. (Refer to IEEE 1394a-2000, 5B.1 for more information.)
Table 9. PHY Register Map for the Cable Environment
Address
Contents
Bit 3 Bit 4
Bit 0
RHB
Bit 1
Bit 2
Bit 5
Bit 6
R
Bit 7
PS
00002
00012
00102
00112
01002
01012
01102
01112
10002
Physical_ID
IBR
Extended (7)
Max_speed
Contender
ISBR
Gap_count
Total_ports
Delay
Pwr_class
Timeout Port_event Enab_accel Enab_multi
XXXXX
XXXXX
Jitter
LCtrl
Watchdog
Loop
Pwr_fail
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Page_select
Port_select
XXXXX
Register 0 Page_select
11112
Register 7 Page_select
REQUIRED
RESERVED
XXXXX
The meanings of the register fields within the PHY register map are defined by Table 10 below. Power reset
values not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 10. PHY Register Fields for the Cable Environment
Field
Size Type Power Reset
Value
Description
Physical_ID
6
r
000000
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
R
1
1
1
r
r
0
—
0
When set to one, indicates that this node is the root.
Cable power active.
PS
RHB
rw
Root hold-off bit. When set to one, the force_root variable is TRUE,
which instructs the PHY to attempt to become the root during the
next tree identify process.
IBR
1
rw
0
Initiate bus reset. When set to one, instructs the PHY to set ibr
TRUE and reset_time to RESET_TIME. These values in turn
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166 µs. This bit is self-clearing.
Gap_count
Extended
6
3
rw
r
3F16
111
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of IEEE Standard 1394a-2000 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY register map.
20
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Internal Register Configuration (continued)
Table 10. PHY Register Fields for the Cable Environment (continued)
Field
Size Type Power Reset Value
Description
Total_ports
4
r
0010
The number of ports implemented by this PHY. This count
reflects the number.
Max_speed
3
r
010
Indicates the speed(s) this PHY supports:
0002 = 98.304 Mbits/s
0012 = 98.304 and 196.608 Mbits/s
0102 = 98.304, 196.608, and 393.216 Mbits/s
0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s
1002 = 98.304, 196.608, 393.216, 786.432, and
1,572.864 Mbits/s
1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and
3,145.728 Mbits/s
All other values are reserved for future definition.
Delay
LCtrl
4
1
r
0000
1
Worst-case repeater delay, expressed as 144 + (delay * 20) ns.
rw
Link active. Cleared or set by software to control the value of
the L bit transmitted in the node’s self-ID packet 0, which will be
the logical AND of this bit and LPS active.
Contender
1
rw
See description.
Cleared or set by software to control the value of the C bit
transmitted in the self-ID packet. Powerup reset value is set by
C_LKON ball.
Jitter
3
3
r
000
000
The difference between the fastest and slowest repeater data
delay, expressed as (jitter + 1) * 20 ns.
Pwr_class
rw
Power class. Controls the value of the pwr field transmitted in
the self-ID packet. See Section 4.3.4.1 of IEEE Standard
1394a-2000 for the encoding of this field.
Watchdog
ISBR
1
1
rw
rw
0
0
When set to one, the PHY will set Port_event to one if resume
operations commence for any port.
Initiate short (arbitrated) bus reset. A write of one to this bit
instructs the PHY to set ISBR true and reset_time to
SHORT_RESET_TIME. These values in turn cause the PHY to
arbitrate and issue a short bus reset. This bit is self-clearing.
Loop
1
1
rw
rw
0
1
Loop detect. A write of one to this bit clears it to zero.
Pwr_fail
Cable power failure detect. Set to one when the PS bit changes
from one to zero. A write of one to this bit clears it to zero.
Timeout
1
1
rw
rw
0
0
Arbitration state machine timeout. A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port_event
Port event detect. The PHY sets this bit to one if any of con-
nected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY also sets this bit to one if
resume operations commence for any port and Watchdog is
one. A write of one to this bit clears it to zero.
Agere Systems Inc.
21
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Internal Register Configuration (continued)
Table 10. PHY Register Fields for the Cable Environment (continued)
Field
Size Type Power Reset
Value
Description
Enab_accel
1
rw
0
Enable arbitration acceleration. When set to one, the PHY will use
the enhancements specified in Section 4.4 of 1394a-2000 specifi-
cation. PHY behavior is unspecified if the value of Enab_accel is
changed while a bus request is pending.
Enab_multi
1
3
rw
rw
0
Enable multispeed packet concatenation. When set to one, the link
will signal the speed of all packets to the PHY.
Page_select
000
Selects which of eight possible PHY register pages are accessible
through the window at PHY register addresses 10002 through
11112, inclusive.
Port_select
4
rw
0000
If the page selected by Page_select presents per-port information,
this field selects which port’s registers are accessible through the
window at PHY register addresses 10002 through 11112, inclusive.
Ports are numbered monotonically starting at zero, p0.
The port status page is used to access configuration and status information for each of the PHY’s ports. The port is
selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address
01112. The format of the port status page is illustrated by Table 11 below; reserved fields are shown shaded. The
meanings of the register fields with the port status page are defined by Table 12.
Table 11. PHY Register Page 0: Port Status Page
Address
Contents
Bit 3 Bit 4
Bit 0
Bit 1
Bit 2
Bit 5
Bit 6
Bias
Bit 7
10002
10012
10102
10112
11002
11012
11102
11112
AStat
Negotiated_speed
BStat
Int_enable
Child
Fault
Connected
Disabled
XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
REQUIRED
RESERVED
XXXXX
22
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Internal Register Configuration (continued)
the meanings of the register fields with the port status page are defined by Table 12 below.
Table 12. PHY Register Port Status Page Fields
Field
Size Type Power Reset
Value
Description
TPA line state for the port:
AStat
2
r
—
002 = invalid
012 = 1
102 = 0
112 = Z
BStat
Child
2
1
r
r
—
0
TPB line state for the port (same encoding as AStat).
If equal to one, the port is a child; otherwise, a parent. The
meaning of this bit is undefined from the time a bus reset is
detected until the PHY transitions to state T1: Child Hand-
shake during the tree identify process (see Section 4.4.2.2 in
IEEE Standard 1394-1995).
Connected
Bias
1
1
1
3
r
r
0
0
If equal to one, the port is connected.
If equal to one, incoming TPBIAS is detected.
If equal to one, the port is disabled.
Disabled
rw
r
0
Negotiated_speed
000
Indicates the maximum speed negotiated between this PHY
port and its immediately connected port; the encoding is the
same as for they PHY register Max_speed field.
Int_enable
Fault
1
1
rw
rw
0
0
Enable port event interrupts. When set to one, the PHY will
set Port_event to one if any of connected, bias, disabled, or
fault (for this port) change state.
Set to one if an error is detected during a suspend or resume
operation. A write of one to this bit clears it to zero.
Agere Systems Inc.
23
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Internal Register Configuration (continued)
The vendor identification page is used to identify the PHY’s vendor and compliance level. The page is selected by
writing one to Page_select in the PHY register at address 01112. The format of the vendor identification page is
shown in Table 13; reserved fields are shown shaded.
Table 13. PHY Register Page 1: Vendor Identification Page
Address
Contents
Bit 3 Bit 4
Compliance_level
Bit 0
Bit 1
Bit 2
Bit 5
Bit 6
Bit 7
10002
10012
10102
10112
11002
11012
11102
11112
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Vendor_ID
Product_ID
REQUIRED
RESERVED
XXXXX
The meanings of the register fields within the vendor identification page are defined by Table 14.
Table 14. PHY Register Vendor Identification Page Fields
Field
Size Type
Description
Compliance_level
8
r
r
r
Standard to which the PHY implementation complies:
0 = not specified
1 = IEEE 1394a-2000
Agere’s FW802BF compliance level is 1.
All other values reserved for future standardization.
Vendor_ID
Product_ID
24
24
The company ID or organizationally unique identifier (OUI) of the manufacturer
of the PHY. Agere’s vendor ID is 00601D16. This number is obtained from the
IEEE registration authority committee (RAC). The most significant byte of
Vendor_ID appears at PHY register location 10102 and the least significant at
11002.
The meaning of this number is determined by the company or organization that
has been granted Vendor_ID. Agere’s FW802BF product ID is 08020116. The
most significant byte of Product_ID appears at PHY register location 11012 and
the least significant at 11112.
The vendor-dependent page provides access to information used in manufacturing test of the FW802BF.
24
Agere Systems Inc.
FW802BF PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Outline Diagrams
48-Ball VTFSBGAC
Dimensions are in millimeters.
TOP VIEW
BOTTOM VIEW
PKG TYPE
A
B
C
FSBGA
0.36 REF 0.70 ± 0.05 1.28 ± 0.18
TFSBGA 0.21 REF 0.70 ± 0.05 1.13 ± 0.13
VTFSBGA 0.21 REf 0.45 ± 0.03 0.88 ± 0.10
DETAIL A
Note:
1. GLOBAL PLANE IS BEST FIT PLANE AS DETERMINED
BY COPLANARITY MEASUREMENT EQUIPMENT.
2. THIS PACKAGE CONFIGURATION HAS SOLDER MASK
DEFINED BGA PADS (SMD). FOR DETAILS SEE INDI-
VIDUAL SUBSTRATE DRAWINGS (BOTTOM VIEW).
3. THE SOLDER BALL DIAMETER BEFORE REFLOW =
0.30 mm +0.10/-0.05 mm.
Ordering Information
Device Code
Package
Comcode
700050786
FW802BF-09-DB
48-ball VTFSBGAC
Agere Systems Inc.
25
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For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
E-MAIL:
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docmaster@agere.com
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1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei)
Tel. (44) 1344 296 400
EUROPE:
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Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
Copyright © 2005 Agere Systems Inc.
All Rights Reserved
January 2005
DS05-046CMPR (Replaces DS03-081CMPR-2)
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