LCK4993YH-DT_技术文档

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

1 Features

2 Description

■ 12 MHz—100 MHz (LCK4993), or 24 MHz—200 MHz

(LCK4994) output operation

The LCK4993 and LCK4994 low-voltage PLL clock drivers

offer user-selectable control over system clock functions.

The multiple-output clock drivers provide the system

integrator with functions necessary to optimize the timing of

high-performance computer and communication systems.

■ Matched pair output skew <200 ps

■ Zero input-to-output delay

■ 18 LVTTL 50% duty-cycle outputs capable of driving

50 Ω terminated lines

Each of the eighteen configurable outputs drive terminated

transmission lines with impedances as low as 50 Ω while

delivering minimal and specified output skews at LVTTL

levels. The outputs are arranged in five banks. Banks 1—4

allow a divide function of 1 to 12, while simultaneously

allowing phase adjustments in 625 ps—1300 ps increments

up to 10.4 ns. One of the output banks also includes an

independent clock invert function. The feedback bank

consists of two outputs that allow divide-by functionality

from 1 to 12 and limited phase adjustments. Any one of

these eighteen outputs can be connected to the feedback

input or drive other inputs.

■ 3.3 V/2.5 V LVTTL/LV differential (LVPECL) fault tolerant

and hot insertable reference inputs

■ Phase adjustments from 625 ps up to 1300 ps steps up

to ±10.4 ns

■ Output divide ratios of (1—6, 8, 10, 12)

■ Multiply ratios of (1—6, 8) x input frequency

■ Individual output bank disable for aggressive power

management and EMI reduction

Selectable reference input is a fault tolerance feature that

allows smooth change over to the secondary clock source

when the primary clock source is not in operation. The

reference inputs and feedback inputs are configurable to

accommodate both LVTTL or differential (LVPECL) inputs.

The completely integrated PLL reduces jitter and simplifies

board layout.

■ Output high-impedance (HI-Z) option for testing

purposes

■ Fully integrated PLL with lock indicator

■ Single 3.3 V/2.5 V ± 10% supply

■ 100-pin TQFP package

■ 100-ball FSBGA package

■ Pin-for-pin compatible with CYPRESS^®CY7B993V and

CY7B994V

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

Table of Contents

Contents

Page

1 Features .............................................................................................................................................................................1

2 Description ..........................................................................................................................................................................1

3 Functional Block Diagram ...................................................................................................................................................3

4 Pin Information ...................................................................................................................................................................4

4.1 100-Pin TQFP Diagram ...............................................................................................................................................4

4.2 Pin Descriptions ...........................................................................................................................................................5

5 Functional Description ........................................................................................................................................................7

5.1 Phase Frequency Detector and Filter ..........................................................................................................................7

5.2 VCO, Control Logic, Divider, and Phase Generator ....................................................................................................7

5.3 Time Unit Definition .....................................................................................................................................................7

5.4 Divide and Phase Select Matrix ...................................................................................................................................8

5.5 Timing Relationship of Programmable Skew Outputs .................................................................................................9

5.6 Output Disable Description ........................................................................................................................................10

5.7 INV3 Pin Function ......................................................................................................................................................10

5.8 Lock Detect Output Description .................................................................................................................................10

5.9 Factory Test Mode Description ..................................................................................................................................11

5.9.1 Factory Test Reset ...........................................................................................................................................11

5.10 Absolute Maximum Ratings .....................................................................................................................................11

5.11 Handling Precautions ..............................................................................................................................................12

5.12 Thermal Parameters (Definitions and Values) .........................................................................................................12

6 Electrical Characteristics ..................................................................................................................................................14

7 Timing ...............................................................................................................................................................................18

7.1 Switching Characteristics ..........................................................................................................................................18

7.2 ac Test Loads and Waveforms ..................................................................................................................................21

7.3 ac Timing Diagrams ...................................................................................................................................................22

8 Outline Diagrams ..............................................................................................................................................................23

8.1 100-Pin TQFP ............................................................................................................................................................23

8.2 100-Ball FSBGA ........................................................................................................................................................24

9 Ordering Information .........................................................................................................................................................25

Tables

Table 4-1. 100-Pin FSBGA Pin Assignments .........................................................................................................................4

Table 4-2. 100-Pin TQFP Descriptions...................................................................................................................................5

Table 5-1. Frequency Range Select .......................................................................................................................................7

Table 5-2. N Factor Determination..........................................................................................................................................7

Table 5-3. Output Skew Select Function ................................................................................................................................8

Table 5-4. Output Divider Function.........................................................................................................................................8

Table 5-5. DIS[1:4]/FBDIS Pin Functionality.........................................................................................................................10

Table 5-6. Factory Test Mode Frequency Divide Select ....................................................................................................... 11

Table 5-7. Absolute Maximum Ratings................................................................................................................................. 11

Table 5-8. Handling Precautions...........................................................................................................................................12

Table 5-9. Thermal Parameter Values..................................................................................................................................13

Table 6-1. Electrical Characteristics (TA –40 °C to +85 °C, VDD = 3.3 V ± 10%)..................................................................14

Table 6-2. Electrical Characteristics (TA –40 °C to +85 °C, VDD = 2.5 V ± 10%)..................................................................16

Table 7-1. Switching Characteristics (TA –40 °C to +85 °C, VDD = 3.3 V ± 10%).................................................................18

Table 7-2. Switching Characteristics (TA –40 °C to +85 °C, VDD = 2.5 V ± 10%).................................................................20

Table 9-1. LCK4993 Ordering Information............................................................................................................................25

Table 9-2. LCK4994 Ordering Information............................................................................................................................25

Figures

Figure 3-1. LCK4993 and LCK4994 Functional Block Diagram .............................................................................................3

Figure 4-1. 100-Pin TQFP Package (Top View).....................................................................................................................4

Figure 5-1. Typical Outputs with FB Connected to a Zero-Skew Output................................................................................9

Figure 7-1. ac Test Loads and Waveforms ..........................................................................................................................21

Figure 7-2. ac Timing Diagrams ...........................................................................................................................................22

2

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

3 Functional Block Diagram

FBKA+

FBKA–

LOCK

FBKB+

FBKB–

FBSEL

PHASE

FREQUENCY

CONTROL LOGIC

DIVIDE AND PHASE

VCO

FILTER

REFA+

REFA–

REFB+

REFB–

REFSEL

DETECTOR

GENERATOR

FS

3

OUTPUT_MODE

3

FBF0

3

DIVIDE AND

PHASE SELECT

MATRIX

QFA0

QFA1

FBDS0

3

FEEDBACK BANK

FBDS1

FBDIS

3

4F0

4F1

4QA0

4QA1

DIVIDE AND

PHASE SELECT

MATRIX

BANK 4

4DS0

4DS1

DIS4

4QB0

4QB1

3F0

3F1

3

3QA0

3QA1

DIVIDE AND

PHASE SELECT

MATRIX

BANK 3

3DS0

3QB0

3QB1

3DS1

DIS3

INV3

2F0

2F1

3

2QA0

2QA1

DIVIDE AND

PHASE SELECT

MATRIX

BANK 2

BANK 1

2DS0

2DS1

DIS2

2QB0

2QB1

1F0

1F1

3

1QA0

1QA1

DIVIDE AND

PHASE SELECT

MATRIX

1DS0

1QB0

1QB1

1DS1

DIS1

Figure 3-1. LCK4993 and LCK4994 Functional Block Diagram

Agere Systems Inc.

3

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

4 Pin Information

4.1 100-Pin TQFP Diagram

GND

3F1

4F1

3F0

4F0

4DS1

3DS1

GND

4QB1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDDQ

1

REFA+

REFA–

REFSEL

REFB–

REFB+

2F0

FS

GND

2QA0

VDDN

2

3

4

5

6

7

8

9

VDDN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

4QB0

GND

4QA1

2QA1

GND

2QB0

VDDN

4QA0

GND

2DS1

1DS1

2QB1

GND

FBF0

1F0

VDDQ

GND

4DS0

3DS0

2DS0

1DS0

GND

VDDQ

FBDIS

DIS4

DIS3

OUTPUT_MODE

5-8885 (F) r.1

Figure 4-1. 100-Pin TQFP Package (Top View)

Table 4-1. 100-Pin FSBGA Pin Assignments

1

2

3

4

5

6

7

8

9

10

1QB1

1QB0

1QA1

1QA0

QFA0

QFA1

FBKB+

VDDQ

FBKA–

FBSEL

GND

FBKA+

REFA+

REFA–

A

B

C

D

E

F

VDDN

GND

VDDN

GND

4F0

VDDN

GND

3F1

VDDN

GND

VDDN

GND

VDDN

GND

VDDQ

2F0

FBKB–

GND

VDDQ

FS

LOCK

4QB1

4QB0

4QA1

FBDS1 FBDS0

REFSEL REFB–

VDDN

2DS1

4DS1

3DS1

VDDQ

3F0

GND

4F1

GND

VDDN

1F0

REFB+

2QA0

2QA1

FBF0

VDDQ

G

4QA0

1DS1

1DS0

VDDQ

GND

VDDQ OUTPUT_ FBDIS

MODE

2QB0

H

4DS0

2F1

3DS0

1F1

2DS0

DIS2

DIS1

VDDN

GND

INV3

DIS3

2QB1

DIS4

J

3QA0

3QA1

3QB0

3QB1

K

4

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

4.2 Pin Descriptions

For all 3-state inputs, low indicates a connection to GND, mid indicates an open connection, and high indicates a

connection to VDD. Internal termination circuitry holds an unconnected input to VDD/2.

Table 4-2. 100-Pin TQFP Descriptions

Symbol

Type

I/O

Description

1, 8, 12, 13, 17, 25—28,

35, 39, 40, 44, 47, 50,

55, 58, 62, 63, 67, 82,

83, 87, 88, 92, 93, 97

GND

Power — Ground.

2—5, 31, 32, 56, 69

3-Level

Input

I

Output Phase Function Select. Each pair controls the phase

function of the respective bank of outputs, see Table 5-3.

[1:4]F[0:1]

6, 7, 18, 19, 21—24

[1:4]DS[0:1]

3-Level

Input

Output Divider Function Select. Each pair controls the divide

function of the respective bank of outputs, see Table 5-4.

9, 11, 14, 16, 36, 38, 41, [1:4]Q[A:B][0:1] LVTTL

43, 59, 61, 64, 66, 89,

O

Clock Output. These outputs provide numerous divide and

phase select functions determined by the [1:4]DS[0:1] and

[1:4]F[0:1] inputs.

91, 94, 96

10, 15, 37, 42, 60, 65,

85, 90, 95

Power — Output Buffer Power. Power supply for each output pair.

Power — Internal Power. Power supply for the internal circuitry.

VDDN

VDDQ

20, 29, 30, 45, 49, 54,

75, 76

33, 34, 51, 52

LVTTL

I^dOutput Disable. Each input controls the state of the respective

output bank.

DIS[1:4]

Low = the [1:4]Q[A:B][0:1] is enabled, see Table 5-5.

High = the output bank is disabled to the hold-off or HI-Z state;

the disable state is determined by OUTPUT_MODE.

46

48

INV3

3-Level

Input

I

Invert Mode. This input only affects Bank3.

Low = each matched output pair will become complementary

(3QA0+, 3QA1–, 3QB0+, 3QB1–).

Mid = all four outputs will be noninverting.

High = all four outputs in the same bank will be inverted.

OUTPUT_MODE 3-Level

Input

Output Mode. This pin determines the clock outputs’ disable

state.

Low = the clock outputs will disable to hold-off mode.

Mid = the device enters factory test mode.

High = the clock outputs will disable to HI-Z.

53

57

FBDIS

LVTTL

I^dFeedback Disable. This input controls the state of QFA[0:1].

Low = the QFA[0:1] is enabled, see Table 5-5.

High = the QFA[0:1] is disabled to the hold-off or HI-Z state; the

disable state is determined by OUTPUT_MODE.

FBF0

FS

3-Level

Input

I

Feedback Output Phase Function Select. This input deter-

mines the phase function of the feedback banks QFA[0:1] out-

puts, see Table 5-3.

68

3-Level

Input

I

Frequency Select. This input must be set according to the

nominal frequency (f^NOM), see Table 5-1).

70, 71, 73, 74

REFB+, REFB–, LVTTL/

REFA–, REFA+ LVDIFF

Reference Inputs. These inputs can operate as differential

PECL or single-ended TTL reference inputs to the PLL. When

operating as a single-ended LVTTL input, the complementary

input must be left open.

d

Note: I = each input has an internal pull-down resistor.

Agere Systems Inc.

5

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

Table 4-2. 100-Pin TQFP Descriptions (continued)

Symbol

Type

I/O

Description

72

REFSEL

LVTTL

I^dReference Input Select. The REFSEL input controls how the

reference input is configured.

Low = REFSEL uses the REFA pair as the reference input.

High = REFSEL uses the REFB pair as the reference input.

77, 78, 80, 81

FBKA+, FBKA–, LVTTL/

FBKB–, FBKB+ LVDIFF

I

Feedback Inputs. One pair of inputs selected by the FBSEL is

used to feedback the clock output xQn to the phase detector.

The PLL will operate so that the rising edges of the reference

and feedback signals are aligned in both phase and frequency.

These inputs can operate as differential PECL or single-ended

TTL inputs. When operating as a single-ended LVTTL input,

the complementary input must be left open.

79

FBSEL

LVTTL

I^dFeedback Input Select.

Low = FBKA inputs are selected.

High = FBKB inputs are selected.

84, 86

QFA[0:1]

O

Clock Feedback Output. This pair of clock outputs is intended

to be connected to the FB input. These outputs have numerous

divide options and three choices of phase adjustments. The

function is determined by setting the FBDS[0:1] pins and FBF0.

98, 99

100

FBDS[0:1]

LOCK

3-Level

Input

I

Feedback Divider Function Select. These inputs determine

the function of the QFA0 and QFA1 outputs, see Table 5-4.

LVTTL

O

PLL Lock Indicator.

Low = the PLL is attempting to acquire lock.

High = this output indicates the internal PLL is locked to the ref-

erence signal.

d

Note: I = each input has an internal pull-down resistor.

6

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

5 Functional Description

5.1 Phase Frequency Detector and Filter

These two blocks accept signals from the REF inputs (REFA+, REFA–, REFB+, or REFB–) and the FB inputs (FBKA+,

FBKA–, FBKB+, or FBKB–). Correction information is then generated to control the frequency of the voltage-controlled

oscillator (VCO). These two blocks, along with the VCO, form a phase-locked loop (PLL) that tracks the incoming REF

signal.

The devices have a flexible REF and FB input scheme. These inputs allow using either differential LVPECL or single-ended

LVTTL inputs. To configure as single-ended LVTTL inputs, the complementary input pin must be left open (internally pulled

to 1.5 V), and the other input pin can then be used as an LVTTL input. The REF inputs are also tolerant to hot insertion.

The REF inputs can be changed dynamically. When changing from one reference input to the other reference input of the

same frequency, the PLL is optimized to ensure that the clock output period will not be less than the calculated system

budget (tMIN = tREF (nominal reference clock period) – tCCJ (cycle-to-cycle jitter) – tPDEV (maximum period deviation)) while

reacquiring lock.

5.2 VCO, Control Logic, Divider, and Phase Generator

The VCO accepts analog control inputs from the PLL filter block. The FS control pin setting determines the nominal

operational frequency (fNOM) range of the divide-by-one output of the device. fNOM is directly related to the VCO frequency.

There are two versions of the device, a low-speed device (LCK4993) where fNOM ranges from 12 MHz to 100 MHz, and a

high-speed device (LCK4994) where fNOM ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in

Table 5-1.

The fNOM frequency is seen on divide-by-one outputs. For the LCK4994, the upper fNOM range extends from 96 MHz to

200 MHz.

Table 5-1. Frequency Range Select

FS^*

LCK4993

LCK4994

fNOM (MHz)

Min

12

24

Max

26

52

Min

24

48

Max

52

100

200

Low

Mid

High

48

100

96

* The level to be set on FS is determined by the fNOM of the VCO and phase generator. fNOM always appears on an output when the output is

operating in the divide by 1 mode. The REF and FB are at fNOM when the output connected to FB is in the divide by 1 mode.

5.3 Time Unit Definition

Selectable skew is in discrete increments of time unit (tU). The value of tU is determined by the FS setting and the fNOM

frequency. The equation to be used to determine the tU is as follows:

1

(eq. 1)

tU = -------------------------

fNOM × N

Where N is a multiplication factor, determined by the FS setting and is defined in Table 5-2; where fNOM is the nominal

operating frequency of the VCO.

Table 5-2. N Factor Determination

FS

LCK4993

LCK4994

N

fNOM (MHz) at which tU = 1.0 ns

N

32

16

8

fNOM (MHz) at which tU = 1.0 ns

Low

Mid

High

64

32

16

15.265

31.25

62.5

31.25

62.5

125

Agere Systems Inc.

7

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

5.4 Divide and Phase Select Matrix

The divide and phase select matrix is comprised of five independent banks as follows: four banks for clock outputs and one

bank for feedback. Each clock output bank has two pairs of low-skew, high-fanout output buffers ([1:4]Q[A:B][0:1]), two

phase function select inputs ([1:4]F[0:1]), two divider function selects ([1:4]DS[0:1]), and one output disable (DIS[1:4]).

The feedback bank has one pair of low-skew, high-fanout output buffers (QFA[0:1]). One of these outputs may connect to

the selected feedback input (FBK[A:B]±). This feedback bank also has one phase function select input (FBF0), two divider

function selects FSDS[0:1], and one output disable (FBDIS).

The phase capabilities that are chosen by the phase function select pins are shown in Table 5-3. The divide capabilities for

each bank are shown in Table 5-4.

Table 5-3. Output Skew Select Function

Function Selects

Output Skew Function

[1:4]F1

[1:4]F0 and FBF0

Bank1

–4 t^U

–3 tU

–2 t^U

– 1t^U

0 t^U

Bank2

–4 tU

–3 tU

–2 tU

–1 tU

0 tU

Bank3

–8 tU

–7 tU

–6 tU

BK1^*

0 tU

Bank4

–8 tU

–7 tU

–6 tU

BK1*

0 tU

Feedback Bank

Low

Mid

Low

Mid

–4 tU

NA

High

Low

Mid

NA

Mid

0 tU

NA

Mid

High

Low

Mid

1 tU

BK2^†

High

2 t^U

2 tU

6 tU

NA

3 t^U

3 tU

7 tU

NA

High

4 t^U

4 tU

8 tU

4 tU

* BK1 denotes following the skew of Bank1.

† BK2 denotes following the skew of Bank2.

Table 5-4. Output Divider Function

Function Selects*

Output Divider Function

[1:4]DS1 and FBDS1

[1:4]DS0 and FBDS0

Bank1

Bank2

Bank3

Bank4

Feedback Bank

Low

Mid

Low

Mid

/1

/2

/1

/2

/1

/2

/1

/2

/1

/2

High

Low

Mid

/3

/4

Mid

/5

Mid

High

Low

Mid

/6

High

/8

/10

/12

/10

/12

/10

/12

/10

/12

/10

/12

High

* Output frequency = f

(VCO frequency)/value of output divisor.

NOM

8

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

5.5 Timing Relationship of Programmable Skew Outputs

Figure 5-1 illustrates the timing relationship of programmable skew outputs. All times are measured with respect to REF,

with the output used for feedback programed with 0 tU skew. The PLL naturally aligns the rising edge of the FB input and

REF input. If the output used for feedback is programmed to another skew position, then the whole tU matrix will shift with

respect to REF. For example, if the output used for feedback is programmed to shift –8 tU, then the whole matrix is shifted

forward in time by 8 tU. Therefore, an output programed with 8 tU of skew will effectively be skewed 16 tU with respect to

REF.

FB Input

REF Input

1F[1:0] 3F[1:0]

2F[1:0] 4F[1:0]

NA

LL

LM

LH

–8 tU

–7 tU

–6 tU

–4 tU

–3 tU

–2 tU

–1 tU

0 tU

NA

MM

NA

HL

LM

LH

ML

MM

MH

HL

1 tU

2 tU

HM

HH

NA

3 tU

4 tU

6 tU

HM

HH

7 tU

8 tU

Note: FB connected to an output selected for zero skew (i.e., FBF0 = mid or xF[1:0] = mid).

Figure 5-1. Typical Outputs with FB Connected to a Zero-Skew Output

Agere Systems Inc.

9

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

5.6 Output Disable Description

The feedback divide and phase select matrix bank has two outputs, each of the four divide and phase select matrix banks

have four outputs. The outputs of each bank can be independently put into a hold-off, or HI-Z state. The combination of the

OUTPUT_MODE and DIS[1:4]/FBDIS inputs determines the clock outputs’ state for each bank. When the DIS[1:4]/FBDIS

is low, the outputs of the corresponding bank will be enabled. When the DIS[1:4]/FBDIS is high the outputs for that bank will

be disabled to a HI-Z or hold-off state, depending on the OUTPUT_MODE input. Table 5-5 defines the disabled output

functions.

The hold-off state is intended to be a power saving feature. An output bank is disabled to the hold-off state in a maximum of

six output clock cycles from the time when the disable input (DIS[1:4]/FBDIS) is high. When disabled to the hold-off state,

noninverting outputs are driven to a logic-low state on its falling edge. Inverting outputs are driven to a logic-high state on its

rising edge. This ensures the output clocks are stopped without a glitch. When a bank of outputs is disabled to a HI-Z state,

the respective bank of outputs will go HI-Z immediately.

Table 5-5. DIS[1:4]/FBDIS Pin Functionality

OUTPUT_MODE

DIS[1:4]/FBDIS

Output Mode

High/Low

High

Low

High

X

Enabled

HI-Z

Low

Hold-off

Mid

Factory Test

5.7 INV3 Pin Function

Bank3 has signal invert capability. The four outputs of Bank3 will act as two pairs of complementary outputs when the INV3

pin is driven low. In complementary output mode, 3QA0 and 3QB0 are noninverting; 3QA1 and 3QB1 are inverting outputs.

All four outputs will be inverted when the INV3 pin is driven high. When the INV3 pin is left in mid, the outputs will not invert.

Inversion of the outputs are independent of the skew and divide functions. Therefore, clock outputs of Bank3 can be

inverted, divided, and skewed at the same time.

5.8 Lock Detect Output Description

The LOCK detect output indicates the lock condition of the integrated PLL. Lock detection is accomplished by comparing

the phase difference between the reference and feedback inputs. Phase error is declared when the phase difference

between the two inputs is greater than the specified device propagation delay limit (tPD).

When in the locked state, after four or more consecutive feedback clock cycles with phase-errors, the LOCK output will be

forced low to indicate out-of-lock state.

When in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the LOCK output

to indicate lock condition (LOCK = high).

If the feedback clock is removed after LOCK has gone high, a watchdog circuit is implemented to indicate the out-of-lock

condition after a time-out period by deasserting LOCK low. This time-out period is based on a divided down reference

clock. This assumes that there is activity on the selected REF input. If there is no activity on the selected REF input, then

the LOCK detect pin may not accurately reflect the state of the internal PLL.

10

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

5.9 Factory Test Mode Description

The device will enter factory test mode when the OUTPUT_MODE input is driven to a mid level. In factory test mode, the

device will operate with its internal PLL disconnected. The reference input will replace the PLL output. While operating in

factory test mode, the selected FB input(s) must both be tied low. The output frequency is a function of the input level set on

the FS pin (see Table 5-6). When operating in factory test mode, all outputs must be set to the divide by 1 function. Output

skew select function operates normally, output bank disable is unavailable while operating in factory test mode. The

OUTPUT_MODE input is designed to be a static input. Dynamically toggling this input from low to high may temporarily

cause the device to go into factory test mode (when passing through the mid state).

5.9.1 Factory Test Reset

When operating in factory test mode (OUTPUT_MODE = mid), the device can be reset to a deterministic state by forcing

the DIS4 input to a logic high. With DIS4 in a logic high state, all clock outputs will go to HI-Z. After the selected reference

clock pin has five positive transitions, all the internal finite state machines (FSM) will be set to a deterministic state. The

deterministic state of the state machines will depend on the configuration of the divide select, skew select, and frequency

select inputs. All clock outputs will stay in high-impedance mode, and all FSMs will stay in the deterministic state until DIS4

is deasserted. When DIS4 is deasserted (with OUTPUT_MODE still at mid), the device will re-enter factory test mode.

Table 5-6. Factory Test Mode Frequency Divide Select

FS

LCK4993

Output Frequency

Divide By

LCK4994

Output Frequency

Divide By

Low

Mid

32

16

8

16

8

High

4

5.10 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute

stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those

given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can

adversely affect device reliability.

Table 5-7. Absolute Maximum Ratings

Parameter

Storage Temperature

Symbol

Min

Max

Unit

Tstg

VDD

VDC

IOUT

IL

–40

–0.5

–0.3

—

125

4.6

°C

V

Supply Voltage

dc Input Voltage

VDD + 0.5

40

V

Output Current into Outputs (low)

Latch-Up Current

mA

—

±200

Agere Systems Inc.

11

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

5.11 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be

taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere

employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to deter-

mine ESD susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit

parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) stan-

dards.

Table 5-8. Handling Precautions

Device

Minimum Threshold

HBM

CDM

LCK4993

LCK4994

2000 V

500 V

Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and pack-

aging MOS devices should be observed.

5.12 Thermal Parameters (Definitions and Values)

System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal

characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they

can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 °C, temperature-activated

failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system

designer choose the best package for their applications, including allowing the system designer to thermally design and in-

tegrate their systems.

It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle

size) and choice of materials, the amount of copper in the test board or system board, and system airflow.

Θ_JA- Junction to Air Thermal Resistance

Θ_JAis a number used to express the thermal performance of a part under JEDEC standard natural convection conditions.

Θ_JAis calculated using the following formula:

Θ_JA= (T_J– T_amb) / P; where P = power

Θ_JMA- Junction to Moving Air Thermal Resistance

Θ_JMAis effectively identical to Θ_JAbut represents performance of a part mounted on a JEDEC four-layer board inside a wind

tunnel with forced air convection. Θ_JMAis reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which

roughly correspond to 1 m/s and 2.5 m/s (respectively). Θ_JMAis calculated using the following formula:

Θ_JMA= (T_J– T_amb) / P

Θ_JC- Junction to Case Thermal Resistance

Θ_JCis the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the

heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top

of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. Θ_JCis calculated using

the following formula:

Θ_JC= (T_J– T_C) / P

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Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Θ_JB- Junction to Board Thermal Resistance

Θ_JBis the thermal resistance from junction to board. This number is determined by forcing the heat generated in the die out

of the package through the leads or balls by lowering the board temperature and insulating the package top. This is done

using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package

while insulating the package top. Θ_JBis calculated using the following formula:

Θ_JB= (T_J– T_B) / P

Ψ_JT

Ψ_JTcorrelates the junction temperature to the case temperature. It is generally used by the customer to infer the junction

temperature while the part is operating in their system. It is not considered a true thermal resistance. Ψ_JTis calculated using

the following formula:

Ψ_JT= (T_J– T_C) / P

Table 5-9. Thermal Parameter Values

Parameter

Temperature °C/Watt

100-Pin TQFP

100-Ball FSBGA

Θ_JA

38

32.9

30.4

32.9

29.9

1

71.9

66.6

64.7

24.5

56.8

1

Θ_JMA(1 m/s)

Θ_JMA(2.5 m/s)

Θ_JC

Θ_JB

Ψ_JT

Agere Systems Inc.

13

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

6 Electrical Characteristics

.

Table 6-1. Electrical Characteristics (TA –40 °C to +85 °C, VDD = 3.3 V ± 10%)

Parameter

Symbol

Description

Test Conditions

Min

Max

Unit

LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B], LOCK

High-Voltage

Output (LVTTL)

VOH

QFA[0:1], [1:4]Q[A:B][0:1]

VDD = min, IOH = –30 mA

VDD = min, IOH = –2 mA

VDD = min, IOH = 30 mA

VDD = min, IOH = 2 mA

—

2.4

—

V

LOCK

Low-Voltage

Output (LVTTL)

VOL

QFA[0:1], [1:4]Q[A:B][0:1]

0.5

100

V

LOCK

—

V

High-Imped-

IOZ

—

–100

µA

ance State Leak-

age Current

LVTTL Compatible Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])

High-Voltage

Input (LVTTL)

VIH

VIL

IIH

FBK[A:B]±, REF[A:B]±

Min ≤ VDD ≤ max

—

2.0

VDD + 0.3

0.8

V

REFSEL, FBSEL, FBDIS, DIS[1:4]

FBK[A:B]±, REF[A:B]±

Low-Voltage

Input (LVTTL)

Min ≤ VDD ≤ max

—

–0.3

—

V

REFSEL, FBSEL, FBDIS, DIS[1:4]

FBK[A:B]±, REF[A:B]±

0.8

V

High-Input

Current (LVTTL)

VDD = max, VIN = VDD

VIN = VDD

500

µA

REFSEL, FBSEL, FBDIS, DIS[1:4]

FBK[A:B]±, REF[A:B]±

—

500

Low-Input

Current (LVTTL)

IIL

VDD = max, VIN = GND

VIN = GND

–500

—

REFSEL, FBSEL, FBDIS, DIS[1:4]

—

3-Level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST)

Low-Voltage

VILL

VIMM

VIHH

IILL

—

Min ≤ VDD ≤ max

—

0.13 x VDD

V

3-Level Input¹

Mid-Voltage

0.47 x VDD 0.53 x VDD

3-Level Input¹

High-Voltage

3-Level Input¹

0.87 x VDD

—

Low-Current

3-Level Input

3-level input pins excluding FBF0 VIN = GND

FBF0 VIN = GND

3-level input pins excluding FBF0 VIN = VDD/2

FBF0 VIN = VDD/2

3-level input pins excluding FBF0 VIN = VDD

FBF0 VIN = VDD

–200

–400

–50

–100

—

µA

Mid-Current

3-Level Input

IIMM

IIHH

50

100

200

400

High-Current

3-Level Input

—

1. These inputs are normally wired to VDD, GND, or left unconnected (actual threshold voltages vary as a percentage of VDD). Internal termination

resistors hold the unconnected inputs at VDD/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may

require an additional tLOCK time before all data sheet limits are achieved.

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Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Table 6-1. Electrical Characteristics (TA –40 °C to +85 °C, VDD = 3.3 V ± 10%) (continued)

Parameter

Symbol

Description

Test Conditions

Min

Max

Unit

LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)

Input Differential

Voltage

VDIFF

VILLP

VIHHP

VCOM

—

400

GND

1.0

VDD

VDD – 0.4

VDD

mV

V

Lowest Input

Low Voltage

Highest Input

High Voltage

V

Common-mode

Range (crossing

voltage)

0.8

VDD

V

Operating Current

Internal Operat-

ing Current

ICCI

LCK4993

LCK4994

LCK4993

VDD = max, fmax

VDD = max,

—

250

40

mA

1

Output Current

Dissipation/Pair²

ICCN

CLOAD = 25 pF,

RLOAD = 50 Ω at

VDD/2, fmax

LCK4994

VDD = max,

—

50

5

mA

pF

CLOAD = 25 pF,

RLOAD = 50 Ω at

VDD/2, fmax

Capacitance

Input Capaci-

tance

CIN

—

TA = 25 °C, f = 1 MHz,

VDD = 3.3 V/2.5 V

1. ICCI measurements are performed with Bank1 and FB bank configured to run at maximum frequency (fNOM = 100 MHz for LCK4993, fNOM =

200 MHz for LCK4994), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the high

state.

2. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and

maximum load of 25 pF terminated to 50 Ω at VDD/2.

Agere Systems Inc.

15

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

Table 6-2. Electrical Characteristics (TA –40 °C to +85 °C, VDD = 2.5 V ± 10%)

Parameter

Symbol

Description

Test Conditions

Min

Max

Unit

LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B], LOCK)

High-Voltage

Output (LVTTL)

VOH

QFA[0:1], [1:4]Q[A:B][0:1]

VDD = min, IOH = –30 mA

VDD = min, IOH = –2 mA

VDD = min, IOH = 30 mA

VDD = min, IOH = 2 mA

—

1.6

—

V

LOCK

Low-Voltage

Output (LVTTL)

VOL

QFA[0:1], [1:4]Q[A:B][0:1]

0.5

100

V

LOCK

—

V

High-Imped-

IOZ

—

–100

µA

ance State Leak-

age Current

LVTTL Compatible Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])

High-Voltage

Input (LVTTL)

VIH

VIL

IIH

FBK[A:B]±, REF[A:B]±

Min ≤ VDD ≤ max

2.0

VDD + 0.3

0.8

V

REFSEL, FBSEL, FBDIS, DIS[1:4]

FBK[A:B]±, REF[A:B]±

—

Min ≤ VDD ≤ max

—

Low-Voltage

Input (LVTTL)

–0.3

—

V

REFSEL, FBSEL, FBDIS, DIS[1:4]

FBK[A:B]±, REF[A:B]±

0.8

V

High-Input

Current (LVTTL)

VDD = max, VIN = VDD

500

µA

REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VDD

—

500

Low-Input

Current (LVTTL)

IIL

FBK[A:B]±, REF[A:B]±

VDD = max, VIN = GND

—

500

REFSEL, FBSEL, FBDIS, DIS[1:4]

—

–500

—

3-Level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))

Low-Voltage

VILL

VIMM

VIHH

IILL

—

Min ≤ VDD ≤ max

—

0.13 x VDD

V

3-Level Input¹

Mid-Voltage

0.47 x VDD 0.53 x VDD

3-Level Input¹

High-Voltage

3-Level Input¹

0.87 x VDD

—

Low-Current

3-Level Input

3-level input pins excluding FBF0

VIN = GND

VIN = VDD/2

VIN = VDD

–200

–400

–50

–100

—

µA

FBF0

Mid-Current

3-Level Input

IIMM

IIHH

3-level input pins excluding FBF0

50

FBF0

100

200

400

High-Current

3-Level Input

3-level input pins excluding FBF0

FBF0

—

1. These inputs are normally wired to VDD, GND, or left unconnected (actual threshold voltages vary as a percentage of VDD). Internal termination

resistors hold the unconnected inputs at VDD/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may

require an additional tLOCK time before all data sheet limits are achieved.

16

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Table 6-2. Electrical Characteristics (TA –40 °C to +85 °C, VDD = 2.5 V ± 10%) (continued)

Parameter

Symbol

Description

Test Conditions

Min

Max

Unit

LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)

Input Differential

Voltage

VDIFF

VILLP

VIHHP

VCOM

—

400

GND

1.0

VDD

VDD – 0.4

VDD

mV

V

Lowest Input

Low Voltage

Highest Input

High Voltage

V

Common-mode

Range (crossing

voltage)

0.8

VDD

V

Operating Current

Internal Operat-

ing Current

ICCI

LCK4993

LCK4994

LCK4993

VDD = max, fmax

VDD = max,

—

250

40

mA

1

Output Current

Dissipation/Pair²

ICCN

CLOAD = 25 pF,

RLOAD = 50 Ω at

VDD/2, fmax

LCK4994

VDD = max,

—

50

5

mA

pF

CLOAD = 25 pF,

RLOAD = 50 Ω at

VDD/2, fmax

Capacitance

Input Capaci-

tance

CIN

—

TA = 25 °C, f = 1 MHz,

VDD = 3.3 V/2.5 V

1. ICCI measurements are performed with Bank1 and FB bank configured to run at maximum frequency (fNOM = 100 MHz for LCK4993, fNOM =

200 MHz for LCK4994), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the high

state.

2. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and

maximum load of 25 pF terminated to 50 Ω at VDD/2.

Agere Systems Inc.

17

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1

May 5, 2004

7 Timing

7.1 Switching Characteristics

The following switching characteristics and assumptions apply for non 3-level inputs.

■ A maximum 25 pF load capacitance is used for frequencies up to 185 MHz. A maximum 10 pF load capacitance is used

for the frequency of 200 MHz.

■ Both outputs of the pair must be terminated, even if only one is being used.

■ ac parameters are measured at 50%, unless otherwise indicated.

Table 7-1. Switching Characteristics (TA –40 °C to +85 °C, VDD = 3.3 V ± 10%)

Parameter

Clock Input Frequency

Symbol

Description

Min

12

24

12

24

2.0

—

Max

100

200

100

200

—

Unit

MHz

ns

fIN

LCK4993

LCK4994

LCK4993

LCK4994

Pulse width low.⁸

Pulse width high.⁸

Clock Output Frequency

REF Input

fOUT

tREFPWL

tREFPWH

tSKEWPR

—

200

ns

ps

Matched-Pair Skew^{1, 2}

Interbank Skew

Same frequency and phase, rise-to-rise and fall-to-

fall. (Matched pair outputs within a bank.)^{1, 2}

tSKEWBNK Same frequency and phase, rise-to-rise and fall-to-

fall. (All outputs within a bank.)^{1, 2}

—

200

250

500

200

ps

Output-Output Skew

tSKEW0

tSKEW1

tSKEW2

tSKEW3

Same frequency and phase, rise-to-rise and fall-to-

fall. (All outputs across all banks.)^{1, 2}

Different frequency same phase, rise-to-rise and

fall-to-fall. (All outputs all banks.)^{1, 2}

Same frequency and phase, rise-to-fall and fall-to-

rise. (Bank 3 inverted to all other banks.)^{1, 2, 3}

All output configurations outside tSKEW1 and

tSKEW2.^{1, 2}

Complementary

Outputs Skew

tSKEWCPR Crossing to crossing, complementary outputs.

(Bank 3 only.)^{1, 2, 3, 4}

Cycle-to-Cycle Jitter

Propagation Delay

tCCJ

tPD

Divide by 1 output frequency, FB = divide by 1—8.

REF to FB rise.

Difference between two devices.⁴

—

–250

—

150

250

200

2.0

ps

ns

tPDDELTA

Output Rise/Fall Time⁵

tR/tF

—

0.15

1. Test load CL maximum 25 pF (fnom ≤185 MHz) and maximum 10 pF (fnom = 200 MHz) both terminated 50 Ω to VDD/2.

2. SKEW is defined as the time between the earliest and latest output transition among all outputs for which the same phase delay has been

selected and all outputs are equally loaded and properly terminated.

3. Complementary output skews are measured at complementary signal pair intersections.

4. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

5. Rise and fall times are measured at 20% and 80% of the output voltage swing.

6. fNOM must be within the frequency range defined by the FS state (see Table 5-1).

7. ac parameters are measured at 50%, unless otherwise indicated.

8. tPWL is measured at 20%. tPWH is measured at 80%.

9. UI = unit interval. Examples: 1 UI is a full period. 0.1 UI is 10% of a period.

10. Measured at 0.5 V deviation from starting voltage.

11. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL = 25 pF to 185 MHz or 10 pF at 200 MHz.

18

Agere Systems Inc.

Data Sheet, Revision 1

May 5, 2004

LCK4993/LCK4994

Low-Voltage PLL Clock Drivers

Table 7-1. Switching Characteristics (TA –40 °C to +85 °C, VDD = 3.3 V ± 10%) (continued)

Parameter

Symbol

Description

Min

Max

Unit

PLL Lock Time from

Powerup

tLOCK

—

10

ms

PLL Relock Time

tRELOCK1

tRELOCK2

From same frequency, different phase, and with sta-

ble power supply.

From different frequency, different phase, and with

stable power supply.⁶

—

500

µs

1000

Output Duty Cycle ⁷

Period Deviation

tODCV

tPDEV

tOZA

—

45

—

0.5

55

0.025

14

%

UI⁹

ns

When changing from reference to reference.

DIS[1:4]/FBDIS low to output active from output is

high-impedance.^{10, 11}

Output Disable Time

Output Enable Time

tOAZ

DIS[1:4]/FBDIS high to output high-impedance from

1.0

10

ns

active.^{1, 10}