HCPL-063L#020 [AGILENT]
IC Output Optocoupler, 2-Element, 2500V Isolation;
| 型号： | HCPL-063L#020 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | IC Output Optocoupler, 2-Element, 2500V Isolation |
| 文件： | 总15页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HCPL-260L/ 060L/263L/063L
High Speed LVTTL Compatible
3.3 Volt Optocouplers
Data Sheet
Features
•
Low power consumption
•
15 kV/µs minimum Common Mode
Rejection (CMR) at VCM = 50 V
•
•
•
High speed: 15 MBd typical
LVTTL/LVCMOS compatible
Low input current capability:
5 mA
Description
•
Guaranteed AC and DC performance
over temperature: –40˚C to +85˚C
The HCPL-260L/060L/263L/063L
are optically coupled gates that
combine a GaAsP light emitting
diode and an integrated high gain
photo detector. An enable input
allows the detector to be strobed.
The output of the detector IC is an
open collector Schottky-clamped
transistor. The internal shield
provides a guaranteed common
mode transient immunity
This unique design provides
maximum AC and DC circuit
isolation while achieving
LVTTL/LVCMOS compatibility.
The optocoupler AC and DC
operational parameters are
guaranteed from –40˚C to +85˚C
allowing trouble-free system
performance.
•
•
Available in 8-pin DIP, SOIC-8
Strobable output (single channel
products only)
•
Safety approvals; UL, CSA, VDE
(pending)
Applications
•
•
•
•
Isolated line receiver
specification of 15 kV/µs.
Computer-peripheral interfaces
Microprocessor system interfaces
Functional Diagram
Digital isolation for A/D, D/A
conversion
HCPL-260L/060L
HCPL-263L/063L
1
2
V
V
V
ANODE
CATHODE
CATHODE
ANODE
1
2
V
V
8
7
8
7
NC
CC
CC
O1
O2
1
1
•
•
•
•
•
Switching power supply
Instrument input/output isolation
Ground loop elimination
Pulse transformer replacement
Field buses
ANODE
E
V
CATHODE
NC
3
4
6
5
3
4
6
5
O
2
2
GND
GND
SHIELD
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
TRUTH TABLE
(POSITIVE LOGIC)
LED ENABLE OUTPUT
LED OUTPUT
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
L
H
H
H
L
ON
OFF
L
H
H
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.
These optocouplers are suitable
for high speed logic interfacing,
input/output buffering, as line
receivers in environments that
conventional line receivers
cannot tolerate and are
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-260L #XXX
060 = VDE 0884 V
= 630 Vpeak Option
IORM
recommended for use in
extremely high ground or induced
noise environments.
500 = Tape and Reel Packaging Option
Option data sheets available. Contact Agilent sales representative or
authorized distributor for information.
These optocouplers are available
in an 8-pin DIP and industry
standard SO-8 package. The part
numbers are as follows:
8-pin DIP
HCPL-260L
HCPL-263L
SO-8 Package
HCPL-060L
HCPL-063L
Schematic
HCPL-260L/060L
HCPL-263L/063L
I
F
I
I
CC
I
CC
I
V
V
V
V
CC
CC
8
6
2+
8
7
1
+
I
F1
O
O1
O
O1
V
F1
–
2
V
F
–
3
GND
SHIELD
5
SHIELD
I
E
7
E
3
–
I
V
F2
I
O2
V
O2
6
5
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
V
F2
+
4
GND
SHIELD
2
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
1
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
2.54 ± 0.25
(0.100 ± 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED.
3
Small Outline SO-8 Package
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
3
PIN ONE
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSG
0.432
(0.017)
*
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
Solder Reflow Temperature Profile
(Surface Mount Option Parts)
Regulatory Information
The HCPL-260L/060L/263L/063L
are pending by the following
organizations:
260
240
220
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
UL
200
180
160
140
120
100
Approval (pending) under UL
1577, Component Recognition
Program, File E55361.
80
∆T = 100°C, 1.5°C/SEC
CSA
60
40
20
0
Approval (pending) under CSA
Component Acceptance Notice
#5, File CA 88324.
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
VDE
NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS HIGHLY RECOMMENDED.
Approval (pending) according to
VDE 0884/06.92.
4
Insulation and Safety Related Specifications
8-Pin DIP
(300 Mil)
Value
SO-8
Parameter
Symbol
Value Units Conditions
Minimum External Air
Gap (External Clearance)
Minimum External Tracking L (102)
(External Creepage)
Minimum Internal Plastic
Gap (Internal Clearance)
L (101)
7.1
4.9
mm
mm
mm
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
7.4
4.8
terminals, shortest distance path along body.
0.08
0.08
Through insulation distance, conductor to
conductor, usually the direct distance
between the photoemitter and photodetector
inside the optocoupler cavity.
Minimum Internal Tracking
(Internal Creepage)
Tracking Resistance
(Comparative Tracking
Index)
NA
200
NA
200
mm
Measured from input terminals to output
terminals, along internal cavity.
CTI
Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
VDE 0884 Insulation Related Characteristics
Description
Symbol
Characteristic Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
I-IV
I-III
for rated mains voltage ≤ 450 V rms
Climatic Classification
55/85/21
2
630
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
V
V
V
IORM
peak
V
IORM
x 1.875 = V , 100% Production Test with t = 1 sec,
1181
PR
m
PR
peak
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
x 1.5 = V , Type and Sample Test,
V
V
945
V
V
IORM
PR
PR
peak
t = 60 sec, Partial Discharge < 5 pC
m
Highest Allowable Overvoltage*
6000
IOTM
peak
(Transient Overvoltage, t = 10 sec)
ini
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
T
175
230
600
˚C
mA
mW
S
Input Current
Output Power
I
S,INPUT
P
R
S,OUTPUT
S
9
Insulation Resistance at T , V = 500 V
≥ 10
Ω
S
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
5
Absolute Maximum Ratings (No Derating Required up to 85˚C)
Parameter
Symbol
Package**
Min.
–55
–40
Max.
125
85
Units
˚C
˚C
Note
Storage Temperature
Operating Temperature†
Average Forward Input Current
T
T
S
A
I
Single 8-Pin DIP
Single SO-8
20
mA
2
F
Dual 8-Pin DIP
Dual SO-8
8-Pin DIP, SO-8
15
1, 3
1
Reverse Input Voltage
V
R
5
V
3
Input Power Dissipation
Supply Voltage (1 Minute Maximum)
Enable Input Voltage (Not to Exceed
P
V
V
40
7
mW
V
V
I
CC
E
Single 8-Pin DIP
Single SO-8
V
CC
+ 0.5
V
CC
by more than 500 mV)
Enable Input Current
I
I
V
P
5
50
7
mA
mA
V
E
Output Collector Current
Output Collector Voltage
Output Collector Power Dissipation
1
1
O
O
O
Single 8-Pin DIP
Single SO-8
85
mW
Dual 8-Pin DIP
Dual SO-8
60
1, 4
Lead Solder Temperature
(Through Hole Parts Only)
T
LS
8-Pin DIP
260˚C for 10 sec., 1.6 mm below
seating plane
260˚C for 10 sec., up to seating
plane
Solder Reflow Temperature Profile
(Surface Mount Parts Only)
SO-8
See Package Outline Drawings
section
**Ratings apply to all devices except otherwise noted in the Package column.
Recommended Operating Conditions
Parameter
Symbol
I *
Min.
0
5
2.7
0
2.0
–40
Max.
250
15
3.3
0.8
Units
µA
mA
V
V
V
Input Current, Low Level
Input Current, High Level
Power Supply Voltage
Low Level Enable Voltage
High Level Enable Voltage
FL
[1]
I
**
FH
V
V
V
CC
EL
EH
A
V
CC
Operating Temperature
Fan Out (at R = 1 kΩ)
T
85
5
˚C
[1]
N
TTL Loads
L
Output Pull-up Resistor
R
L
330
4 k
Ω
*The off condition can also be guaranteed by ensuring that V ≤ 0.8 volts.
FL
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used
for best performance and to permit at least a 20% LED degradation guardband.
6
Electrical Specifications
Over Recommended Temperature (T = –40˚C to +85˚C) unless otherwise specified. All Typicals at V = 3.3 V,
A
CC
T = 25˚C. All enable test conditions apply to single channel products only. See Note 5.
A
Parameter
Sym.
Min. Typ.
Max. Units Test Conditions
Fig.
Note
High Level Output Current
I
*
4.5
50
µA
V
= 3.3 V, V = 2.0 V,
1
1, 15
OH
CC
E
V = 3.3 V, I = 250 µA
O
F
Input Threshold Current
Low Level Output Voltage
I
3.0
5.0
mA
V
= 3.3 V, V = 2.0 V,
2
3
15
15
TH
CC
E
V = 0.6 V,
O
I
(Sinking) = 13 mA
= 3.3 V, V = 2.0 V,
OL
V
*
0.35
0.6
V
V
OL
CC E
I = 5 mA,
F
I
(Sinking) = 13 mA
OL
High Level Supply Current
Low Level Supply Current
I
I
I
4.7
7.0
7.0
mA
mA
V = 0.5 V
V
= 3.3 V
CCH
CCL
EH
E
CC
I = 0 mA
F
10.0
V = 0.5 V
E
V
CC
= 3.3 V
I = 10 mA
F
High Level Enable Current
Low Level Enable Current
High Level Enable Voltage
Low Level Enable Voltage
Input Forward Voltage
–0.5
–0.5
2.0
–1.2
–1.2
mA
mA
V
V
V
V
CC
V
CC
= 3.3 V, V = 2.0 V
E
= 3.3 V, V = 0.5 V
E
I *
EL
V
V
V
15
EH
EL
F
0.8
1.75*
1.4
5
1.5
T = 25˚C I = 10 mA
5
1
1
A
F
Input Reverse Breakdown
Voltage
BV *
V
I = 10 µA
R
R
Input Diode Temperature
Coefficient
∆V /
–1.6
mV˚C I = 10 mA
1
F
F
∆T
A
–1.9
60
Input Capacitance
C
IN
pF
f = 1 MHz, V = 0 V
F
1
*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.
7
Switching Specifications
Over Recommended Temperature (T = –40˚C to +85˚C), V = 3.3 V, I = 7.5 mA unless otherwise specified. All Typicals
A
CC
F
at T = 25˚C, V = 3.3 V.
A
CC
Parameter
Sym.
Package** Min. Typ. Max. Units Test Conditions
Fig.
Note
Propagation Delay
Time to High Output
Level
Propagation Delay
Time to Low Output
Level
t
90
ns
T = 25˚C
A
R = 350 Ω 6, 7, 8 1, 6, 15
C = 15 pF
L
PLH
PHL
L
t
75
ns
1, 7, 15
Pulse Width
Distortion
Propagation Delay
Skew
Output Rise Time
(10-90%)
Output Fall Time
(90-10%)
|t
– t | 8-Pin DIP
25
40
ns
ns
ns
ns
ns
8
9
9, 15
8, 9, 15
1, 15
1, 15
10
PHL
PSK
r
PLH
SO-8
t
t
t
t
45
20
45
f
Propagation Delay
Time of Enable from
R = 350 Ω,
L
C = 15 pF,
L
ELH
V
EH
tp V
V = 0 V, V = 3 V
EL EH
EL
Propagation Delay
Time of Enable from
t
30
ns
11
EHL
V
EL
to V
EH
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter Sym.
Device
Min. Typ.
Units Test Conditions
Fig. Note
Logic High |CM | HCPL-263L 15,000 25,000 V/µs |V | = 10 V
V
= 3.3 V, I = 0 mA,
11
12, 14, 15
H
CM
CC
F
Common
Mode
HCPL-063L
V
= 2 V,
O(MIN)
R = 350 Ω, T = 25˚C
L
A
Transient
Immunity
HCPL-260L 15,000 25,000
HCPL-060L
|V | = 50 V
CM
Logic Low
Common
Mode
Transient
Immunity
|CM | HCPL-263L 15,000 25,000 V/µs |V | = 10 V
V
V
= 3.3 V, I = 7.5 mA,
11
13, 14, 15
L
CM
CC
F
HCPL-063L
= 0.8 V,
O(MAX)
R = 350 Ω, T = 25˚C
L
A
HCPL-260L 15,00 25,000
HCPL-060L
|V | = 50 V
CM
8
Package Characteristics
All Typicals at T = 25˚C.
A
Parameter
Input-Output
Insulation
Sym. Package
Min. Typ. Max
Units Test Conditions
µA 45% RH, t = 5 s,
= 3 kV DC, T = 25˚C
Fig. Note
16, 17
I
*
Single 8-Pin DIP
Single SO-8
1
I-O
V
I-O
A
Input-Output
Momentary
Withstand
Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation
Leakage
Current
V
8-Pin DIP, SO-8
2500
V rms RH ≤ 50%, t = 1 min,
T = 25˚C
16, 17
ISO
A
12
R
C
8-Pin, SO-8
10
Ω
V
I-O
=500 V dc
1, 16, 19
1, 16, 19
20
I-O
8-Pin DIP, SO-8
Dual Channel
0.6
pF
µA
f = 1 MHz, T = 25˚C
I-O
A
I
0.005
RH ≤ 45%, t = 5 s,
I-I
V
I-I
= 500 V
11
Resistance
(Input-Input)
Capacitance
(Input-Input)
R
C
Dual Channel
10
Ω
20
20
I-I
Dual 8-Pin Dip
Dual SO-8
0.03
0.25
pG
f = 1 MHz
I-I
*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level
safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The t
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
PLH
of the output pulse.
7. The t
of the output pulse.
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
PHL
8. t
is equal to the worst case difference in t
and/or t
that will be seen between units at any given temperature and specified test
PSK
conditions.
PHL
PLH
9. See test circuit for measurement details.
10. The t
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
ELH
rising edge of the output pulse.
11. The t
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
ELH
falling edge of the output pulse.
12. CM is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
H
(i.e., V > 2.0 V).
o
13. CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
L
(i.e., V < 0.8 V).
14. For sinusoidal voltages, (|dV | / dt)
o
= πf
V
(p-p).
CM
max
CM CM
15. No external pull up is required for a high logic state on the enable input. If the V pin is not used, tying V to V will result in improved
E
E
CC
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second (leakage
detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
I-O
VDE 0884 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage
detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
I-O
VDE 0884 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
9
8-PIN DIP, SO-8
= 3.3 V
8-PIN DIP, SO-8
15
10
12
10
0.8
0.7
V
V
V
V
= 3.3 V * FOR SINGLE
CC
CC
= 0.6 V
V
V
V
= 3.3 V
= 3.3 V
= 2.0 V*
= 250 µA
CC
O
E
= 2.0 V*
= 5.0 mA
CHANNEL
PRODUCTS ONLY
O
E
I
F
0.6
0.5
0.4
0.3
0.2
I
F
8
6
4
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
R
= 350 Ω
L
R
= 1 KΩ
L
I
= 13 mA
O
5
0
2
0
0.1
0
R
= 4 KΩ
L
0
20 40
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40
80 100
-60 -40 -20
80 100
60
60
T
– TEMPERATURE – °C
A
T
– TEMPERATURE – °C
A
T
– TEMPERATURE – °C
A
Figure 1. Typical high level output current vs.
temperature.
Figure 2. Typical input threshold current vs.
temperature.
Figure 3. Typical low level output voltage vs.
temperature.
8-PIN DIP, SO-8
1000
70
V
V
V
= 3.3 V
= 2.0 V*
= 0.6 V
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
CC
E
OL
T
= 25 °C
A
100
10
I
F
60
50
+
F
V
–
1.0
I
= 5.0 mA
F
0.1
0.01
40
20
0.001
1.1
1.2
1.3
1.4
1.5
1.6
-60 -40 -20
0
20 40
80 100
60
V
– FORWARD VOLTAGE – V
F
T
– TEMPERATURE – °C
A
Figure 4. Typical low level output current vs.
temperature.
Figure 5. Typical input diode forward
characteristic.
PULSE GEN.
= 50 Ω
Z
O
t = t = 5 ns
f
r
SINGLE CHANNEL
DUAL CHANNEL
3.3 V
3.3 V
I
F
I
F
PULSE GEN.
= 50 Ω
V
V
1
2
3
4
8
7
6
5
1
2
3
4
8
CC
CC
Z
O
R
L
t
= t = 5 ns
r
f
INPUT
MONITORING
NODE
OUTPUT V
O
MONITORING
NODE
0.1 µF
BYPASS
R
7
6
5
L
0.1 µF
BYPASS
OUTPUT V
MONITORING
NODE
INPUT
MONITORING
NODE
O
*C
L
R
C *
L
M
R
M
GND
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
I
I
= 7.50 mA
= 3.75 mA
F
INPUT
F
I
F
t
t
PLH
PHL
OUTPUT
V
O
1.5 V
Figure 6. Test circuit for t
and t
.
PLH
PHL
10
150
120
50
40
30
20
10
0
V
= 3.3 V
CC
= 7.5 mA
V
= 3.3 V
CC
= 7.5 mA
I
F
I
F
t
, R = 350 Ω
L
PLH
90
60
R
= 350 Ω
L
t
, R = 350 Ω
L
PHL
30
0
-60
-40 -20
0
20 40
80 100
-60 -40 -20
0
20 40
80 100
60
60
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 7. Typical propagation delay vs.
temperature.
Figure 8. Typical pulse width distortion vs.
temperature.
PULSE GEN.
Z
= 50 Ω
r
O
t = t = 5 ns
f
INPUT V
MONITORING NODE
E
+3.3 V
V
3.0 V
1.5 V
1
2
3
4
8
7
6
5
CC
INPUT
V
7.5 mA
E
0.1 µF
BYPASS
R
L
I
F
t
t
ELH
EHL
OUTPUT V
MONITORING
NODE
O
OUTPUT
V
O
1.5 V
*C
L
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
Figure 9. Test circuit for t
and t
.
EHL
ELH
I
F
SINGLE CHANNEL
DUAL CHANNEL
V
B
A
I
F
V
+3.3 V
+3.3 V
1
2
3
4
8
1
2
3
4
8
7
6
5
CC
CC
R
B
A
L
OUTPUT V
MONITORING
NODE
O
0.1 µF
BYPASS
R
7
6
5
L
V
FF
OUTPUT V
MONITORING
NODE
O
V
0.1 µF
BYPASS
FF
GND
GND
V
V
CM
CM
+
–
+
–
PULSE
GENERATOR
PULSE
GENERATOR
= 50 Ω
Z
= 50 Ω
Z
O
O
V
(PEAK)
(MIN.)
CM
V
CM
0 V
SWITCH AT A: I = 0 mA
F
3.3 V
CM
H
V
V
O
V
O
SWITCH AT B: I = 7.5 mA
F
V
(MAX.)
O
O
0.5 V
CM
L
Figure 10. Test circuit for common mode transient immunity and typical waveforms.
11
GND BUS (BACK)
V
BUS (FRONT)
NC
CC
ENABLE
OUTPUT
0.1µF
NC
10 mm MAX.
(SEE NOTE 5)
SINGLE CHANNEL
DEVICE ILLUSTRATED.
Figure 11. Recommended printed circuit board layout.
SINGLE CHANNEL DEVICE
3.3 V
3.3 V
8
6
V
CC1
V
CC2
R
L
220 Ω
I
F
+
2
3
D1*
V
0.1 µF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
V
E
7
1
2
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
3.3 V
3.3 V
8
7
V
CC1
V
CC2
R
L
220 Ω
I
F
+
1
2
D1*
V
0.1 µF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
1
2
Figure 12. Recommended LVTTL interface circuit.
12
Application Information
Common-Mode Rejection for
HCPL-260L Families:
Figure 13 shows the recom-
mended drive circuit for optimal
common-mode rejection
performance. Two main points to
note are:
*
1
HCPL-260L
8
7
V
V
V
CC
CC+
0.01 µF
220 Ω
220 Ω
350 Ω
2
3
4
6
5
O
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
GND
SHIELD
*
1. The enable pin is tied to VCC
rather than floating (this
applies to single-channel parts
only).
GND1
GND2
* HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
2. Two LED-current setting
resistors are used instead of
one. This is to balance ILED
variation during common-
mode transients.
Figure 13. Recommended drive circuit for High-CMR.
1
2
8
7
V
V
+
CC
If the enable pin is left floating, it
is possible for common-mode
transients to couple to the enable
pin, resulting in common-mode
failure. This failure mechanism
only occurs when the LED is on
and the output is in the Low
State. It is identified as occurring
when the transient output voltage
rises above 0.8 V. Therefore, the
enable pin should be connected
to either VCC or logic-level high
for best common-mode
1/2 R
1/2 R
0.01 µF
LED
350 Ω
I
LP
LED
C
I
LA
LN
3
4
6
5
O
15 pF
C
LC
GND
SHIELD
+
–
V
CM
Figure 14. AC equivalent circuit.
performance with the output low
(CMRL). This failure mechanism
is only present in single-channel
parts which have the enable
function.
For transients occurring when the
LED is on, common-mode rejec-
tion (CMRL, since the output is in
the “low” state) depends upon the
amount of LED current drive (IF).
For conditions where IF is close
to the switching threshold (ITH),
CMRL also depends on the extent
which ILP and ILN balance each
other. In other words, any
condition where common-mode
transients cause a momentary
decrease in IF will cause
common-mode failure for
transients which are fast enough.
output is “high”), if an imbalance
between ILP and ILN results in a
transient IF equal to or greater
than the switching threshold of
the optocoupler, the transient
“signal” may cause the output to
spike below 2 V (which consti-
tutes a CMRH failure).
Also, common-mode transients
can capacitively couple from the
LED anode (or cathode) to the
output-side ground causing
current to be shunted away from
the LED (which can be bad if the
LED is on) or conversely cause
current to be injected into the
LED (bad if the LED is meant to
be off). Figure 14 shows the
parasitic capacitances which
exists between LED
By using the recommended
circuit in Figure 13, good CMR
can be achieved. The balanced
ILED-setting resistors help equalize
ILP and ILN to reduce the amount
by which ILED is modulated from
transient coupling through CLA
and CLC.
anode/cathode and output ground
(CLA and CLC). Also shown in
Figure 14 on the input side is an
AC-equivalent circuit.
Likewise for common-mode
transients which occur when the
LED is off (i.e. CMRH, since the
13
V
CMR with Other Drive
Circuits
CC
HCPL-260L
CMR performance with drive
circuits other than that shown in
Figure 13 may be enhanced by
following these guidelines:
1
2
420 Ω
(MAX)
2N3906
(ANY PNP)
74L504
(ANY
LED
1. Use of drive circuits where
current is shunted from the
LED in the LED “off” state (as
shown in Figures 15 and 16).
This is beneficial for good
CMRH.
TTL/CMOS
GATE)
3
4
2. Use of IFH > 3.5 mA. This is
good for high CMRL.
Figure 15. TTL interface circuit.
Figure 15 shows a circuit which
can be used with any totem-pole-
output TTL/LSTTL/HCMOS logic
gate. The buffer PNP transistor
allows the circuit to be used with
logic devices which have low
current-sinking capability. It also
helps maintain the driving-gate
power-supply current at a
V
CC
HCPL-260L
1
2
R
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
LED
3
4
LOGIC GATE)
constant level to minimize ground
shifting for other devices
connected to the input-supply
ground.
Figure 16. TTL open-collector/open drain gate drive circuit.
When using an open-collector
TTL or open-drain CMOS logic
gate, the circuit in Figure 16 may
be used. When using a CMOS
gate to drive the optocoupler, the
circuit shown in Figure 17 may
be used. The diode in parallel
with the RLED speeds the turn-off
of the optocoupler LED.
V
CC
HCPL-260L
1N4148
1
2
220 Ω
74HC04
(OR ANY
LED
TOTEM-POLE
OUTPUT LOGIC
GATE)
3
4
Figure 17. CMOS gate drive circuit.
14
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
5980-2523EN (11/00)
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