HCPL-2631300 [AGILENT]
2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10 Mbps, 0.300 INCH, SURFACE MOUNT, DIP-8;
| 型号： | HCPL-2631300 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10 Mbps, 0.300 INCH, SURFACE MOUNT, DIP-8 输出元件 |
| 文件： | 总20页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High CMR, High Speed TTL
Compatible Optocouplers
6N137
HCNW137
HCPL-0631
HCNW2601 HCPL-0661
HCNW2611 HCPL-2601
HCPL-0600 HCPL-2611
HCPL-0601 HCPL-2630
HCPL-0611 HCPL-2631
HCPL-0630 HCPL-4661
Technical Data
Applications
• Isolated Line Receiver
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
• Digital Isolation for A/D,
D/A Conversion
• Switching Power Supply
• Instrument Input/Output
Isolation
• Ground Loop Elimination
Features
• Power Transistor Isolation
in Motor Drives
• Isolation of High Speed
Logic Systems
• 5 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 50 V for HCPL-X601/
X631, HCNW2601 and
10 kV/µs Minimum CMR at
VCM = 1000 V for HCPL-
X611/X661, HCNW2611
• High Speed: 10 MBd Typical
• LSTTL/TTL Compatible
• Low Input Current
Capability: 5 mA
• Guaranteed ac and dc
Performance over Temper-
ature: -40°C to +85°C
• Available in 8-Pin DIP,
SOIC-8, Widebody Packages
Description
The 6N137, HCPL-26XX/06XX/
4661, HCNW137/26X1 are
optically coupled gates that
combine a GaAsP light emitting
diode and an integrated high gain
photo detector. An enable input
allows the detector to be strobed.
The output of the detector IC is
• Pulse Transformer
Replacement
• Strobable Output (Single
Channel Products Only)
• Safety Approval
Functional Diagram
6N137, HCPL-2601/2611
HCPL-0600/0601/0611
HCPL-2630/2631/4661
HCPL-0630/0631/0661
UL Recognized - 3750 V rms
for 1 minute and 5000 V rms*
for 1 minute per UL1577
CSA Approved
IEC/EN/DIN EN 60747-5-2
Approved with
1
2
V
V
V
ANODE
CATHODE
CATHODE
ANODE
1
2
V
V
8
7
8
7
NC
CC
CC
O1
O2
1
1
ANODE
E
V
CATHODE
NC
3
4
6
5
3
4
6
5
O
2
2
GND
GND
SHIELD
SHIELD
V
IORM = 630 V peak for
HCPL-2611 Option 060 and
VIORM = 1414 V peak for
TRUTH TABLE
TRUTH TABLE
(POSITIVE LOGIC)
(POSITIVE LOGIC)
HCNW137/26X1
LED ENABLE OUTPUT
LED OUTPUT
• MIL-PRF-38534 Hermetic
Version Available (HCPL-
56XX/66XX)
ON
H
H
L
L
NC
NC
L
H
H
H
L
ON
OFF
L
H
OFF
ON
OFF
ON
OFF
H
*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only.
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
2
an open collector Schottky-
clamped transistor. The internal
shield provides a guaranteed
common mode transient
immunity specification of 5,000
V/µs for the HCPL-X601/X631
and HCNW2601, and 10,000 V/µs
for the HCPL-X611/X661 and
HCNW2611.
This unique design provides
maximum ac and dc circuit
isolation while achieving TTL
compatibility. The optocoupler ac
and dc operational parameters
are guaranteed from -40°C to
+85°C allowing troublefree
system performance.
The 6N137, HCPL-26XX, HCPL-
06XX, HCPL-4661, HCNW137,
and HCNW26X1 are suitable for
high speed logic interfacing,
input/output buffering, as line
receivers in environments that
conventional line receivers
cannot tolerate and are recom-
mended for use in extremely high
ground or induced noise
environments.
Selection Guide
Widebody
Minimum CMR
Input
8-Pin DIP (300 Mil)
Small-Outline SO-8
(400 Mil)
Hermetic
Single
On-
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
and Dual
Channel
Packages
dV/dt
V
CM
Current Output
(mA)
(V/µs)
(V)
Enable
YES
NO
NA
NA
5
6N137
HCPL-0600
HCPL-0601
HCPL-0611
HCNW137
HCNW2601
HCNW2611
HCPL-2630
HCPL-2631
HCPL-4661
HCPL-0630
HCPL-0631
HCPL-0661
5,000
50
YES
NO
HCPL-2601
HCPL-2611
10,000 1,000
YES
NO
[1]
1,000
3, 500
1,000
50
300
50
YES
YES
YES
NO
HCPL-2602
HCPL-2612
HCPL-261A
[1]
[1]
[1]
3
HCPL-061A
[1]
[1]
HCPL-263A
HCPL-063A
[2]
[1]
[1]
1,000
1,000
50
YES
HCPL-261N
HCPL-061N
[1]
[1]
NO
[3]
HCPL-263N
HCPL-063N
[1]
1,000
12.5
HCPL-193X
HCPL-56XX
HCPL-66XX
[1]
[1]
Notes:
1. Technical data are on separate Agilent publications.
2. 15 kV/µs with VCM = 1 kV can be achieved using Agilent application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
3
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2611#XXXX
020 = 5000 V rms/1 minute UL Rating Option*
060 = IEC/EN/DIN EN 60747-5-2 VIORM = 630 Vpeak Option**
300 = Gull Wing Surface Mount Option†
500 = Tape and Reel Packaging Option
XXXE = Lead Free Option
Option data sheets available. Contact Agilent sales representative or authorized distributor for information.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July
2001 and lead free option will use “-”
*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only.
**For HCPL-2611 only. Combination of Option 020 and Option 060 is not available.
†Gull wing surface mount option applies to through hole parts only.
Schematic
HCPL-2630/2631/4661
HCPL-0630/0631/0661
6N137, HCPL-2601/2611
I
CC
I
HCPL-0600/0601/0611
HCNW137, HCNW2601/2611
V
V
CC
O1
8
7
I
1
+
F
I
I
F1
CC
V
V
O1
CC
O
8
6
2+
I
O
V
F1
–
2
V
SHIELD
F
–
3
3
GND
I
5
SHIELD
I
O2
V
–
E
7
E
O2
6
5
V
V
F2
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
+
4
I
F2
GND
SHIELD
4
Package Outline Drawings
8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
3.56 ± 0.13
(0.140 ± 0.005)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
2.54 ± 0.25
(0.100 ± 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED.
**JEDEC Registered Data (for 6N137 only).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
8-pin DIP Package with Gull Wing Surface Mount Option 300
(6N137, HCPL-2601/11/30/31, HCPL-4661)
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
1.016 (0.040)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2.0 (0.080)
2
3
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
5
Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
3
PIN ONE
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
(0.017)
*
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)
11.00
MAX.
11.15 ± 0.15
(0.442 ± 0.006)
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
7
6
5
8
TYPE NUMBER
DATE CODE
A
HCNWXXXX
YYWW
1
3
2
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
- 0.0051
0.254
+ 0.003)
- 0.002)
(0.010
5.10
(0.201)
MAX.
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
6
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300
(HCNW137, HCNW2601/11)
11.15 ± 0.15
(0.442 ± 0.006)
LAND PATTERN RECOMMENDATION
7
6
5
8
9.00 ± 0.15
(0.354 ± 0.006)
13.56
(0.534)
1
3
2
4
2.29
1.3
(0.09)
(0.051)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00
MAX.
(0.433)
4.00
MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
+ 0.076
- 0.0051
2.54
(0.100)
BSC
0.254
+ 0.003)
- 0.002)
(0.010
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
7
Recommended Pb-free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
t
p
20-40 SEC.
260 +0/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
Regulatory Information
The 6N137, HCPL-26XX/06XX/
46XX, and HCNW137/26XX have
been approved by the following
organizations:
UL
IEC/EN/DIN EN 60747-5-2
Approved under
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
Recognized under UL 1577,
Component Recognition Program,
File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
(Option 060 and HCNW only)
Insulation and Safety Related Specifications
8-pin DIP
Widebody
(300 Mil) SO-8 (400 Mil)
Parameter
Symbol
Value
Value
Value
Units
Conditions
Minimum External
Air Gap (External
Clearance)
L(101)
7.1
4.9
9.6
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External
Tracking (External
Creepage)
Minimum Internal
Plastic Gap
L(102)
7.4
4.8
10.0
1.0
mm
mm
Measured from input terminals
to output terminals, shortest
distance path along body.
Through insulation distance,
conductor to conductor, usually
the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
0.08
0.08
(Internal Clearance)
Minimum Internal
Tracking (Internal
Creepage)
Tracking Resistance
(Comparative
Tracking Index)
Isolation Group
NA
200
IIIa
NA
200
IIIa
4.0
200
IIIa
mm
Measured from input terminals
to output terminals, along
internal cavity.
CTI
Volts DIN IEC 112/VDE 0303 Part 1
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
8
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
(HCPL-2611 Option 060 Only)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
Symbol Characteristic Units
I-IV
I-III
55/85/21
2
V
630
Vpeak
Vpeak
IORM
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
1181
945
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
Vpeak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
6000
Vpeak
IOTM
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
RS
175
230
600
≥ 109
°C
mA
mW
Ω
Insulation Resistance at TS, V = 500 V
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN
60747-5-2, for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics(HCNW137/2601/2611 Only)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
Symbol Characteristic Units
I-IV
I-III
for rated mains voltage ≤ 1000 V rms
Climatic Classification (DIN IEC 68 part 1)
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
55/100/21
2
V
1414
Vpeak
Vpeak
IORM
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
2651
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and sample test,
2121
8000
Vpeak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
Vpeak
IOTM
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
TS
IS,INPUT
PS,OUTPUT
150
400
700
≥ 109
°C
mA
mW
Input Current
Output Power
Insulation Resistance at TS, V = 500 V
RS
Ω
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN
60747-5-2, for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
9
Absolute Maximum Ratings* (No Derating Required up to 85°C)
Parameter
Storage Temperature
Operating Temperature†
Average Forward Input Current
Symbol
Package**
Min.
-55
-40
Max.
125
85
Units
°C
°C
Note
T
S
T
A
F
I
Single 8-Pin DIP
Single SO-8
Widebody
20
mA
2
Dual 8-Pin DIP
Dual SO-8
8-Pin DIP, SO-8
Widebody
15
1, 3
1
Reverse Input Voltage
V
R
5
3
V
Input Power Dissipation
Supply Voltage
P
V
CC
Widebody
40
7
mW
V
I
(1 Minute Maximum)
Enable Input Voltage (Not to
V
E
Single 8-Pin DIP
Single SO-8
Widebody
V
CC
+ 0.5
V
Exceed V by more than
CC
500 mV)
Enable Input Current
Output Collector Current
Output Collector Voltage
I
5
50
7
mA
mA
V
E
I
1
1
O
V
O
Output Collector Power
Dissipation
P
O
Single 8-Pin DIP
Single SO-8
Widebody
85
mW
Dual 8-Pin DIP
Dual SO-8
60
1, 4
Lead Solder Temperature
(Through Hole Parts Only)
T
8-Pin DIP
260°C for 10 sec.,
1.6 mm below seating plane
LS
Widebody
260°C for 10 sec.,
up to seating plane
Solder Reflow Temperature
Profile (Surface Mount Parts Only)
SO-8 and
Option 300
See Package Outline
Drawings section
*JEDEC Registered Data (for 6N137 only).
**Ratings apply to all devices except otherwise noted in the Package column.
†0°C to 70°C on JEDEC Registration.
Recommended Operating Conditions
Parameter
Input Current, Low Level
Symbol
IFL*
IFH**
VCC
Min.
0
5
4.5
0
2.0
-40
Max.
250
15
5.5
0.8
VCC
85
Units
µA
mA
V
Input Current, High Level[1]
Power Supply Voltage
Low Level Enable Voltage†
High Level Enable Voltage†
Operating Temperature
Fan Out (at RL = 1 kΩ)[1]
Output Pull-up Resistor
VEL
VEH
TA
N
RL
V
V
°C
TTL Loads
Ω
5
4 k
330
*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit
at least a 20% LED degradation guardband.
†For single channel products only.
10
Electrical Specifications
Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. All Typicals at VCC = 5 V,
TA = 25°C. All enable test conditions apply to single channel products only. See note 5.
Parameter
Sym.
Package
Min.
Typ. Max. Units
Test Conditions
Fig. Note
High Level Output IOH
Current
*
All
5.5
100
µA
V
CC = 5.5 V, VE = 2.0 V,
1
1, 6,
19
V = 5.5 V, IF = 250 µA
O
Input Threshold
Current
ITH Single Channel
Widebody
2.0
5.0
mA
V
CC = 5.5 V, VE = 2.0 V, 2, 3
19
VO = 0.6 V,
Dual Channel
2.5
IOL (Sinking) = 13 mA
Low Level Output
Voltage
VOL*
8-Pin DIP
SO-8
0.35
0.6
V
VCC = 5.5 V, VE = 2.0 V, 2, 3, 1, 19
IF = 5 mA,
4, 5
Widebody
0.4
IOL (Sinking) = 13 mA
High Level Supply ICCH Single Channel
Current
7.0
6.5
10
10.0*
15
mA
VE = 0.5 V VCC = 5.5 V
7
8
VE = VCC
Both
IF = 0 mA
Dual Channel
Channels
Low Level Supply
Current
ICCL Single Channel
Dual Channel
9.0
8.5
13
13.0*
21
mA
VE = 0.5 V VCC = 5.5 V
VE = VCC
Both
IF = 10 mA
Channels
High Level Enable
Current
IEH Single Channel
-0.7
-0.9
-1.6
-1.6
mA
mA
V
VCC = 5.5 V, VE = 2.0 V
VCC = 5.5 V, VE = 0.5 V
Low Level Enable
Current
IEL*
9
High Level Enable
Voltage
VEH
VEL
VF
2.0
19
Low Level Enable
Voltage
0.8
V
Input Forward
Voltage
8-Pin DIP
SO-8
1.4
1.3
1.25
1.2
1.5
1.75*
1.80
1.85
2.05
V
TA = 25°C IF = 10 mA 6, 7
TA = 25°C
1
Widebody
1.64
Input Reverse
Breakdown
Voltage
BVR*
8-Pin DIP
SO-8
Widebody
5
V
IR = 10 µA
1
1
1
3
IR = 100 µA, TA = 25°C
Input Diode
Temperature
Coefficient
∆VF/
∆TA
8-Pin DIP
SO-8
Widebody
-1.6
mV/°C IF = 10 mA
7
-1.9
60
Input Capacitance
CIN
8-Pin DIP
SO-8
pF
f = 1 MHz, VF = 0 V
Widebody
70
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.
11
Switching Specifications (AC)
Over Recommended Temperature (TA = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
All Typicals at TA = 25°C, VCC = 5 V.
Parameter
Sym.
Package**
Min. Typ. Max. Units
Test Conditions
Fig. Note
Propagation Delay
Time to High
tPLH
20
48
75*
100
ns TA = 25°C RL = 350 Ω 8, 9, 1, 10,
CL = 15 pF 10
19
Output Level
Propagation Delay
Time to Low
tPHL
25
50
75*
100
ns TA = 25°C
1, 11,
19
Output Level
Pulse Width
Distortion
|tPHL - tPLH
|
8-Pin DIP
SO-8
Widebody
3.5
35
ns
8, 9, 13, 19
10,
11
40
40
Propagation Delay
Skew
tPSK
tr
ns
ns
ns
12, 13,
19
Output Rise
Time (10-90%)
24
10
30
12
12
1, 19
1, 19
14
Output Fall
Time (90-10%)
tf
Propagation Delay
Time of Enable
from VEH to VEL
tELH
Single Channel
Single Channel
ns RL = 350 Ω,
13,
14
CL = 15 pF,
VEL = 0 V, VEH = 3 V
Propagation Delay
Time of Enable
from VEL to VEH
tEHL
20
ns
15
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter Sym.
Device
Min.
Typ. Units
Test Conditions
Fig. Note
Logic High |CMH| 6N137
10,000 V/µs |VCM| = 10 V VCC = 5 V, IF = 0 mA,
VO(MIN) = 2 V,
15
1, 16,
18, 19
Common
Mode
Transient
Immunity
HCPL-2630
HCPL-0600/0630
HCNW137
HCPL-2601/2631
HCPL-0601/0631
HCNW2601
RL = 350 Ω, TA = 25°C
5,000 10,000
|VCM| = 50 V
|VCM| = 1 kV
HCPL-2611/4661 10,000 15,000
HCPL-0611/0661
HCNW2611
Logic Low
Common
Mode
Transient
Immunity
|CML| 6N137
HCPL-2630
10,000 V/µs |VCM| = 10 V VCC = 5 V, IF = 7.5 mA,
VO(MAX) = 0.8 V,
15
1, 17,
18, 19
HCPL-0600/0630
HCNW137
HCPL-2601/2631
HCPL-0601/0631
HCNW2601
HCPL-2611/4661 10,000 15,000
HCPL-0611/0661
HCNW2611
RL = 350 Ω, TA = 25°C
5,000 10,000
|VCM| = 50 V
|VCM| = 1 kV
12
Package Characteristics
All Typicals at TA = 25°C.
Parameter
Sym.
II-O
Package
Min. Typ. Max. Units
Test Conditions
Fig. Note
Input-Output
Insulation
*
Single 8-Pin DIP
Single SO-8
1
µA
45% RH, t = 5 s,
I-O = 3 kV dc, T = 25°C
20, 21
V
A
Input-Output
Momentary With-
stand Voltage**
VISO
8-Pin DIP, SO-8 3750
V rms RH ≤ 50%, t = 1 min,
TA = 25°C
20, 21
20, 22
Widebody
5000
5000
OPT 020†
Input-Output
Resistance
RI-O
8-Pin DIP, SO-8
Widebody
1012
1013
Ω
VI-O = 500 V dc
1, 20,
23
1012
1011
TA = 25°C
TA = 100°C
Input-Output
Capacitance
CI-O
II-I
8-Pin DIP, SO-8
Widebody
0.6
0.5
pF
f = 1 MHz, TA = 25°C
1, 20,
23
0.6
Input-Input
Dual Channel
0.005
µA
RH ≤ 45%, t = 5 s,
24
Insulation
VI-I = 500 V
Leakage Current
Resistance
(Input-Input)
RI-I
CI-I
Dual Channel
1011
Ω
24
24
Capacitance
(Input-Input)
Dual 8-Pin DIP
Dual SO-8
0.03
0.25
pF
f = 1 MHz
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. Agilent specifies -40°C to 85°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table
(if applicable), your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output
Endurance Voltage.”
†For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does
not exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does
not exceed 15 mA.
4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 µA. Agilent guarantees a maximum IOH of 100 µA.
7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. Agilent guarantees a maximum ICCH of 10 mA.
8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. Agilent guarantees a maximum ICCL of 13 mA.
9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. Agilent guarantees a maximum IEL of -1.6 mA.
10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified
test conditions.
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V
point on the rising edge of the output pulse.
15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point
on the falling edge of the output pulse.
16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., VO > 2.0 V).
17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., VO < 0.8 V).
18. For sinusoidal voltages, (|dVCM | / dt)max = π fCMVCM(p-p).
13
19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in
improved CMR performance. For single channel products only.
20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second
(leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge
(Method b) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second
(leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge
(Method b) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products
only.
24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
8-PIN DIP, SO-8
WIDEBODY
6
6
15
10
V
T
= 5 V
V
= 5 V
V
V
V
= 5.5 V
= 5.5 V
= 2.0 V*
= 250 µA
CC
= 25 °C
CC
T = 25 °C
A
CC
O
E
A
5
4
3
2
5
4
3
2
I
F
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
R
= 350 Ω
= 1 KΩ
R
= 350 Ω
= 1 KΩ
L
L
R
R
L
L
5
0
R
= 4 KΩ
R = 4 KΩ
L
L
1
0
1
0
-60 -40 -20
0
20 40 60 80 100
0
1
2
3
I – FORWARD INPUT CURRENT – mA
F
4
6
0
1
2
3
4
6
5
5
T
– TEMPERATURE – °C
I
– FORWARD INPUT CURRENT – mA
A
F
Figure 1. Typical High Level Output
Current vs. Temperature.
Figure 2. Typical Output Voltage vs. Forward Input Current.
8-PIN DIP, SO-8
6
WIDEBODY
6
V
V
= 5.0 V
V
V
= 5.0 V
CC
CC
= 0.6 V
= 0.6 V
O
O
5
4
3
2
5
4
3
2
R
= 350 Ω
L
R
= 1 KΩ
R
= 350 Ω
= 4 KΩ
L
L
R
= 1 KΩ
L
1
0
1
0
R
= 4 KΩ
R
L
L
-60 -40 -20
0
20 40
80 100
60
-60 -40 -20
0
20 40
80 100
60
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 3. Typical Input Threshold Current vs. Temperature.
14
8-PIN DIP, SO-8
WIDEBODY
0.8
0.7
70
60
50
0.8
0.7
V
V
I
= 5.5 V * FOR SINGLE
V
V
I
= 5.5 V
V
V
V
= 5.0 V
= 2.0 V*
= 0.6 V
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
CC
E
F
CC
= 2.0 V
F
CC
E
OL
= 2.0 V*
= 5.0 mA
CHANNEL
PRODUCTS ONLY
E
= 5.0 mA
0.6
0.5
0.4
0.3
0.2
0.6
0.5
0.4
0.3
0.2
I
= 16 mA
O
I
= 10-15 mA
F
I
= 16 mA
= 9.6 mA
I
= 12.8 mA
O
O
I
= 12.8 mA
= 6.4 mA
O
I
I
= 9.6 mA
I = 6.4 mA
O
O
I
O
I
= 5.0 mA
F
40
20
O
0.1
0
0.1
0
-60 -40 -20
0
20 40
80 100
60
-60 -40 -20
0
20 40
80 100
-60 -40 -20
0
20 40
80 100
60
60
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
A
Figure 4. Typical Low Level Output Voltage vs. Temperature.
Figure 5. Typical Low Level Output
Current vs. Temperature.
8-PIN DIP, SO-8
T
WIDEBODY
1000
1000
= 25 °C
T = 25 °C
A
A
100
10
100
10
I
I
F
+
V
F
F
+
F
V
–
–
1.0
1.0
0.1
0.01
0.1
0.01
0.001
0.001
1.2
1.3
1.4
1.5
1.6
1.7
1.1
1.2
1.3
1.4
1.5
1.6
V
– FORWARD VOLTAGE – V
V
– FORWARD VOLTAGE – V
F
F
Figure 6. Typical Input Diode Forward Characteristic.
8-PIN DIP, SO-8
WIDEBODY
-2.4
-2.2
-2.3
-2.2
-2.0
-1.8
-1.6
-2.1
-2.0
-1.9
-1.8
-1.4
-1.2
0.1
1
10
100
0.1
1
10
I – PULSE INPUT CURRENT – mA
F
100
I
– PULSE INPUT CURRENT – mA
F
Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.
15
PULSE GEN.
= 50 Ω
Z
O
t
= t = 5 ns
r
f
SINGLE CHANNEL
DUAL CHANNEL
+5 V
+5 V
I
F
I
F
PULSE GEN.
= 50 Ω
V
V
CC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC
Z
O
R
L
t
= t = 5 ns
r
f
INPUT
MONITORING
NODE
OUTPUT V
O
0.1µF
BYPASS
R
L
MONITORING
NODE
0.1µF
BYPASS
OUTPUT V
MONITORING
NODE
INPUT
MONITORING
NODE
O
*C
L
R
C *
L
M
R
M
GND
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
I
= 7.50 mA
= 3.75 mA
F
INPUT
I
I
F
F
t
t
PHL
PLH
OUTPUT
V
O
1.5 V
Figure 8. Test Circuit for tPHL and tPLH
.
100
105
V
I
= 5.0 V
V
= 5.0 V
CC
= 7.5 mA
CC
= 25°C
T
F
A
t
, R = 4 KΩ
L
80
t
, R = 4 KΩ
90
PLH
PLH
L
t
, R = 350 Ω
L
PHL
1 KΩ
4 KΩ
60
40
75
60
t
, R = 350 Ω
L
PLH
t
, R = 1 KΩ
L
PLH
t
, R = 1 KΩ
L
PLH
t
, R = 350 Ω
L
PLH
45
30
20
0
t
, R = 350 Ω
PHL
L
1 KΩ
4 KΩ
5
7
9
11
13
15
-60 -40 -20
0
20 40
80 100
60
I
– PULSE INPUT CURRENT – mA
T
– TEMPERATURE – °C
F
A
Figure 9. Typical Propagation Delay
vs. Temperature.
Figure 10. Typical Propagation Delay
vs. Pulse Input Current.
40
V
= 5.0 V
t
t
CC
I = 7.5 mA
F
RISE
FALL
R
= 4 kΩ
L
30
20
10
0
V
I
= 5.0 V
CC
= 7.5 mA
R
= 4 kΩ
= 1 kΩ
F
300
290
60
L
R
= 350 Ω
L
R
L
40
R
R
= 350 Ω
L
20
0
R
= 1 kΩ
L
= 350 Ω, 1 kΩ, 4 kΩ
L
0
-10
-60
-40 -20
0
20 40
80 100
60
-60 -40 -20
20 40 60 80 100
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 11. Typical Pulse Width
Distortion vs. Temperature.
Figure 12. Typical Rise and Fall Time
vs. Temperature.
16
PULSE GEN.
= 50 Ω
Z
O
t
= t = 5 ns
f
r
INPUT V
MONITORING NODE
E
+5 V
V
3.0 V
1.5 V
1
2
3
4
8
7
6
5
CC
INPUT
V
7.5 mA
E
0.1 µF
BYPASS
R
L
I
F
t
t
EHL
ELH
OUTPUT V
MONITORING
NODE
O
OUTPUT
V
O
1.5 V
*C
L
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
Figure 13. Test Circuit for tEHL and tELH
.
120
V
V
V
= 5.0 V
= 3.0 V
= 0 V
CC
EH
EL
I
= 7.5 mA
F
90
60
t
, R = 4 kΩ
L
ELH
t
, R = 1 kΩ
ELH
L
30
0
t
, R = 350 Ω
ELH
L
t
, R = 350 Ω, 1 kΩ, 4 kΩ
L
EHL
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
A
Figure 14. Typical Enable Propagation
Delay vs. Temperature.
I
F
SINGLE CHANNEL
DUAL CHANNEL
B
I
F
V
1
2
3
4
8
7
6
5
+5 V
V
CC
+5 V
CC
1
2
3
4
8
A
R
B
A
L
OUTPUT V
MONITORING
NODE
0.1 µF
BYPASS
O
R
7
6
5
L
V
FF
OUTPUT V
MONITORING
NODE
O
V
FF
0.1 µF
BYPASS
GND
GND
V
CM
V
CM
+
–
+
–
PULSE
GENERATOR
= 50 Ω
PULSE
GENERATOR
= 50 Ω
Z
Z
O
O
V
CM
(PEAK)
V
CM
0 V
5 V
SWITCH AT A: I = 0 mA
F
CM
H
V
O
V
(MIN.)
O
SWITCH AT B: I = 7.5 mA
F
V
(MAX.)
O
V
O
0.5 V
CM
L
Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
17
HCPL-2611 OPTION 060
(mW)
HCNWXXXX
P (mW)
S
800
700
600
500
400
300
200
100
0
P
S
I
(mA)
I (mA)
S
S
800
700
600
500
400
300
200
100
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25
T – CASE TEMPERATURE – °C
S
50 75 100 125 150 175
T
S
Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per IEC/EN/DIN EN 60747-5-2.
GND BUS (BACK)
V
BUS (FRONT)
NC
CC
ENABLE
OUTPUT
0.1µF
NC
10 mm MAX.
(SEE NOTE 5)
SINGLE CHANNEL
DEVICE ILLUSTRATED.
Figure 17. Recommended Printed Circuit Board Layout.
18
SINGLE CHANNEL DEVICE
5 V
5 V
8
6
V
CC1
V
CC2
390 Ω
470 Ω
I
F
+
2
3
D1*
V
0.1 µF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
V
E
7
1
2
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
5 V
5 V
8
7
V
CC1
V
CC2
390 Ω
470 Ω
I
F
+
1
2
D1*
V
0.1 µF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
1
2
Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
19
Propagation Delay, Pulse- tions where synchronization of
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
Width Distortion and
signals on parallel data lines is a
concern. If the parallel data is
being sent through a group of
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of the
optocouplers at different times. If
this difference in propagation
delays is large enough, it will
determine the maximum rate at
which parallel data can be sent
through the optocouplers.
Propagation Delay Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (tPLH
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
)
Propagation delay skew repre-
sents the uncertainty of where an
edge might be after being sent
through an optocoupler. Figure
20 shows that there will be
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output causing the output to
change from high to low (see
Figure 8).
Propagation delay skew is defined
as the difference between the
minimum and maximum
propagation delays, either tPLH or
tPHL, for any given group of
uncertainty in both the data and
the clock lines. It is important
that these two areas of uncertainty
not overlap, otherwise the clock
signal might arrive before all of
the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice tPSK. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
Pulse-width distortion (PWD)
results when tPLH and tPHL differ in
value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being
operating temperature). As
illustrated in Figure 19, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, tPSK is the
difference between the shortest
propagation delay, either tPLH or
tPHL, and the longest propagation
uncertainty in the rest of the
circuit does not cause a problem.
transmitted. Typically, PWD on
the order of 20-30% of the
delay, either tPLH or tPHL
.
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-l, etc.).
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 20
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
The tPSK specified optocouplers
offer the advantages of
guaranteed specifications for
propagation delays, pulsewidth
distortion and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
Propagation delay skew, tPSK, is
an important parameter to
consider in parallel data applica-
DATA
INPUTS
I
F
50%
50%
CLOCK
1.5 V
V
O
DATA
I
F
OUTPUTS
CLOCK
t
PSK
V
1.5 V
O
t
PSK
t
PSK
Figure 19. Illustration of Propagation
Delay Skew - t
Figure 20. Parallel Data Transmission
Example.
.
PSK
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(916)788-6763
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (+65) 6756 2394
India, Australia, New Zealand: (+65) 6755 1939
Japan: (+81 3) 3335-8152 (Domestic/Interna-
tional), or 0120-61-1280 (Domestic Only)
Korea: (+65) 6755 1989
Singapore, Malaysia, Vietnam, Thailand,
Philippines, Indonesia: (+65) 6755 2044
Taiwan: (+65) 6755 1843
Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5989-0302EN
December 29, 2004
5989-2126EN
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