HCPL-7710-XXXE [AGILENT]
40 ns Propagation Delay, CMOS Optocoupler; 40 ns的传播延迟， CMOS光电耦合器
| 型号： | HCPL-7710-XXXE |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | 40 ns Propagation Delay, CMOS Optocoupler |
| 文件： | 总17页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HCPL-7710, HCPL-0710
40 ns Propagation Delay,
CMOS Optocoupler
Data Sheet
Features
• +5 V CMOS compatibility
• 8 ns maximum pulse width
distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
Description
Basic building blocks of the
HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high-speed
• 10 kV/ µs minimum common mode
rejection
Available in either an 8-pin DIP or
SO-8 package style respectively,
the HCPL-7710 or HCPL-0710
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with
very low power consumption. The
HCPL-x710 require only two
bypass capacitors for complete
CMOS compatibility.
• -40°C to 100°C temperature range
• Safety and regulatory approvals
UL Recognized
3750 V rms for 1 min. per
UL 1577
CSA Component Acceptance
Notice # 5
transimpedance amplifier, and a
voltage comparator with an
output driver.
IEC/ EN/ DIN EN 60747-5-2
– VIORM = 630 Vpeak for
HCPL-7710 Option 060
Functional Diagram
– VIORM = 560 Vpeak for
HCPL-0710 Option 060
TRUTH TABLE
(POSITIVE LOGIC)
**V
1
2
8
7
V
**
DD2
DD1
Applications
V , INPUT
I
LED1
V
, OUTPUT
O
H
L
OFF
ON
H
L
• Digital fieldbus isolation:
DeviceNet, SDS, Profibus
V
I
NC*
I
O
• AC plasma display panel level
shifting
3
4
6
5
*
V
O
LED1
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
GND
GND
2
1
SHIELD
* Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet
performance. Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
8-Pin DIP
(300 Mil)
Small Outline
SO-8
HCPL-7710
HCPL-0710
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-7710#XXXX
060 = IEC/EN/DIN EN 60747-5-2 Option.
300 = Gull Wing Surface Mount Option (HCPL-7710 only).
500 = Tape and Reel Packaging Option.
XXXE = Lead Free Option
No Option and Option 300 contain 50 units (HCPL-7710), 100 units (HCPL-0710) per tube.
Option 500 contain 1000 units (HCPL-7710), 1500 units (HCPL-0710) per reel.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–”
Package Outline Drawing
HCPL-7710 8-Pin DIP Package
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
OPTION 060 CODE*
DATE CODE
TYPE NUMBER
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
A XXXXV
YYWW
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*OPTION 300 AND 500 NOT MARKED.
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
2
Package Outline Drawing
HCPL-7710 Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
1.016 (0.040)
9.65 ± 0.25
(0.380 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2.0 (0.080)
2
3
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Package Outline Drawing
HCPL-0710 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
3
PIN ONE
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
(0.017)
*
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3
Regulatory Information
Solder Reflow Thermal Profile
300
The HCPL-x710 have been
approved by the following
organizations:
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
UL
200
100
0
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
Recognized under UL 1577,
component recognition program,
File E55361.
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
CSA
TIGHT
TYPICAL
LOOSE
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
IEC/ EN/ DIN EN 60747-5-2
Recommended Pb-Free IR Profile
Approved under:
TIME WITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
t
p
20-40 SEC.
260 +0/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
(Option 060 only)
150 - 200 °C
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
Insulation and Safety Related Specifications
Value
0710
Parameter
Symbol
7710
Units
Conditions
Minimum External Air
Gap (Clearance)
L(I01)
7.1
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(I02)
CTI
7.4
4.8
mm
Measured from input terminals to output
terminals, shortest distance path along
body.
Insulation thickness between emitter and
detector; also known as distance through
insulation.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08
≥175
IIIa
0.08
≥175
IIIa
mm
Tracking Resistance
(Comparative Tracking
Index)
Volts
DIN IEC 112/ VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/ 89,
Table 1)
board, minimum creepage and
clearance requirements must be
met as specified for individual
equipment standards. For
creepage, the shortest distance
path along the surface of a
printed circuit board between the
solder fillets of the input and
output leads must be considered.
There are recommended
All Agilent data sheets report the
creepage and clearance inherent
to the optocoupler component
itself. These dimensions are
needed as a starting point for the
equipment designer when
determining the circuit insulation
requirements. However, once
mounted on a printed circuit
techniques such as grooves and
ribs which may be used on a
printed circuit board to achieve
desired creepage and clearances.
Creepage and clearance distances
will also change depending on
factors such as pollution degree
and insulation level.
4
IEC/ EN/ DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
HCPL-7710
Option 060
HCPL-0710
Option 060
Description
Symbol
Units
Installation classification per DIN VDE 0110/ 1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
I-IV
I-IV
I-III
I-IV
I-III
for rated mains voltage ≤450 V rms
Climatic Classification
55/ 100/ 21
55/ 100/ 21
Pollution Degree (DIN VDE 0110/ 1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b†
2
2
V
630
1181
560
1050
Vpeak
Vpeak
IORM
V
PR
V
IORM
x 1.875 = V , 100% Production
PR
Test with t = 1 sec, Partial Discharge < 5 pC
m
Input to Output Test Voltage, Method a†
V
945
840
Vpeak
Vpeak
PR
V
IORM
x 1.5 = V , Type and Sample Test,
PR
t = 60 sec, Partial Discharge < 5 pC
m
Highest Allowable Overvoltage†
V
IOTM
6000
4000
(Transient Overvoltage, t = 10 sec)
ini
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
T
175
230
600
150
150
600
°C
mA
mW
S
I
S,INPUT
P
S,OUTPUT
9
9
Insulation Resistance at T , V = 500 V
R
IO
≥10
≥10
Ω
S
10
†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section
IEC/ EN/ DIN EN 60747-5-2, for a detailed description.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
–55
–40
0
Max.
125
Units
°C
Figure
Storage Temperature
Ambient Operating Temperature
Supply Voltages
TA
+100
6.0
°C
V
DD1, V
Volts
Volts
Volts
mA
DD2
Input Voltage
V
I
–0.5
–0.5
–10
VDD1 +0.5
Output Voltage
V
O
VDD2 +0.5
Input Current
I
I
+10
10
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
IO
mA
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
Min.
–40
4.5
Max.
+100
5.5
Units
°C
V
Figure
Ambient Operating Temperature
Supply Voltages
TA
V
DD1, V
DD2
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
V
2.0
V
V
1, 2
IH
DD1
V
IL
0.0
0.8
1.0
V
tr, tf
ms
5
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications
are at T = +25°C, VDD1 = VDD2 = +5 V.
A
Parameter
Symbol Min.
Typ.
Max. Units
Test Conditions
Fig. Note
DC Specifications
Logic Low Input
Supply Current
IDD1L
IDD1H
6.0
1.5
10.0 mA
V = 0 V
1
I
Logic High Input
Supply Current
3.0
mA
V = V
I
DDI
Input Supply Current
Output Supply Current
Input Current
IDD1
IDD2
13.0 mA
11.0 mA
5.5
I
I
-10
4.4
4.0
10
µA
Logic High Output
Voltage
V
OH
5.0
4.8
0
V
IO = -20 µA, V = V
1, 2
I
IH
IO = -4 mA, V = V
I
IH
Logic Low Output
Voltage
V
OL
0.1
1.0
V
IO = 20 µA, V = V
I
IL
0.5
IO = 4 mA, V = V
I
IL
Switching Specifications
Propagation Delay Time
to Logic Low Output
tPHL
tPLH
PW
20
23
40
40
ns
CL = 15 pF
CMOS Signal Levels
3, 7
2
3
Propagation Delay Time
to Logic High Output
Pulse Width
80
Data Rate
12.5 MBd
Pulse Width Distortion
PWD
3
8
ns
4, 8
5, 9
4
5
| tPHL - tPLH
|
Propagation Delay Skew
tPSK
tR
20
Output Rise Time
(10 - 90%)
9
Output Fall Time
(90 - 10%)
tF
8
6,
10
Common Mode
Transient Immunity at
Logic High Output
| CMH|
10
10
20
kV/ µs
V = VDD1, V >
6
7
I
O
0.8 V ,
DD1
V = 1000 V
CM
Common Mode
Transient Immunity at
Logic Low Output
| CML|
CPD1
20
60
10
V = 0 V, V > 0.8 V,
I
O
V = 1000 V
CM
Input Dynamic Power
Dissipation
Capacitance
pF
Output Dynamic Power
Dissipation
CPD2
Capacitance
6
Package Characteristics
Parameter
Symbol Min. Typ. Max. Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage
0710
7710
V
ISO
3750
3750
Vrms
RH ≤ 50%,
t = 1 min.,
TA = 25°C
8, 9,
10
Resistance
(Input-Output)
R
1012
0.6
Ω
V = 500 Vdc
8
I-O
I-O
Capacitance
C
I-O
pF
f = 1 MHz
(Input-Output)
Input Capacitance
C
I
3.0
11
Input IC Junction-to-Case
Thermal Resistance
-7710
-0710
θjci
145
160
°C/ W
Thermocouple
located at center
underside of package
Output IC Junction-to-Case
Thermal Resistance
-7710
-0710
θjco
PPD
140
135
Package Power Dissipation
150
mW
Notes:
1. The LED is ON when V is low and OFF
4. PWD is defined as | tPHL - tPLH| .
9. In accordance with UL1577, each HCPL-
0710 is proof tested by applying an
insulation test voltage ≥4500 VRMS for 1
second (leakage detection current limit, I
≤5 µA). Each HCPL-7710 is proof tested by
applying an insulation test voltage ≥ 4500 V
rms for 1 second (leakage detection current
limit, II-O ≤ 5 µA).
I
when V is high.
%PWD (percent pulse width distortion) is
equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst
case difference in tPHL and/ or tPLH that will
be seen between units at any given
temperature within the recommended
operating conditions.
I
2. tPHL propagation delay is measured from
the 50% level on the falling edge of the V
signal to the 50% level of the falling edge
I
I-O
of the V signal. tPLH propagation delay is
O
measured from the 50% level on the rising
edge of the V signal to the 50% level of the
I
rising edge of the V signal.
6. CMH is the maximum common mode
voltage slew rate that can be sustained
10. The Input-Output Momentary Withstand
Voltage is a dielectric voltage rating that
should not be interpreted as an input-output
continuous voltage rating. For the
O
3. Mimimum Pulse Width is the shortest
pulse width at which 10% maximum, Pulse
Width Distortion can be guaranteed.
Maximum Data Rate is the inverse of
Minimum Pulse Width. Operating the
HCPL-x710 at data rates above 12.5 MBd is
possible provided PWD and data
dependent jitter increases and relaxed
noise margins are tolerable within the
application. For instance, if the maximum
allowable variation of bit width is 30%, the
maximum data rate becomes 37.5 MBd.
Please note that HCPL-x710 performances
above 12.5 MBd are not guaranteed by
Hewlett-Packard.
while maintaining V > 0.8 VDD2. CML is the
O
maximum common mode voltage slew rate
that can be sustained while maintaining V
< 0.8 V. The common mode voltage slew
rates apply to both rising and falling
common mode voltage edges.
continuous voltage rating refer to your
equipment level safety specification or
Agilent Application Note 1074 entitled
“Optocoupler Input-Output Endurance
Voltage.”
O
7. Unloaded dynamic power dissipation is
calculated as follows: CPD * VDD2 * f + IDD
*
11. C is the capacitance measured at pin 2 (V).
I
I
VDD, where f is switching frequency in
MHz.
8. Device considered a two-terminal device:
pins 1, 2, 3, and 4 shorted together and
pins 5, 6, 7, and 8 shorted together.
2.2
29
27
25
23
5
0 °C
25 °C
85 °C
2.1
2.0
1.9
0 °C
25 °C
85 °C
4
3
2
1
0
T
T
PLH
PHL
21
19
17
15
1.8
1.7
1.6
0
1
2
3
4
5
4.5
4.75
5
5.25
5.5
0
10 20 30 40 50 60 70 80
(C)
V (V)
V
(V)
T
I
DD1
A
Figure 1. Typical output voltage vs. input
voltage.
Figure 2. Typical input voltage switching
threshold vs. input supply voltage.
Figure 3. Typical propagation delays vs.
temperature.
7
4
3
2
11
10
7
6
5
4
3
2
9
8
1
0
0
20
40
60
80
0
20
40
60
80
0
20
40
60
80
T
(C)
T
(C)
T (C)
A
A
A
Figure 4. Typical pulse width distortion vs.
temperature.
Figure 5. Typical rise time vs. temperature.
Figure 6. Typical fall time vs. temperature.
29
27
25
6
5
4
3
2
1
21
19
17
15
13
11
9
T
PHL
23
21
19
17
15
T
PLH
7
5
3
0
1
15 20 25 30 35 40 45 50
15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35
C (pF)
I
C (pF)
I
C (pF)
I
Figure 7. Typical propagation delays vs.
output load capacitance.
Figure 8. Typical pulse width distortion vs.
output load capacitance.
Figure 9. Typical rise time vs. load
capacitance.
STANDARD 8 PIN DIP PRODUCT
800
SURFACE MOUNT SO8 PRODUCT
(mW)
10
9
8
7
6
5
4
3
2
1
0
800
700
600
500
400
300
P
(mW)
P
S
S
700
600
500
400
300
I
(mA)
I (mA)
S
S
(230)
200
200
(150)
100
100
0
0
0
5
10 15 20 25 30 35
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
C (pF)
I
T
T
A
A
Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature
per IEC/ EN/ DIN EN 60747-5-2.
Figure 10. Typical fall time vs. load
capacitance.
8
Application Information
0.1 µF. For each capacitor, the
total lead length between both
ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 13
illustrates the recommended
printed circuit board layout for
the HPCL-x710.
connected directly to the inputs
and outputs.
Bypassing and PC Board Layout
The HCPL-x710 optocouplers are
extremely easy to use. No external
interface circuitry is required
because the HCPL-x710 use high-
speed CMOS IC technology
As shown in Figure 12, the only
external components required for
proper operation are two bypass
capacitors. Capacitor values
should be between 0.01 µF and
allowing CMOS logic to be
V
8
7
6
5
V
DD1
1
2
3
4
DD2
C1
C2
V
I
NC
NC
V
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 12. Recommended Printed Circuit Board layout.
V
DD1
V
V
DD2
V
I
C1
C2
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 13. Recommended Printed Circuit Board layout.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay
Skew
tion delay from low to high (tPLH
)
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low. See
Figure 14.
is the amount of time required for
an input signal to propagate to the
output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
Propagation Delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
INPUT
5 V CMOS
V
50%
0 V
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
10%
10%
O
V
OL
Figure 14.
9
Pulse-width distortion (PWD) is
the difference between tPHL and
tPLH and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being trans-
mitted. Typically, PWD on the
order of 20 - 30% of the minimum
pulse width is tolerable. The PWD
specification for the HCPL-x710 is
8 ns (10%) maximum across
on parallel data lines is a concern.
If the parallel data is being sent
through a group of optocouplers,
differences in propagation delays
will cause the data to arrive at the
outputs of the optocouplers at
different times. If this difference
in propagation delay is large
enough it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
temperature). As illustrated in
Figure 15, if the inputs of a group
of optocouplers are switched
either ON or OFF at the same
time, tPSK is the difference
between the shortest propagation
delay, either tPLH or tPHL, and the
longest propagation delay, either
tPLH or tPHL
.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 16
is the timing diagram of a typical
parallel data application with
both the clock and data lines
being sent through the
recommended operating condi-
tions. 10% maximum is dictated
by the most stringent of the three
fieldbus standards, PROFIBUS.
Propagation delay skew is defined
as the difference between the
minimum and maximum propa-
gation delays, either tPLH or tPHL
,
for any given group of optocoup-
lers which are operating under
the same conditions (i.e., the same
drive current, supply voltage,
output load, and operating
optocouplers. The figure shows
data and clock signals at the
inputs and outputs of the
optocouplers. In this case the data
is assumed to be clocked off of the
rising edge of the clock.
Propagation delay skew, tPSK, is
an important parameter to con-
sider in parallel data applications
where synchronization of signals
V
I
50%
DATA
INPUTS
CLOCK
2.5 V,
CMOS
V
O
t
PSK
V
50%
I
DATA
OUTPUTS
t
PSK
2.5 V,
CMOS
CLOCK
V
O
t
PSK
Figure 15. Propagation delay skew waveform.
Figure 16. Parallel data transmission example.
Propagation delay skew repre-
sents the uncertainty of where an
edge might be after being sent
through an optocoupler. Figure 16
shows that there will be
uncertainty in both the data and
clock lines. It is important that
these two areas of uncertainty not
overlap, otherwise the clock
some of the data outputs may
uncertainty in the rest of the
circuit does not cause a problem.
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice tPSK
A cautious design should use a
slightly longer pulse width to
ensure that any additional
The HCPL-x710 optocouplers
offer the advantage of guaranteed
specifications for propagation
delays, pulse-width distortion,
and propagation delay skew over
the recommended temperature
and power supply ranges.
.
signal might arrive before all of
the data outputs have settled, or
10
Digital Field Bus Communication
Networks
monitor it. With the advent of
digital field bus communication
networks such as DeviceNet,
PROFIBUS, and Smart
Distributed Systems (SDS), gone
are the days of constrained
information. Controllers can now
receive multiple readings from
field devices (sensors, actuators,
etc.) in addition to diagnostic
information.
The physical model for each of
these digital field bus communica-
tion networks is very similar as
shown in Figure 17. Each includes
one or more buses, an interface
unit, optical isolation, transceiver,
and sensing and/or actuating
devices.
To date, despite its many draw-
backs, the 4 - 20 mA analog
current loop has been the most
widely accepted standard for
implementing process control
systems. In today’s manufacturing
environment, however, automated
systems are expected to help
manage the process, not merely
CONTROLLER
BUS
INTERFACE
OPTICAL
ISOLATION
TRANSCEIVER
FIELD BUS
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
OPTICAL
OPTICAL
OPTICAL
OPTICAL
ISOLATION
ISOLATION
ISOLATION
ISOLATION
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
XXXXXX
YYY
SENSOR
DEVICE
CONFIGURATION
MOTOR
CONTROLLER
MOTOR
STARTER
Figure 17. Typical field bus communication physical model.
Optical Isolation for Field Bus
Networks
network receives maximum
protection from power system
faults and ground loops.
transceiver and input (network)
side of the optocouplers.
To recognize the full benefits of
these networks, each recommends
providing galvanic isolation using
Agilent optocouplers. Since
network communication is bi-
directional (involving receiving
data from and transmitting data
onto the network), two Agilent
optocouplers are needed. By
providing galvanic isolation, data
integrity is retained via noise
reduction and the elimination of
false signals. In addition, the
Isolation of nodes connected to
any of the three types of digital
field bus networks is best
achieved by using the HCPL-x710
optocouplers. For each network,
the HCPL-x710 satisify the critical
propagation delay and pulse
width distortion requirements
over the temperature range of 0°C
to +85°C, and power supply
Within an isolated node, such as
the DeviceNet Node shown in
Figure 18, some of the node’s
components are referenced to a
ground other than V- of the
network. These components could
include such things as devices
with serial ports, parallel ports,
RS232 and RS485 type ports. As
shown in Figure 18, power from
the network is used only for the
voltage range of 4.5 V to 5.5 V.
11
AC LINE
NODE/APP SPECIFIC
uP/CAN
LOCAL
NODE
SUPPLY
GALVANIC
ISOLATION
BOUNDARY
HCPL
x710
HCPL
x710
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
Figure 18. Typical DeviceNet node.
Implementing DeviceNet and SDS
with the HCPL-x710
Isolated Node with Transceiver
Powered by the Network (Figure
20), and Isolated Node Providing
Power to the Network (Figure 21).
components are still powered by
the network. This node contains
two regulators: one is isolated and
powers the CAN controller, node-
specific application and isolated
(node) side of the two optocoup-
lers while the other is non-
With transmission rates up to 1
Mbit/s, both DeviceNet and SDS
are based upon the same
broadcast-oriented, communica-
tions protocol — the Controller
Area Network (CAN). Three types
of isolated nodes are
recommended for use on these
networks: Isolated Node Powered
by the Network (Figure 19),
Isolated Node Powered by the
Network
isolated. The non-isolated
This type of node is very flexible
and as can be seen in Figure 19, is
regarded as “isolated” because not
all of its components have the
same ground reference. Yet, all
regulator supplies the transceiver
and the non-isolated (network)
half of the two optocouplers.
NODE/APP SPECIFIC
uP/CAN
ISOLATED
SWITCHING
POWER
GALVANIC
ISOLATION
BOUNDARY
HCPL
x710
HCPL
x710
SUPPLY
REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
Figure 19. Isolated node powered by the network.
12
Isolated Node with Transceiver
Powered by the Network
power to the node is lost or the
node powered-off. Specifically,
when input power (VDD1) to the
HCPL-x710 located in the
transmit path is eliminated, a
RECESSIVE bus state is ensured
as the HCPL-x710 output voltage
(VO) go HIGH.
DeviceNet Object to the “auto-
reset” (01) value. Refer to Volume
1, Section 5.5.3. This would cause
the node to continually reset until
bus power was detected. Once
power was detected, the BOI
attribute would be returned to the
“hold in bus-off” (00) value. The
BOI attribute should not be left in
the “auto-reset” (01) value since
this defeats the jabber protection
capability of the CAN error
Figure 20 shows a node powered
by both the network and another
source. In this case, the trans-
ceiver and isolated (network) side
of the two optocouplers are
powered by the network. The rest
of the node is powered by the AC
line which is very beneficial when
an application requires a
*Bus V+ Sensing
It is suggested that the Bus V+
sense block shown in Figure 20 be
implemented. A locally powered
node with an un-powered isolated
Physical Layer will accumulate
errors and become bus-off if it
attempts to transmit. The Bus V+
sense signal would be used to
change the BOI attribute of the
significant amount of power. This
method is also desirable as it does
not heavily load the network.
confinement. Any inexpensive
low frequency optical isolator can
be used to implement this feature.
More importantly, the unique
“dual-inverting” design of the
HCPL-x710 ensure the network
will not “lock-up” if either AC line
AC LINE
NON ISO
5 V
NODE/APP SPECIFIC
uP/CAN
GALVANIC
ISOLATION
BOUNDARY
HCPL
x710
HCPL
x710
*HCPL
x710
REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
* OPTIONAL FOR BUS V + SENSE
SUPPLY
Figure 20. Isolated node with transceiver powered by the network.
13
Isolated Node Providing Power to
the Network
(network) side of the two
will not “lock-up” if either AC line
power to the node is lost or the
node powered-off. Specifically,
when input power (VDD1) to the
HCPL-x710 located in the
transmit path is eliminated, a
RECESSIVE bus state is ensured
as the HCPL-x710 output voltage
(VO) go HIGH.
optocouplers. This method is
recommended when there are a
limited number of devices on the
network that don’t require much
power, thus eliminating the need
for separate power supplies.
Figure 21 shows a node providing
power to the network. The AC line
powers a regulator which
provides five (5) volts locally. The
AC line also powers a 24 volt
isolated supply, which powers the
network, and another five-volt
regulator, which, in turn, powers
the transceiver and isolated
More importantly, the unique
“dual-inverting” design of the
HCPL-x710 ensure the network
AC LINE
DEVICENET NODE
NODE/APP SPECIFIC
uP/CAN
5 V REG.
ISOLATED
SWITCHING
POWER
GALVANIC
ISOLATION
BOUNDARY
HCPL
x710
HCPL
x710
SUPPLY
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
Figure 21. Isolated node providing power to the network.
14
Power Supplies and Bypassing
transceiver. Two bypass
lead length between both ends of
the capacitor and the power
supply pins should not exceed 20
mm. The bypass capacitors are
required because of the high-
speed digital nature of the signals
inside the optocoupler.
capacitors (with values between
0.01 and 0.1 µF) are required and
should be located as close as
possible to the input and output
power-supply pins of the HCPL-
x710. For each capacitor, the total
The recommended DeviceNet
application circuit is shown in
Figure 22. Since the HCPL-x710
are fully compatible with CMOS
logic level signals, the optocoupler
is connected directly to the CAN
GALVANIC
ISOLATION
BOUNDARY
ISO 5 V
5 V
LINEAR OR
SWITCHING
REGULATOR
+
V
V
V
DD2
1
2
8
7
DD1
IN
+
0.01
µF
TX0
HCPL-x710
V
CC
5 V+
TxD
Rs
V
O
0.01 µF
3
4
6
5
CANH
4 CAN+
3 SHIELD
2 CAN–
1 V–
82C250
GND
GND
GND
+
1
2
2
C4
0.01 µF
CANL
REF
GND
VREF
RXD
GND
GND
5
6
4
3
1
C1
0.01 µF
500 V
0.01
µF
D1
R1
1 M
RX0
V
O
30 V
HCPL-x710
V
0.01 µF
7
8
2
1
IN
V
V
DD1
DD2
ISO 5 V
5 V
Figure 22. Recommended DeviceNet application circuit.
Implementing PROFIBUS with the
HCPL-x710
PROFIBUS USER:
CONTROL STATION
(CENTRAL PROCESSING)
OR FIELD DEVICE
An acronym for Process Fieldbus,
PROFIBUS is essentially a
twisted-pair serial link very
USER INTERFACE
FDL/APP
PROCESSOR
similar to RS-485 capable of
achieving high-speed communi-
cation up to 12 MBd. As shown in
Figure 23, a PROFIBUS Controller
UART
PBC
(PBC) establishes the connection
of a field automation unit (control
or central processing station) or a
field device to the transmission
medium. The PBC consists of the
line transceiver, optical isolation,
frame character transmitter/
receiver (UART), and the FDL/
APP processor with the interface
to the PROFIBUS user.
OPTICAL ISOLATION
TRANSCEIVER
MEDIUM
Figure 23. PROFIBUS Controller (PBC).
15
Power Supplies and Bypassing
the total lead length between both
ends of the capacitor and the
power supply pins should not
exceed 20 mm. The bypass
capacitors are required because of
the high-speed digital nature of
the signals inside the optocoupler.
after each master/slave
transmission cycle. Specifically,
the HCPL-061N disables the
transmitter of the line driver by
putting it into a high state mode.
In addition, the HCPL-061N
switches the RX/TX driver IC into
the listen mode. The HCPL-061N
offers HCMOS compatibility and
the high CMR performance
(1 kV/µs at VCM = 1000 V)
The recommended PROFIBUS
application circuit is shown in
Figure 24. Since the HCPL-x710
are fully compatible with CMOS
logic level signals, the
optocoupler is connected directly
to the transceiver. Two bypass
capacitors (with values between
0.01 and 0.1 µF) are required and
should be located as close as
possible to the input and output
power-supply pins of the
Being very similar to multi-station
RS485 systems, the HCPL-061N
optocoupler provides a transmit
disable function which is
essential in industrial
communication interfaces.
necessary to make the bus free
HCPL-x710. For each capacitor,
GALVANIC
ISOLATION
BOUNDARY
5 V
ISO 5 V
V
V
V
8
7
1
2
ISO 5 V
DD2
DD1
V
0.01 µF
IN
8
HCPL-x710
V
CC
0.01
µF
1
R
6
5
3
4
Rx
O
6
7
+
A
B
0.01
µF
RT
SHIELD
SN75176B
GND
GND
1
2
4
3
2
D
–
DE
RE
5 V
ISO 5 V
GND
5
V
V
DD2
1
2
8
7
DD1
0.01
µF
1 M
0.01 µF
V
Tx
IN
HCPL-x710
V
O
3
4
6
5
0.01 µF
GND
GND
2
1
ISO 5 V
V
1
2
8
7
CC
5 V
V
E
ANODE
680 Ω
0.01
µF
1, 0 kΩ
V
3
4
CATHODE
6
5
Tx ENABLE
O
GND
HCPL-061N
Figure 24. Recommended PROFIBUS application circuit.
16
www.agilent.com/ semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/ Canada: +1 (800) 235-0312 or
(916) 788-6763
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (+65) 6756 2394
India, Australia, New Zealand: (+65) 6755 1939
Japan: (+81 3) 3335-8152 (Domestic/ Interna-
tional), or 0120-61-1280 (Domestic Only)
Korea: (+65) 6755 1989
Singapore, Malaysia, Vietnam, Thailand,
Philippines, Indonesia: (+65) 6755 2044
Taiwan: (+65) 6755 1843
Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-0789EN
February 28, 2005
5989-2134EN
相关型号：
HCPL-7720-300
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 25Mbps, 0.300 INCH, LEAD FREE, SURFACE MOUNT, DIP-8
AVAGO
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