HCPL-7720#300 [ETC]

FET-OUTPUT OPTOCOUPLER ; 场效应管输出光电耦合器


型号：	HCPL-7720#300
厂家：	ETC
描述：	FET-OUTPUT OPTOCOUPLER 场效应管输出光电耦合器光电输出元件
文件：	总16页 (文件大小：308K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

40 ns Propagation Delay,

CMOS Optocoupler

Technical Data

HCPL-7720 HCPL-7721

HCPL-0720 HCPL-0721

Features

• Multiplexed Data

Transmission

• Computer Peripheral

Interface

• Microprocessor System

Interface

Functional Diagram

• +5 V CMOS Compatibility

• 20 ns max. Prop. Delay Skew

• High Speed: 25 MBd

• 40 ns max. Prop. Delay

**V

DD1

DD2

NC*

• 10 kV/µs Minimum Common

Mode Rejection

• –40 to 85°C Temp. Range

• Safety and Regulatory

Approvals

UL Recognized

2500 V rms for 1 min. per

UL 1577 for HCPL-072X,

3750 V rms for 1 min. per

UL 1577 for HCPL-772X

CSA Component Acceptance

Notice #5

Description

Available in either an 8-pin DIP or

SO-8 package style respectively,

the HCPL-772X or HCPL-072X

optocouplers utilize the latest

CMOS IC technology to achieve

outstanding performance with

very low power consumption. The

HCPL-772X/072X require only

two bypass capacitors for

LED1

GND

SHIELD

TRUTH TABLE

(POSITIVE LOGIC)

V , INPUT

LED1

, OUTPUT

OFF

complete CMOS compatability.

VDE 0884

– V_IORM= 630 Vpeak for

HCPL-772X Option 060

– V_IORM= 560 Vpeak for

HCPL-072X Option 060

Basic building blocks of the

HCPL-772X/072X are a CMOS

LED driver IC, a high speed LED

and a CMOS detector IC. A CMOS

logic input signal controls the

LED driver IC which supplies

current to the LED. The detector

IC incorporates an integrated

photodiode, a high-speed

transimpedance amplifier, and a

voltage comparator with an

output driver.

Applications

• Digital Fieldbus Isolation:

CC-Link, DeviceNet,

Profibus, SDS

• AC Plasma Display Panel

Level Shifting

*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance.

Pin 7 is not connected internally.

**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.

CAUTION:Itisadvisedthatnormalstaticprecautionsbetakeninhandlingandassemblyofthiscomponent

to prevent damage and/or degradation which may be induced by ESD.

Selection Guide

8-Pin DIP

(300 Mil)

HCPL-7721

HCPL-7720

Small Outline

SO-8

HCPL-0721

HCPL-0720

Data Rate

25 MB

PWD

6 ns

8 ns

Ordering Information

Specify Part Number followed by Option Number (if desired)

Example

HCPL-7720#XXX

060 = VDE0884 Option.

300 = Gull Wing Surface Mount Option (HCPL-7720 only).

500 = Tape and Reel Packaging Option.

No Option and Option 300 contain 50 units (HCPL-772X), 100 units (HCPL-072X) per tube.

Option 500 contain 1000 units (HCPL-772X), 1500 units (HCPL-072X) per reel.

Option data sheets available. Contact Agilent sales representative or authorized distributor.

Package Outline Drawing

HCPL-772X 8-Pin DIP Package

9.65 ± 0.25

(0.380 ± 0.010)

7.62 ± 0.25

(0.300 ± 0.010)

OPTION 060 CODE*

DATE CODE

TYPE NUMBER

6.35 ± 0.25

(0.250 ± 0.010)

A XXXXV

YYWW

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076

- 0.051

0.254

5° TYP.

+ 0.003)

- 0.002)

(0.010

4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

*OPTION 300 AND 500 NOT MARKED.

1.080 ± 0.320

0.65 (0.025) MAX.

(0.043 ± 0.013)

2.54 ± 0.25

(0.100 ± 0.010)

Package Outline Drawing

HCPL-772X Package with Gull Wing Surface Mount Option 300

PAD LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25

(0.380 ± 0.010)

1.016 (0.040)

1.194 (0.047)

4.826

TYP.

(0.190)

6.350 ± 0.25

(0.250 ± 0.010)

9.398 (0.370)

9.906 (0.390)

0.381 (0.015)

0.635 (0.025)

1.194 (0.047)

1.778 (0.070)

9.65 ± 0.25

(0.380 ± 0.010)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

7.62 ± 0.25

(0.300 ± 0.010)

+ 0.076

- 0.051

0.254

4.19

+ 0.003)

- 0.002)

MAX.

(0.165)

(0.010

1.080 ± 0.320

(0.043 ± 0.013)

0.635 ± 0.25

(0.025 ± 0.010)

12° NOM.

0.635 ± 0.130

(0.025 ± 0.005)

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

Package Outline Drawing

HCPL-072X Outline Drawing (Small Outline SO-8 Package)

5.842 ± 0.203

(0.236 ± 0.008)

72XV

YWW

OPTION 060 CODE*

3.937 ± 0.127

(0.155 ± 0.005)

TYPE NUMBER (LAST 3 DIGITS)

DATE CODE

ONE

0.381 ± 0.076

(0.016 ± 0.003)

1.270

BSG

(0.050)

0.432

(0.017)

7°

45° X

5.080 ± 0.005

(0.200 ± 0.005)

3.175 ± 0.127

(0.125 ± 0.005)

0.228 ± 0.025

(0.009 ± 0.001)

1.524

(0.060)

0.152 ± 0.051

(0.006 ± 0.002)

0.305

MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

*OPTION 500 NOT MARKED.

(0.012)

Solder Reflow Thermal Profile

260

240

220

∆T = 145°C, 1°C/SEC

∆T = 115°C, 0.3°C/SEC

200

180

160

140

120

100

∆T = 100°C, 1.5°C/SEC

TIME – MINUTES

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

TUV Rheinland

Regulatory Information

CSA

The HCPL-772X/072X have been

approved by the following

organizations:

Approved under CSA Component

Acceptance Notice #5, File

CA88324.

(HCPL-072X Option 060)

Approved according to

VDE 0884/06.92, Certificate

R9650938.

VDE

(HCPL-772X Option 060)

Approved according to

VDE 0884/06.92,

Recognized under UL 1577,

component recognition program,

File E55361.

File 6591-23-4880-1005.

Insulation and Safety Related Specifications

Value

Parameter

Symbol 772X 072X Units

Conditions

Minimum External Air

Gap (Clearance)

L(I01)

7.1

4.9

Measured from input terminals to output

terminals, shortest distance through air.

Minimum External

Tracking (Creepage)

L(I02)

7.4

4.8

Measured from input terminals to output

terminals, shortest distance path along

body.

Minimum Internal Plastic

Gap (Internal Clearance)

0.08

Insulation thickness between emitter and

detector; also known as distance through

insulation.

Tracking Resistance

(Comparative Tracking

Index)

CTI

≥ 175 ≥ 175 Volts DIN IEC 112/VDE 0303 Part 1

Isolation Group

IIIa

Material Group (DIN VDE 0110, 1/89,

Table 1)

board, minimum creepage and

clearance requirements must be

met as specified for individual

equipment standards. For

creepage, the shortest distance

path along the surface of a

printed circuit board between the

solder fillets of the input and

output leads must be considered.

There are recommended

All Agilent data sheets report the

creepage and clearance inherent

to the optocoupler component

itself. These dimensions are

needed as a starting point for the

equipment designer when

determining the circuit insulation

requirements. However, once

mounted on a printed circuit

techniques such as grooves and

ribs which may be used on a

printed circuit board to achieve

desired creepage and clearances.

Creepage and clearance distances

will also change depending on

factors such as pollution degree

and insulation level.

VDE 0884 Insulation Related Characteristics (Option 060)

HCPL-772X

Option 060

HCPL-072X

Option 060 Units

Description

Symbol

Installation classification per DIN VDE 0110/1.89,

Table 1

for rated mains voltage ≤ 150 V rms

for rated mains voltage ≤ 300 V rms

for rated mains voltage ≤ 450 V rms

I-IV

I-III

I-IV

I-III

Climatic Classification

55/85/21

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b†

630

560

V peak

IORM

1181

1050

IORM

x 1.875 = V , 100% Production

Test with t = 1 sec, Partial Discharge < 5 pC

Input to Output Test Voltage, Method a†

945

840

V peak

x 1.5 = V , Type and Sample Test,

IORM

t = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage†

6000

4000

IOTM

(Transient Overvoltage, t = 10 sec)

ini

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Thermal Derating curve, Figure 11.)

Case Temperature

Input Current

Output Power

175

230

600

150

600

°C

S,INPUT

S,OUTPUT

Insulation Resistance at T , V = 500 V

≥ 10

Ω

†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety

Regulations section (VDE 0884), for a detailed description.

Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data

shall be ensured by means of protective circuits.

Note: The surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter

Storage Temperature

Ambient Operating Temperature^[1]

Supply Voltages

Input Voltage

Output Voltage

Average Output Current

Lead Solder Temperature

Solder Reflow Temperature Profile

Symbol

T_S

Min.

–55

–40

–0.5

Max.

125

+85

Units

°C

Volts

Figure

T_A

V_DD1, V_DD2

5.5

V_DD1+0.5

V_DD2+0.5

V_O

I_O

260°C for 10 sec., 1.6 mm below seating plane

See Solder Reflow Temperature Profile Section

Recommended Operating Conditions

Parameter

Symbol

Min.

–40

4.5

Max.

+85

5.5

Units

°C

Figure

Ambient Operating Temperature

Supply Voltages

T_A

V_DD1, V_DD2

Logic High Input Voltage

Logic Low Input Voltage

Input Signal Rise and Fall Times

2.0

0.0

V_DD1

0.8

1.0

1, 2

t_r, t_f

Electrical Specifications

Test conditions that are not specified can be anywhere within the recommended operating range.

All typical specifications are at T = +25°C, V_DD1= V_DD2= +5 V.

Parameter

Symbol

Min.

Typ.

Max. Units

Test Conditions

Fig. Note

DC Specifications

Logic Low Input

Supply Current

Logic High Input

Supply Current

I_DD1L

I_DD1H

6.0

1.5

10.0

3.0

mA V_I= 0 V

mA V_I= V_DD1

Output Supply Current

I_DD2L

I_DD2H

I_I

5.5

7.0

9.0

Input Current

–10

4.4

4.0

µA

V_OH

5.0

4.8

I_O= –20 µA, V_I= V_IH1, 2

Logic High Output

Voltage

I_O= -4 mA, V_I= V_IH

I_O= 20 µA, V_I= V_IL

I_O= 400 µA, V_I= V_IL

I_O= 4 mA, V_I= V_IL

V_OL

0.1

1.0

Logic Low Output

Voltage

0.5

Switching Specifications

Propagation Delay Time

to Logic Low Output

Propagation Delay Time

to Logic High Output

Pulse Width

Data Rate

t_PHL

t_PLH

C_L= 15 pF

CMOS Signal Levels

3, 6

MBd

PWD 7721/0721

Pulse Width Distortion

|t_PHL- t_PLH

7720/0720

Propagation Delay Skew

Output Rise Time

(10 - 90%)

Output Fall Time

(90 - 10%)

t_PSK

t_R

t_F

Common Mode

Transient Immunity at

Logic High Output

Common Mode

Transient Immunity at

Logic Low Output

Input Dynamic Power

Dissipation

Capacitance

Output Dynamic Power

Dissipation

|CM_H|

|CM_L|

C_PD1

kV/µs V_I= V_DD1, V_O>

0.8 V_DD1

V_CM= 1000 V

V_I= 0 V, V_O> 0.8 V,

V_CM= 1000 V

C_PD2

Capacitance

Package Characteristics

Parameter

Symbol Min. Typ. Max. Units Test Conditions Fig. Note

Input-Output Momentary

Withstand Voltage

ISO

2500

3750

Vrms RH ≤ 50%,

t = 1 min.,

8, 9,

072X

772X

T_A= 25°C

Resistance

(Input-Output)

Capacitance

R_I-O

C_I-O

10¹²

0.6

Ω

_I-O= 500 Vdc

f = 1 MHz

(Input-Output)

Input Capacitance

C_I

3.0

Input IC Junction-to-Case -772X

Thermal Resistance

Output IC Junction-to-Case -772X θ_jco

θ_jci

145

160

140

135

°C/W Thermocouple

located at center

underside of

-072X

package

Thermal Resistance

-072X

Package Power Dissipation

P_PD

150 mW

Notes:

6. CM_His the maximum common mode

voltage slew rate that can be sustained

while maintaining V_O> 0.8 V_DD2. CM_L

is the maximum common mode voltage

slew rate that can be sustained while

maintaining V_O< 0.8 V. The common

mode voltage slew rates apply to both

rising and falling common mode

voltage edges.

HCPL-772X is proof tested by applying

an insulation test voltage ≥ 4500 Vrms

for 1 second (leakage detection

current limit. I_I-O≤ 5 µA.)

1. Absolute Maximum ambient operating

temperature means the device will not

be damaged if operated under these

conditions. It does not guarantee

functionality.

10. The Input-Output Momentary Withstand

Voltage is a dielectric voltage rating

that should not be interpreted as an

input-output continuous voltage rating.

For the continuous voltage rating refer

to your equipment level safety

2. The LED is ON when V_Iis low and OFF

when V_Iis high.

3. t_PHLpropagation delay is measured

from the 50% level on the falling edge

of the V_Isignal to the 50% level of the

falling edge of the V_Osignal. t_PLH

propagation delay is measured from

the 50% level on the rising edge of the

V_Isignal to the 50% level of the rising

edge of the V_Osignal.

4. PWD is defined as |t_PHL- t_PLH|.

%PWD (percent pulse width distortion)

is equal to the PWD divided by pulse

width.

5. t_PSKis equal to the magnitude of the

worst case difference in t_PHLand/or

t_PLHthat will be seen between units at

any given temperature within the

recommended operating conditions.

7. Unloaded dynamic power dissipation is

calculated as follows: C_PD* V_DD2* f +

I_DD* V_DD, where f is switching

specification or Agilent Application

Note 1074 entitled “Optocoupler Input-

Output Endurance Voltage.”

frequency in MHz.

8. Device considered a two-terminal

device: pins 1, 2, 3, and 4 shorted

together and pins 5, 6, 7, and 8

shorted together.

9. In accordance with UL1577, each

HCPL-072X is proof tested by applying

an insulation test voltage ≥ 3000 V_RMS

for 1 second (leakage detection

current limit, I_I-O≤ 5 µA). Each

11. C_Iis the capacitance measured at pin 2

(V_I).

2.2

0 °C

25 °C

85 °C

2.1

2.0

1.9

0 °C

25 °C

85 °C

PLH

PHL

1.8

1.7

1.6

4.5

4.75

5.25

5.5

10 20 30 40 50 60 70 80

(C)

V (V)

(V)

DD1

Figure 1. Typical Output Voltage vs.

Input Voltage.

Figure 2. Typical Input Voltage

Switching Threshold vs. Input Supply

Voltage.

Figure 3. Typical Propagation Delays

vs. Temperature.

(C)

T (C)

Figure 4. Typical Pulse Width

Distortion vs. Temperature.

Figure 5. Typical Rise Time vs.

Temperature.

Figure 6. Typical Fall Time vs.

Temperature.

PHL

PLH

15 20 25 30 35 40 45 50

C (pF)

Figure 7. Typical Propagation Delays

vs. Output Load Capacitance.

Figure 8. Typical Pulse Width Distortion

vs. Output Load Capacitance.

STANDARD 8 PIN DIP PRODUCT

800

SURFACE MOUNT SO8 PRODUCT

800

(mW)

P (mW)

I (mA)

700

600

500

400

300

700

600

500

400

300

(mA)

(230)

200

(150)

100

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – °C

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – °C

Figure 9. Thermal Derating Curve, Dependence of Safety Limiting Value with

Case Temperature per VDE 0884.

CMOS IC technology allowing

CMOS logic to be connected

directly to the inputs and outputs.

0.1 µF. For each capacitor, the

total lead length between both

ends of the capacitor and the

power-supply pins should not

exceed 20 mm. Figure 11

illustrates the recommended

printed circuit board layout for

the HPCL-772X/072X.

Application Information

Bypassing and PC Board

Layout

The HCPL-772X/072X

As shown in Figure 10, the only

external components required for

proper operation are two bypass

capacitors. Capacitor values

optocouplers are extremely easy

to use. No external interface

circuitry is required because the

HCPL-772X/072X use high-speed

should be between 0.01 µF and

DD1

DD2

GND

C1, C2 = 0.01 µF TO 0.1 µF

Figure 10. Recommended Printed Circuit Board Layout.

DD1

DD2

GND

C1, C2 = 0.01 µF TO 0.1 µF

Figure 11. Recommended Printed Circuit Board Layout.

Propagation Delay, Pulse- tion delay from low to high (t_PLH

)

amount of time required for the

input signal to propagate to the

output, causing the output to

change from high to low. See

Figure 12.

Width Distortion and

is the amount of time required for

Propagation Delay Skew

Propagation Delay is a figure of

merit which describes how

an input signal to propagate to

the output, causing the output to

change from low to high.

Similarly, the propagation delay

from high to low (t_PHL) is the

quickly a logic signal propagates

through a system. The propaga-

INPUT

5 V CMOS

50%

0 V

PHL

PLH

2.5 V CMOS

OUTPUT

90%

10%

Figure 12.

will cause the data to arrive at the

outputs of the optocouplers at

different times. If this difference

in propagation delay is large

enough it will determine the

maximum rate at which parallel

data can be sent through the

optocouplers.

Pulse-width distortion (PWD) is

the difference between t_PHLand

t_PLHand often determines the

maximum data rate capability of a

transmission system. PWD can be

expressed in percent by dividing

the PWD (in ns) by the minimum

pulse width (in ns) being trans-

mitted. Typically, PWD on the

order of 20 - 30% of the minimum

pulse width is tolerable.

of optocouplers are switched

either ON or OFF at the same

time, t_PSKis the difference

between the shortest propagation

delay, either t_PLHor t_PHL, and the

longest propagation delay, either

t_PLHor t_PHL

As mentioned earlier, t_PSKcan

determine the maximum parallel

data transmission rate. Figure 14

is the timing diagram of a typical

parallel data application with both

the clock and data lines being

sent through the optocouplers.

The figure shows data and clock

signals at the inputs and outputs

of the optocouplers. In this case

the data is assumed to be clocked

off of the rising edge of the clock.

Propagation delay skew is defined

as the difference between the

minimum and maximum propa-

gation delays, either t_PLHor t_PHL

Propagation delay skew, t_PSK, is

an important parameter to con-

sider in parallel data applications

where synchronization of signals

on parallel data lines is a concern.

If the parallel data is being sent

through a group of optocouplers,

differences in propagation delays

for any given group of optocoup-

lers which are operating under

the same conditions (i.e., the

same drive current, supply volt-

age, output load, and operating

temperature). As illustrated in

Figure 13, if the inputs of a group

DATA

50%

INPUTS

CLOCK

2.5 V,

CMOS

PSK

50%

DATA

OUTPUTS

CLOCK

PSK

2.5 V,

CMOS

PSK

Figure 13. Propagation Delay Skew Waveform.

Figure 14. Parallel Data Transmission Example.

Propagation delay skew repre-

sents the uncertainty of where an

edge might be after being sent

through an optocoupler.

Figure 14 shows that there will be

uncertainty in both the data and

clock lines. It is important that

these two areas of uncertainty not

overlap, otherwise the clock

some of the data outputs may

start to change before the clock

signal has arrived. From these

considerations, the absolute

minimum pulse width that can be

sent through optocouplers in a

uncertainty in the rest of the

circuit does not cause a problem.

The HCPL-772X/072X

optocouplers offer the advantage

of guaranteed specifications for

propagation delays, pulse-width

distortion, and propagation delay

skew over the recommended

temperature and power supply

ranges.

parallel application is twice t_PSK

A cautious design should use a

slightly longer pulse width to

ensure that any additional

signal might arrive before all of

the data outputs have settled, or

systems. In today’s manufacturing

environment, however, automated

systems are expected to help

manage the process, not merely

monitor it. With the advent of

digital field bus communication

networks such as CC-Link,

DeviceNet, PROFIBUS, and Smart

Distributed Systems (SDS), gone

are the days of constrained

Digital Field Bus

Communication

Networks

To date, despite its many draw-

backs, the 4 - 20 mA analog

current loop has been the most

widely accepted standard for

implementing process control

CONTROLLER

BUS

INTERFACE

OPTICAL

ISOLATION

TRANSCEIVER

FIELD BUS

information. Controllers can now

receive multiple readings from

field devices (sensors, actuators,

etc.) in addition to diagnostic

information.

TRANSCEIVER

OPTICAL

ISOLATION

OPTICAL

ISOLATION

OPTICAL

ISOLATION

OPTICAL

ISOLATION

BUS

INTERFACE

BUS

INTERFACE

BUS

INTERFACE

BUS

INTERFACE

The physical model for each of

these digital field bus communica-

tion networks is very similar as

shown in Figure 15. Each

includes one or more buses, an

interface unit, optical isolation,

transceiver, and sensing and/or

actuating devices.

XXXXXX

YYY

SENSOR

DEVICE

CONFIGURATION

MOTOR

CONTROLLER

MOTOR

STARTER

Figure 15. Typical Field Bus Communication Physical Model.

network receives maximum

protection from power system

faults and ground loops.

(involving receiving data from

and transmitting data onto the

network), two Agilent

optocouplers are needed. By

providing galvanic isolation, data

integrity is retained via noise

reduction and the elimination of

false signals. In addition, the

Optical Isolation for

Field Bus Networks

To recognize the full benefits of

these networks, each recom-

mends providing galvanic

isolation using Agilent

Within an isolated node, such as

the DeviceNet Node shown in

Figure 16, some of the node’s

components are referenced to a

ground other than V- of the

optocouplers. Since network

communication is bi-directional

network. These components could

include such things as devices with

serial ports, parallel ports, RS232

and RS485 type ports. As shown in

Figure 16, power from the network

is used only for the transceiver and

input (network) side of the

AC LINE

NODE/APP SPECIFIC

uP/CAN

LOCAL

NODE

SUPPLY

GALVANIC

ISOLATION

BOUNDARY

HCPL

772x/072x

optocouplers.

772x/072x

5 V REG.

Isolation of nodes connected to any

of the three types of digital field

bus networks is best achieved by

using the HCPL-772X/072X

optocouplers. For each network,

the HCPL-772X/072X satisify the

critical propagation delay and pulse

width distortion requirements over

the temperature range of 0°C to

+85°C, and power supply voltage

range of 4.5 V to 5.5 V.

TRANSCEIVER

DRAIN/SHIELD

SIGNAL

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

POWER

NETWORK

POWER

SUPPLY

Figure 16. Typical DeviceNet Node.

Implementing CC-Link

with the HCPL-772X/

072X

CC-Link (Control and

Communication Link) is

developed to merge control and

information in the low-level

network (field network) by PCs,

thereby making the multivendor

environment a reality. It has data

control and message-exchange

function, as well as bit control

function, and operates at the

speed up to 10 Mbps.

Power Supplies and Bypassing

possible to the input and output

power supply pins of the HCPL-

772X/072X. For each capacitor,

the total lead length between both

ends of capacitor and the power

supply pins should not exceed

20 mm. The bypass capacitors are

required because of the high

speed digital nature of the signals

inside the optocoupler.

The recommended CC-Link circuit

is shown in Figure 17. Since the

HCPL-772X/072X are fully

compatible with CMOS logic level

signals, the optocoupler is

connected directly to the

transceiver. Two bypass

capacitors (with values between

0.01 µF and 0.1 µF) are required

and should be located as close as

RS485

TRANSCEIVER IC

DD1

(5 V)

DD2

(5 V)

HCPL-7720#500

FIL

DD2

DD1

10 K

0.1 µ

RD1

0.1 µ

GND

HCPL-7720#500

SLD

DD1

DD2

0.1 µ

GND

HCPL-2611#560

1 K

–

MPU

BOARD

OUTPUT

HC14

390

GND

HC14

10 K

HCPL-2611#560

1 K

–

SDGATEON

HC14

390

GND

HC14

10 K

Figure 17. Recommended CC-Link Application Circuit.

Implementing DeviceNet

and SDS with the

broadcast-oriented, communica-

tions protocol — the Controller

Area Network (CAN). Three types

of isolated nodes are

recommended for use on these

networks: Isolated Node Powered

by the Network (Figure 18),

Isolated Node with Transceiver

19), and Isolated Node Providing

Power to the Network

HCPL-772X/072X

With transmission rates up to 1

Mbit/s, both DeviceNet and SDS

are based upon the same

(Figure 20).

Isolated Node Powered by the

Network

This type of node is very flexible

and as can be seen in Figure 18,

is regarded as “isolated” because

not all of its components have the

same ground reference. Yet, all

components are still powered by

the network. This node contains

two regulators: one is isolated and

powers the CAN controller, node-

specific application and isolated

(node) side of the two optocoup-

lers while the other is non-

NODE/APP SPECIFIC

uP/CAN

ISOLATED

GALVANIC

SWITCHING

ISOLATION

POWER

HCPL

772x/072x

HCPL

772x/072x

BOUNDARY

SUPPLY

REG.

TRANSCEIVER

DRAIN/SHIELD

SIGNAL

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

isolated. The non-isolated

regulator supplies the transceiver

and the non-isolated (network)

half of the two optocouplers.

POWER

NETWORK

POWER

SUPPLY

Figure 18. Isolated Node Powered by the Network.

an application requires a

Specifically, when input power

(V_DD1) to the HCPL-772X/072X

located in the transmit path is

eliminated, a RECESSIVE bus

state is ensured as the

Isolated Node with

Transceiver Powered by the

Network

Figure 19 shows a node powered

by both the network and another

source. In this case, the trans-

ceiver and isolated (network) side

of the two optocouplers are

significant amount of power. This

method is also desirable as it does

not heavily load the network.

HCPL-772X/072X output voltage

(V_O) go HIGH.

More importantly, the unique

“dual-inverting” design of the

HCPL-772X/072X ensure the

network will not “lock-up” if

either AC line power to the node

is lost or the node powered-off.

*Bus V+ Sensing

It is suggested that the Bus V+

sense block shown in Figure 19

of the node is powered by the AC

line which is very beneficial when

AC LINE

be implemented. A locally

powered node with an un-

powered isolated Physical Layer

will accumulate errors and

NON ISO

5 V

NODE/APP SPECIFIC

uP/CAN

become bus-off if it attempts to

transmit. The Bus V+ sense

signal would be used to change

the BOI attribute of the DeviceNet

Object to the “auto-reset” (01)

value. Refer to Volume 1, Section

5.5.3. This would cause the node

to continually reset until bus

power was detected. Once power

was detected, the BOI attribute

would be returned to the “hold in

bus-off” (00) value. The BOI

attribute should not be left in the

“auto-reset” (01) value since this

defeats the jabber protection

capability of the CAN error

GALVANIC

ISOLATION

BOUNDARY

HCPL

772x/072x

HCPL

772x/072x

*HCPL

772x/072x

REG.

TRANSCEIVER

DRAIN/SHIELD

SIGNAL

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

POWER

NETWORK

POWER

SUPPLY

* OPTIONAL FOR BUS V + SENSE

confinement. Any inexpensive low

frequency optical isolator can be

used to implement this feature.

Figure 19. Isolated Node with Transceiver Powered by the Network.

provides five (5) volts locally. The

Isolated Node Providing

Power to the Network

Figure 20 shows a node providing

power to the network. The AC line

powers a regulator which

the transceiver and isolated

(network) side of the two

AC line also powers a 24 volt

isolated supply, which powers the

network, and another five-volt

regulator, which, in turn, powers

optocouplers. This method is

recommended when there are a

limited number of devices on the

network that don’t require much

power, thus eliminating the need

for separate power supplies.

AC LINE

DEVICENET NODE

More importantly, the unique

“dual-inverting” design of the

HCPL-772X/072X ensure the

network will not “lock-up” if

either AC line power to the node

is lost or the node powered-off.

Specifically, when input power

(V_DD1) to the HCPL-772X/072X

located in the transmit path is

eliminated, a RECESSIVE bus

state is ensured as the

NODE/APP SPECIFIC

5 V REG.

uP/CAN

ISOLATED

GALVANIC

SWITCHING

ISOLATION

POWER

HCPL

772x/072x

HCPL

772x/072x

BOUNDARY

SUPPLY

5 V REG.

TRANSCEIVER

DRAIN/SHIELD

SIGNAL

HCPL-772X/072X output voltage

(V_O) go HIGH.

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

POWER

Figure 20. Isolated Node Providing Power to the Network.

Power Supplies and Bypassing

to the CAN transceiver. Two

bypass capacitors (with values

between 0.01 and 0.1 µF) are

required and should be located as

close as possible to the input and

output power-supply pins of the

HCPL-772X/072X. For each

capacitor, the total lead length

between both ends of the

capacitor and the power supply

pins should not exceed 20 mm.

The bypass capacitors are

required because of the high-

speed digital nature of the signals

inside the optocoupler.

The recommended DeviceNet

application circuit is shown in

Figure 21. Since the HCPL-772X/

072X are fully compatible with

CMOS logic level signals, the

optocoupler is connected directly

GALVANIC

ISOLATION

BOUNDARY

ISO 5 V

5 V

LINEAR OR

SWITCHING

REGULATOR

DD2

DD1

0.01

µF

TX0

HCPL-772x

HCPL-072x

5 V+

TxD

0.01 µF

CANH

4 CAN+

3 SHIELD

2 CAN–

1 V–

82C250

GND

0.01 µF

CANL

REF

GND

VREF

RXD

GND

0.01 µF

500 V

0.01

µF

1 M

RX0

30 V

HCPL-772x

HCPL-072x

0.01 µF

DD1

DD2

ISO 5 V

5 V

Figure 21. Recommended DeviceNet Application Circuit.

Implementing PROFIBUS

with the HCPL-772X/072X

PROFIBUS USER:

CONTROL STATION

(CENTRAL PROCESSING)

OR FIELD DEVICE

An acronym for Process Fieldbus,

PROFIBUS is essentially a twisted-

pair serial link very similar to RS-

485 capable of achieving high-speed

communication up to 12 MBd. As

shown in Figure 22, a PROFIBUS

Controller (PBC) establishes the

USER INTERFACE

FDL/APP

PROCESSOR

UART

connection of a field automation

PBC

unit (control or central processing

station) or a field device to the

transmission medium. The PBC

consists of the line transceiver,

OPTICAL ISOLATION

TRANSCEIVER

optical isolation, frame character

transmitter/receiver (UART), and

MEDIUM

the FDL/APP processor with the

interface to the PROFIBUS user.

Figure 22. PROFIBUS Controller (PBC).

Power Supplies and Bypassing

capacitor, the total lead length

between both ends of the

capacitor and the power supply

pins should not exceed 20 mm.

The bypass capacitors are

required because of the high-

speed digital nature of the signals

inside the optocoupler.

after each master/slave

transmission cycle. Specifically,

the HCPL-061N disables the

transmitter of the line driver by

putting it into a high state mode.

In addition, the HCPL-061N

switches the RX/TX driver IC into

the listen mode. The HCPL-061N

offers HCMOS compatibility and

the high CMR performance

(1 kV/µs at V_CM= 1000 V)

essential in industrial

The recommended PROFIBUS

application circuit is shown in

Figure 23. Since the HCPL-772X/

072X are fully compatible with

CMOS logic level signals, the

optocoupler is connected directly

to the transceiver. Two bypass

capacitors (with values between

0.01 and 0.1 µF) are required and

should be located as close as

possible to the input and output

power-supply pins of the

Being very similar to multi-station

RS485 systems, the HCPL-061N

optocoupler provides a transmit

disable function which is

communication interfaces.

necessary to make the bus free

HCPL-772X/072X. For each

GALVANIC

ISOLATION

BOUNDARY

5 V

ISO 5 V

DD1

ISO 5 V

DD2

0.01 µF

HCPL-772x

HCPL-072x

0.01

µF

0.01

µF

SHIELD

–

SN75176B

GND

5 V

ISO 5 V

GND

DD2

DD1

0.01

µF

1 M

0.01 µF

HCPL-772x

HCPL-072x

0.01 µF

GND

ISO 5 V

5 V

ANODE

680 Ω

0.01

µF

1, 0 kΩ

CATHODE

Tx ENABLE

GND

HCPL-061N

www.semiconductor.agilent.com

Data subject to change.

Figure 23. Recommended PROFIBUS Application Circuit.

Obsoletes 5967-6174E (5/98)

5968-2122E (11/99)

HCPL-7720#300 [ETC]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E