HCPL-7723-060 [AGILENT]
50 MBd 2 ns PWD High Speed CMOS Optocoupler; 50 MBd的2纳秒PWD高速CMOS光电耦合器
| 型号： | HCPL-7723-060 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | 50 MBd 2 ns PWD High Speed CMOS Optocoupler |
| 文件： | 总12页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HCPL-7723 & HCPL-0723
50 MBd 2 ns PWD
High Speed CMOS Optocoupler
Data Sheet
Features
• +5 V CMOS compatibility
• High speed: 50 MBd min.
• 2 ns max. pulse width distortion
• 22 ns max. prop. delay
Description
Basic building blocks of HCPL-
7723/0723 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC, which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high speed
Available in either 8-pin DIP or
SO-8 package style respectively, the
HCPL-7723 or HCPL-0723
optocoupler utilize the latest CMOS
IC technology to achieve out-
standing speed performance of
minimum 50 MBd data rate and
2 ns maximum pulse width
distortion.
• 16 ns max. prop. delay skew
• 10 kV/µs min. common mode
rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals
(Pending)
UL recognized
– 2500 V rms for 1 min. per UL1577
for HCPL-7723
– 3750 V rms for 1 min. per UL1577
for HCPL-0723
transimpedance amplifier, and a
voltage comparator with an
output driver.
CSA component acceptance
notice #5
Functional Diagram
VDE 0884
– Viorm = 630 Vpeak for HCPL-7723
option 060
– Viorm = 560 Vpeak for HCPL-0723
option 060
**V
1
2
8
7
V
**
DD2
DD1
V
NC*
I
I
O
3
4
6
5
*
V
O
Applications
LED1
• Digital fieldbus isolation: CC-Link,
DeviceNet, Profibus, SDS
GND
GND
2
1
SHIELD
Isolated A/D or D/A conversion
•
*
PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
• Multiplexed data transmission
• High Speed Digital Input/Output
• Computer peripheral interface
• Microprocessor system interface
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
TRUTH TABLE
(POSITIVE LOGIC)
V , INPUT
I
LED1
V
, OUTPUT
O
H
L
OFF
ON
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.
Package Outline Drawings
HCPL-7723 8-Pin DIP Package
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
OPTION 060 CODE*
DATE CODE
TYPE NUMBER
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
A XXXXV
YYWW
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*OPTION 300 AND 500 NOT MARKED.
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
2
HCPL-7723 Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
1.016 (0.040)
1.194 (0.047)
6
5
8
1
7
4.826
(0.190)
TYP.
6.350 ± 0.25
(0.250 ± 0.010)
9.398 (0.370)
9.906 (0.390)
2
3
4
0.381 (0.015)
0.635 (0.025)
1.194 (0.047)
1.778 (0.070)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
4.19
+ 0.003)
- 0.002)
MAX.
(0.165)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS AND (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
HCPL-0723 Small Outline SO-8 Package
TYPE NUMBER
8
7
6
5
4
5.842 ± 0.203
(0.236 ± 0.008)
XXXV
YWW
OPTION 060 CODE*
3.937 ± 0.127
(0.155 ± 0.005)
DATE CODE
2
1
3
0.381 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSG
0.432
(0.017)
7°
45° X
5.080 ± 0.005
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.152 ± 0.051
(0.006 ± 0.002)
0.305
MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
*OPTION 500 NOT MARKED.
(0.012)
3
Device Selection Guide
8-Pin DIP (300 mil)
HCPL-7723
Small Outline SO-8
HCPL-0723
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example:
HCPL-7723-XXX
060 = VDE0884 Option.
300 = Gull Wing Surface Mount Option (HCPL-7723 only).
500 = Tape and Reel Packaging Option.
No Option and Option 300 contain 50 units (HCPL-7723), 100 units (HCPL-0723) per tube. Option 500
contain 1000 units (HCPL-7723), 1500 units (HCPL-0723) per reel. Option data sheets available. Contact
sales representative or authorized distributor.
4
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
100
0
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
Regulatory Information
The HCPL-7723/0723 will be
approved by the following
organizations:
VDE
(HCPL-7723 option 060)
Approved according to VDE
0884/06.92, File 6591-23-4880-
1005.
UL
Recognized under UL1577,
component recognition program,
File E55361.
TUV Rheinland
(HCPL-0723 Option 060)
Approved according to VDE
0884/06.92, Certificate
R9650938.
CSA
Approved under CSA Component
Acceptance Notice #5, File
CA88324.
Insulation and Safety Related Specifications
Value
Symbol 7723 0723
Parameter
Units
Conditions
Minimum External Air Gap
(Clearance)
L(I01)
7.1
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(Creepage)
L(I02)
7.4
4.8
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
0.08
Insulation thickness between emitter and
detector; also known as distance through
insulation.
Tracking Resistance
(Comparative Tracking Index)
CTI
≥ 175 ≥ 175 Volts
IIIa IIIa
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
5
All Agilent data sheets report the
creepage and clearance inherent
to the optocoupler component
itself. These dimensions are
needed as a starting point for the
equipment designer when
determining the circuit insulation
requirements. However, once
mounted on a printed circuit
board, minimum creepage and
clearance requirements must be
met as specified for individual
equipment standards. For
creepage, the shortest distance
path along the surface of a
printed circuit board between the
solder fillets of the input and
output leads must be considered.
There are recommended
techniques such as grooves and
ribs, which may be used on a
printed circuit board to achieve
desired creepage and clearances.
Creepage and clearance distances
will also change depending on
factors such as pollution degree
and insulation level.
VDE 0884 Insulation Related Characteristics (Option 060)
Description
HCPL-7723
Option 060
HCPL-0723
Option 060
Symbol
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V rms
for rated mains voltage ≤ 300 V rms
I-IV
I-IV
I-III
I-IV
I-III
for rated mains voltage ≤ 450 V rms
Climatic Classification
55/85/21
2
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
V
630
560
V peak
V peak
IORM
1181
1050
PR
V
IORM
x 1.875 = V , 100% Production Test with t = 1 sec,
PR m
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
945
840
V peak
V peak
PR
V
IORM
x 1.5 = V , Type and Sample Test, t = 60 sec,
PR m
Partial Discharge < 5 pC
Highest Allowable Overvoltage*
V
6000
4000
IOTM
(Transient Overvoltage, t = 10 sec)
ini
Safety Limiting Values (maximum values allowed in the
event of a failure, also see Thermal Derating curve,
Figure 11)
Case Temperature
Input Current
Output Power
T
175
230
600
150
150
600
°C
mA
mW
S
I
S,INPUT
S,OUTPUT
P
9
9
Insulation Resistance at T , V = 500 V
R
IO
≥ 10
≥ 10
Ω
S
IO
*Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section
(VDE 0884), for a detailed description.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be
ensured by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.
6
Absolute Maximum Ratings
Parameter
Symbol
Min.
–55
–40
0
Max.
125
Units
°C
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltages
TS
TA
85
°C
VDD1, VDD2
6.0
Volts
Volts
Volts
mA
Input Voltage
VI
–0.5
–0.5
VDD1 +0.5
VDD2 +0.5
10
Output Voltage
VO
IO
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
TA
Min.
–40
4.5
Max.
85
Units
°C
V
Ambient Operating Temperature
Supply Voltages
VDD1, VDD2
VIH
5.5
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
2.0
VDD1
0.8
V
VIL
0.0
V
tr, tf
1.0
ms
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T = +25°C, V
= V = +5 V.
DD2
A
DD1
Parameter
Symbol
Min.
Typ.
7
Max. Units
Test Conditions
[2]
Logic Low Input Supply Current
Logic High Input Supply Current
Output Supply Current
I
10
mA
mA
mA
mA
µA
V
V = 0 V
I
DD1L
DD1H
DD2L
DD2H
I
[2]
I
I
I
I
1.8
12.5
12
3
V = V
I DD1
17.5
16.5
10
Input Current
–10
4.4
4.0
Logic High Output Voltage
V
OH
5.0
4.8
0
I = –20 µA, V = V
O I IH
V
I = –4 mA, V = V
O I IH
Logic Low Output Voltage
V
OL
0.1
1.0
V
I = 20 µA, V = V
O I IL
0.5
V
I = 4 mA, V = V
O I IL
7
Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T = +25°C, V
= V
= +5 V.
DD2
A
DD1
Parameter
Symbol Min. Typ.
Max. Units Test Conditions
Propagation Delay Time to Logic
Low Output
t
16
22
ns
C = 15 pF CMOS Signal Levels
L
PHL
[3]
Propagation Delay Time to Logic
High Output
t
16
22
ns
C = 15 pF CMOS Signal Levels
L
PLH
[3]
Pulse Width
PW
20
50
ns
C = 15 pF CMOS Signal Levels
L
Maximum Data Rate
MBd
ns
C = 15 pF CMOS Signal Levels
L
[4]
Pulse Width Distortion |t
- t
|
|PWD|
1
2
C = 15 pF CMOS Signal Levels
L
PHL
PLH
[5]
Propagation Delay Skew
t
t
t
16
ns
C = 15 pF CMOS Signal Levels
L
PSK
R
Output Rise Time (10% – 90%)
Output Fall Time (90% - 10%)
8
ns
C = 15 pF CMOS Signal Levels
L
6
ns
C = 15 pF CMOS Signal Levels
L
F
Common Mode Transient Immunity
at Logic High Output
|CM |
10
10
15
kV/µs
V
= 1000 V T = 25°C,
H
CM
,
A
[6]
V = V
I
V
> 0.8 V
DD1,
O
DD2
Common Mode Transient Immunity
|CM |
15
kV/µs
V
= 1000 V T = 25°C,
L
CM , A
[6]
at Logic Low Output
V = 0 V V < 0.8 V
I , O
8
Package Characteristics
All Typical Specifications are at T = 25°C.
A
Parameter
Symbol Min.
Typ.
Max. Units
V rms RH ≤ 50%, t = 1 min,
T = 25°C
Test Conditions
Input-Output Momentary
Withstand Voltage
–7723
–0723
V
2500
3750
ISO
[7,8,9]
A
[7]
12
Input-Output Resistance
R
C
C
θ
10
Ω
V
= 500 V dc
I-O
I-O
I
I-O
Input-Output Capacitance
0.6
3.0
145
pF
f = 1 MHz
[10]
Input Capacitance
pF
Input IC Junction-to-Case
Thermal Resistance
–7723
°C/W
Thermocouple located at
center underside of package
jci
–0723
–7723
–0723
160
145
135
Output IC Junction-to-Case
Thermal Resistance
θ
°C/W
jco
Package Power Dissipation
P
PD
150
mW
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when VI is low and OFF when VI is high.
3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 µA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 3000 Vrms for 1 second (leakage detection
current limit. II-O ≤ 5 µA.)
9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
10. CI is the capacitance measured at pin 2 (VI).
9
Application Information
should be between 0.01 µF and 0.1 a system as illustrated in Figure 3.
µF. For each capacitor, the total
lead length between both ends of
The propagation delay from low to
high (t ) is the amount of time
Bypassing and PC Board Layout
PLH
The HCPL-7723/0723
the capacitor and the power-supply required for an input signal to
optocouplers are extremely easy
to use. No external interface
circuitry is required because the
HCPL-7723/0723 use high-speed
CMOS IC technology allowing
CMOS logic to be connected
directly to the inputs and outputs.
pins should not exceed 20 mm.
Figure 2 illustrates the
recommended printed circuit
board layout for the HCPL-7723/
0723.
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low (t
) is
PHL
the amount of time required for
the input signal to propagate to
the output, causing the output to
Propagation Delay, Pulse-Width
Distortion and Propagation Delay Skew change from high to low.
As shown in Figure 1, the only
external components required for
proper operation are two bypass
capacitors. Capacitor values
Propagation Delay is a figure of
merit which describes how quickly
a logic signal propagates through
V
8
7
6
5
V
DD1
1
2
3
4
DD2
C1
C2
V
I
NC
NC
V
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 1. Functional diagram.
V
DD1
V
V
DD2
V
I
C1
C2
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 2. Recommended printed circuit board layout.
INPUT
5 V CMOS
0 V
V
50%
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
10%
10%
O
V
OL
Figure 3. Timing diagram to illustrate propagation delay, tplh and tphl.
10
Pulse-width distortion (PWD) is
the difference between t and
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of
the optocouplers at different
times. If this difference in
propagation delay is large enough
it will determine the maximum
rate at which parallel data can be
sent through the optocouplers.
illustrated in Figure 4, if the
inputs of a group of optocouplers
are switched either ON or OFF at
PHL
t
and often determines the
PHL
maximum data rate capability of
a transmission system. PWD can
be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically,
PWD on the order of 20-30% of
the minimum pulse width is
tolerable.
the same time, t
is the
PSK
difference between the shortest
propagation delay, either t
or
PLH
t
, and the longest propagation
PHL
delay, either t
or t
.
PLH
PHL
As mentioned earlier, t
can
PSK
Propagation delay skew is defined
as the difference between the
minimum and maximum
determine the maximum parallel
data transmission rate. Figure 5
is the timing diagram of a typical
parallel data application with
both the clock and data lines
being sent through the
optocouplers. The figure shows
data and clock signals at the
inputs and outputs of the
Propagation delay skew, t , is
propagation delays, either t
or
PSK
PLH
an important parameter to
t
, for any given group of
PHL
consider in parallel data applica-
tions where synchronization of
signals on parallel data lines is a
concern. If the parallel data is
being sent through a group of
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
operating temperature). As
optocouplers. In this case the
data is assumed to be clocked off
of the rising edge of the clock.
V
I
50%
Propagation delay skew
represents the uncertainty of
where an edge might be after
being sent through an
optocoupler. Figure 5 shows that
there will be uncertainty in both
the data and clock lines. It is
important that these two areas of
uncertainty not overlap,
2.5 V,
CMOS
V
O
t
PSK
V
50%
I
otherwise the clock signal might
arrive before all of the data
outputs have settled, or some of
the data outputs may start to
change before the clock signal
has arrived. From these
2.5 V,
CMOS
V
O
Figure 4. Timing diagram to illustrate propagation delay skew, tpsk.
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
DATA
parallel application is twice t
.
PSK
A cautious design should use a
slightly longer pulse width to
ensure that any additional
INPUTS
CLOCK
uncertainty in the rest of the
circuit does not cause a problem.
DATA
The HCPL-7723/0723
optocouplers offer the advantage
of guaranteed specifications for
propagation delays, pulse-width
distortion, and propagation delay
skew over the recommended
temperature and power supply
ranges.
OUTPUTS
t
PSK
CLOCK
t
PSK
Figure 5. Parallel data transmission example.
11
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(408) 654-8675
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (+65) 6271 2451
India, Australia, New Zealand: (+65) 6271 2394
Japan: (+81 3) 3335-8152(Domestic/Interna-
tional), or 0120-61-1280(Domestic Only)
Korea: (+65) 6271 2194
Malaysia, Singapore: (+65) 6271 2054
Taiwan: (+65) 6271 2654
Data subject to change.
Copyright © 2002 Agilent Technologies, Inc.
December 2, 2002
5988-7986EN
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