HCPL-7723-320E [AVAGO]
50 MBd 2 ns PWD High Speed CMOS Optocoupler; 50 MBd的2纳秒PWD高速CMOS光电耦合器
| 型号： | HCPL-7723-320E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 50 MBd 2 ns PWD High Speed CMOS Optocoupler |
| 文件： | 总12页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-7723/0723
50 MBd 2 ns PWD High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
• +5 V CMOS compatibility
• High speed: 50 MBd min.
• 2 ns max. pulse width distortion
• 22 ns max. prop. delay
Available in either 8-pin DIP or SO-8 package style respec-
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize
the latest CMOS IC technology to achieve outstanding
speed performance of minimum 50 MBd data rate and
2ns maximum pulse width distortion.
• 16 ns max. prop. delay skew
• 10 kV/µs min. common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals:
Basic building blocks of HCPL-7723/0723 are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver
IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
UL recognized
– 5000 V for 1 min. per UL1577 for HCPL-7723 for
rms
option 020
– 3750 V for 1 min. per UL1577 for HCPL-0723
rms
CSA component acceptance notice #5
Functional Diagram
IEC/EN/DIN EN 60747-5-5
– V
– V
= 630 V
= 567 V
for HCPL-7723 option 060
for HCPL-0723 option 060
iorm
peak
iorm
peak
**V
1
2
8
7
V
**
DD2
DD1
V
I
NC*
Applications
I
O
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
3
4
6
5
NC*
V
O
LED1
• Multiplexed data transmission
• High speed digital input/output
• Computer peripheral interface
• Microprocessor system interface
GND
GND
2
1
SHIELD
*
PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
TRUTH TABLE
(POSITIVE LOGIC)
V , INPUT
I
LED1
V
, OUTPUT
O
H
L
OFF
ON
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.
Package Outline Drawings
HCPL-7723 8-Pin DIP Package
9.65 ꢀ.ꢁ5
(ꢀ.38ꢀ ꢀ.ꢀ0ꢀꢂ
7.6ꢁ ꢀ.ꢁ5
(ꢀ.3ꢀꢀ ꢀ.ꢀ0ꢀꢂ
OPTION ꢀ6ꢀ CODE*
DATE CODE
TYPE NUMBER
8
0
7
6
5
6.35 ꢀ.ꢁ5
(ꢀ.ꢁ5ꢀ ꢀ.ꢀ0ꢀꢂ
A XXXXV
YYWW
ꢁ
3
4
0.78 (ꢀ.ꢀ7ꢀꢂ MAX.
0.09 (ꢀ.ꢀ47ꢂ MAX.
+ ꢀ.ꢀ76
- ꢀ.ꢀ50
ꢀ.ꢁ54
5° TYP.
+ ꢀ.ꢀꢀ3ꢂ
- ꢀ.ꢀꢀꢁꢂ
(ꢀ.ꢀ0ꢀ
3.56 ꢀ.03
(ꢀ.04ꢀ ꢀ.ꢀꢀ5ꢂ
4.7ꢀ (ꢀ.085ꢂ MAX.
ꢀ.50 (ꢀ.ꢀꢁꢀꢂ MIN.
ꢁ.9ꢁ (ꢀ.005ꢂ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢂ.
*OPTION 3ꢀꢀ AND 5ꢀꢀ NOT MARKED.
0.ꢀ8ꢀ ꢀ.3ꢁꢀ
(ꢀ.ꢀ43 ꢀ.ꢀ03ꢂ
ꢀ.65 (ꢀ.ꢀꢁ5ꢂ MAX.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.05 mm (6 milsꢂ MAX.
ꢁ.54 ꢀ.ꢁ5
(ꢀ.0ꢀꢀ ꢀ.ꢀ0ꢀꢂ
2
HCPL-7723 Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 0.ꢀ5
(0.380 0.0ꢁ0ꢂ
ꢁ.0ꢁ6 (0.040ꢂ
6
5
8
ꢁ
7
6.350 0.ꢀ5
(0.ꢀ50 0.0ꢁ0ꢂ
ꢁ0.9 (0.430ꢂ
ꢀ.0 (0.080ꢂ
ꢀ
4
3
ꢁ.ꢀ7 (0.050ꢂ
9.65 0.ꢀ5
(0.380 0.0ꢁ0ꢂ
7.6ꢀ 0.ꢀ5
ꢁ.780
(0.070ꢂ
MAX.
ꢁ.ꢁ9
(0.047ꢂ
MAX.
(0.300 0.0ꢁ0ꢂ
+ 0.076
0.ꢀ54
- 0.05ꢁ
3.56 0.ꢁ3
(0.ꢁ40 0.005ꢂ
+ 0.003ꢂ
(0.0ꢁ0
- 0.00ꢀꢂ
ꢁ.080 0.3ꢀ0
(0.043 0.0ꢁ3ꢂ
0.635 0.ꢀ5
(0.0ꢀ5 0.0ꢁ0ꢂ
ꢁꢀ° NOM.
0.635 0.ꢁ30
(0.0ꢀ5 0.005ꢂ
ꢀ.54
(0.ꢁ00ꢂ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢂ.
LEAD COPLANARITY = 0.ꢁ0 mm (0.004 INCHESꢂ.
NOTE: FLOATING LEAD PROTRUSION IS 0.ꢁ5 mm (6 milsꢂ MAX.
HCPL-0723 Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ꢀ.2ꢀ3
(ꢀ.236 ꢀ.ꢀꢀ8ꢁ
XXXV
YWW
3.937 ꢀ.127
(ꢀ.155 ꢀ.ꢀꢀ5ꢁ
TYPE NUMBER
(LAST 3 DIGITSꢁ
DATE CODE
7.49 (ꢀ.295ꢁ
3
PIN ONE
1.9 (ꢀ.ꢀ75ꢁ
ꢀ.4ꢀ6 ꢀ.ꢀ76
(ꢀ.ꢀ16 ꢀ.ꢀꢀ3ꢁ
1.27ꢀ
(ꢀ.ꢀ5ꢀꢁ
BSC
ꢀ.64 (ꢀ.ꢀ25ꢁ
ꢀ.432
(ꢀ.ꢀ17ꢁ
*
7°
5.ꢀ8ꢀ ꢀ.127
(ꢀ.2ꢀꢀ ꢀ.ꢀꢀ5ꢁ
45° X
3.175 ꢀ.127
(ꢀ.125 ꢀ.ꢀꢀ5ꢁ
ꢀ ~ 7°
ꢀ.228 ꢀ.ꢀ25
(ꢀ.ꢀꢀ9 ꢀ.ꢀꢀ1ꢁ
1.524
(ꢀ.ꢀ6ꢀꢁ
ꢀ.2ꢀ3 ꢀ.1ꢀ2
(ꢀ.ꢀꢀ8 ꢀ.ꢀꢀ4ꢁ
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASHꢁ
5.2ꢀ7 ꢀ.254 (ꢀ.2ꢀ5 ꢀ.ꢀ1ꢀꢁ
*
ꢀ.3ꢀ5
(ꢀ.ꢀ12ꢁ
MIN.
DIMENSIONS IN MILLIMETERS (INCHESꢁ. LEAD COPLANARITY = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 INCHESꢁ MAX.
OPTION NUMBER 5ꢀꢀ NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.15 mm (6 milsꢁ MAX.
3
Device Selection Guide
8-Pin DIP (300 mil)
HCPL-7723
Small Outline SO-8
HCPL-0723
Ordering Information
HCPL-0723 and HCPL-7723 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
RoHS
non RoHS
Surface
Mount
Gull
Wing
Tape
UL 5000 Vrms/
IEC/EN/DIN
Compliant Compliant Package
& Reel 1 Minute rating EN 60747-5-5 Quantity
-000E
-300E
-500E
-020E
no option
-300
300 mil DIP-8
50 per tube
50 per tube
X
X
X
X
-500
X
X
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
-020
X
X
X
HCPL-7723 -320E
-320
X
X
X
X
-520E
-520
-060E
-060
X
X
X
-360E
-560E
-360
X
X
X
X
X
X
X
X
-560
X
X
X
-000E
no option
-500
SO-8
HCPL-0723 -500E
-060E
-060
X
X
-560E
-560
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7723-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-5 Safety Approval and RoHS compliant.
Example 2:
HCPL-0723 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
4
Regulatory Information
The HCPL-7723/0723 have been approved by the following organizations:
UL
Recognized under UL1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-5
Approved with Maximum Working Insulation Voltage:
V
V
= 567 V
= 630 V
for HCPL-0723,
for HCPL-7723
iorm
peak
iorm
peak
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Insulation and Safety Related Specifications
Value
Parameter
Symbol
7723
0723
Units
Conditions
Minimum External Air Gap
(Clearance)
L(I01)
7.1
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(Creepage)
L(I02)
CTI
7.4
4.8
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
0.08
Insulation thickness between emitter and
detector; also known as distance through
insulation.
Tracking Resistance
(Comparative Tracking Index)
≥ 175
IIIa
≥ 175
IIIa
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
5
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the
equipment designer when determining the circuit insula-
tion requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance require-
ments must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs, which may be used on a printed circuit board
to achieve desired creepage and clearances. Creepage
and clearance distances will also change depending
on factors such as pollution degree and insulation
level.
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics (Option 060)
Characteristic
Description
Symbol
HCPL-7723 HCPL-0723 Unit
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
Climatic Classification
I – IV
I – III
I – IV
I – IV
I – III
I – III
55/85/21 55/85/21
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
2
2
VIORM
630
567
Vpeak
VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
VPR
1181
1063
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature
VPR
1008
8000
907
Vpeak
Vpeak
VIOTM
6000
TS
175
230
150
°C
Input Current
IS, INPUT
150
mA
mW
Ω
Output Power
PS, OUTPUT 600
RS
≥ 109
600
≥ 109
Insulation Resistance at TS, VIO = 500 V
*Refer to the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
6
Absolute Maximum Ratings
Parameter
Symbol
Min.
–55
–40
0
Max.
125
85
Units
°C
Storage Temperature
Ambient Operating Temperature
Supply Voltages
T
S
[1]
T
A
°C
V
V
V
, V
6.0
Volts
Volts
Volts
mA
DD1 DD2
Input Voltage
–0.5
–0.5
V
V
+0.5
+0.5
I
DD1
Output Voltage
O
DD2
Average Output Current
Lead Solder Temperature
I
O
10
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Solder Reflow Temperature Profile
Recommended Operating Conditions
Parameter
Symbol
Min.
–40
4.5
Max.
85
Units
°C
Ambient Operating Temperature
Supply Voltages
T
A
V
V
V
, V
5.5
V
DD1 DD2
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
2.0
V
DD1
V
IH
IL
0.0
0.8
1.0
V
t t
r, f
ms
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T = +25°C, V = V = +5 V.
A
DD1
DD2
Parameter
Symbol
Min.
Typ.
8.4
0.6
2.1
2.0
Max.
10
3
Units
Test Conditions
[2]
Logic Low Input Supply Current
I
I
I
I
I
mA
mA
mA
mA
µA
V
V = 0 V; Figure 1
I
DD1L
DD1H
DD2L
DD2H
I
[2]
Logic High Input Supply Current
Output Supply Current
V = V ; Figure 2
I DD1
5
Figure 3
Figure 4
5
Input Current
–10
4.4
10
Logic High Output Voltage
V
OH
5.0
4.8
0
I = –20 µA, V = V
O I IH
4.0
V
I = –4 mA, V = V
O I IH
Logic Low Output Voltage
V
OL
0.1
1.0
V
I = 20 µA, V = V
O I IL
0.5
V
I = 4 mA, V = V
O I IL
7
Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T = +25°C, V = V = +5 V.
A
DD1
DD2
Parameter
Symbol
Min. Typ.
Max.
Units
Test Conditions
C = 15 pF CMOS Signal Levels; Figure 5
Propagation Delay Time to Logic
t
PHL
16
22
ns
L
[3]
Low Output
Propagation Delay Time to Logic
High Output
t
PLH
16
22
ns
C = 15 pF CMOS Signal Levels; Figure 5
L
[3]
Pulse Width
PW
20
50
1
ns
C = 15 pF CMOS Signal Levels
L
Maximum Data Rate
MBd
ns
C = 15 pF CMOS Signal Levels
L
[4]
Pulse Width Distortion |t - t
|
|PWD|
2
C = 15 pF CMOS Signal Levels; Figure 6
L
PHL PLH
[5]
Propagation Delay Skew
t
t
t
16
ns
C = 15 pF CMOS Signal Levels
L
PSK
Output Rise Time (10% – 90%)
Output Fall Time (90% - 10%)
Common Mode Transient Immunity
8
6
ns
C = 15 pF CMOS Signal Levels
L
R
ns
C = 15 pF CMOS Signal Levels
L
F
|CM |
10
10
15
kV/µs
V = 1000 V T = 25°C,
CM , A
H
[6]
at Logic High Output
V = V
V > 0.8 V
DD1, O DD2
I
Common Mode Transient Immunity
|CM |
15
kV/µs
V = 1000 V T = 25°C,
CM , A
V = 0 V V < 0.8 V
I , O
L
[6]
at Logic Low Output
8
Package Characteristics
All Typical Specifications are at T = 25°C.
A
Parameter
Symbol Min.
Typ.
Max.
Units
Test Conditions
Input-Output Momentary
Withstand Voltage
–7723
Option 020
–0723
V
ISO
3750
5000
3750
V rms
RH ≤ 50%, t = 1 min,
T = 25°C
A
[7,8,9]
[7]
12
Input-Output Resistance
R
C
C
10
Ω
V = 500 V dc
I-O
I-O
I-O
I
Input-Output Capacitance
0.6
3.0
pF
f = 1 MHz
[10]
Input Capacitance
pF
Input IC Junction-to-Case
Thermal Resistance
–7723
–0723
θ
145
160
°C/W
Thermocouple located at
center underside of package
jci
jco
PD
Output IC Junction-to-Case
Thermal Resistance
–7723
–0723
θ
145
135
°C/W
mW
Package Power Dissipation
P
150
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when V is low and OFF when V is high.
I
I
3.
t
propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the V sig-
P
H
L
O
nal. t
propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the V
O
PLH
signal.
4. PWD is defined as |t
PHL PLH
5.
t
PSK
is equal to the magnitude of the worst case difference in t
within the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining V > 0.8 V . CML is the maximum com-
O
DD2
mon mode voltage slew rate that can be sustained while maintaining V < 0.8 V. The common mode voltage slew rates apply to both rising
O
and falling common mode voltage edges.
7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detec-
tion current limit, I ≤ 5 µA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detec-
I-O
tion current limit. I ≤ 5 µA.)
I-O
9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
10. C is the capacitance measured at pin 2 (V ).
I
I
9
9.0
8.5
8.0
7.5
7.0
6.5
0.6
0.55
0.5
0.45
0.4
-40
-20
0
20
T (°C)
40
60
80
100
-40
-20
0
20
40
T (°C)
60
80
100
A
A
Figure 1: Typical Logic Low Input Supply Current vs. temperature
Figure 2. Typical Logic High Input Supply Current vs. temperature
3
2.5
2
3.0
2.5
2.0
1.5
1.0
1.5
1
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
T (°C)
A
T (°C)
A
Figure 3. Typical Logic Low Output Supply Current vs. temperature
Figure 4. Typical Logic High Output Supply Current vs. temperature
2
1.8
1.6
1.4
1.2
1
22
20
18
16
0.8
0.6
0.4
0.2
0
14
T
T
plh
phl
12
10
-20
-40
0
20
40
T (°C)
60
80
100
-40
-20
0
20
40
T (°C)
60
80
100
A
A
Figure 5. Typical propagation delay vs. temperature
Figure 6. Typical pulse width distortion vs. temperature
10
Application Information
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Bypassing and PC Board Layout
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 9. The propagation delay from low
The HCPL-7723/0723 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-7723/0723 use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
to high (t ) is the amount of time required for an input
PLH
signal to propagate to the output, causing the output to
change from low to high. Similarly, the propagation delay
from high to low (t ) is the amount of time required for
the input signal to propagate to the output, causing the
output to change from high to low.
PHL
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 8 illustrates the recommended
printed circuit board layout for the HCPL-7723/0723.
V
8
7
6
5
V
V
DD1
1
2
3
4
DD2
C1
C2
V
I
NC
NC
O
GND
GND
1
2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Functional diagram.
V
DD1
V
V
DD2
V
I
C1
C2
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 8. Recommended printed circuit board layout.
INPUT
5 V CMOS
0 V
V
50%
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
10%
10%
O
V
OL
Figure 9. Timing diagram to illustrate propagation delay, tplh and tphl.
11
Pulse-width distortion (PWD) is the difference between
and t and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse width
is tolerable.
As mentioned earlier, t
can determine the maximum
PSK
t
parallel data transmission rate. Figure 11 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
PHL
PLH
Propagation delay skew, t , is an important parameter
PSK
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocou-
plers.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure 11 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consid-
erations, the absolute minimum pulse width that can
be sent through optocouplers in a parallel application is
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
twice t . A cautious design should use a slightly longer
PSK
pulse width to ensure that any additional uncertainty in
the rest of the circuit does not cause a problem.
delays, either t
or t , for any given group of opto-
PLH
PHL
couplers which are operating under the same conditions
(i.e., the same drive current, supply voltage, output load,
and operating temperature). As illustrated in Figure 10,
if the inputs of a group of optocouplers are switched
The HCPL-7723/0723 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
either ON or OFF at the same time, t is the difference
PSK
between the shortest propagation delay, either t
or
or
PLH
t
t
, and the longest propagation delay, either t
.
PHL
PLH
PHL
V
DATA
I
50%
INPUTS
CLOCK
2.5 V,
CMOS
V
O
t
PSK
V
50%
I
DATA
OUTPUTS
t
PSK
CLOCK
2.5 V,
CMOS
V
O
t
PSK
Figure 10. Timing diagram to illustrate propagation delay skew, tpsk.
Figure 11. Parallel data transmission example.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0566EN
AV02-0643EN - February 26, 2013
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