HMMC-3024 [AGILENT]
DC-12 GHz High Efficiency GaAs HBT MMIC Divide-by-4 Prescaler; DC - 12 GHz的高效率砷化镓HBT MMIC除以4分频器
| 型号： | HMMC-3024 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | DC-12 GHz High Efficiency GaAs HBT MMIC Divide-by-4 Prescaler |
| 文件： | 总9页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HMMC–3024
DC–12 GHz High Efficiency
GaAs HBT MMIC
Divide–by–4 Prescaler
1GC1-8007
Data Sheet
Features
• Wide Frequency Range:
0.2-12 GHz
• High Input Power Sensitivity:
On-chip pre- and post-amps
-25 to +10 dBm (1–8 GHz)
-15 to +18 dBm (8–10 GHz)
-10 to +2 dBm (10–12 GHz)
Chip Size:
1330 x 440 µm (52.4 x 17.3 mils)
10 µm ( 0.4 mils)
Chip Size Tolerance:
Chip Thickness:
Pad Dimensions:
127 15 µm (5.0 0.ꢀ mils)
70 x 70 µm (2.8 x 2.8 mils)
• Dual-mode P : (Chip Form)
out
0 dBm (0.5 V ) @ 40 mA
p–p
-6.0 dBm (0.25 V ) @ 30 mA
p–p
• Low Phase Noise:
-153 dBc/Hz @ 100 kHz Offset
1
Absolute Maximum Ratings
• (+) or (-) Single Supply Bias
Operation
(@ T = 25°C, unless otherwise indicated)
A
• Wide Bias Supply Range:
4.5 to 6.5 volt operating range
Symbol
Parameters/Conditions
Bias supply voltage
Bias supply voltage
Bias supply delta
Min.
Max.
Units
volts
volts
volts
volts
volts
dBm
• Differential I/0 with on-chip
V
V
V
V
+7
CC
EE
CC
50 Ω matching
-7
0
Description
The HMMC-3024 GaAs HBT MMIC
prescaler offers dc to 12 GHz fre-
quency translation for use in
communications and EW systems
incorporating high-frequency PLL
oscillator circuits and signal-path
down conversion applications.
The prescaler provides a large input
power sensitivity window and low
phase noise. In addition to the fea-
tures listed above the device offers
an input disable contact pad to elimi-
nate any self-oscillation condition.
- V
+7
EE
Pre-amp disable voltage
Logic threshold voltage
CW RF input power
DC input voltage
V
V
V
V
Disable
EE
CC
VLogic
-1.5
-1.2
CC
CC
P
V
+10
in(CW)
RFin
(@ RF or RF ports)
V 0.5 volts
CC
in
in
2
T
T
T
Backside operating temperature -40
+85
+1ꢀ5
310
°C
°C
°C
BS
Storage temperature
-ꢀ5
st
Maximum assembly temperature
(ꢀ0 s max.)
max
Notes
1. Operation in excess of any parameter limit (except T ) may cause permanent damage to the device.
BS
ꢀ
2. MTTF > 1 x 10 hours @ T ≤ 85°C. Operation in excess of maximum operating temperature (T ) will degrade MTTF.
BS
BS
dc Specifications/Physical Properties
(T = 25°C, V – V = 5.0 volts, unless otherwise listed)
A
CC
EE
Symbol
Parameters/Conditions
Min.
Typ.
Max.
Units
V
– V
Operating bias supply difference1
4.5
5.0
ꢀ.5
volts
CC
EE
|I | or |I
CC
|
Bias supply current
EE
(HIGH Output Power Configuration2: V
= V
)
34
25
40
30
4ꢀ
35
mA
EE
PwrSel
Bias supply current
(LOW Output Power Configuration: V
= open)
mA
PwrSel
V
V
Quiescent dc voltage appearing at all RF ports
V
volts
CC
RFin(q)
RFout(q)
V
Nominal ECL Logic Level
Logic
(V
contact self-bias voltage, generated on-chip)
V
-1.45
V
-1.32
V
-1.25
volts
CC
CC
CC
Logic
Notes
1. Prescaler will operate over full specified supply voltage range, V or V not to exceed limits specified in Absolute Maximum Ratings section.
CC
EE
2. High output power configuration: P = 0 dBm (V = 0.5 V ). Low output power configuration: P = -ꢀ.0 dBm (V = 0.25 V )
out
out
p-p
out
out
p-p
RF Specifications
(T = 25°C, Z = 50 Ω, V – V = 5.0 volts)
(÷4)
A
0
CC
EE
Symbol
Parameters/Conditions
Min.
Typ.
14
Max.
Units
GHz
ƒ
ƒ
Maximum input frequency of operation
Minimum input frequency of operation1
12
in(max)
in(min)
0.2
0.5
GHz
(P = -10 dBm)
in
ƒ
Output Self-Oscillation Frequency2
@ dc, (Square-wave input)
3.4
GHz
Self–Osc.
P
-15
-15
-15
-10
-5
> -25
> -20
> -20
> -15
> -10
15
+10
+10
+10
+ 5
-1
dBm
dBm
dBm
dBm
dBm
dB
in
@ ƒ = 500 MHz, (Sine-wave input)
in
ƒ
ƒ
ƒ
= 1 to 8 GHz
= 8 to 10 GHz
= 10 to 12 GHz
in
in
in
RL
Small-Signal Input/Output Return Loss (@ ƒ < 10 GHz)
in
S
Small-Signal Reverse Isolation (@ ƒ < 10 GHz)
30
dB
12
in
φ
SSB Phase noise (@ P = 0 dBm, 100 kHz offset from a
-153
dBc/Hz
N
in
ƒ
= 1.2 GHz Carrier)
out
Jitter
Input signal time variation @ zero–crossing
(ƒ = 10 GHz, P = -10 dBm)
1
ps
ps
in
in
T or T
r
Output edge speed (10% to 90% rise/fall time)
70
f
Notes
1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate.
2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Pre-amp
Disable ( V
) feature, or the Differential Input de-biasing technique.
Disable
2
RF Specifications (Continued)
(T = 25°C, Z = 50 Ω, V – V = 5.0 volts)
A
0
CC
EE
1
High Output Power Operating Mode
Symbol
Parameters/Conditions
@ ƒ < 1 GHz
Min.
-2.0
-2.5
-3.0
0.39
0.37
0.35
Typ.
Max.
Units
dBM
dBm
dBm
volts
volts
volts
dBm
P
0.0
out
out
@ ƒ = 2.5 GHz
-0.5
-1.0
0.5
out
@ ƒ = 3.0 GHz
out
|V
P
|
@ ƒ < 1 GHz
out
out(p–p)
@ ƒ = 2.5 GHz
0.47
0.44
-53
out
@ ƒ = 3.0 GHz
out
ƒ
power level appearing at RF or RF
in
in
in
Spitback
out
(@ ƒ 10 GHz, Unused RF or RF unterminated)
out
out
ƒ
power level appearing at RF or RF
-73
-30
dBm
dBc
in
in
out
(@ ƒ = 10 GHz, Both RF & RF terminated)
out
out
in
P
Power level of ƒ appearing at RF or RF
out out
in
feedthru
(@ ƒ = 12 GHz, P = 0 dBm, referred to P (ƒ )
in
in
in
in
H
Second harmonic distortion output level
(@ ƒ = 3.0 GHz, referred to P (ƒ ))
2
-25
dBc
out
out out
2
Low Output Power Operating Mode
P
@ ƒ < 1 GHz
-8.0
-8.5
-9.0
0.20
0.19
0.18
-ꢀ.0
-ꢀ.5
-7.0
0.25
0.24
0.22
dBm
dBm
dBm
volts
volts
volts
out
out
@ ƒ = 2.5 GHz
out
@ ƒ = 3.0 GHz
out
|V
|
@ ƒ < 1 GHz
out
out(p–p)
@ ƒ = 2.5 GHz
out
@ ƒ = 3.0 GHz
out
P
ƒ
power level appearing at RF or RF
Spitback
out in in
(@ ƒ 12 GHz, Unused RF or RF unterminated)
-ꢀ1
-82
-30
-30
dBm
dBm
dBc
dBc
in
out
out
ƒ
power level appearing at RF or RF
in in
out
(@ ƒ = 12 GHz, both RF & RF terminated)
in
out
out
P
Power level of ƒ appearing at RF or RF
out
feedthru
in
out
(@ ƒ = 12 GHz, P = 0 dBm, referred to P (ƒ ))
in
in
in in
H
Second harmonic distortion output level
(@ ƒ = 3.0 GHz, referred to P (ƒ ))
2
out
out out
Notes
1. V
= V
.
PwrSel
PwrSel
EE
2.
V
= Open Circuit.
3
Post Amplifier Stage
Input Preamplifier Stage
4
Figure 1. Simplified Schematic
Several features are designed into this
prescaler:
divide. The device will operate at fre-
quencies down to dc when driven with
a square-wave.
Applications
The HMMC-3024 is designed for use in
high frequency communications, micro-
wave instrumentation, and EW radar
systems where low phase-noise PLL
control circuitry or broad-band frequency
translation is required.
1. Dual-Output Power Feature
Bonding both V and V
pads to
The device may be biased from either a
single positive or single negative sup-
ply bias. The backside of the device is
not dc connected to any dc bias point
on the device.
EE
PwrSel
either ground (positive bias mode) or
the negative supply (negative bias
mode), will deliver ~0 dBm [0.5 V
at the RF output port while drawing
~40 mA supply current. Eliminating
]
p–p
Operation
the V
connection results in re-
For positive supply operation V is
CC
PwrSel
The device is designed to operate
when driven with either a single-ended
or differential sinusoidal input signal
over a 200 MHz to 12 GHz bandwidth.
Below 200 MHz the prescaler input is
“slew-rate” limited, requiring fast ris-
ing and falling edge speeds to properly
duced output power and voltage swing,
nominally biased at any voltage in the
+4.5 to +ꢀ.5 volt range with V (or V
-ꢀ.0 dBm [0.25 V ] but at a reduced
current draw of ~30 mA resulting in
less overall power dissipation.
p–p
EE
EE
& V
) grounded. For negative bias
PwrSel
operation V is typically grounded and
CC
a negative voltage between -4.5 to
(NOTE: V must ALWAYS
EE
-ꢀ.5 volts is applied to V (or V
&
EE
EE
be bonded and V
must
PwrSel
V
).
PwrSel
NEVER be biased to any potential
other than V or open-circuited.)
EE
4
All bonds between the device and this
bypass capacitor should be as short
as possible to limit the inductance.
For operation at frequencies below 1
GHz, a large value capacitor must be
added to provide proper RF bypassing.
Note however, that the input sensitivity
will be reduced slightly due to the
presence of this offset.
2. V
ECL Contact Pad
Logic
Under normal conditions
no connection or external bias
is required to this pad and it
is self-biased to the on-chip ECL
logic threshold voltage
Assembly Techniques
(V -1.35 V). The user can
CC
Figure 3 shows the chip assembly
diagram for single-ended I/O opera-
tion through 12 GHz for either positive
or negative bias supply operation. In
either case the supply contact to the
chip must be capacitively bypassed to
provide good input sensitivity and low
input power feedthrough. Independent
of the bias applied to the device, the
backside of the chip should always be
connected to both a good RF ground
plane and a good thermal heat sinking
region on the mounting surface.
Due to on-chip 50 Ω matching resis-
tors at all four RF ports, no external
termination is required on any unused
RF port. However, improved “Spit-
provide an external bias to this pad
(1.5 to 1.2 volts less than V ) to force
CC
the prescaler to
operate at a system generated logic
threshold voltage.
back” performance ( 20 dB) and
~
input sensitivity can be achieved by
terminating the unused RF port to
3. Input Disable Feature
out
V
through 50 Ω (positive supply) or
If an RF signal with sufficient signal-
to-noise ratio is present at the RF
input, the prescaler will operate and
provide a divided output equal to the
input frequency divided by the divide
modulus. Under certain “ideal” condi-
tions where the input is well matched
at the right input frequency, the
CC
to ground via
a 50 Ω termination (negative
supply operation).
GaAs MMICs are ESD sensitive.
ESD preventive measures must be
employed in all aspects of storage,
handling, and assembly.
All RF ports are dc connected
on-chip to the V contact through
CC
device may “self-oscillate,” especially
under small signal input powers or
with only noise present at the input.
This “self-oscillation” will produce a
undesired output signal also known
as a false trigger. By applying an
external bias to the input disable
on-chip 50 Ω resistors. Under any
bias conditions where V is not dc
CC
MMIC ESD precautions, handling
considerations, die attach and bond-
ing methods are critical factors in suc-
cessful GaAs MMIC performance and
reliability.
grounded, the RF ports should be ac
coupled via series capacitors mounted
on the thin-film substrate at each RF
port. Only under bias conditions where
V
is dc grounded (as is typical for
CC
contact pad (more positive than V
-
CC
negative bias supply operation) may
the RF ports be direct coupled to adja-
cent circuitry or in some cases, such
as level shifting to subsequent stages.
In the latter case the device backside
may be “floated” and bias applied as
Agilent application note #54, “GaAs
MMIC ESD, Die Attach and Bonding
Guidelines” provides basic
1.35 V), the input preamplifier stage is
locked into either logic “high” or logic
“low” preventing frequency division
and any self-oscillation frequency
which may be present.
information on these subjects.
the difference between V and V .
EE
CC
4. Input dc Offset
Another method used to prevent false
triggers or self-oscillation
conditions is to apply a 20 to
100 mV dc offset voltage between
the RF and RF ports. This prevents
in
in
noise or spurious low level signals
from triggering the divider.
Adding a 10 KΩ resistor between the
unused RF input to a contact point at
the V potential will result in an off-
EE
set of ≈25 mV between the RF inputs.
5
Optional dc Operating Values/Logic Levels
(T = 25°C)
A
Function
Symbol
Conditions
Min
(volts/mA)
Typical
(volts/mA)
Max
(volts/mA)
1
Logic Threshold
Input Disable
Input Disable
Input Disable
Input Disable
V
V
-1.45
V
-1.32
V -1.25
CC
Logic
CC
CC
V
V
[Disable]
[Enable]
V
+0.25
V
V
V
Disable(High)
Disable(Low)
Disable
Logic
Logic
CC
V
V
-0.25
Logic
EE
Logic
I
I
V > V +3 (V
-V -3)/500
(V
-V -3)/500
(V
-V -3)/500
D
EE
Disable EE
Disable EE
Disable EE
V < V +3
0
0
0
Disable
D
EE
Note:
1. Acceptable voltage range when applied from external source.
Notes:
• All dimensions in micrometers.
• All Pad Dim: 70 x 70 ꢁm
(except where noted).
• Tolerances: 10 ꢁm
• Chip Thickness: 127 15 ꢁm
Figure 2. Pad locations and chip dimensions
ꢀ
Figure 3. Assembly diagrams
7
Figure 4. Typical input sensitivity window
Figure 5. Typical supply current & V
vs. supply voltage
Logic
Figure 7. Typical output power vs. output frequency, ƒ (GHz)
Figure 6. Typical phase noise performance
out
Figure 8. Typical “Spitback” power P(ƒ ) appearing
out
at RF input port
8
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