HMMC-3122-BLK [AGILENT]

Prescaler, 3122 Series, 1-Func, GAAS, PDSO8, 4.90 X 3.90 MM, 1.55 MM HEIGHT, 1.25 MM PITCH, PLASTIC, MS-012, SOIC-8;
HMMC-3122-BLK
型号: HMMC-3122-BLK
厂家: AGILENT TECHNOLOGIES, LTD.    AGILENT TECHNOLOGIES, LTD.
描述:

Prescaler, 3122 Series, 1-Func, GAAS, PDSO8, 4.90 X 3.90 MM, 1.55 MM HEIGHT, 1.25 MM PITCH, PLASTIC, MS-012, SOIC-8

时钟 光电二极管 逻辑集成电路
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Agilent HMMC-3122  
DC-12 GHz Packaged High Efficiency  
Divide-by-2 Prescaler  
HMMC-3122-TR1 - 7” diameter reel/500 each  
HMMC-3122-BLK - Bubble strip/10 each  
Data Sheet  
Description  
Features  
The HMMC-3122 is a packaged  
GaAs HBT MMIC prescaler  
which offers DC to 12 GHz  
frequency translation for use in  
communications and EW  
systemsincorporatinghigh–  
frequencyPLL oscillator circuits  
and signal–path down  
conversion applications. The  
prescalerprovides a large input  
power sensitivity window and  
low phase noise.  
Wide Frequency Range:  
0.2–12 GHz  
High Input Power Sensitivity:  
On–chip pre– and post–amps  
-15 to +10 dBm (1–8 GHz)  
-10 to +8 dBm (8–10 GHz)  
-5 to +2 dBm (10–12 GHz)  
Package Type: SOIC-8 Plastic  
Package Dimensions: 4.9 x 3.9 mm typ  
Package Thickness: 1.55 mm typ  
Lead Pitch: 1.25 mm nom  
P
: 0 dBm (0.5 V  
)
p-p  
out  
Low Phase Noise:  
Lead Width: 0.42 mm nom  
-153 dBc/Hz @ 100 kHz Offset  
(+) or (-) Single Supply Bias  
Operation  
Wide Bias Supply Range:  
4.5 to 6.5 volt operating range  
Differential I/0 with on–chip  
50W matching  
1
Absolute Maximum Ratings  
(@ T = +25 °C, unless otherwise stated)  
A
Symbol  
VCC  
Parameters/Conditions  
Bias Supply Voltage  
Bias Supply Voltage  
Bias Supply Delta  
Min  
-7  
Max  
Units  
volts  
volts  
volts  
volts  
dBm  
volts  
°C  
+7  
VEE  
|VCC - VEE|  
VLogic  
+7  
Logic Threshold Voltage  
CW RF Input Power  
VCC - 1.5  
VCC -1.2  
+10  
Pin(CW)  
VRFin  
DC Input Voltage (@ RFin or RFin Ports)  
Backside Operating Temperature  
VCC 0.5  
+85  
2
TBS  
-40  
-65  
Tst  
Storage Temperature  
+165  
310  
°C  
Tmax  
Maximum Assembly Temperature (60 seconds max)  
°C  
Notes:  
1. Operation in excess of any parameter limit (except T ) may cause permanent damage to the device.  
BS  
6
2. MTTF >1 x 10 hours @ T <85°C. Operation in excess of maximum operating temperature (T ) will degrade MTTF.  
BS  
BS  
DC Specifications/Physical Properties  
(T = +25 °C, V - V = 5.0 volts, unless otherwise listed)  
A
CC  
EE  
Symbol  
Parameters/Conditions  
Min  
Typ  
Max  
Units  
VCC - VEE  
Operating bias supply difference1  
Bias supply current  
4.5  
34  
5.0  
40  
6.5  
46  
volts  
mA  
|ICC| or |IEE|  
VRFin(q)  
Quiescent dc voltage appearing at all RF ports  
VCC  
volts  
VRFout(q)  
VLogic  
Nominal ECL Logic Level  
VCC -1.45  
VCC -1.32  
VCC -1.25  
volts  
(VLogic contact self-bias voltage, generated on-chip)  
Notes:  
1. Prescaler will operate over full specified supply voltage range. V or V not to exceed limits specified in Absolute Maximum Ratings section.  
CC  
EE  
2
RF Specifications  
(T = +25 °C, Z = 50 W, V - V = 5.0 volts)  
A
0
CC  
EE  
Symbol  
Parameters/Conditions  
Min  
Typ  
Max  
Units  
ƒin(max)  
ƒin(min)  
ƒSel-Osc.  
Pin  
Maximum input frequency of operation  
Minimum input frequency of operation1 (Pin = -10 dBm)  
Output Self-Oscillation Frequency2  
@ DC, (Square-wave input)  
12  
14  
GHz  
GHz  
GHz  
dBm  
dBm  
dBm  
dBm  
dBm  
dB  
0.2  
0.5  
3.4  
-15  
-15  
-15  
-10  
-5  
>-25  
>-20  
>-20  
>-15  
>-10  
15  
+10  
+10  
+10  
+5  
@ ƒin = 500 MHz, (Sine-wave input)  
ƒin = 1 to 8 GHz  
ƒin = 8 to 10 GHz  
ƒin = 10 to 12 GHz  
-1  
RL  
S12  
Small-Signal Input/Output Return Loss (@ ƒin <10 GHz)  
Small-Signal Reverse Isolation (@ ƒin <10 GHz)  
30  
dB  
SSB Phase noise (@ Pin = 0 dBm, 100 KHz offset from a ƒout =  
1.2 GHz Carrier)  
-153  
dBc/Hz  
N
Jitter  
Input signal time variation @ zero-crossing (ƒin = 10 GHz, Pin =  
-10 dBm)  
1
ps  
Tr or Tf  
Output transition time (10% to 90% rise/fall time)  
@ ƒout < 1 GHz  
70  
ps  
3
Pout  
-2.0  
-3.5  
-4.5  
0.0  
dBm  
dBm  
dBm  
volts  
volts  
volts  
dBm  
@ ƒout = 2.5 GHz  
-1.5  
-2.5  
0.5  
@ ƒout = 3.0 GHz  
4
|Vout(p-p)  
|
@ ƒout < 1 GHz  
@ ƒout = 2.5 GHz  
0.42  
0.37  
-50  
@ ƒout = 3.0 GHz  
PSpitback  
ƒout power level appearing at RFin or RFout (@ ƒin 10 GHz,  
Unused RFout or RFout unterminated)  
ƒout power level appearing at RFin or RFout (@ ƒin 10 GHz, Both  
RFout or RFout unterminated)  
-55  
-30  
-25  
dBm  
dBc  
dBc  
Pfeedthru  
Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz,  
Pin = 0 dBm, Referred to Pin in))  
H2  
Second harmonic distortion output level (@ ƒout = 3.0 GHz,  
Referred to Pout out))  
Notes:  
1. For sine–wave input signal. Prescaler will operate down to dc for square–wave input signal. Min. divide frequency limited by input slew rate.  
2. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition can be eliminated by use of the Input dc offset  
technique described on page 4.  
3. Fundamental of output square wave’s Fourier Series.  
4. Square wave amplitude calculated from P  
.
out  
3
Applications  
TheHMMC-3122isdesignedfor  
use in high frequency  
communications, microwave  
instrumentation, and EW radar  
systems where low phase–noise  
PLL control circuitry or broad–  
band frequency translation is  
required.  
For positive supply operation,  
V pins are nominally biased at If an RF signal with sufficient  
CC  
Input dc Offset  
any voltage in the +4.5 to +6.5  
volt range with pin 8 (V  
grounded. For negative bias  
signal to noise ratio is present at  
the RF input lead, the prescaler  
will operate and provide a  
)
EE  
operationV pins are typically  
grounded and a negative voltage  
between-4.5 to- 6.5voltsis  
divided output equal the input  
frequencydivided by the divide  
modulus. Under certain “ideal”  
conditions where the input is  
well matched at the right input  
frequency, the component may  
“self–oscillate”, especially under  
small signal input powers or  
with only noise present at the  
input. Thisself–oscillationwill  
produce an undesired output  
signalalso known as a false  
trigger.Topreventfalsetriggers  
or self– oscillationconditions,  
apply a 20 to 100 mV dc offset  
voltagebetween the RFin and  
RFin ports. This prevents noise  
or spurious low level signals  
fromtriggeringthedivider.  
CC  
appliedto pin 8 (V ).  
EE  
Operation  
ac–Coupling and dc–Blocking  
All RF ports are dc connected  
The device is designed to  
operatewhen driven with either  
a single–endedordifferential  
sinusoidalinput signal over a  
200 MHz to 12 GHz bandwidth.  
Below200 MHz the prescaler  
input is “slew–rate” limited,  
requiringfastrisingandfalling  
edge speeds to properly divide.  
The device will operate at  
frequenciesdown to dc when  
driven with a square–wave.  
on–chip to the V contact  
CC  
through on–chip 50W resistors.  
Under any bias conditions where  
V
is not dc grounded the RF  
CC  
ports should be ac coupled via  
series capacitors mounted on  
the PC– board at each RF port.  
Only under biasconditions  
where V is dc grounded (as is  
CC  
typical for negativebias supply  
operation) maythe RF ports be  
direct coupled to adjacent  
circuitry or in some cases,such  
as level shifting to subsequent  
stages. In the latter case the  
package heat sink may be  
Due to the presence of an off–  
chip RF–bypass capacitor inside  
the package (connected to the  
Adding a 10KW resistorbetween  
the unused RF input to a contact  
point at the VEE potentialwill  
V
CC  
contact on the device), and  
the unique design of the device  
itself, the component may be  
biasedfrom either a single  
“floated” and bias applied as the result in an offset of» 25mV  
differencebetweenV and V  
.
betweenthe RF inputs. Note,  
however, that the input  
sensitivitywill be reduced  
slightly due tothe presence of  
thisoffset.  
CC  
EE  
positiveor single negative  
supply bias. The backside of the  
package is not dc connected to  
any dc bias point on the device.  
VCC  
VCC  
VCC  
6
4
2
150p  
V
cc  
V
cc  
V
cc  
By  
poss  
50  
50  
50  
50  
OUT  
IN  
IN  
IN  
IN  
OUT  
OUT  
5
7
3
÷
OUT  
Pin 1  
Vpwr  
sel  
V
ee  
SOIC8 w/Backside GND  
8
VEE  
Figure 1. Simplified Schematic  
4
Assembly Notes  
Agilent application note #54,  
“GaAs MMIC ESD, Die Attach  
and Bonding Guidelines”  
providesbasic information on  
these subjects.  
Independent of the bias applied  
to the package, the backside of  
the package should always be  
connected to both a good RF  
ground plane and a good  
thermalheat sinking region on  
the PC–board to optimize  
performance. For single–ended  
output operation the unused RF  
output lead should be  
A minimum RF and thermal PC  
board contact area equal to or  
greater than 2.67 x 1.65 mm  
(0.105" x 0.065") with eight  
0.020" diameter plated–wall  
thermal vias is recommended.  
Moisture Sensitivity  
Classification: Class 1, per  
JESD22-A112-A.  
MMIC ESD precautions,  
handling considerations, die  
attachand bonding methods are  
critical factorsinsuccessful  
GaAs MMIC performance and  
reliability.  
Additional References:  
PN #18, “HBT Prescaler  
Evaluation Board.”  
terminated into50W to a contact  
point at the V potentialorto  
CC  
RF groundthrough a dc blocking  
capacitor.  
Notes:  
-
-
All dimensions in millimeters.  
Refer to JEDEC Outline MS-012 for  
additional tolerances.  
Symbol  
Min  
1.35  
0.0  
Max  
1.75  
.25  
A
A1  
B
C
0.33  
0.19  
4.80  
3.80  
0.51  
.025  
5.00  
4.00  
D
E
e
1.27 BSC  
H
L
5.80  
0.40  
0°  
6.20  
1.27  
8°  
a
Figure 2. Package & Dimensions  
-
-
Exposed heat slug area on pkg bottom =  
2.67 x 1.65  
Exposed heat sink on package bottom must  
be soldered to PCB RF ground plane.  
+6.5 volts  
)
V
(+4.5 to  
CC  
~ 1 mf Mo  
noblock  
Capacitor  
To operate component from a negative supply, ground each  
connection and supply V witha negative voltage (-4.5  
V
CC  
EE  
to -6.5v)bypassed to ground with~1 mf capacitor.  
V
CC  
RFin  
V
CC  
RFout  
V
CC  
RFin  
V
EE  
RFout  
RF shouldbeterminatedin50 to ground. (dc blocking  
out  
capacitor required for positive bias configuration.)  
Exposed heat sink on package bottom  
must be soldered toPCB RF ground.  
Figure 3. Assembly Diagram (Single-supply, Positive-bias Configuration shown)  
5
Supplemental Data  
Figure 4. Typical Input Sensitivity Window  
Figure 5. Typical Supply Current & V  
vs. Supply Voltage  
Logic  
Figure 6. Typical Phase Noise Performance  
Figure 7. Typical Output Power vs. Output Frequency ƒ (GHz)  
out  
Figure 8. Typical “Spitback” Power (Pƒ  
appearing at RF input port  
)
out  
6
Device Orientation  
Reel  
Tape  
User  
Feed  
Direction  
Cover Tape  
Tape Dimensions and Product Orientation  
2.0 0.05  
See Note 6  
1.5+0.1/-0.0  
4.0  
See Note 1  
A
0.30 0.05  
1.75  
R0.3 MAX.  
5.5 0.05  
See Note 6  
12.0 0.3  
Bo  
Ao  
R0.5 Typical  
Ko  
1.5 MIN  
SECTION A-A  
A
Ao =6.4mm  
8.0  
Bo =5.2 mm  
Ko =2.1 mm  
Notes:  
1. 10 sprocket hole pitch cumulative tolerance: 0.2mm.  
2. Camber not to exceed 1mm in 100mm.  
3. Material: Black Conductive Advantek Polystyrene.  
4. Ao and Bo measured on a plane 0.3mm above the bottom of the pocket.  
5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier.  
6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.  
7
www.agilent.com/  
semiconductors  
Forproductinformationandacompletelistof  
distributors, please go to our web site.  
For technical assistance call:  
Americas/Canada: +1 (800) 235-0312 or  
(916)788-6763  
Europe: +49 (0) 6441 92460  
China: 10800 650 0017  
Hong Kong: (+65) 6756 2394  
India, Australia, New Zealand: (+65) 6755 1939  
Japan: (+81 3) 3335-8152(Domestic/International), or  
0120-61-1280(DomesticOnly)  
Korea: (+65) 6755 1989  
Singapore, Malaysia, Vietnam, Thailand, Philippines,  
Indonesia: (+65) 6755 2044  
Taiwan: (+65) 6755 1843  
Data subject to change.  
Copyright © 2003 Agilent Technologies, Inc.  
Obsoletes:5988-6160EN  
October7,2003  
5989-0200EN  

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