AK4480EF [AKM]
High Performance 114dB 32-Bit DAC; 高性能114分贝32位DAC
| 型号： | AK4480EF |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | High Performance 114dB 32-Bit DAC |
| 文件： | 总44页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK4480]
AK4480
High Performance 114dB 32-Bit DAC
GENERAL DESCRIPTION
The AK4480 is a 32-bit DAC, which corresponds to Blu-ray Disc systems. An internal circuit includes
newly developed 32bit Digital Filter for better sound quality achieving low distortion characteristics and
wide dynamic range. The AK4480 has full differential SCF outputs, removing the need for AC coupling
capacitors and increasing performance for systems with excessive clock jitter. The AK4480 accepts
216kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including Blu-ray Discs and
SACDs.
FEATURES
• 128x Over Sampling
• Sampling Rate: 30kHz ∼ 216kHz
• 32Bit 8x Digital Filter
- Ripple: ±0.005dB, Attenuation: 70dB
- Minimum delay option GD=7/fs
- Sharp Roll-off Filter
- Slow Roll-off Filter
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• DSD Data Input
• Digital De-emphasis for 32, 44.1, 48kHz Sampling
• Soft Mute
• Digital Attenuator (Linear 256 steps)
• Mono Mode
• External Digital Filter Mode
• THD+N: -100dB
• DR, S/N: 114dB (117dB when Mono mode)
• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD
• Master Clock:
30kHz ~ 32kHz: 1152fs
30kHz ~ 54kHz: 512fs or 768fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
• Power Supply: 4.75 ∼ 5.25V
• Digital Input Level: TTL
• Package: 30pin VSOP
MS1146-E-03
2012/01
- 1 -
[AK4480]
■ Block Diagram
DVDD
VSS3
PDN
AVDD
VSS4
VSS2
VDDL
BICK/DCLK
PCM
Data
Interface
AOUTLP
AOUTLN
8X
SCF
LRCK/DSDR/WCK
Interpolator
SDATA/DSDL
VREFHL
VREFLL
DSD
Data
Interface
Bias
Vref
DATT
Soft Mute
ΔΣ
Modulator
VREFLR
VREFLL
External
DF
Interface
AOUTRP
AOUTRN
BCK
DINL
DINR
SCF
CSN/SMUTE
CCLK/DEM0
CDTI/DEM1
VDDR
VSS1
Control
Register
Clock
Divider
DZFR
MCLK
CAD0/SD CAD1/DIF0
PSN
DZFL/DIF1 DIF2
Block Diagram
MS1146-E-03
2012/01
- 2 -
[AK4480]
■ Ordering Guide
AK4480EF
AKD4480
−10 ∼ +70°C
Evaluation Board for AK4480
30pin VSOP (0.65mm pitch)
■ Pin Layout
SMUTE/CSN
SD/CAD0
1
2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LRCK/DSDR/WCK
SDATA/DSDL/DINL
BICK/DLCK/BCK
PDN
DEM0/CCLK
DEM1/CDTI
3
4
DIF0/CAD1
DIF1/DZFL
5
DVDD
VSS4
6
AK4480
Top
View
DIF2/DINR
PSN
7
MCLK
8
AVDD
9
VSS3
ACKS/DZFR
AOUTRP
10
11
12
13
14
15
AOUTLP
AOUTLN
VSS2
AOUTRN
VSS1
VDDR
VDDL
VREFHR
VREFLR
VREFHL
VREFLL
MS1146-E-03
2012/01
- 3 -
[AK4480]
PIN/FUNCTION
No. Pin Name
I/O
Function
Soft Mute in Parallel Control Mode
SMUTE
1
I
When this pin goes to “H”, soft mute cycle is initiated.
When returning to “L”, the output mute releases.
Chip Select in Serial Control Mode
CSN
I
I
SD
2
Digital Filter Select Pin
CAD0
I
Chip Address 0 in Serial Control Mode
De-emphasis Enable 0 in Parallel Control Mode
Control Data Clock in Serial Control Mode
De-emphasis Enable 1 in Parallel Control Mode
Control Data Input in Serial Control Mode
Digital Input Format 0 in PCM Mode
DEM0
I
3
CCLK
I
DEM1
I
4
CDTI
I
DIF0
5
I
CAD1
I
Chip Address 1 in Serial Control Mode
Digital Input Format 1 in PCM Mode
DIF1
6
I
DZFL
O
I
Left Channel Zero Input Detect in Serial Control Mode
Digital Input Format 2 in PCM Mode
DIF2
7
DINR
I
Rch Audio Serial Data Input in External DF Mode.
Parallel/Serial Select
(Internal pull-up pin)
8
9
PSN
I
“L”: Serial Control Mode, “H”: Parallel Control Mode
Clock Auto Setting Mode Pin
ACKS
DZFR
I
O
O
O
-
Rch Zero Input Detect in Serial Control Mode
Right Channel Positive Analog Output
Right Channel Negative Analog Output
Connected to VSS2/3/4 Ground
10 AOUTRP
11 AOUTRN
12 VSS1
13 VDDR
14 VREFHR
15 VREFLR
16 VREFLL
17 VREFHL
18 VDDL
19 VSS2
-
Right Channel Analog Power Supply, 4.75~5.25V
Right Channel High Level Voltage Reference Input
Right Channel Low Level Voltage Reference Input
Left Channel Low Level Voltage Reference Input
Left Channel High Level Voltage Reference Input
Left Channel Analog Power Supply, 4.75~5.25V
Ground (connected to VSS1/3/4 ground)
Left Channel Negative Analog Output
Left Channel Positive Analog Output
I
I
I
I
-
-
20 AOUTLN
21 AOUTLP
22 VSS3
O
O
-
Ground (connected to VSS1/2/4 ground)
Analog Power Supply, 4.75 to 5.25V
23 AVDD
24 MCLK
25 VSS4
-
I
Master Clock Input
-
Connected to VSS1/2/3 Ground
26 DVDD
-
Digital Power Supply, 4.75 ∼ 5.25V
Power-Down Mode
27 PDN
I
When at “L”, the AK4480 is in power-down mode and is held in reset.
The AK4480 should always be reset upon power-up.
Note: All input pins except internal pull-up/down pins must not be left floating.
MS1146-E-03
2012/01
- 4 -
[AK4480]
PIN/FUNCTION (Continued)
Function
No. Pin Name
I/O
BICK
I
I
I
I
I
I
I
I
I
Audio Serial Data Clock in PCM Mode
Audio Serial Data Clock in DSD Mode
Audio Serial Data Clock in EXDF Mode
Audio Serial Data Input in PCM Mode
Lch Audio Serial Data Clock in DSD Mode
Lch Audio Serial Data Clock in EXDF Mode
L/R Clock in PCM Mode
28
29
30
DCLK
BCK
SDATA
DSDL
DINL
LRCK
DSDR
WCK
Rch Audio Serial Data Input Pin in DSD Mode
Word Clock Pin in EXDF Mode
Note: All input pins except internal pull-up/down pins must not be left floating.
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
(1) Parallel Mode (PCM Mode only)
Classification Pin Name
AOUTLP, AOUTLN
Setting
These pins must be open.
Analog
AOUTRP, AOUTRN These pins must be open.
(2) Serial Mode
1. PCM Mode
Classification Pin Name
Setting
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
These pins must be open.
AOUTLP, AOUTLN
Analog
Digital
AOUTRP, AOUTRN
DIF2, PSN
DZFL, DZFR
2. DSD Mode
Classification Pin Name
Setting
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
These pins must be open.
AOUTLP, AOUTLN
Analog
Digital
AOUTRP, AOUTRN
DIF2, PSN
DZFL, DZFR
3. Ex DF Mode
Classification Pin Name
Setting
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
These pins must be open.
AOUTLP, AOUTLN
Analog
Digital
AOUTRP, AOUTRN
DIF2, PSN
DZFL, DZFR
MS1146-E-03
2012/01
- 5 -
[AK4480]
ABSOLUTE MAXIMUM RATINGS
(VSS1-4 =0V; Note 1)
Parameter
Symbol
min
−0.3
−0.3
−0.3
-
max
6.0
Unit
Power Supplies:
Analog
Analog
Digital
AVDD
VDDL/R
DVDD
V
V
V
6.0
6.0
Input Current, Any Pin Except Supplies
Digital Input Voltage
IIN
VIND
Ta
±10
DVDD+0.3
70
mA
V
−0.3
−10
−65
Ambient Temperature (Power applied)
Storage Temperature
°C
°C
Tstg
150
Note 1. All voltages with respect to ground.
Note 2. VSS1-4 must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1-4 =0V; Note 1)
Parameter
Symbol
AVDD
VDDL/R
DVDD
min
4.75
4.75
4.75
typ
5.0
5.0
5.0
max
5.25
5.25
5.25
Unit
V
V
Analog
Analog
Digital
Power Supplies
(Note 3)
V
Voltage
Reference
(Note 4)
VREFHL/R
VREFLL/R
VREFHL/R
VREFLL/R
AVDD−0.5
-
AVDD
-
V
V
-
VSS
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD, VDDL/R and DVDD is not critical.
Note 4. The VREFLL/R pin must be the same voltage as VSS.
The analog output voltage scales with the voltage of (VREFH − VREFL).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS1146-E-03
2012/01
- 6 -
[AK4480]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;
Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
-
-
32
Bits
Dynamic Characteristics
THD+N
(Note 5)
0dBFS
−60dBFS
0dBFS
−60dBFS
0dBFS
−60dBFS
−60dBFS
fs=44.1kHz
BW=20kHz
fs=96kHz
-
-
-
-
-100
-51
97
-48
97
-48
-45
114
114
110
-93
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
-
-
-
-
-
-
BW=40kHz
fs=192kHz
BW=40kHz
BW=80kHz
Dynamic Range (−60dBFS with A-weighted)
S/N (A-weighted)
Interchannel Isolation (1kHz)
DC Accuracy
(Note 6)
(Note 7)
108
108
100
Interchannel Gain Mismatch
Gain Drift
Output Voltage
-
-
0
20
±2.4
-
0.3
dB
ppm/°C
Vpp
pF
(Note 8)
(Note 9)
-
±2.55
25
±2.25
-
Load Capacitance
Load Resistance
(Note 10)
2
-
-
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R
-
-
-
30
15
24
45
-
36
mA
mA
mA
DVDD (fs ≤ 96kHz)
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
AVDD+VDDL/R+DVDD
(Note 11)
-
10
100
μA
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. Figure 20 External LPF Circuit Example 2. 100dB for 16-bit data.
Note 7. Figure 20 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 8. The voltage on (VREFH − VREFL) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.
Note 10. Regarding Load Resistance, AC load is 2kΩ (min) with a DC cut capacitor. Please refer to Figure 20. The load
resistance is 4k ohm (min) to ground when without a DC cut capacitor. Please refer to Figure 19. Load Resistance
is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected output pin.
Therefore the capacitive load must be minimized.
Note 11. In the power down mode. P/S pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held VSS4.
MS1146-E-03
2012/01
- 7 -
[AK4480]
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit =“0”,
SD bit=“0”)
Parameter
Digital Filter
Passband
Symbol
min
typ
max
Unit
(Note 12)
PB
PB
0
0
-
-
20.0
20.0
-
kHz
kHz
kHz
kHz
dB
±0.05dB
−6.0dB
(Note 12)
Frequency Response
22.05
Stopband
SB
PR
SA
GD
24.1
-0.005
70
Passband Ripple
Stopband Attenuation
Group Delay
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
+0.0001
-
dB
1/fs
(Note 13)
-
27
-
-0.2
+0.2
dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit =“0”,
SD bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband (Note 12)
Frequency Response
PB
0
0
-
-
-
43.5
43.5
-
kHz
kHz
kHz
kHz
dB
±0.05dB
−6.0dB
(Note 12)
48.0
-
-
-
27
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
SB
PR
SA
GD
52.5
-0.005
70
+0.0001
-
-
dB
1/fs
(Note 13)
-
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-0.3
-
+0.3
dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit =“0”, SD
bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 12)
PB
0
0
-
-
87.0
87.0
-
kHz
kHz
kHz
kHz
dB
±0.05dB
−6.0dB
(Note 12)
96.0
Stopband
SB
PR
SA
GD
105
-0.005
70
Passband Ripple
Stopband Attenuation
Group Delay
-
-
27
+0.0001
-
-
dB
1/fs
(Note 13)
-
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-1
-
+0.1
dB
Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@±0.01dB), SB=0.546×fs.
Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24/32bit data
of both channels to input register to the output of analog signal.
MS1146-E-03
2012/01
- 8 -
[AK4480]
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”,
SD bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 14)
PB
0
0
-
-
-
8.1
8.1
-
-
+0.02
-
-
kHz
kHz
kHz
kHz
dB
±0.07dB
−3.0dB
(Note 14)
18.2
-
-
-
27
Stopband
SB
PR
SA
GD
39.2
-0.07
73
-
Passband Ripple
Stopband Attenuation
Group Delay
dB
1/fs
(Note 13)
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-5
-
+0.1
dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode DEM=OFF; SLOW bit=“1”, SD
bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 14)
PB
0
0
-
-
-
17.7
17.7
-
-
+0.02
-
-
kHz
kHz
kHz
kHz
dB
±0.07dB
−3.0dB
(Note 14)
39.6
-
-
-
27
Stopband
SB
PR
SA
GD
85.3
-0.07
73
-
Passband Ripple
Stopband Attenuation
Group Delay
dB
1/fs
(Note 13)
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-4
-
+0.1
dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”, SD
bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 14)
PB
0
0
-
-
-
35.5
35.5
-
-
+0.02
-
-
kHz
kHz
kHz
kHz
dB
±0.07dB
−3.0dB
(Note 14)
79.1
-
-
-
27
Stopband
SB
PR
SA
GD
171
-0.07
73
-
Passband Ripple
Stopband Attenuation
Group Delay
dB
1/fs
(Note 13)
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-5
-
+0.1
dB
Note 14. The passband and stopband frequencies scale with fs. For example, PB=0.185×fs (@±0.04dB), SB=0.888×fs.
MS1146-E-03
2012/01
- 9 -
[AK4480]
MINIMUM DELAY FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 14) ±0.01dB
±0.06dB
PB
0
0
-
-
20.0
20.0
-
-
kHz
kHz
kHz
kHz
dB
−6.0dB
(Note 14)
-
24.1
-0.0052
70
22.05
-
-
-
7
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
+0.0006
-
-
dB
1/fs
(Note 13)
-
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-0.2
-
+0.2
dB
MINIMUM DELAY FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 14) ±0.01dB
±0.06dB
PB
0
0
-
-
43.5
43.5
-
-
kHz
kHz
kHz
kHz
dB
−6.0dB
(Note 14)
-
52.5
-0.0052
70
48.0
-
-
-
7
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
+0.0006
-
-
dB
1/fs
(Note 13)
-
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-0.3
-
+0.3
dB
MINIMUM DELAY FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”, SD
bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
Frequency Response
(Note 14) ±0.01dB
±0.06dB
PB
0
0
-
-
87.0
87.0
-
-
kHz
kHz
kHz
kHz
dB
−6.0dB
(Note 14)
-
105
-0.0052
70
96.0
-
-
-
7
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
+0.0006
-
-
dB
1/fs
(Note 13)
-
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-1
-
+0.1
dB
MS1146-E-03
2012/01
- 10 -
[AK4480]
DC CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
max
-
0.8
-
0.5
±10
Unit
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
VIH
VIL
2.2
-
-
-
-
-
-
(Iout=−100μA)
(Iout=100μA)
(Note 15)
VOH
VOL
Iin
DVDD−0.5
V
V
μA
-
-
Note 15. The TEST1/CAD0 pin is an internal pull-down pin, and the P/S pin is an internal pull-up pin, nominally 100kΩ.
Therefore TEST1/CAD0 pin and P/S pin are not included.
MS1146-E-03
2012/01
- 11 -
[AK4480]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
Frequency
fCLK
dCLK
7.7
40
41.472
60
MHz
%
Duty Cycle
LRCK Frequency
(Note 16)
1152fs, 512fs or 768fs
fsn
fsd
fsq
30
54
108
45
54
108
216
55
kHz
kHz
kHz
%
256fs or 384fs
128fs or 192fs
Duty Cycle
Duty
PCM Audio Interface Timing
BICK Period
1152fs, 512fs or 768fs
256fs or 384fs
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
1/128fsn
1/64fsd
1/64fsq
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
128fs or 192fs
BICK Pulse Width Low
BICK Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA Hold Time
SDATA Setup Time
30
(Note 17)
(Note 17)
20
tLRB
20
tSDH
tSDS
20
20
External Digital Filter Mode
BICK Period
tB
tBL
27
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCK Pulse Width Low
BCK Pulse Width High
BCK “↑” to WCK Edge
WCK Edge to BCK “↑”
WCK Pulse Width Low
WCK Pulse Width High
DATA Hold Time
tBH
tBW
tWB
tWCK
tWCH
tDH
5
54
54
5
tDS
5
DATA Setup Time
DSD Audio Interface Timing
DCLK Period
tDCK
tDCKL
tDCKH
tDDD
-
1/64fs
ns
ns
ns
ns
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
160
160
−20
(Note 18)
20
Control Interface Timing
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
200
80
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
80
CDTI Setup Time
50
CDTI Hold Time
tCDH
tCSW
tCSS
50
CSN High Time
150
50
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 19)
tPD
150
ns
MS1146-E-03
2012/01
- 12 -
[AK4480]
Note 16. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4480 should be reset by the
PDN pin or RSTN bit.
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. DSD data transmitting device must meet this time.
Note 19. The AK4480 can be reset by bringing the PDN pin “L” to “H” upon power-up.
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tBCKH
tBH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
BICK
VIL
tBCK
VIH
VIL
tBCKL
1/fs
tB
VIH
VIL
WCK
BCK
VIH
VIL
tBL
Clock Timing
MS1146-E-03
2012/01
- 13 -
[AK4480]
VIH
VIL
LRCK
BICK
tBLR
tLRB
tSDS
VIH
VIL
tSDH
VIH
VIL
SDATA
Audio Interface Timing (PCM Mode)
tDCK
tDCKL
tDCKH
VIH
VIL
DCLK
tDDD
VIH
VIL
DSDL
DSDR
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
VIL
DCLK
tDDD
tDDD
VIH
VIL
DSDL
DSDR
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
MS1146-E-03
2012/01
- 14 -
[AK4480]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
VIL
CCLK
CDTI
tCDS tCDH
C0
VIH
VIL
C1
R/W
A4
WRITE Command Input Timing
tCSW
VIH
VIL
CSN
tCSH
VIH
VIL
CCLK
CDTI
VIH
VIL
D3
D2
D1
D0
WRITE Data Input Timing
MS1146-E-03
2012/01
- 15 -
[AK4480]
tPD
PDN
VIL
Power Down & Reset Timing
VIH
VIL
WCK
BCK
tBW
tWB
VIH
VIL
tDS
tDH
VIH
VIL
DATA
External Digital Filter I/F mode
MS1146-E-03
2012/01
- 16 -
[AK4480]
OPERATION OVERVIEW
■ D/A Conversion Mode
In serial mode, the AK4480 can covert both PCM and DSD data. The D/P bit controls PCM/DSD mode. When DSD
mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK,
LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4480 should be reset by RSTN bit. It takes
about 2/fs ~ 3/fs to change the mode. In parallel mode, the AK4480 can only convert PCM data.
D/P bit
Interface
PCM
DSD
0
1
Table 1. PCM/DSD Mode Control
When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter
(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXD bit controls the modes. When
switching internal and external digital filters, the AK4480 must be reset by RSTN bit. A Digital filter switching takes
2~3k/fs.
Ex DF bit
Interface
PCM
EX DF I/F
0
1
Table 2. Digital Filter Control (DP bit = “0”)
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4480, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. There are two modes for setting MCLK frequency, Manual Setting Mode and Auto Setting Mode.
In auto setting mode, sampling speed and MCLK frequency are detected automatically and then the initial master clock is
set to the appropriate frequency (Table 3). When external clocks are changed, the AK4480 should be reset by the PDN pin
or RSTN bit.
The AK4480 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation
mode, and the analog output goes to AVDD/2 (typ). When MCLK and LRCK are input again, the AK4480 is powered up.
After exiting reset following power-up, the AK4480 is not fully operational until MCLK and LRCK are input.
The MCLK frequency corresponding to each sampling speed should be provided (Table 3).
(1) Parallel Mode (P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. Quad
speed mode is not supported in this mode.
MS1146-E-03
2012/01
- 17 -
[AK4480]
LRCK
fs
MCLK (MHz)
384fs
BICK
64fs
128fs
N/A
N/A
N/A
11.2896
12.2880
192fs
N/A
N/A
N/A
16.9344
18.4320
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
512fs
16.3840
22.5792
24.5760
N/A
768fs
24.5760
33.8688
36.8640
N/A
1152fs
36.8640
N/A
N/A
N/A
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
12.2880
16.9344
18.4320
33.8688
36.8640
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
N/A
N/A
N/A
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)(N/A: Not available)
32kHz ~ 96kHz sampling rates are supported (Table 4). However, when the sampling rate is 32kHz ~ 48kHz, DR and S/N
will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS pin
MCLK
256fs/384fs/512fs/768fs
256fs/384fs
DR,S/N
114dB
111dB
114dB
L
H
H
512fs/768fs
Table 4. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)
2. Auto Setting Mode (ACKS pin = “H”)
MCLK frequency and the sampling speed are detected automatically (Table 5). MCLK with appropriate frequency should
be input externally for each speed (Table 6).
MCLK
1152fs
Sampling Speed
Normal (fs≤32kHz)
Normal
512fs/256fs
768fs/384fs
384fs
256fs
128fs
Double
Quad
192fs
Table 5. Sampling Speed (Auto Setting Mode @Parallel Mode)
LRCK
fs
MCLK (MHz)
Sampling
Speed
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
192fs
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
512fs
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
Normal
Double
Quad
N/A
N/A
Table 6. System Clock Example (Auto Setting Mode @Parallel Mode) (N/A: Not available)
MCLK= 256fs/384fs supports sampling rate of 32kHz ~ 96kHz (Table 7). However, when the sampling rate is 32kHz ~
48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS pin
MCLK
256fs/384fs/512fs/768fs
256fs/384fs
DR,S/N
114dB
111dB
114dB
L
H
H
512fs/768fs
Table 7. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)
MS1146-E-03
2012/01
- 18 -
[AK4480]
(2) Serial Mode (P/S pin = “L”)
1. Manual Setting Mode (ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 8). The MCLK frequency
corresponding to each sampling speed should be provided (Table 9). The AK4480 is set to Manual Setting Mode at
power-up (PDN pin = “L” → “H”). When DFS1-0 bits are changed, the AK4480 should be reset by RSTN bit.
DFS1 bit DFS0 bit
Sampling Rate (fs)
(default)
0
0
1
0
1
0
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
30kHz ∼ 54kHz
54kHz ∼ 108kHz
120kHz ∼ 216kHz
Table 8. Sampling Speed (Manual Setting Mode @Serial Mode)
LRCK
fs
MCLK (MHz)
BICK
64fs
128fs
N/A
N/A
192fs
N/A
N/A
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
512fs
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
11.2896MHz
12.2880MHz
N/A
N/A
11.2896
12.2880
22.5792
24.5760
16.9344
18.4320
33.8688
36.8640
N/A
N/A
Table 9. System Clock Example (Manual Setting Mode @Serial Mode)
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 10) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided (Table 11).
MCLK
1152fs
Sampling Speed
Normal (fs≤32kHz)
Normal
512fs/256fs
768fs/384fs
384fs
256fs
128fs
Double
Quad
192fs
Table 10. Sampling Speed (Auto Setting Mode @Serial Mode)
LRCK
fs
MCLK (MHz)
Sampling
Speed
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
192fs
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
512fs
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
Normal
Double
Quad
N/A
N/A
Table 11. System Clock Example (Auto Setting Mode @Serial Mode)
MS1146-E-03
2012/01
- 19 -
[AK4480]
MCLK= 256fs/384fs supports sampling rate of 32kHz ~ 96kHz (Table 12). However, when the sampling rate is 32kHz ~
48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS bit
MCLK
256fs/384fs/512fs/768fs
256fs/384fs
DR,S/N
114dB
111dB
114dB
0
1
1
512fs/768fs
Table 12. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)
[2] DSD Mode
The external clocks, which are required to operate the AK4480, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4480 is automatically placed in reset state when MCLK is stopped during a normal operation, and the analog
output becomes AVDD/2 (typ).
DCKS bit
MCLK Frequency
512fs
DCLK Frequency
0
1
64fs
64fs
(default)
768fs
Table 13. System Clock (DSD Mode)
MS1146-E-03
2012/01
- 20 -
[AK4480]
■ Audio Interface Format
[1] PCM Mode
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the
DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 14. In all formats the serial
data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and
16-bit MSB justified formats by zeroing the unused LSBs.
Mode
DIF2
DIF1
DIF0
Input Format
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 64fs
≥64fs
≥ 64fs
Figure
Figure 1
Figure 2
Figure 3 (default)
Figure 4
Figure 2
Figure 5
Figure 6
Figure 7
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16bit LSB justified
20bit LSB justified
24bit MSB justified
24bit I2S Compatible
24bit LSB justified
32bit LSB justified
32bit MSB justified
32bit I2S Compatible
Table 14. Audio Interface Format
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15 14
6
5
4
3
2
1
0
0
15 14
6
5
4
3
2
1
0
0
15 14
0
1
14
15
16
17
31
0
1
14
15
16
17
31
0
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15 14
Don’t care
15 14
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
BICK
(64fs)
SDATA
Mode 1
Don’t care
Don’t care
Don’t care
19
0
0
19
0
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23 22 21 20 19
23 22 21 20 19
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
MS1146-E-03
2012/01
- 21 -
[AK4480]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23 22
23:MSB, 0:LSB
1
0
Don’t care
0
Don’t care
23 22
1
23 22
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDATA
0
1
23 22
23:MSB, 0:LSB
Don’t care
23 22
1
0
Don’t care
23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31
1
1
0
0
31
1
1
0
0
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
9
8
31 30
20 19 18
9
8
31
Lch Data
Rch Data
31: MSB, 0:LSB
Figure 5. Mode 5 Timing
MS1146-E-03
2012/01
- 22 -
[AK4480]
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31 30
12 11 10
0
9
31 30
12 11 10
0
9
31
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
1
BICK(64fs)
SDATA
8
1
0
31 30
20 19 18
8
1
0
31
31 30
20 19 18
Lch Data
Rch Data
31: MSB, 0:LSB
Figure 6. Mode 6 Timing
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
0
1
BICK(128fs)
SDATA
31
31
13 12 11
0
9
31
13 12 11
0
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDATA
0
21 20 19
8
2
1
0
31
21 20 19
Rch Data
9
8
2
1
0
Lch Data
31: MSB, 0:LSB
Figure 7. Mode 7 Timing
[2] DSD Mode
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
D0
D1
D2
D3
D3
DSDL,DSDR
Phase Modulation
D1
D2
D1
D2
Figure 8. DSD Mode Timing
MS1146-E-03
2012/01
- 23 -
[AK4480]
[3] External Digital Filter Mode (EX DF I/F Mode)
DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL
and DINR pins. Three formats are available (Table 16) by DIF2-0 bits setting. The data is latched on the rising edge of
BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each
sampling speed are shown in Table 15.
Sampling
Speed[kHz]
WCK
MCLK&BCK [MHz]
ECS
128fs
N/A
192fs
N/A
256fs
N/A
384fs
N/A
512fs
22.5792
32
768fs
33.8688
48
16fs
DW
8fs
44.1(30~54)
44.1(30~54)
96(54~108)
96(54~108)
0
1
0
1
(default)
16.9344
48
33.8688
N/A
N/A
N/A
N/A
11.2896
32
N/A
96
DW
24.576
32
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
8fs
DW
4fs
DW
4fs
48
18.432
48
36.864
96
12.288
32
N/A
24.576
32
N/A
36.864
N/A
N/A
N/A
192(108~216)
192(108~216)
0
1
48
36.864
96
DW
2fs
DW
N/A
Table 15. System Clock Example (EX DF I/F mode) (N/A: Not available)
Mode
DIF2
DIF1
DIF0
Input Format
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16bit LSB justified
N/A
N/A
N/A
24bit LSB justified
32bit LSB justified (default)
N/A
N/A
Table 16. Audio Interface Format (EX DF I/F mode) (N/A: Not available)
MS1146-E-03
2012/01
- 24 -
[AK4480]
1/16fs or 1/8fs or 1/4fs or 1/2fs
WCK
BCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
DINL or
DINR
31 30
24
23 22 21 20 17 16 15 14
6
5
4
3
2
1
0
65
92
93
94
0
1
5
6
7
8
47
48
49
95
0
1
BCK
DINL or
DINR
Don’t care
Don’t care
Don’t care
31
31
2
2
1
1
3
0
0
Don’t care
17
44
45
46
0
1
5
6
7
8
23
24
25
47
0
1
BCK
DINL or
DINR
Don’t care
Don’t care
Don’t care
Don’t care
3
Figure 9. EX DF I/F Mode Timing
MS1146-E-03
2012/01
- 25 -
[AK4480]
■ D/A Conversion Mode Switching Timing
RSTN bit
≥4/fs
D/A Mode
D/A Data
PCM Mode
DSD Mode
≥0
PCM Data
DSD Data
Figure 10. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 11. D/A Mode Switching Timing (DSD to PCM)
Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty
range at the SACD format book (Scarlet Book).
■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs). It is enabled and
disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is
always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are
switched.
DEM1
DEM0
Mode
44.1kHz
OFF
48kHz
32kHz
0
0
1
1
0
1
0
1
(default)
Table 17. De-emphasis Control
■ Output Volume (PCM and DSD)
The AK4480 includes channel independent digital output volume control (ATT) with 255 levels at linear step including
MUTE. This volume control is in front of the DAC and it can attenuate the input data from 0dB to –48dB and mute. When
changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions.
Transition Time
Sampling Speed
1 Level
4LRCK
8LRCK
16LRCK
4LRCK
255 to 0
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
DSD Mode
1020LRCK
2040LRCK
4080LRCK
1020LRCK
Table 18. ATT Transition Time
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[AK4480]
■ Zero Detection (PCM and DSD)
The AK4480 has channel-independent zero detect function. When the input data at each channel is continuously zeros for
8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to “L” if
the input data of each channel is not zero after becoming “H”. When the RSTN bit is “0”, the DZF pins of both channels
become “H”. The DZF pins of both channels become “L” in 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to
“1”, the DZF pins of both channels go to “H” only when the input data for both channels are continuously zeros for 8192
LRCK cycles. The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels
are always “L”. The DZFB bit can invert the polarity of the DZF pin.
■ Mono Output (PSM, DSD, Ex DF I/F)
The AK4480 can select input/output for both output channels by setting the MONO bit and SELLR bit. This function is
available for any audio format.
MONO bit
SELLR bit
Lch Out
Rch Out
0
0
1
1
0
1
0
1
Lch In
Rch In
Lch In
Rch In
Rch In
Lch In
Lch In
Rch In
Table 19. MONO Mode Output Select
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[AK4480]
■ Soft Mute Operation (PCM and DSD)
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,
the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the
SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before
attenuating −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1)
(1)
ATT_Level
Attenuation
(3)
-∞
GD
(2)
GD
(2)
AOUT
(4)
8192/fs
DZF pin
Notes:
(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in
Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel
goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.
Figure 12. Soft Mute Function
■ System Reset
The AK4480 should be reset once by bringing the PDN pin = “L” upon power-up. The analog block exits power-down
mode by MCLK input and the digital block exits power-down mode after the internal counter counts MCLK for 4/fs.
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[AK4480]
■ Power ON/OFF timing
The AK4480 is placed in power-down mode by bringing the PDN pin “L” and the registers are initialized. The analog
outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN signal, the analog output should be muted
externally if the click noise influences system application.
The AK4480 can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding
analog outputs become AVDD/2 (typ). As some click noise occurs at the edge of RSTN signal, the analog output should
be muted externally if the click noise influences system application.
Power
(1)
PDN pin
Internal
State
Normal Operation
Reset
DAC In
(Digital)
“0”data
“0”data
GD
(2)
GD
(3)
(4)
(4)
(3)
DAC Out
(Analog)
(5)
Don’t care
Clock In
MCLK,LRCK,BICK
Don’t care
(7)
DZFL/DZFR
External
Mute
(6)
Mute ON
Mute ON
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”). (DZFB bit = “0”)
Figure 13. Power-down/up Sequence Example
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[AK4480]
■ Reset Function
(1) RESET by RSTN bit = “0”
When RSTN bit = “0”, the AK4480’s digital section is powered down but the internal register values are not initialized.
The analog outputs become VCML/R voltage and DZF pins of both channels become “H”. Figure 14 shows the example
of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN Timing
Internal
State
Normal Operation
Digital Block
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(2)
(3)
D/A Out
(Analog)
(4)
Clock In
MCLK, BICK, LRCK
Don’t care
2/fs(5)
DZFL/DZFR
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) The analog outputs are VCOM voltage when RSTN bit = “0”.
(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) The DZF pins become “H” when the RSTN bit is set to “0”, and return to “L” in 2/fs after the RSTN bit is changed
to “1”.
(5) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) or Hi-z output (2) influences system applications. The timing
example is shown in this figure.
Figure 14. Reset Sequence Example 1
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[AK4480]
(2) RESET by MCLK or LRCK/WCK stop
The AK4480 is automatically placed in reset state when MCLK or LRCK is stopped during PCM mode (RSTN pin
=“H”), and the analog outputs become AVDD/2 (typ). When MCLK and LRCK are input again, the AK4480 exit reset
state and starts the operation. Zero detect function is not available when MCLK or LRCK is stopped. The AK4480 is set to
reset state automatically and the analog outputs become Hi-Z when MCLK is stopped in DSD mode, and when MCLK or
WCK is stopped in external digital filter mode.
AVDD pin
DVDD pin
(1)
PDN pin
Internal
State
Power-down
Power-down
Normal Operation
Reset
Normal Operation
D/A In
(Digital)
(3)
GD (2)
GD (2)
(4)
(5)
(4)
Hi-Z
VCOM
D/A Out
(Analog)
(4)
(6)
Clock In
MCLK, LRCK
MCLK or LRCK Stop
External
MUTE
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK or LRCK/WCK is input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 3 ∼ 4LRCK cycles from rising edge (↑ ) of PDN signal or MCLK inputs. This noise is
output even if “0” data is input.
(5) MCLK, BICK and LRCK/WCK clocks can be stopped in reset mode (MCLK or LRCK/WCK stopped).
(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.
Figure 15. Reset sequence example 2
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[AK4480]
■ Register Control Interface
Functions of the AK4480 can be controlled in parallel control mode (by pins) and serial control mode (by registers). In
parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state
of the PSN pin is changed, the AK4480 should be reset by the PDN pin. The serial control interface is enabled by the PSN
pin = “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this
interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit; fixed to “1”), Register address (MSB first, 5-bits) and
Control data (MSB first, 8-bits). The AK4480 latches the data on the rising edge of CCLK, so data should be clocked in on
the falling edge. The writing of data is valid when CSN “↑”. The clock speed of CCLK is 5MHz (max).
Function
Parallel Control Mode Serial Control Mode
Audio Format
Auto Setting Mode
De-emphasis
SMUTE
DSD Mode
Y
-
Y
Y
-
-
-
Y
-
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EX DF I/F
Zero Detection
Sharp Roll Off Filter
Slow Roll Off Filter
Minimum delay Filter
Digital Attenuator
Table 20. Function List (Y: Available, -: Not available)
Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is
reset by the RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 16. Control I/F Timing
* The AK4480 does not support the read command.
* When the AK4480 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control
registers is prohibited.
* The control data can not be written when the CCLK rising edge is 15 times and less or 17 times and more during CSN is
“L”.
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[AK4480]
Function List
Function
Default
0dB
Address
Bit
PCM
Y
DSD
Y
Ex DF I/F
-
Attenuation Level
03H
04H
00H
00H
ATT7-0
External Digital Filter I/F Mode
Ex DF I/F mode clock setting
Audio Data Interface Modes
Data Zero Detect Enable
Data Zero Detect Mode
Minimum delay Filter Enable
De-emphasis Response
Disable
16fs(fs=44.1kHz)
24bit MSB justified 00H
Disable
Separated
Sharp roll-off filter
OFF
Normal Operation
PCM mode
512fs
EXDF
ESC
DIF2-0
DZFE
DZFM
SD
DEM1-0
SMUTE
DP
Y
-
-
-
-
Y
Y
-
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
01H
01H
01H
01H
01H
02H
02H
-
-
-
-
Soft Mute Enable
DSD/PCM Mode Select
Master Clock Frequency Select at
DSD mode
DCKS
-
Y
-
MONO mode Stereo mode select
Inverting Enable of DZF
The data selection of L channel and R channel
R channel
Stereo
“H” active
02H
02H
02H
MONO
DZFB
SELLR
Y
Y
Y
Y
Y
-
Y
Y
Y
(Y: Available, -: Not available)
Table 21. Function List
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[AK4480]
■ Register Map
Addr Register Name
00H Control 1
01H Control 2
02H Control 3
D7
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
D5
ECS
SD
DCKS
ATT5
ATT5
0
D4
0
DFS1
DCKB
ATT4
ATT4
0
D3
DIF2
DFS0
MONO
ATT3
ATT3
0
D2
DIF1
DEM1
DZFB
ATT2
ATT2
0
D1
DIF0
DEM0
SELLR
ATT1
ATT1
0
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
0
ACKS
DZFE
DP
ATT7
ATT7
INVL
03H
04H
Lch ATT
Rch ATT
05H Control 4
Notes:
Data must not be written into addresses from 06H to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4480 should be reset by the PDN pin.
■ Register Definitions
Addr Register Name
00H Control 1
Default
D7
ACKS
0
D6
EXDF
0
D5
ECS
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
When internal clocks are changed, the AK4480 should be reset by the PDN pin or RSTN bit.
DIF2-0: Audio Data Interface Modes (Table 14)
Initial value is “010” (Mode 2: 24-bit MSB justified).
ECS: Ex DF I/F mode clock setting (Table 15)
0: BCK 32fs setting. MCLK, BCK are 512fs, 256fs and 128fs (default)
1: No BCK 32fs setting. MCLK, BCK are 768fs, 384fs and 192fs.
EXDF: External Digital Filter I/F Mode (PCM only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
When ACKS bit is “1”, sampling frequency and MCLK frequency is detected automatically.
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[AK4480]
Addr Register Name
01H Control 2
Default
D7
DZFE
0
D6
DZFM
0
D5
SD
1
D4
DFS1
0
D3
DFS0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1-0: De-emphasis Response (Table 17)
Initial value is “01” (OFF).
SD:
Minimum delay Filter Enable
0: Sharp roll-off filter (default)
1: Minimum delay filter
SD
0
0
1
1
SLOW
Mode
Sharp roll-off filter
Slow roll-off filter
Minimum delay filter (default)
Reserved
0
1
0
1
Table 22. Digital Filter setting
DFS1-0: Sampling Speed Control (Table 8)
The default is “00” (Normal Speed). A click noise occurs when switching DFS1-0 bits.
DZFM: Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels become “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
DZFE:
Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
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[AK4480]
Addr Register Name
02H Control 3
Default
D7
DP
0
D6
0
0
D5
DCKS
0
D4
DCKB
0
D3
MONO
0
D2
DZFB
0
D1
SELLR
0
D0
SLOW
0
SLOW: Slow Roll-off Filter Enable
0: (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output R channel data, when MONO mode. (default)
1: All channel output L channel data, when MONO mode.
In Mono mode, Rch’s date is output to both channels by setting SELLR bit = “0”, and Lch’s data is output
to both channels by setting SELLR bit = “1”. In Stereo mode, the output data of L and R channels are
switched their output ports by setting SELLR bit = “1”. (Table 19)
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
DZFB setting is valid regardless of the DZFE bit setting.
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4480 should be reset by RSTN bit.
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
ATT7-0: Attenuation Level
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH: 0dB (default)
00H: Mute
MS1146-E-03
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[AK4480]
Addr Register Name
05H Control 4
Default
D7
INVL
0
D6
INVR
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
INVR:
INVL:
AOUTR Output Phase Invert
0: Disable (default)
1: Enable
AOUTL Output Phase Invert
0: Disable (default)
1: Enable
MS1146-E-03
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[AK4480]
SYSTEM DESIGN
Figure 17 shows the system connection diagram. Figure 19, Figure 20 and Figure 21 show the analog output circuit
examples. An evaluation board (AKD4480) demonstrates the optimum layout, power supply arrangements and
measurement results.
Digital 5.0V
1
2
CSN
LRCK 30
CAD0
SDATA 29
Micro-
3
4
CCLK
CDTI
BICK 28
PDN 27
Controller
DSP
+
5
6
CAD1
DZFL
DVDD 26
VSS4 25
0.1u
10u
MCLK
7
8
DIF2
PSN
24
AK4480
Top
+
AVDD 23
View
0.1u
10u
DZFR
9
VSS3 22
10 AOUTRP
AOUTRN
AOUTLP 21
Rch
Mute
Lch
Mute
Rch
LPF
Lch
LPF
Lch Out
Rch Out
11
AOUTLN 20
VSS2 19
12 VSS1
0.1u
0.1u
10u
+
+
0.1u
0.1u
10u
+
+
VDDL
13 VDDR
18
14 VREFHR
VREFHL 17
VREFLL 16
10u
10u
15 VREFLR
Digital
Ground
Analog
Ground
Analog 5.0V
+
Elec trolytic Capacitor
Ceramic Capacitor
Notes:
- Power lines of AVDD and DVDD should be distributed separately from regulators with keeping low impedance.
- VSS1/2/3/4 must be connected to the same analog ground plane.
- When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the
capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 17. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial Control Mode)
MS1146-E-03
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[AK4480]
Analog Ground
Digital Ground
1
2
SMUTE/CSN
LRCK 30
SDATA 29
BICK 28
SD/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0/CAD1
DIF1/DZFL
DIF2
3
4
PDN
27
5
DVDD 26
VSS4 25
MCLK 24
AVDD 23
System
Controller
6
7
AK4480
8
PSN
ACKS/DZFR
9
VSS3 22
AOUTRP
10
AOUTLP 21
11 AOUTRN
12 VSS1
AOUTLN 20
VSS2
19
VDRR
13
14
VDDL 18
VREFHL 17
VREFLL 16
VREFHR
15 VREFLR
Figure 18. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD
respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from regulators with keeping low
impedance. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be connected
to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to
the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency
noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4480.
3. Analog Outputs
The analog outputs are full differential outputs and 2.4Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around
AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−.
If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.
MS1146-E-03
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[AK4480]
AK4480
AOUT-
3.9k
4.7k
470p
150
+Vop
3.9n
3.9k
Analog
Out
150
AOUT+
-Vop
4.7k
470p
Figure 19. External LPF Circuit Example 1 for PCM (fc = 99.0kHz, Q=0.680)
Frequency Response
20kHz
Gain
−0.036dB
−0.225dB
−1.855dB
40kHz
80kHz
Table 23. Frequency Response of External LPF Circuit Example 1 for PCM
+15
-15
3.3n
+
10u
100u
180
3.9n
0.1u
7
4
3
2
+
AOUTL-
6
+
-
330
10u
+
0.1u
10u
NJM5534D
560
+
0.1u
1.0n
680
100
2
-
4
620
620
6
Lch
+
3
1.0n 7NJM5534D
3.3n
180
3.9n
+
10u
10u
100u
0.1u
7
+
3
AOUTL+
+
-
6
2
330
+10u
0.1u
4
NJM5534D
+
0.1u
680
Figure 20. External LPF Circuit Example 2 for PCM
1st Stage
182kHz
0.637
2nd Stage
284kHz
-
Total
-
-
Cut-off Frequency
Q
Gain
+3.9dB
-0.025
-0.106
-0.517
-0.88dB
-0.021
-0.085
-0.331
+3.02dB
-0.046dB
-0.191dB
-0.848dB
20kHz
40kHz
80kHz
Frequency
Response
Table 24. Frequency Response of External LPF Circuit Example 2 for PCM
MS1146-E-03
2012/01
- 40 -
[AK4480]
It is recommended in SACD format book (the Scarlet Book) that the filter response at SACD playback is an analog low
pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum -30dB/Oct. The AK4480 can achieve this
filter response by combination of the internal filter (Table 25) and an external filter (Figure 21).
Frequency
20kHz
50kHz
Gain
−0.4dB
−2.8dB
−15.5dB
100kHz
Table 25. Internal Filter Response at DSD Mode
2.0k
1.8k
1.8k
4.3k
AOUT-
AOUT+
1.0k
1.0k
270p
2.4Vpp
2.4Vpp
2200p
+Vop
3300p
4.3k
-
2.0k
Analog
Out
5.42Vpp
+
-Vop
270p
Figure 21. External 3rd Order LPF Circuit Example for DSD
Frequency
20kHz
50kHz
Gain
−0.05dB
−0.51dB
−16.8dB
100kHz
DC gain = 1.07dB
Table 26. 3rd Order LPF (Figure 21) Response
MS1146-E-03
2012/01
- 41 -
[AK4480]
PACKAGE
30pin VSOP (Unit: mm)
*9.7 0.1
1.5MAX
±
0.3
30
16
A
15
1
+0.10
-0.05
0.65
0.22 0.1
±
0.15
0.12
M
Detail A
0.08
NOTE: Dimension "*" does not include mold flash.
■ Material & Lead finish
Package molding compound:
Lead frame material:
Epoxy, Halogen (bromine and chlorine) free
Cu
Lead frame surface treatment:
Solder (Pb free) plate
MS1146-E-03
2012/01
- 42 -
[AK4480]
MARKING
AK4480EF
XXXXXXXXX
1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK4480
5) Audio 4 pro Logo
REVISION HISTORY
Date (Y/M/D) Revision Reason
Page
3, 4
17
Contents
10/01/28
10/02/17
00
01
First Edition
Error
Pin No.9 was changed.
TST2/DZFR pin → ACKS/DZFR pin
OPERATION OVERVIEW
Correction
■ System Clock/[1] PCM Mode
(1) Parallel Mode, 1. Manual Setting Mode
Descriptions about the DFS0 pin were deleted.
Table 3 was deleted.
18
Table 4 and descriptions were added.
2. Auto Setting Mode
Descriptions about the DFS0 pin were deleted.
(2) Serial Mode, 2. Auto Setting Mode
Table 12: ACKS pin → ACKS bit
■ Register Definitions
The description of SELLR was changed.
■ Register Map
20
36
34
11/11/01
12/01/12
02
03
Error
Correction
Error
Correction
Write prohibited address: “05H to 1FH” → “06H to 1FH”
MS1146-E-03
2012/01
- 43 -
[AK4480]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS1146-E-03
2012/01
- 44 -
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