AK4601VQ [AKM]

Audio HUB CODEC with Digital Mixer;


型号：	AK4601VQ
厂家：	ASAHI KASEI MICROSYSTEMS
描述：	Audio HUB CODEC with Digital Mixer
文件：	总111页 (文件大小：2429K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

[AK4601]

AK4601

Audio HUB CODEC with Digital Mixer

1. General Description

The AK4601 is an Audio HUB CODEC including 5ch ADC, 6ch DAC and digital mixers. The analog input

block consists of a 24-bit stereo ADC, a 24-bit stereo ADC with input selector and a monaural ADC, and

the analog output block consists of 32-bit 6ch DAC. The transfer block for digital signals integrates a

serial interface that supports Data BUS and TDM format, realizing an audio HUB function. It gives

scalability to the device for both analog and digital signals.

A car audio system that is capable of processing both sound and voice such as for hands-free function

simultaneously can be realized by using the AK4601 with AKM’s multi-core DSP, the AK7707. The

AK4601 is available in a space saving 48-pin LQFP package.

2. Features

□ ADC1: 24-bit Stereo ADC with MIC Gain Amplifiers

- Sampling Frequency: fs=8kHz to 192kHz

- Channel Independent Analog Gain Amplifiers

(0 to 18dB(2dB Step), 18 to 36dB(3dB step))

- Differential Input or Single-ended Input

- ADC Characteristics

S/N: 106dB (fs=48kHz, Differential Input, MIC Gain=0dB,)

- Channel Independent Digital Volume Control (+24 to -103dB, 0.5dB Step, Mute)

- Digital HPF for DC Offset Cancelling

- Low Noise MIC Power Output: 2ch

- 4 types of Digital Filter for Sound Color Selection

□ ADC2: 24-bit Stereo ADC with Input Selector

- Sampling Frequency: fs=8kHz to 192kHz

- Analog Input Selector: Differential Input x1 or Single-ended Input x2,

Semi-Differential Input x1

- ADC Characteristics

S/N: 106dB (fs=48kHz, Differential Input)

- Channel Independent Digital Volume (+24 to -103dB, 0.5dB Step, Mute)

- Digital HPF for DC Offset Cancelling

- 4 types of Digital Filter for Sound Color Selection

□ ADCM: 24-bit Monaural ADC

- Sampling Frequency: fs=8kHz to 192kHz

- Differential Input or Single-ended Input

- ADC Characteristics

S/N: 106dB (fs=48kHz, Differential Input)

- Channel Independent Digital Volume (+24 to -103dB, 0.5dB Step, Mute)

- Digital HPF for DC Offset Cancelling

- 4 types of Digital Filter for Sound Color Selection

□ DAC: Advanced 32-bit DAC

- 2ch x3

- Sampling Frequency: fs=8kHz to 192kHz

- Single-ended Output

- DAC Characteristics

S/N: 108dB (fs=48kHz)

- Channel Independent Digital Volume Control (+12 to -115dB, 0.5dB Step, Mute)

- 4 types of Digital Filter for Sound Color Selection

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□ Digital Interface:

- Digital Input Port: max 20ch(16ch x 1Port, 2ch x 2Port) when TDM mode

- Digital Output Port: max 20ch(16ch x 1Port, 2ch x 2Port) when TDM mode

- Independent LRCK/BICK Input port x 2 Lines

- Data Format: MSB 32,24-bit / LSB 24,20,16-bit / I²S

- PCM Short / Long Frame Supported

- TDM Format Supported

□ Digital Mixer Circuit

□ Independent Digital Volume (+12 to -115dB, 0.5dB Step, Mute)

□ PLL Circuit

□ μP Interface: SPI(7MHz max), I²C-bus (max 1MHz, Fast Mode Plus)

□ Power Supply:

- Analog AVDD: 3.0 to 3.6V (typ. 3.3V)

- Digital LVDD: 3.0 to 3.6V (typ. 3.3V) (3.3V → 1.2V regulator integrated)

- I/F

TVDD: 1.7 to 3.6V (typ. 3.3V)

□ Operating Temperature Range: -40°C to 85°C

□ Package: 48-pin LQFP (7mm x 7mm, 0.5mm pitch)

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3. Table of Contents

1. General Description.............................................................................................................................. 1

2. Features................................................................................................................................................ 1

3. Table of Contents ................................................................................................................................. 3

4. Block Diagram and Functions .............................................................................................................. 4

■ Device Block Diagram....................................................................................................................... 4

5. Pin Configuration and Functions .......................................................................................................... 5

■ Pin Layout ......................................................................................................................................... 5

■ Pin Functions..................................................................................................................................... 6

■ Handling of Unused Pins................................................................................................................... 8

■ Pull-down Pin Statuses ..................................................................................................................... 9

■ Power-down Status of Output Pins................................................................................................. 10

6. Absolute Maximum Ratings................................................................................................................ 11

7. Recommended Operating Conditions................................................................................................ 11

8. Electrical Characteristics .................................................................................................................... 12

■ Analog Characteristics .................................................................................................................... 12

■ Power Consumption........................................................................................................................ 18

9. Digital Filter Characteristics................................................................................................................ 19

10. DC Characteristics.............................................................................................................................. 27

■ DC Characteristics .......................................................................................................................... 27

11. Switching Characteristics ................................................................................................................... 28

12. Functional Descriptions ...................................................................................................................... 35

■ System Clock .................................................................................................................................. 35

■ Data Path Setting............................................................................................................................ 45

■ Power-up Sequence........................................................................................................................ 64

■ LDO (Internal Circuit Drive Regulator)............................................................................................ 65

■ Power-down and Reset................................................................................................................... 65

■ STO Bit Status................................................................................................................................. 67

■ μP Interface Setting and Pin Status................................................................................................ 67

■ I²C Bus Interface (CSN = “H”)......................................................................................................... 69

■ Mixer................................................................................................................................................ 73

■ Vol ................................................................................................................................................... 74

■ Analog Input Blcok .......................................................................................................................... 76

■ ADC Block (ADC1, ADC2, ADCM) ................................................................................................. 78

■ DAC Block (DAC1, DAC2 and DAC3) ............................................................................................ 82

■ Register Map................................................................................................................................... 86

■ Register Definitions......................................................................................................................... 89

13. Recommended External Circuits...................................................................................................... 104

■ Connection Diagram .....................................................................................................................104

■ Peripheral Circuit...........................................................................................................................106

14. Package............................................................................................................................................ 108

■ Outline Dimensions.......................................................................................................................108

■ Material and Lead Finish...............................................................................................................108

■ Marking..........................................................................................................................................109

15. Ordering Guide ................................................................................................................................. 109

■ Ordering Guide..............................................................................................................................109

16. Revision History................................................................................................................................ 110

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4. Block Diagram and Functions

■ Device Block Diagram

Figure 1. Block Diagram

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5. Pin Configuration and Functions

■ Pin Layout

AVDD

AINMN

AVDD

AVSS

VCOM

MPWR2

MPWR1

MPREF

TESTI

LVDD

VREFH

VREFL

DVSS2

LVDD

48pin LQFP

( Top View )

AOUT1R

AOUT1L

AOUT2R

AOUT2L

AOUT3R

AOUT3L

AVDRV

PDN

SI / I2CFIL

SCLK / SCL

SO/SDA

CSN

TVDD

Input

Output

I / O

Power

は、プルダウン抵抗付ピンです。 *：ピン名

Pins with framed name are pu**lled down internally.

***

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■ Pin Functions

No. Pin Name

I/O

Function

CLKO

BICK1

Master Clock Output Pin

I/O

Serial Bit Clock 1 Pin

LRCK1

LR Channel Select Clock 1 Pin

SDIN1

Serial Digital Data Input 1 Pin

Serial Digital Data Output 1 Pin

SDOUT1

DVSS1

TVDD

Digital Ground 1 Pin 0V

Digital I/F Power Supply Pin 1.7~3.6V (typ.3.3V)

Serial Data Output 2 Pin

SDOUT2

SDIN2

Serial Data Input 2 Pin

LR Channel Select Clock 2 Pin

(MSELN bit = “L”, default)

Serial Data Output 3 Pin

(MSELN bit = “H”)

Serial Bit Clock 2 Pin

(MSELN bit = “L”, default)

Serial Data Input 3 Pin

(MSELN bit = “H”)

LRCK2

SDOUT3

BICK2

I/O

SDIN3

MCKI

Master Clock Pin

SPI I/F Chip Select N Pin

CSN

During power-down state or when μP I/F are not in use, leave this pin

“H” level.

Serial Data Output Pin for SPI I/F

This pin outputs “Hi-Z” during power-down state.

Serial Data In/Output Pin for I²C I/F

This pin outputs “Hi-Z” during power-down state.

SDA

I/O

SCLK

SCL

Serial Data Clock Input Pin for SPI I/F

Serial Data Clock Input Pin for I²C I/F

Serial Data Input Pin for SPI I/F

I²C I/F Mode Select Input Pin

I2CFIL

PDN

I2CFIL = “L”: Fast Mode (400kHz)

I2CFIL = “H”: Fast Mode Plus (1MHz) (should be fixed to TVDD)

Power-down N Pin

Use this pin to power down the AK4601.

The PDN pin should be held “L” when power is supplied.

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No. Pin Name

I/O

Function

LDO Output Pin

AVDRV

Connect a 2.2uF ceramic capacitor between this pin and DVSS2.

Do not connect this pin to an external circuit.

LVDD

Digital Core Power Supply Pin 3.0~3.6V (typ.3.3V)

Digital Ground 2 Pin 0V

DVSS2

Test Input Pin

TESTI

It must be tied “L”.

Ripple Filter Pin for Microphone Power Supply

Connect a 1uF ceramic capacitor between this pin and AVSS.

Do not connect this pin to an external circuit.

Power Supply Output 1 Pin for Microphone

This pin outputs “Hi-Z” during power-down state.

Power Supply Output 2 Pin for Microphone

This pin outputs “Hi-Z” during power-down state.

MPREF

MPWR1

MPWR2

INN1

MIC Lch Inverted Differential Input 1 Pin

MIC Lch Single-ended Input 1 Pin

AIN1L

INP1

MIC Lch Non-inverted Differential Input 1 Pin

MIC Rch Inverted Differential Input 2 Pin

MIC Rch Single-ended Input 1 Pin

INN2

AIN1R

INP2

MIC Rch Non-inverted Differential Input 2 Pin

ADC2 Rch Non-inverted Differential Input 2 Pin

ADC2 Rch Single-ended Input 3 Pin

AIN2RP

AIN3R

AIN2RN

AIN4R

AIN2LP

AIN3L

AIN2LN

AIN4L

AIN5L

GNDIN5

AIN5R

AINMP

AINM

ADC2 Rch Inverted Differential Input 2 Pin

ADC2 Rch Single-ended Input 4 Pin

ADC2 Lch Non-inverted Differential Input 2 Pin

ADC2 Lch Single-ended Input 3 Pin

ADC2 Lch Inverted Differential Input 2 Pin

ADC2 Lch Single-ended Input 4 Pin

ADC2 Lch Pseudo Differential Input 5 Pin

ADC2 Pseudo Differential Ground Input 5 Pin

ADC2 Rch Pseudo Differential Input 5 Pin

ADCM Non-inverted Differential Input Pin

ADCM Single-ended Input Pin

AINMN

AVDD

AVSS

ADCM Inverted Differential Input Pin

Analog Power Supply Pin 3.0~3.6V (typ.3.3V)

Analog Ground Pin 0V

Analog Common Voltage Output Pin

Connect a 2.2uF ceramic capacitor between this pin and AVSS.

Do not connect this pin to an external circuit.

This pin outputs “L” during power-down state.

VCOM

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No. Pin Name

I/O

Function

Analog High-level Reference Voltage Input Pin

Connect this pin to AVDD.

Analog Low-level Reference Voltage Input Pin

Connect this pin to AVSS.

DAC1 Rch Analog Output Pin

This pin outputs “Hi-Z” during power-down state.

DAC1 Lch Analog Output Pin

This pin outputs “Hi-Z” during power-down state.

DAC2 Rch Analog Output Pin

This pin outputs “Hi-Z” during power-down state.

DAC2 Lch Analog Output Pin

This pin outputs “Hi-Z” during power-down state.

DAC3 Rch Analog Output Pin

This pin outputs “Hi-Z” during power-down state.

DAC3 Lch Analog Output Pin

VREFH

VREFL

AOUT1R

AOUT1L

AOUT2R

AOUT2L

AOUT3R

AOUT3L

This pin outputs “Hi-Z” during power-down state.

■ Handling of Unused Pins

Unused I/O pins must be connected appropriately.

Classification Pin Name

Setting

Open

Analog

Digital

MPREF, MPWR1, MPWR2, AIN1L/INP1, INN1, AIN1R/INP2, INN2,

AIN2LP/AIN3L, AIN2LN/AIN4L, AIN2RP/AIN3R, AIN2RN/AIN4R,

AIN5L, GNDIN5, AIN5R, AINMP/AINM, AINMN, AOUT1L, AOUT1R

AOUT2L, AOUT2R, AOUT3L, AOUT3R

SDOUT1, SDOUT2, CLKO

BICK2/SDIN3, SDIN2, SDIN1, LRCK1, BICK1, LRCK2/SDOUT3,

MCKI, TESTI

Open

Connect to

DVSS1 ~ 2

Table 1. Handling of Unused Pins

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■ Pull-down Pin Statuses

Power-down Release

PDN pin = “H”

(Slave Mode, MSNx bit = “0”)

Power-down

Release

PDN pin = “H”

(Master Mode

MSNx bit = “1”)

No.

Power-down

PDN pin = “L”

PSWxN bit = “1”

PSWxN bit = “0”

CLKO

BICK1

Pulled-down (50K)

Output

Input

HiZ

Input

HiZ

Output

Input

Pulled-down (46K)

Input

Output

LRCK1

Pulled-down (50K)

Output

Pulled-down (46K)

SDOUT1

SDOUT2

LRCK2/SDOUT3

LRCK2

(MSELN bit = “L”)

Pulled-down (50K)

Output

Input

Pulled-down (46K)

Input

HiZ

Output

SDOUT3

(MSELN bit = “H”)

BICK2/SDIN3

BICK2

(MSELN bit = “L”)

Output

Pulled-down (50K)

Input

Pulled-down (46K)

Input

HiZ

Input

HiZ

Output

SDIN3

(MSELN bit = “H”)

Input

HiZ

AVDRV

TESTI

Pulled-down (70Ω)

Pulled-down (25K)

Output

Pulled-down (25K) Pulled-down (25K) Pulled-down (25K)

Table 2. Pull-down Pin Statuses (x=1~2)

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■ Power-down Status of Output Pins

Pin Name

CLKO

BICK1

LRCK1

SDOUT1

SDOUT2

I/O Power-down Status No

Pin Name

MPWR1

MPWR2

VCOM

AOUT1R

AOUT1L

AOUT2R

AOUT2L

AOUT3R

AOUT3L

I/O Power-down Status

I/O

“L” Output

Input

“Hi-Z” Output

“L” Output

“Hi-Z” Output

Input

“L” Output

Input

10 LRCK2/ SDOUT3 I/O

11 BICK2/SDIN3

I/O

Input

SO/SDA

AVDRV

MPREF

“Hi-Z” Output

“L” Output

Table 3. Power-down Status of Output Pins

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6. Absolute Maximum Ratings

(AVSS=DVSS1=DVSS2=0V; Note 1)

Parameter

Symbol

Min.

Max.

Unit

Power Supplies

Analog

Digital1(Core)

Digital2(I/F)

Difference (AVSS, DVSS1 ~ 2) (Note 1)

Input Current (except power supply pins)

AVDD

LVDD

TVDD

ΔGND

IIN

-0.3

4.3

0.3

±10

－

Analog Input Voltage

Digital Input Voltage

Ambient Temperature (Power applied)

Storage Temperature

(Note 2)

(Note 3)

VINA

VIND1

-0.3

-40

-65

(AVDD+0.3) or 4.3

(TVDD+0.3) or 4.3

C

150

Tstg

Note 1. All voltages are with respect to ground. AVSS and DVSS1-2 must be connected to the same

ground.

Note 2. The maximum analog input voltage is a smaller value between (AVDD+0.3)V and 4.3V.

Note 3. The maximum digital input voltage of SDIN1, SDIN2, BICK2/SDIN3, LRCK1, BICK1, MCKI,

LRCK2/SDOUT3, PDN, SCLK/SCL, SO/SDA, CSN, SI/I2CFIL pins is a smaller value between

(TVDD+0.3)V and 4.3V.

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal

operation is not guaranteed at these extremes.

7. Recommended Operating Conditions

(AVSS=DVSS1=DVSS2=0V; Note 1)

Parameter

Power Supplies

Analog

Symbol

Min.

Typ.

Max.

Unit

AVDD

LVDD

TVDD

3.0

1.7

-0.1

3.3

3.6

+0.1

Digital1(Core)

Digital2(I/F)

Difference1

Difference2

AVDD – LVDD

LVDD – TVDD

Note 4. The power-up sequence with AVDD, LVDD, TVDD is not critical. The PDN pin should be held

“L” when power is supplied. The PDN pin is allowed to be “H” after all power supplies are

applied and settled.

Note 5. Do not turn off the power supply of the AK4601 with the power supply of the peripheral device

turned on when using the I²C interface. Pull-up resistors of SDA and SCL pins should be

connected to TVDD or less voltage.

WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.

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8. Electrical Characteristics

■ Analog Characteristics

1. MIC AMP Gain

(Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1=DVSS2=0V, ADC1VL/R bit =

“0”)

Parameter

Input Impedance

Min.

-1

Typ.

Max.

Unit

kΩ

MGNL[3:0]bits=0h, MGNR[3:0]bits=0h

MGNL[3:0]bits=1h, MGNR[3:0]bits=1h

MGNL[3:0]bits=2h, MGNR[3:0]bits=2h

MGNL[3:0]bits=3h, MGNR[3:0]bits=3h

MGNL[3:0]bits=4h, MGNR[3:0]bits=4h

MGNL[3:0]bits=5h, MGNR[3:0]bits=5h

MGNL[3:0]bits=6h, MGNR[3:0]bits=6h

MGNL[3:0]bits=7h, MGNR[3:0]bits=7h

MGNL[3:0]bits=8h, MGNR[3:0]bits=8h

MGNL[3:0]bits=9h, MGNR[3:0]bits=9h

MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah

MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh

MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch

MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh

MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh

MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh

MIC

AMP

Gain

2. MIC Bias Output

(Ta=25C; AVDD=VREFH=LVDD=TVDD =3.3V; AVSS=VREFL=DVSS1=DVSS2=0V; Measurement

Frequency = 20Hz~20kHz)

Parameter

Output Voltage

Load Resistance

Load Capaitance

Output Noise (A-weighted)

Min.

2.3

Typ.

2.5

Max.

2.7

Unit

kΩ

dBV

MIC Bias

-108

-114

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3. MIC AMP + ADC1

(Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL= DVSS1= DVSS2 =0V; Signal

Frequency =1kHz; 24bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz;

Measurement Frequency BW=20Hz ~ 40kHz @fs=96kHz,192kHz; ADC1VL/R bit =”0”; MGNL/R[3:0]

bits = 0h (0dB))

Parameter

Min.

Typ.

Max.

Unit

Resolution

bit

Differential Input

(Note 7)

(Note 8)

(Note 9)

(Note 7)

(Note 8)

(Note 7)

(Note 8)

(Note 7)

(Note 8)

±2.1

±2.3

±2.5

Full-scale Input

Voltage

±0.264 ±0.290 ±0.315 Vpp

±2.55

±2.83

106

±3.11

fs=48kHz

fs=96kHz

fs=192kHz

S/(N+D)

(-1dBFS)

fs=48kHz (A-weighted) (Note 7)

fs=48kHz (A-weighted) (Note 8)

MIC AMP

+ ADC1

fs=96kHz

fs=192kHz

(Note 7)

(Note 8)

(Note 7)

(Note 8)

Dynamic Range

(-60dBFS)

fs=48kHz (A-weighted) (Note 7)

fs=48kHz (A-weighted) (Note 8)

fs=96kHz

fs=192kHz

(Note 7)

(Note 8)

(Note 7)

(Note 8)

(Note 6)

S/N

Inter-Channel Isolation

Channel Gain Mismatch

PSRR

105

0.0

0.3

(Note 7, Note 10)

(Note 11)

CMRR

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Parameter

Min.

Typ.

Max.

Unit

Single-ended Input

(Note 7)

(Note 8)

(Note 9)

(Note 7)

(Note 8)

(Note 7)

(Note 8)

(Note 7)

(Note 8)

2.1

0.264

2.55

2.3

0.290

2.83

2.5

0.315

3.11

Full-scale Input

Voltage

Vpp

fs=48kHz

fs=96kHz

fs=192kHz

S/(N+D)

(-1dBFS)

fs=48kHz (A-weighted) (Note 7)

fs=48kHz (A-weighted) (Note 8)

104

105

0.0

fs=96kHz

fs=192kHz

(Note 7)

(Note 8)

(Note 7)

(Note 8)

Dynamic Range

(-60dBFS)

fs=48kHz (A-weighted) (Note 7)

fs=48kHz (A-weighted) (Note 8)

fs=96kHz

fs=192kHz

(Note 7)

(Note 8)

(Note 7)

(Note 8)

(Note 6)

S/N

Inter-Channel Isolation

Channel Gain Mismatch

PSRR

0.3

(Note 7, Note 10)

Note 6. Inter-channel isolation with -1dBFS signal input between Lch and Rch.

Note 7. ADC1VL/R bit = “0”,MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is propotional to

AVDD (0.7 x AVDD).

Note 8. ADC1VL/R bit = “0”,MGNL/R[3:0] bits = 9h (+18dB). Input full-scale voltage is propotional to

AVDD (0.088 x AVDD).

Note 9. ADC1VL/R bit = “1”, MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is propotional to

AVDD (0.86 x AVDD).

Note 10. PSRR is applied to AVDD and VREFH with 1kHz, 50mVpp.

Note 11. Common mode rejection ratio is applied 1kHz and 100mVpp sine waves to both differential

input pins. It is defined as a reference value when appling 1kHz and ±100mVpp sine waves to

the differential input.

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4. ADC2

(Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1= DVSS2=0V; Signal

Frequency=1kHz; 24bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz;

Measurement Frequency BW=20Hz~40kHz @fs=96kHz,192kHz; ADC2VL/R bit =”0”)

Parameter

Resolution

Input Impedance

Differential Input

Full-scale Input Voltage

(Note 12)

Min.

Typ.

Max.

Unit

bit

kΩ

(Note 13)

±2.1

±2.3

±2.83

±2.5

±3.11

Vpp

(Note 14) ±2.55

fs=48kHz

fs=96kHz

fs=192kHz

S/(N+D)

(-1dBFS)

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

106

Dynamic Range

(-60dBFS)

S/N

fs=192kHz

Inter-Channel Isolation

Channel Gain Mismatch

PSRR

(Note 6)

105

0.0

0.3

(Note 10)

(Note 11)

ADC2

CMRR

Single-ended Input, Pseudo-differential Input

(Note 13)

(Note 14)

2.1

2.55

2.3

2.83

2.5

3.11

Full-scale Input Voltage

(Note 15)

Vpp

fs=48kHz

fs=96kHz

S/(N+D)

(-1dBFS)

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

104

105

0.0

Dynamic Range

(-60dBFS)

S/N

Inter-Channel Isolation

Channel Gain Mismatch

PSRR

(Note 6)

0.3

(Note 10)

(Note 16)

CMRR (Pseudo-differential)

Note 12. AIN2LP, AIN2LN, AIN2RP and AIN2RN pins.

Note 13. ADC2VL/R bit = “0”. Input full-scale voltage is propotional to AVDD (0.7 x AVDD).

Note 14. ADC2VL/R bit = “0”. Input full-scale voltage is propotional to AVDD (0.86 x AVDD).

Note 15. AIN3L, AIN3R, AIN4L, AIN4R, AIN5L and AIN5R pins.

Note 16. Common mode rejection ratio is applied 1kHz and 100mVpp sine waves to both

Pseudo-differential input and Pseudo-differential ground input pins. It is defined as a

reference value when appling 100mVpp sine wave to the Pseudo-differential input.

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[AK4601]

5. ADCM

(Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1=DVSS2=0V; Signal

Frequency=1kHz; 24bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz;

Measurement Frequency BW=20Hz ~ 40kHz @fs=96kHz,192kHz; ADCMV bit =”0”)

Parameter

Resolution

Input Impedance

Differential Input

Full-scale Input Voltage

(Note 17)

Min.

Typ.

Max.

Unit

bit

kΩ

(Note 18)

±2.1

±2.3

±2.83

±2.5

±3.11

Vpp

(Note 19) ±2.55

fs=48kHz

fs=96kHz

fs=192kHz

S/(N+D)

(-1dBFS)

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

106

Dynamic Range

(-60dBFS)

S/N

fs=192kHz

ADCM

PSRR

CMRR

(Note 10)

(Note 11)

Single-ended Input

Full-scale Input Voltage

(Note 20)

(Note 18)

(Note 19)

2.1

2.55

2.3

2.83

2.5

3.11

Vpp

fs=48kHz

fs=96kHz

S/(N+D)

(-1dBFS)

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

104

Dynamic Range

(-60dBFS)

S/N

PSRR

(Note 10)

Note 17. AINMP and AINMN pins.

Note 18. ADCMV bit = “0”. Input full-scale voltage is propotional to AVDD (0.7 x AVDD).

Note 19. ADCMV bit = “1”. Input full-scale voltage is propotional to AVDD (0.86 x AVDD).

Note 20. AINM pin

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[AK4601]

6. DAC

(Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1= DVSS2=0V;

SignalFrequency=1kHz; 32bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz

@fs=48kHz;Measurement Frequency BW=20Hz ~ 40kHz @fs=96kHz,192kHz)

Parameter

Resolution

Min.

Typ.

Max.

Unit

bit

Output Voltage

(Note 21)

2.55

2.83

3.11

Vpp

fs=48kHz

fs=96kHz

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

fs=192kHz

fs=48kHz (A-weighted)

fs=96kHz

S/(N+D)

(0dBFS)

100

108

101

108

101

110

0.0

Dynamic

Range

(-60dBFS)

DAC1

DAC2

DAC3

S/N

fs=192kHz

Inter-Channel Isolation (fin=1kHz)

Channel Gain Mismatch

Load Resistance

Load Capacitance

PSRR

(Note 22)

(Note 23)

(Note 10)

kΩ

0.7

Note 21. Full-scale output Voltage. Output full-scale voltage is propotional to AVDD (0.86 x AVDD).

Note 22. Inter-channel isolation between each DAC of Lch and Rch with 0dBFS signal input. (AOUT1L

and AOUT1R, AOUT2L and AOUT2R and AOUT3L and AOUT3R)

Note 23. to AC Load.

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[AK4601]

■ Power Consumption

(Ta=25C; AVDD=VREFH=3.0~3.6V(typ=3.3V, max=3.6V); LVDD=3.0~3.6V(typ=3.3V, max=3.6V);

TVDD=1.7~3.6V(typ=3.3V, max=3.6V); AVSS=VREFL=DVSS1=DVSS2=0V)

Parameter

Symbol

AVDD

LVDD

TVDD

AVDD

LVDD

TVDD

Min.

Typ.

13.5

0.01

Max.

Unit

Operation Current Consumption

(Note 24) (PDN pin= “H”)

Power-down Current

(PDN pin= “L”)

Note 24. The current consumption of LVDD varies depending on the system frequency.

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[AK4601]

9. Digital Filter Characteristics

1. ADC Block

(Ta= 25C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1

=DVSS2=0V)

1-1 Sharp Roll-Off Filter (ADSD bit = “0”, ADSL bit = “0”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHARP ROLL-OFF

0dB/-0.06dB

-3.0dB

GD

23.7

22.1

kHz

1/fs

Passband (Note 25)

27.8

Stopband

Stopband Attenuation

(Note 25)

Group Delay Distortion : 0Hz~20kHz

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.0

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHARP ROLL-OFF

0dB/-0.06dB

-3.0dB

GD

47.5

44.2

kHz

1/fs

Passband (Note 25)

55.6

Stopband

Stopband Attenuation

(Note 25)

Group Delay Distortion : 0Hz~40kHz

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.9

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHARP ROLL-OFF

0dB/-0.04dB

-3.0dB

GD

96.0

83.7

kHz

1/fs

Passband (Note 25)

Stopband

Stopband Attenuation

(Note 25)

122.9

Group Delay Distortion : 0Hz~40kHz

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

3.9

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[AK4601]

1-2 Slow Roll-Off Filter (ADSD bit = “0”, ADSL bit = “1”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SLOW ROLL-OFF

0dB/-0.074dB

-3.0dB

12.5

kHz

1/fs

Passband (Note 25)

36.5

19.2

Stopband

Stopband Attenuation

(Note 25)

GD

Group Delay Distortion : 0Hz~20kHz

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.0

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SLOW ROLL-OFF

0dB/-0.074dB

-3.0dB

kHz

1/fs

Passband (Note 25)

38.5

Stopband

Stopband Attenuation

(Note 25)

GD

Group Delay Distortion : 0Hz~40kHz

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.9

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SLOW ROLL-OFF

0dB/-0.1dB

-3.0dB

31.1

kHz

1/fs

Passband (Note 25)

62.3

Stopband

Stopband Attenuation

(Note 25)

GD

145.9

Group Delay Distortion : 0Hz~40kHz

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

3.88

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[AK4601]

1-3 Short Delay Sharp Roll-Off Filter (ADSD bit = “1”, ADSL bit = “0”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SHARP ROLL-OFF

0dB/-0.06dB

Passband (Note 25)

-3.0dB

22.1

kHz

1/fs

27.8

23.7

Stopband

(Note 25)

GD

Stopband Attenuation

Group Delay Distortion : 0Hz~20kHz

2.6

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.0

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SHARP ROLL-OFF

0dB/-0.06dB

Passband (Note 25)

-3.0dB

44.2

kHz

1/fs

55.6

47.5

Stopband

(Note 25)

GD

Stopband Attenuation

Group Delay Distortion : 0Hz~40kHz

2.6

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.9

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SHARP ROLL-OFF

0dB/-0.04dB

Passband (Note 25)

-3.0dB

83.7

kHz

1/fs

96.0

Stopband

(Note 25)

GD

122.9

Stopband Attenuation

Group Delay Distortion : 0Hz~40kHz

0.2

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

3.88

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[AK4601]

1-4 Short Delay Slow Roll-Off Filter (ADSD bit = “1”, ADSL bit = “1”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SLOW ROLL-OFF

0dB/-0.074dB

Passband (Note 25)

-3.0dB

12.5

kHz

1/fs

36.5

19.2

Stopband

(Note 25)

GD

Stopband Attenuation

Group Delay Distortion : 0Hz~20kHz

2.6

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.0

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SLOW ROLL-OFF

0dB/-0.074dB

Passband (Note 25)

-3.0dB

kHz

1/fs

38.5

Stopband

(Note 25)

GD

Stopband Attenuation

Group Delay Distortion : 0Hz~40kHz

2.6

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

1.9

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SLOW ROLL-OFF

0db/-0.1dB

Passband (Note 25)

-3.0dB

31.1

kHz

1/fs

63.2

Stopband

(Note 25)

GD

145.9

Stopband Attenuation

Group Delay Distortion : 0Hz~40kHz

0.5

Group Delay

(Note 26)

ADC Digital Filter(HPF)

Frequency Response

-3.0dB

3.88

Note 25. The passband and stopband frequencies are proportional to fs (sampling rate). High-pass

filter characteristics are not included. A reference value of each passband and stopband

frequency is the maximum value of frequency response.

Note 26. Delay time caused by the digital filter calculation. This time is measured from an impulse

signal input until impulse data are set into the output register. It includes group delay by HPF.

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[AK4601]

2. DAC Block

(Ta=25C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1=

DVSS2=0V)

2-1 Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHARP ROLL-OFF

0.05dB

3.0dB

21.7

kHz

Passband

(Note 27)

Passband Ripple

Stopband

Stopband Attenuation

Group Delay

23.4

(Note 28)

(Note 27)

-0.0032

0.0032

26.3

(Note 30, Note 31)

(Note 29)

27.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  20.0kHz

-0.3

0.1

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHARP ROLL-OFF

0.05dB

3.0dB

43.5

kHz

Passband

(Note 27)

Passband Ripple

Stopband

46.8

(Note 28)

(Note 27)

-0.0032

0.0032

52.5

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

27.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  40.0kHz

-0.5

0.1

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHARP ROLL-OFF

0.05dB

3.0dB

87.0

kHz

Passband

(Note 27)

Passband Ripple

Stopband

93.6

(Note 28)

(Note 27)

-0.0032

0.0032

105

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

27.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  80.0kHz

-1.9

0.1

Note 27. The passband and stopband frequencies are proportional to fs (sampling rate).

“PB=0.4535  fs, SB=0.546  fs”

Note 28. Pass-band gain amplitude of double seep over sampling filter at the first step of Interpolator.

Note 29. Delay time caused by the digital filter calculation. This time is measured from setting of the

16/20/24/32-bit impulse data to the input registers to output of the analog peak signal.

Note 30. The output level with a 1kHz, 0dB sine wave input is defined as 0dB.

Note 31. Band width of Stopband Attenuation ranges from 0kHz to fs.

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[AK4601]

2-2 Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SLOW ROLL-OFF

0.05dB

3.0dB

8.8

kHz

Passband

(Note 32)

Passband Ripple

Stopband

19.8

(Note 28)

(Note 32)

-0.043

42.7

0.043

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

6.8

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  20.0kHz

-5.0

0.1

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SLOW ROLL-OFF

0.05dB

3.0dB

17.7

kHz

Passband

(Note 32)

Passband Ripple

Stopband

39.5

(Note 28)

(Note 32)

-0.043

85.3

0.043

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

6.8

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  40.0kHz

-5.2

0.1

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SLOW ROLL-OFF

0.05dB

3.0dB

35.5

kHz

Passband

(Note 32)

Passband Ripple

Stopband

79.0

(Note 28)

(Note 32)

-0.043

171

0.043

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

6.8

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  80.0kHz

-5.90

0.1

Note 32. The passband and stopband frequencies are proportional to fs (sampling rate).

“PB=0.185  fs, SB=0.888  fs”

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[AK4601]

2-3 Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”)

fs=48kHz

Parameter

SHORT DELAY SHARP ROLL-OFF

Symbol

Min.

Typ.

Max.

21.7

Unit

0.05dB

3.0dB

kHz

Passband

(Note 27)

23.4

kHz

Passband Ripple

Stopband

Stopband Attenuation (Note 30, Note 31)

(Note 28)

(Note 27)

-0.0031

0.0031

26.3

Group Delay

(Note 29)

6.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  20.0kHz

-0.3

0.1

fs=96kHz

Parameter

SHORT DELAY SHARP ROLL-OFF

Symbol

Min.

Typ.

Max.

43.5

Unit

0.05dB

3.0dB

kHz

Passband

(Note 27)

46.8

kHz

Passband Ripple

Stopband

Stopband Attenuation (Note 30, Note 31)

(Note 28)

(Note 27)

-0.0031

0.0031

52.5

Group Delay

(Note 29)

6.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  40.0kHz

-0.5

0.1

fs=192kHz

Parameter

SHORT DELAY SHARP ROLL-OFF

Symbol

Min.

Typ.

Max.

87.0

Unit

0.05dB

3.0dB

kHz

Passband

(Note 27)

93.6

kHz

Passband Ripple

Stopband

Stopband Attenuation (Note 30, Note 31)

(Note 28)

(Note 27)

-0.0031

0.0031

105

Group Delay

(Note 29)

6.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  80.0kHz

-1.9

0.1

016000391-E-01

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[AK4601]

9.4 Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”)

fs=48kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SLOW ROLL-OFF

0.05dB

3.0dB

12.0

0.05

kHz

Passband

(Note 33)

Passband Ripple

Stopband

21.1

(Note 28)

(Note 33)

-0.05

41.5

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

5.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  20.0kHz

-4.8

0.1

fs=96kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SLOW ROLL-OFF

0.05dB

3.0dB

24.2

0.05

kHz

Passband

(Note 33)

Passband Ripple

Stopband

42.1

(Note 28)

(Note 33)

-0.05

83.0

Stopband Attenuation (Note 30, Note 31)

Group Delay

(Note 29)

5.3

1/fs

Digital Filter + SCF + SMF

(Note 30)

Frequency Response: 0  40.0kHz

-5.0

0.1

fs=192kHz

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHORT DELAY SLOW ROLL-OFF

0.05dB

3.0dB

48.4

0.05

kHz

Passband

(Note 33)

Passband Ripple

Stopband

84.3

(Note 28)

(Note 33)

-0.05

165.9

Stopband Attenuation (Note 30, Note 31)

Group Delay (Note 29)

5.3

1/fs

Digital Filter + SCF + SMF (Note 30)

Frequency Response: 0  80.0kHz

-5.7

0.1

Note 33. The passband and stopband frequencies are proportional to fs (sampling rate).

“PB=0.252  fs, SB=0.864  fs”

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[AK4601]

10. DC Characteristics

■ DC Characteristics

(Ta=-40~85C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1=

DVSS2=0V)

Parameter

Symbol

VIH1

VIL1

VIH2

VIL2

Min.

80%TVDD

Typ.

Max.

20%TVDD

30%TVDD

0.3

Unit

High-Level Input Voltage 1

Low-Level Input Voltage 1

High-Level Input Voltage 2

Low-Level Input Voltage 2

High-Level Output Voltage Iout= -100A (Note 34)

Low-Level Output Voltage Iout=100A (Note 34)

Fast Mode

(Note 34)

(Note 35)

70%TVDD

TVDD-0.3

VOH1

VOL1

TVDD ≥ 2.0V (Iout=3mA)

VOL2

0.4

20%TVDD

SDA

TVDD < 2.0V (Iout=3mA)

Low Level Output

Fast Mode Plus

Voltage

TVDD ≥ 2.0V (Iout=20mA)

VOL2

Iin

0.4

20%TVDD

±10

A

TVDD < 2.0V (Iout=3mA)

Input Leak Current

(Note 36)

Note 34. CLKO, SDIN1, SDIN2, BICK2/SDIN3, SDOUT1, SDOUT2, LRCK2/SDOUT3, LRCK1, BICK1,

PDN, SCLK, SO, CSN and SI/I2CFIL pins.

Note 35. SCL and SDA pins.

Note 36. SDIN1, SDIN2, SDIN3, PDN, SCLK/SCL, SO/SDA, CSN and SI/I2CFIL pins.

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[AK4601]

11. Switching Characteristics

1. System Clock

(Ta=-40~85C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1=

DVSS2=0V; CL=20pF)

Parameter

Symbol

Min.

Typ.

Max.

Unit

MCKI Input Timing

Duty Cycle

Input Frequency

CLKO Output Timing

Duty

fCLK

0.256

24.576

MHz

Output Frequency

Duty Cycle

LRCK/BICK Input Timing (Slave Mode)

LRCK Input Timing

Frequency

fCLKO

dCLKO

2.048

24.576

MHz

192

kHz

BICK Input Timing

Frequency

Pulse Width Low

Pulse Width High

(Note 37)

fBCLK

tBCLKL

tBCLKH

0.256

0.4 / fBCLK

24.576

MHz

LRCK/BICK Output Timing (Master Mode)

LRCK Output Timing

Frequency

192

kHz

Pulse Width High

PCM Short/Long Frame

tLRCKH

1/fBCLK

I²S/DSP Mode

BICK Output Timing

Frequency

Duty

(Note 37)

fBCLK

dBCLK

0.256

24.576

MHz

Note 37. Required to meet the following expression: “fBCLK ≥ 2 x fs x (Input/Output Data Length)”

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[AK4601]

1/fCLK

VIH1

VIL1

MCKI

1/fs

VIH1

VIL1

LRCK

1/fBCLK

VIH1

VIL1

BICK

tBCLKH

tBCLKL

Figure 2. System Clock Timing

2. Power Down

(Ta=-40~85C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1=

DVSS2=0V)

Parameter

Symbol

Min.

Typ.

Max.

Unit

PDN Pulse Width

(Note 38)

tRST

600

Note 38. The PDN pin must be “L” when power up the AK4601.

PDN

tRST

VIL1

Figure 3. Reset Timing

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[AK4601]

3. Serial Data Interface (SDINx, SDOUTx)

(Ta=-40~85C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1=

DVSS2=0V; CL=20pF)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Slave Mode

Delay Time from BICK “↑” to LRCK

Delay Time from LRCK to BICK “↑”

Serial Data Input Latch Setup Time

Serial Data Input Latch Hold Time

(Note 39)

tBLRD

tLRBD

tBSIDS

tBSIDH

Delay Time from BICK“↓”to Serial Data Output

(Note 40)

Delay Time from BICK “↑”to Serial Data Output

tBSOD1

tBSOD2

(Note 39, Note 41)

Master Mode

32, 48, 64,

128, 256,

512

BICK Frequency

BICK Duty Cycle

Delay Time from BICK “↓” to LRCK

Serial Data Input Latch Setup Time

Serial Data Input Latch Hold Time

fBCLK

Duty

tMBL

tBSIDS

tBSIDH

(Note 40)

-10

Delay Time from BICK“↓”to Serial Data Output

tBSOD

(Note 40, Note 41)

Note 39. It is measured from BICK “↓” when the BICK polarity is inverted by setting BCKPx bit = “1”.

Note 40. It is measured from BICK “↑” when the BICK polarity is inverted by setting BCKPx bit = “1”.

Note 41. Set SDOPHx bit to “1” and the data from SDOUTx pin should be output based on BICK “↑”

when BICKx speed is more than 12.288MHz such as TDM512 mode with 48kHz sampling

frequency, TDM256 mode with 96kHz sampling frequency or TDM128 mode with 192kHz

sampling frequency in slave mode. SDOPHx bit must be set to “0” in master mode.

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[AK4601]

3-1. Slave Mode

VIH1

VIL1

LRCK(I)

tBLRD

tLRBD

VIH1

VIL1

BICK(I)

SDINx

tBSIDS

tBSIDH

VIH1

VIL1

Figure 4. Serial Interface Input Timing in Slave Mode

VIH1

VIL1

LRCK(I)

BICK(I)

tBLRD

tLRBD

VIH1

VIL1

tBSOD1

50%TVDD

SDOUTx

Figure 5. Serial Interface Output Timing in Slave Mode (SDOPHx bit = “0”)

VIH1

VIL1

LRCK(I)

BICK(I)

tBLRD

tLRBD

VIH1

VIL1

tBSOD2

50%TVDD

SDOUTx

Figure 6. Serial Interface Output Timing in Slave Mode (SDOPHx bit = “1”)

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[AK4601]

3-2. Master Mode

50%TVDD

LRCK(O)

tMBL

50%TVDD

BICK(O)

SDINx

tBSIDS

tBSIDH

VIH1

VIL1

Figure 7. Serial Interface Input Timing in Master Mode

50%TVDD

LRCK(O)

BICK(O)

SDOUTx

50%TVDD

tBSOD

Figure 8. Serial Interface Output Timing in Master Mode

4. SPI Interface

(Ta=-40~85C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1=

DVSS2=0V; CL=20pF)

Parameter

Symbol

Min.

Typ.

Max.

Unit

μP Interface Signal

SCLK Frequency

fSCLK

tSCLKL

tSCLKH

MHz

SCLK Low-level Width

SCLK High-level Width

Microcontroller → AK4601

CSN High-level Width

From CSN “↑” to PDN “↑”

From PDN “↑” to CSN “↓”

From CSN “↓” to SCLK “↓”

From SCLK “↑” to CSN “↑”

SI Latch Setup Time

tWRQH

tRST

tIRRQ

tWSC

tSCW

tSIS

150

180

150

240

SI Latch Hold Time

tSIH

AK4601 → Microcontroller

Delay Time from SCLK “↓” to SO Output

tSOS

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[AK4601]

VIH1

VIL1

SCLK

tSCLKL

1/fSCLK

tSCLKH

1/fSCLK

VIH1

PDN

CSN

VIL1

VIH1

VIL1

tRST

tIRRQ

Figure 9. SPI Interface Timing1

VIH1

VIL1

tWRQH

CSN

VIH1

VIL1

tSIS

tSIH

VIH1

VIL1

SCLK

tWSC

tSCW

tWSC

tSCW

Figure 10. SPI Interface Timing 2 (Microcontroller→ AK4601)

VIH2

SCLK

VIL2

VIH2

VIL2

tSOH

tSOS

Figure 11. SPI Interface Timing 3 (AK4601 → Microcontroller)

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5. I²C Interface

(Ta=-40~85C; AVDD=VREFH=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=VREFL=DVSS1

=DVSS2=0V)

<I²C: Fast Mode>

Parameter

Symbol

Min.

Typ.

Max.

Unit

I²C Timing

SCL clock frequency

fSCL

tBUF

400

kHz

s

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first Clock pulse)

Clock Low Time

1.3

0.6

1.3

0.6

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise Suppressed By Input Filter

Capacitive load on bus

0.1

0.3

tSU:STO

tSP

0.6

400

<I²C: Fast Mode Plus>

Parameter

Symbol

Min.

Typ.

Max.

Unit

I²C Timing

SCL clock frequency

fSCL

tBUF

MHz

s

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first Clock pulse)

Clock Low Time

0.5

0.26

0.5

0.26

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise Suppressed By Input Filter

Capacitive load on bus

0.05

0.12

tSU:STO

tSP

0.26

550

VIH2

SDA

VIL2

tLOW tR

tHIGH

tBUF

tSP

VIH2

VIL2

SCL

tHD:STA

Stop Start

tHD:DAT

tSU:DAT tSU:STA

Start

tSU:STO

Stop

Figure 12. I²C BUS Interface Timing

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[AK4601]

12. Functional Descriptions

■ System Clock

1. Clock Mode

The AK4601 has a PLL circuit to generate an internal operation clock. An input pin for the PLL reference

clock is selected by REFSEL[2:0] bits (Table 4). REFMODE[4:0] bits set the frequency of the reference

clock (Table 5). A reference clock input pin and the reference clock frequency must be changed during

clock reset.

REFSEL[2:0] bits

Reference Clock

MCKI pin

BICK1 pin

BICK2 pin

N/A

000

001

010

(default)

Others

Table 4. PLL Reference Clock Frequency Setting

Input Frequency (kHz)

48kHz base 44.1kHz base

256 235.2

REFMODE[4:0]

bits

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

Others

(default)

384

512

352.8

470.4

768

705.6

1,024

1,152

1,536

2,048

2,304

3,072

4,096

4,608

6,144

8,192

9,216

12,288

18,432

24,576

N/A

940.8

1,058.4

1,411.2

1,881.6

2,116.8

2,822.4

3,763.2

4,233.6

5,644.8

7,526.4

8,467.2

11,289.6

16,934.4

22,579.2

N/A

Table 5. Reference Clock Frequency Setting

The PLL block multiplies a input clock which is set by REFMODE[4:0] bits directly and generates a

122.88MHz/112.896MHz master clock (PLL_MCLK) for internal operation (Table 6).

48kHz base 44.1kHz base

122.88MHz 112.896MHz

Master Clock

(PLL_MCLK)

Table 6. Internal Operation Master Clock

A stable BICK is required when using clock input from BICKx (x=1~2) pin as reference clock. A clock

with two different frequencies cannot be used. The MCKI pin must be put to “L” (DVSS1) if the system

does not need the MCKI pin.

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[AK4601]

2. Audio HUB

2-1 Audio HUB

Audio HUB provides simultaneous data transmitting and flexible path configuration for various audio

sources by setting sample rate converters, Input/Output port that supports TDM mode and registers.

Therefore the AK4601 is able to support to various use cases of car-audio systems.

Figure 13 shows an example of when using audio play-back and hands-free talk at the same time in a

car audio system.

With the AK7707, AKM’s multi-core DSP, the AK4601 realizes simultaneous processing of data in

different sampling rates such as microphone input ADC data and Radio tuner audio data.

Figure 13. Audio HUB Example

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2-2. Clock Sync Domain

The AK4601 has two Clock Sync Domains (SD1-2). Reference clocks (LRCKSDx, BICKSDx, x=1~2)are

output according to each register settings for SD1-2 (Figure 14). The internal audio data and input/output

data of the AK4601 must be synchronized with one of these two Clock Sync Domains.

When MSNx bit =“0”, input pins (LRCKx pin/BICKx pin) are selected for the clock sync reference clock.

When MSNx bit = “1”, internal dividing clocks (MLRCKx/MBICKx) are selected for the clock sync

reference clock (Table 7).

MSNx bit

Reference Clock (LRCKSDx/BICKSDx)

Input Pin (LRCKx pin/BICKx pin)

Internal Dividing Clock (MLRCKx/MBICKx)

Reference clock is generated internally by

CKSx[2:0], BDVx[8:0] and SDVx[2:0] bits settings.

Table 7. Reference Clock of Clock Sync Domain

BICK1 pin

LRCK1 pin

BICK_SD1

LRCK_SD1

PLL_MCLK

MCKI

CKS1[2:0]

MBICK1

DIV

BICK1~2

BDV1[8:0]

MSN1

MLRCK1

DIV

SDV1[2:0]

BICK2 pin

LRCK2 pin

BICK_SD2

LRCK_SD2

CKS2[2:0]

BDV2[8:0]

SDV2[2:0]

MSN2

Figure 14. Clock Sync Domain

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[AK4601]

The clock source of Internal dividing clock MBICKx is selected by CKSx[2:0] bits (Table 8). MBICKx is

generated by dividing the selected clock source according to the BDVx[8:0] bits setting (Table 9).

Additionally, MLRCKx is generated by dividing this MBICKx by setting SDVx[2:0] bits (Table 8).

CKSx[2:0] bits

000

Clock Source

TieLow

PLL MCLK

MCKI

(default)

001

010

011

BICK1

100

BICK2

Others

N/A

Table 8. Clock Source of Internal Dividing Clock

BDVx[8:0] bits

0x00

0x01 – 0xFF

Divide by

BDVx+1

(default)

Table 9. MBICKx Setting

SDVx[2:0] bits

Divide by

000

001

010

011

100

101

110

111

128

256

N/A

512

Table 10. MLRCKx Setting (N/A: Not available)

Clock Sync Domain settings when PLL MCLK is selected as the clock source are shown in Table 11.

PLL MCLK = 122.88MHz (48kHz base) / 112.896MHz (44.1kHz base)

MBICKx = PLL MCLK dvided by BDVx[8:0] bits setting

MLRCKx = MBICKx divided by SDVx[2:0] bits setting

e.g.) MBICKx= 122.88MHz/240= 0.512MHz, MLRCKx= 0.512MHz/64= 8kHz when PLL_MCLK =

122.88MHz (fs=48kHz), BDVx[8:0] bits= “0xEF”(divide by 240) and SDVx[2:0] bits = “000” (divide

by 64).

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When PLL_MCLK is selected as the clock source, frequency settings other than shown in Table 11 are

not available.

MLRCKx(kHz)

48kHz 44.1kHz

MBICKx(MHz)

SDVx[2:0]

bits

Dividing

BDVx[8:0] BDVx[8:0] bits

SDVx[2:0]

bits

Dividing

48kHz

base

44.1kHz

base

0.2352

0.3528

0.4704

0.9408

1.8816

3.7632

0.3528

0.7056

1.4112

2.8224

5.6448

0.4704

0.7056

0.9408

1.8816

3.7632

7.5264

0.7056

1.4112

2.8224

5.6448

11.2896

0.9408

1.4112

1.8816

3.7632

7.5264

1.4112

2.8224

5.6448

11.2896

22.5792

2.8224

5.6448

11.2896

22.5792

5.6448

11.2896

22.5792

0x1DF

0x13F

0x0EF

0x077

0x03B

0x01D

0x13F

0x09F

0x04F

0x027

0x013

0x0EF

0x09F

0x077

0x03B

0x01D

0x00E

0x09F

0x04F

0x027

0x013

0x009

0x077

0x04F

0x03B

0x01D

0x00E

0x04F

0x027

0x013

0x009

0x004

0x027

0x013

0x009

0x004

0x013

0x009

0x004

480

320

240

120

0.256

010

001

000

011

100

111

010

000

011

100

111

010

001

000

011

100

111

010

000

011

100

111

010

001

000

011

100

010

000

011

100

111

010

000

011

100

010

000

011

128

256

512

0.384

0.512

1.024

2.048

4.096

0.384

0.768

1.536

3.072

6.144

0.512

0.768

1.024

2.048

4.096

8.192

0.768

1.536

3.072

6.144

12.288

1.024

1.536

2.048

4.096

8.192

1.536

3.072

6.144

12.288

24.576

3.072

6.144

12.288

24.576

6.144

12.288

24.576

320

160

240

160

120

160

120

11.025

14.7

22.050

29.4

44.1

88.2

176.4

192

128

256

512

128

256

512

128

256

512

128

256

128

256

512

128

256

128

Table 11. Clock Sync Domain Setting when PLL MCLK is Clock Source

For Clock Sync Domain, set BDVx[8:0] bits and SDVx[2:0] bits according to the input clock frequency

when the MCKI or BICK pin input is selected as the clock source, as well as the PLL MCLK.

MBICKx= MCKI pin or BICKx pin frequency divided by BDVx[8:0] bits setting

MLRCKx= MBICKx divided by SDVx[2:0] bits setting

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[AK4601]

2-3. Sampling Frequency Setting of ADC, DAC Blocks

The ADC, DAC blocks of the AK4601 are operated by a master clock generated by dividing PLL MCLK.

Sampling frequencies of the ADC1, and the ADC2, ADCM, DAC1, DAC2 and DAC3 (hereinafter called

CODEC) are set by FSMODE[4:0] bits (Table 12).

FSMODE[4:0]

bits

ADC2, ADCM

DAC1, DAC2, DAC3

Mode

ADC1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

8kHz

12kHz

16kHz

24kHz

32kHz

48kHz

96kHz

192kHz

8kHz

12kHz

16kHz

24kHz

32kHz

16kHz

8kHz

48kHz

24kHz

16kHz

8kHz

96kHz

48kHz

32kHz

24kHz

16kHz

8kHz

192kHz

96kHz

48kHz

32kHz

16kHz

(default)

Table 12. Sampling Frequency Settings of Internal Blocks (fs=48kHz base)

Clock Sync Domain of the ADC1 (SDADC1) is selected by SDADC1[2:0] bits and Clock Sync Domain of

the CODEC (SDCODEC) is selected by SDCODEC[2:0] bits (Figure 20). SDADC1 and SDCODEC must

be synchronized with PLL MCLK. The sampling frequency of LRCK SDx for SDADC1 and the sampling

frequency of the ADC1 should be the same. The sampling frequency of LRCK SDx for SDCODEC and

the sampling frequency of the CODEC should also be the same.

Set SDADC1[2:0] bits = “000” (Reference Clocks are Low) when not using the ADC1. In the same

manner, SDCODEC[2:0] bits must be set to “000” (Reference Clocks are Low) when not using the

CODEC.

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[AK4601]

e.g.) Input pin is selected for PLL Reference Clock.

• PLL Setting

REFSEL[2:0] bits = “010” (PLL Reference Clock is set to BICK2 pin=3.072MHz)

• Clock Sync Domain Setting

SDADC1[2:0] bits = “001”, SDCODEC[2:0] bits = “002”, MSN1 bit = MSN2 bit = “0”,

BICK_SD1 = BICK1 pin = 64fs (0.512MHz), LRCK_SD1 = LRCK1 pin = 8kHz

BICK_SD2 = BICK2 pin = 64fs (3.072MHz),LRCK_SD2 = LRCK2 pin = 48kHz

• ADC1 and CODEC Setting

FSMODE[4:0] bits=” 01010” (Set fs = 8kHz for ADC1, Set CODEC, fs = 48kHz)

BICK2 pin=3.072MHz

PLL_MCLK=122.88MHz

PLL

BICK1 pin(64fs)

LRCK1 pin(fs=8kHz)

Divide

BICK_SD1(64fs)

LRCK_SD1(fs=8kHz)

MBICK1

MLRCK1

Internal Dividing Clock

MSN1=”0”

ADC1

fs=8kHz FSMODE1[4:0] bits=”01010”

DATA BUS

fs=8kHz

BICK2 pin(64fs)

LRCK2 pin(fs=48kHz)

Divide

BICK_SD2(64fs)

LRCK_SD2(fs=48kHz)

MBICK2

MLRCK2

Internal Dividing Clock

MSN2=”0”

ADC2,M

DAC1-3

ADC2,M

DAC1-3

FSMODE[4:0] bits=”01010”

fs=48kHz

DATA BUS

Figure 15. ADC, DAC Setting Example (MSNx bit = “0”: Input pin is selected as PLL Reference Clock)

Note 42. BICK1/LRCK1 and BICK2/LRCK2 must be synchronized.

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e.g.) Internal Dividing Clock is Selected as PLL Reference Clock

• PLL Setting

REFSEL[2:0] bits = “000” (PLL Reference Clock is MCKI pin = 3.072MHz), PLL MCLK = 122.88MHz

• Clock Sync Domain Setting

SDADC[2:0] bits = “001”, SDCODEC[2:0] bits = “002”, MSN1 bit = MSN2 bit = “1”,

CKS1[2:0] = “001” (PLL MCLK is set as the reference clock of Clock Sync Domain 1)

BDV1[8:0] = “0x0EF” (BICK SD1 = MBICK1 = 122.88MHz/240 = 0.512MHz)

SDV1[2:0] = “000” (LRCK SD1 = MLRCK1 = 0.512MHz/64 = 8kHz)

CKS2[2:0] = “001” (PLL MCLK is set as the reference clock of Clock Sync Domain 2)

BDV2[8:0] = “0x027” (BICK SD2 = MBICK2 = 122.88MHz/40 = 3.072MHz)

SDV2[2:0] = “000” (LRCK SD2 = MLRCK2 = 3.072MHz/64 = 48kHz)

• ADC1 and CODEC Setting

FSMODE[4:0] bits= “01010” (Set fs = 8kHz for ADC1, Set CODEC, fs = 48kHz)

MCKI pin=3.072MHz

PLL_MCLK=122.88MHz

PLL

BICK1 pin(64fs)

LRCK1 pin(fs=8kHz)

Divide

BICK_SD1(64fs)

LRCK_SD1(fs=8kHz)

MBICK1(64fs)

MLRCK1(fs=8kHz)

Internal Dividing Clock

MSN1=”1”

ADC1

fs=8kHz

FSMODE[4:0] bits=”01010”

DATA BUS

fs=8kHz

BICK2 pin(64fs)

LRCK2 pin(fs=48kHz)

Divide

BICK_SD2(64fs)

LRCK_SD2(fs=48kHz)

MBICK2(64fs)

MLRCK2(fs=48kHz)

Internal Dividing Clock

MSN2=”1”

ADC2,M

DAC1-3

ADC2,M

DAC1-3

FSMODE[4:0] bits=”01010”

fs=48kHz

DATA BUS

Figure 16. ADC, DAC, Setting Example

(MSNx bit = “1”: Internal Dividing Clock is Selected as PLL Reference Clock)

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2-4. CLKO Pin Output Clock

The CLKO pin of the AK4601 outputs a divided clock of PLL MCLK. The output frequency setting of the

CLKO pin is controlled by CLKOSEL[2:0] bits (Table 13).

CLKOSEL[2:0]

bits

Output Frequency

(fs=48kHz base)

Output Frequency

(fs=44.1kHz base)

000

001

010

011

100

101

12.288MHz

24.576MHz

8.192MHz

6.144MHz

4.096MHz

2.048MHz

11.2896MHz

22.5792MHz

7.5264MHz

5.6448MHz

3.7632MHz

1.8816MHz

(default)

Table 13. CLKO Pin Setting

2-5. BICK2/SDIN3 pin and LRCK2/SDOUT3 pin Settings

Pin functions of the BICK2/SDIN3 pin and the LRCK2/SDOUT3 pin are selected by MSELN bit. When

MSELN bit is “0”, the BICK2/SDIN3 pin works as the BICK2 pin and the LRCK2/SDOUT3 pin works as

the LRCK2 pin. When MSELN bit is “1”, the BICK2/SDIN3 pin works as the SDIN3 pin and the

LRCK2/SDOUT3 pin works as the SDOUT3 pin.

MSELN bit

Function

BICK2

SDIN3

(default)

Table 14. BICK2/SDIN3 Pin Setting 1

2-6. SDINx/BICKx/LRCKx Pin Setting

The AK4601 has three SDIN pins and two BICK/LRCK pins. They are independent each other.

Synchronized channel of the SDINx pin can be selected by EXBCKx[2:0] bits from BICKx pin and

LRCKx pin (Table 15).

BICK and LRCK pins that

EXBCKx[2:0] bits

synchronizes to SDINx pin

000

001

010

011

100

101

110

111

TieLow

BICK1 pin, LRCK1 pin

BICK2 pin, LRCK2 pin

(default)

N/A

Table 15. BICKx/LRCKx pin Setting for Synchronization to SDINx pin

MSNx bit selects Master/Slave mode of the BICKx pin and the LRCKx pin. (Table 16)

MSNx bit

BICKx pin, LRCKx pin

Slave Mode (Input)

Master Mode (Output)

(default)

Table 16. BICKx pin/LRCKx pin Mode Select

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Note 43. Set MSNx bit to “0” when using the BICKx pin as PLL reference clock input pin.

When MSELN bit = “1”, the BICK2/SDIN3 pin works as SDIN3 (Input) even setting MSN2 bit to “1”, and

the LRCK2/SDOUT3 pin works as SDOUT3 (Output) even setting MSN2 bit to “0”.

MSELN bit MSN2 bit

Function

BICK2 (Slave mode, Input) LRCK2 (Slave mode, Input)

BICK2 (Master mode, Output) LRCK2 (Master mode, Output)

(default)

SDIN3 (Input) SDOUT3 (Output)

Table 17. BICK2/SDIN3 Pin Setting 2

When BICKx/LRCKx (x=1~2) pin is set to Slave mode, the reference clock of Clock Sync Domain x is the

BICKx/LRCKx pin (Table 7).When BICKx/LRCKx pin is set to Master mode, the output clock of the

BICKx/LRCKx pin can be selected from two Sync Domains by SDBCKx[2:0] bits (x= 1~2). (Table 18)

MSNx bit SDBCKx[2:0] bits

BICKx pin/LRCKx pin

TieLow

BICK SD1, LRCK SD1

BICK SD2, LRCK SD2

000

001

010

011

100

101

110

111

xxx

N/A

Input

(default)

Table 18. Clock Sync Domain Setting of BICKx/LRCKx Pin

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■ Data Path Setting

1. Data Bus, In/Output Port

The AK4601 has a 32-bit serial audio stereo data bus (Figure 17). Inputs and outputs of each internal

block and all input/output pins of the AK4601 are connected to this serial audio data bus. The port that

data is input to this serial audio data bus is defined as “input port” and the port that data is output from

the audio data bus is defined as “output port”. Each port selects Clock Sync Domain and inputs (outputs)

audio data that synchronized to the reference clock of the Clock Sync domain to the data bus (Figure

17).

A stereo data on each port is defined as “data source”. All data sources are connected to the serial audio

bus and a data source on any input port can be output from any output port. Data connection of the data

bus and a data port with the same sampling frequency is defined as “data path”. Input and output ports

on the same data path should have the same Clock Sync Domain. If these ports have different Clock

Sync Domains, reference clocks (BICK SDx, LRCK SDx) must be synchronized and the sampling

frequency must be the same. Phase synchronization of reference clocks is not necessary if the

frequency of these clocks are synchronized. However, frequencies of BICK SDx can be different.

An SRC is necessary for data transmission between two ports that have clock sync domain with different

sampling frequencies or different reference clocks.

: Input Port

SDIN1

SDIN2

SDIN3

: Output Port

: Sync free

SDIN1pin

SDIN2pin

SDIN3pin

ADC1

ADC2

ADCM

ADC1

ADC2

ADCM

SDOUT1

SDOUT2

SDOUT3

SDOUT1pin

SDOUT2pin

SDOUT3pin

MIXAI1

MIXAI2

MIXAO

MIXER A

MIXER B

MIXBI1

MIXBI2

MIXBO

VOLI1

VOL1

VOL2

VOL3

DAC1

DAC2

DAC3

VOLO1

DAC1

DAC2

DAC3

VOLI2

VOLO2

VOLI3

VOLO3

“0” data

0x0000 0000

Data Bus

Figure 17. Data Path, Input/Output Port

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1-1. Data BUS Group Delay

2*(1/fs) group delay occurs in total as audio data will have group delay of 1*(1/fs) at each input and

output port of the data bus that have the same sync domain. Therefore, this group delay will increase as

the number of times that the data go through the data path increases.

2. Clock Sync Domain Setting for Input/Output Port

Domain numbers are assigned to each Clock Sync Domain (Table 19). Each input/output port has

setting registers for Clock Sync Domain (Figure 20).

Set a domain number to clock sync domain setting registers for each input/output port. (Table 20, Table

21)

Domain Number Clock Sync Domain

0x0

0x1

0x2

Reference Clocks are Low

SD1 (BICK SD1, LRCK SD1)

SD2 (BICK SD2, LRCK SD2)

(default)

Table 19. Clock Sync Domain Number

If the output port sync domain setting is in auto mode, an audio data port inherits the sync domain of the

input data.

Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[2:0] bits, MSN bit and

SDBCKx[2:0] bits (Table 15, Table 16, Table 18).

e.g.)

SD2 are selected for Clock Sync Domain of the SDIN2 pin when EXBCK2[2:0] bits = “010” and MSN2 bit

=“0” (Figure 18).

Figure 18. Clock Sync Domain Setting Example1 of SDINx Pin

e.g.)

SD2 are selected for Clock Sync Domain of the SDIN1 pin when EXBCK1[2:0] bits = “001”, MSN1 bit

=“1” and SDBCK1[2:0] bits = “010” (Figure 19).

Figure 19. Clock Sync Domain Setting Example2 of SDINx Pin

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Figure 20. Clock Sync Domain Setting of Input/Output Port

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2. Source Address, Source Selecting Registers

A source address is assigned to each input port source (Table 20). The output port source can be

selected by setting a source address of input port to the registers. Data on the data bus can be selected

freely by this source address. In TDM mode, arbitrary 2 channels audio data can be output from two

selected SDOUTx pins (Table 21).

Source

Address Name

Source

Clock Sync Domain

Setting Register (Table 19)

Source Contents

Input Port

ALL0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x10

0x11

0x12

0x15

0x16

0x17

0x18

0x19

Others

ALL0

0x0000 0000 fixed

SDIN1A

SDIN1B

SDIN1C

SDIN1D

SDIN1E

SDIN1F

SDIN1 Slot1, 2 Input

SDIN1 Slot3, 4 Input

SDIN1 Slot5, 6 Input

SDIN1 Slot7, 8 Input

SDIN1 Slot9, 10 Input

SDIN1 Slot11, 12 Input

SDIN1

Note 44

SDIN1G SDIN1 Slot13, 14 Input

SDIN1H

SDIN2

SDIN3

VOLO1

VOLO2

VOLO3

ADC1

SDIN1 Slot15, 16 Input

SDIN2 Input

SDIN3 Input

VOL1 Output

VOL2 Output

VOL3 Output

ADC1 Output

ADC2 Output

ADCM Output

Mixer A Output

Mixer B Output

N/A

SDIN2

SDIN3

VOLO1

VOLO2

VOLO3

ADC1

Note 44

SDVOL1[2:0]

SDVOL2[2:0]

SDVOL3[2:0]

SDADC1[2:0]

ADC2

CODEC

SDCODEC[2:0]

ADCM

Mixer A

Mixer B

N/A

Mixer A

Mixer B

N/A

SDMIXA[2:0]

SDMIXB[2:0]

N/A

(N/A: Not Available)

Table 20. Clock Sync Domain Setting for Source Address and Input Port

Note 44. Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[2:0] bits,

MSNx bit and SDBCKx[2:0] bits (Table 15, Table 16, Table 18).

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Set a source address of input data by independent setting registers for each block if each block is

obtaining data from the data bus.

If the output port sync domain setting is in auto mode, this register setting for source address is not

necessary since an audio data port inherits the sync domain of the input data.

Clock Sync Domain

Source Select

Contents

Output Port Setting Register

(Table 19)

Registers

SELDO1A[5:0]

SELDO1B[5:0]

SELDO1C[5:0]

SELDO1D[5:0]

SELDO1E[5:0]

SELDO1F[5:0]

SELDO1G[5:0]

SELDO1H[5:0]

SELDO2[5:0]

SELDO3[5:0]

SELDA1[5:0]

SDOUT1 Slot1, Slot2

SDOUT1 Slot3, Slot4

SDOUT1 Slot5, Slot6

SDOUT1 Slot7, Slot8

SDOUT1 Slot9, Slot10

SDOUT1 Slot11, Slot12

SDOUT1 Slot13, Slot14

SDOUT1 Slot15, Slot16

SDOUT2 Slot1, Slot2

SDOUT3 Slot1, Slot2

DAC1 Input

SDOUT1

SDDO1[2:0]

SDOUT2

SDOUT3

DAC1

SDDO2[2:0]

SDDO3[2:0]

SELDA2[5:0]

DAC2 Input

DAC2

SDCODEC[2:0]

SELDA3[5:0]

DAC3 Input

DAC3

SELVOL1[5:0]

SELVOL2[5:0]

SELVOL3[5:0]

SELMIXAI1[5:0]

SELMIXAI2[5:0]

SELMIXBI1[5:0]

SELMIXBI2[5:0]

VOL1 Input

VOL2 Input

VOL3 Input

MixerA Input1

MixerA Input2

MixerB Input1

MixerB Input2

VOLI1

VOLI2

VOLI3

MixerAI1

MixerAI2

MixerBI1

(Auto)

Table 21. Clock Sync Domain Settings for Source Select Registers and Output Port

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3. Input/Output Serial Interface Format

3-1. Data Clocks

The AK4601 has two independent BICK/LRCK pins that are able to switch master and slave mode.

MSNx bit selects Master/Slave mode of the BICKx pin and the LRCKx pin (Table 16). Clock format of

LRCKx/BICKx pins can be selected by DCFx[2:0] bits. If a BICK/LRCK pins are master mode, desirable

clock format is output according to DCFx[2:0] bits setting (Table 22). If a BICK/LRCK pins are slave

mode, set DCFx[2:0] bits according to the input clock format.

Mode

DCFx[2]

DCFx[1]

DCFx[0]

Clock Format

I²S Mode

(default)

DSP Mode

PCM Short Frame

PCM Long Frame

Table 22. AK4601 Data Clock Format

Clock edge relationship can be controlled by BCKPx bit.

BCKPx bit

BICKx Edge Referenced to LRCKx Start Edge

Falling Edeg (FE)

Rising Edge (RE)

(default)

Table 23. Clock Edge Relationship between BICKx and LRCKx

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LRCKx

BICKx

Lch

Rch

Figure 21. I²S Mode

LRCKx

BICKx

Lch

Rch

Figure 22. DSP Mode

LRCKx

BICKx

Lch + Rch

Figure 23. PCM Short Frame / PCM Long Frame (BCKPx bit = “0”)

LRCKx

BICKx

Lch + Rch

Figure 24. PCM Short Frame / PCM Long Frame (BCKPx bit = “1”)

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3-2. Data Definitions

A serial bit stream that is sent or received by the AK4601 is a digital signal composed of slot, word and

bit data.

Bit:

It is a smallest component in a serial data stream. The bit duration is one serial clock cycle.

Word: It is a group of multiple bits that composes transmitting data between external devices and the

AK4601. Figure 25 shows an example of a word consists of eight bits.

Slot:

It is composed of a word and adequate additional bits for interfacing to an external device. In

Figure 25, the audio data is an 8-bit valid data and a 12-bit slot needs additional four zeros to

satisfy an interface protocol of the external device.

If the word length is shorter than the slot length, the data alignment of the word will be the

beginning of the slot (MSB justified) or end of the slot (LSB justified). Figure 25 shows an

example of MSB justified format. The slot length must be longer than the word length.

Bit

Word

Slot

Figure 25. Bit and Word Slot Definition

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5-3. Input/ Output Interface Format

The AK4601 has three digital input ports (SDIN1~SDIN3) and three digital output ports (SDOUT1~

SDOUT3). The input data format is determined by a combination of DISLx[1:0], DIEDGENx, DILSBEx

and DIDLx[1:0] bits settings (x=1~3). The output data format is determined by a of DOSLx[1:0],

DOEDGENx, DOLSBEx and DODLx[1:0] bits settings (x=1~3).

DISLx[1:0] bits / DOSLx[1:0] bits (x=1~3) control input/output data slot length.

DISLx[1] bit

DOSLx[1] bit

DISLx[0] bit

DOSLx[0] bit

Slot Length

24bit

20bit

16bit

32bit

(default)

Table 24. Slot Length Setting of Input/Output Data

DIDLx[1:0] bits / DODLx[1:0] bits (x=1~3) control input/output audio data word length.

DIDLx[1] bit

DODLx[1] bit DODLx[0] bit

DIDLx[0] bit

Word Length

24bit

20bit

16bit

32bit

(default)

Table 25. Word Length Setting of Input/Output Audio Data

DILSBEx bit/ DOLSBEx bit (x=1~3) selects the audio data format of a slot.

DILSBEx bit

DOLSBEx bit

Slot Data Format

MSB First

LSB First

(default)

Table 26. Slot Data Format Setting

DIEDGENx bit / DOEDGENx bit (x=1~3) select data transmission start timing of the data after second channel

DIEDGENx bit

Start Timing

DOEDGENx bit

LRCK Edge Basis

Slot Length Basis

(default)

Table 27. Data Transmission Start Timing of The Data After Second Channel

If the data transmitting timing is set to Slot length basis, the next channel’s data is transmitted

immediately without waiting a LRCK edge after transmitted one slot data (Figure 29 ~ Figure 32).

If the data transmitting timing is set to LRCK edge basis, the next channel’s data will not be transmitted

until a LRCK edge even finished transmitting one slot data (Figure 26 ~ Figure 28).

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5-4. Stereo Mode

AK4601 supports stereo mode. BICK x pin should be set to arbitrary frequency more than word length x

2fs when DIEDGENx bit = “0”. BICK x pin should be set to arbitrary frequency more than slot length x 2fs

when DIEDGENx bit = “1”. BICK clock is supported up to 24.576MHz.

The SDINx input pins of the AK4601 support stereo input mode. Two slots data input is available for

each pin. A source address is assigned to each SDINx input pins when using stereo input mode. (Table

20). DISLx[1:0] bits control input data slot length of the SDINx pin. DIDLx[1:0] bits control the input data

word length of the SDINx pin. The slot data format is set by DILSBEx bit.

In stereo mode, DIEDGENx bit must be set to “0” when the data transmission timing of second channel

are LRCK edge basis. DISLx[1:0] bits setting are ignored when DIEDGENx bit = “0”.

The SDOUTx output pins of the AK4601 support stereo output mode. Two slots data output is available

for each pin. Each slot data can be assigned by setting SELDOxA-H[5:0] bits. DOSLx[1:0] bits control

output data slot length of the SDOUTx pin. DODLx[1:0] bits control the output data word length of the

SDOUTx pin. The slot data format is set by DOLSBEx bit.

In stereo mode, DOEDGENx bit must be set to “0” when the data transmission timing of second channel

are LRCK edge basis. DOSLx[1:0] bits setting are ignored when DIEDGENx bit = “0”.

Setting example of stereo mode is shown in Table 28.

DILSBEx

DIEDGENx

DISLx[1:0]

DIDLx[1:0]

Mode

Data Format

DCFx[2:0]

DOLSBEx DOEDGENx DOSLx[1:0] DODLx[1:0]

I²S Compatible

MSB Justified

000

101

110

111

000

Word Length

LSB Justified

PCM Short Frame

PCM Long Frame

Irregular I²S

Slot Length Word Length

Slot Length

Word Length

Table 28. Input/Output Data Format Setting Example (x: Do Not Care)

5-4-1. Mode 0: I²S Compatible Format

LRCKx

Lch

Rch

BICKx

SDINx

Lch Data (MSB First)

Don’t Care

Rch Data (MSB First)

Don’t Care

SDOUTx

Figure 26. I²S Compatible Format

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5-4-2. Mode 1: MSB Justified Format

LRCKx

BICKx

Lch

Rch

SDINx

Rch Data (MSB First)

Lch Data (MSB First)

Don’t Care

SDOUTx

Figure 27. MSB Justified Format

5-4-3. Mode 2: LSB Justified

LRCKx

BICKx

Lch

Rch

SDINx

Don’t Care

Rch Data (MSB First)

Don’t Care

Lch Data (MSB First)

SDOUTx

Lch Data (MSB First)

Figure 28. LSB Justified Format

5-4-4. Mode 3: PCM Short Frame Format

tBCLK

LRCKx

BICKx

SDINx

Lch Data (MSB First)

Rch Data (MSB First)

Don’t Care

SDOUTx

Lch Data (MSB First)

tBCLK x BitWidth

tBCLK x 2 x BitWidth

Figure 29. PCM Short Frame Format (BCKPx bit = “0”)

tBCLK

LRCKx

BICKx

SDINx

Lch Data (MSB First)

Rch Data (MSB First)

Don’t Care

SDOUTx

Lch Data (MSB First)

tBCLK x BitWidth

tBCLK x 2 x BitWidth

Figure 30. PCM Short Frame Format (BCKPx bit = “1”)

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5-4-5. Mode 4: PCM Long Frame Format

tBCLK

LRCKx(Master)

LRCKx(Slave)

BICKx

Don’t Care

SDINx

Lch Data (MSB First)

Rch Data (MSB First)

Don’t Care

SDOUTx

Lch Data (MSB First)

tBCLK x BitWidth

Figure 31. PCM Long Frame Format (BCKPx bit = “0”)

tBCLK

LRCKx(Master)

LRCKx(Slave)

BICKx

Don’t Care

SDINx

Lch Data (MSB First)

Rch Data (MSB First)

Don’t Care

SDOUTx

Lch Data (MSB First)

tBCLK x BitWidth

Figure 32. PCM Long Frame Format (BCKPx bit = “1”)

5-4-6. Mode 5: Irregular I²S Format

LRCKx

BICKx

Lch

Rch

SDINx

Rch Data (MSB First)

Lch Data (MSB First)

Don’t Care

SDOUTx

Lch Data (MSB First)

Figure 33. Irregular I²S Format

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5-5. TDM Mode

AK4601 supports TDM mode. BICK clock for data input/output should be set to 128fs, 192fs, 256fs or

512fs when using TDM mode. Up to 192kHz in 128fs mode (max. fs=128kHz in 192 mode, max.

fs=96kHz in 256 mode, max. fs=48kHz in 512 mode) sampling frequency is supported.

The SDIN1 input pin of the AK4601 support TDM mode. Sixteen slots data input is available at a

maximum. A source address is assigned to each 2 slot of SDIN1 input pin when using TDM mode.

(Table 20). DISL1[1:0] bits control input data slot length of the SDIN1 pin. DIDL1 [1:0] bits control the

input data word length of the SDIN1 pin. The slot data format is set by DILSBE1 bit.

In TDM mode, DIEDGEN1 bit must be set to “1” since the data transmission timing after second channel

are slot length basis. Slot length, word length and slot data format of each input data slot should be the

same setting.

The SDOUT1 output pins of the AK4601 support TDM mode. Sixteen slots data output is available for

each pin at a maximum. Each slot data can be assigned independently by setting SELDO1A-H[5:0] bits

in every two slots. DOSL1[1:0] bits control output data slot length of the SDOUT1 pin. DODL1[1:0] bits

control the output data word length of the SDOUT1 pin. The slot data format is set by DOLSBE1 bit. In

TDM mode, DOEDGEN1 bit must be set to “1” since the data transmission timing after second channel

are slot length basis. Slot length, word length and slot data format of each input data slot should be the

same setting.

Setting example of TDM mode is shown in Table 29.

DILSBE1 DIEDGEN1 DISL1 [1:0]

DOLSBE1 DOEDGEN1 DOSL1[1:0]

DIDL1 [1:0]

DODL1[1:0]

Mode

Data Format

DCF1[2:0]

I²S Compatible

MSB Justified

000

101

110

111

000

11 (32bit)

Word Length

LSB Justified

PCM Short Frame

PCM Long Frame

Irregular I²S

Slot Length Word Length

Slot Length

Word Length

Table 29. TDM Mode Setting Example

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5-5-1. I²S Compatible Format

512BICK

LRCKx

BICKx

32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK

SDIN1/SDOUT1

SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 SLOT8 SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

Figure 34. TDM Mode I²S Compatible (BICK = 512fs)

256BICK

LRCKx

BICKx

32 BICK

SLOT1

32 BICK

SLOT2

32 BICK

SLOT3

32 BICK

SLOT4

32 BICK

SLOT5

32 BICK

SLOT6

32 BICK

SLOT7

32 BICK

SLOT8

SDIN1/SDOUT1

Figure 35. TDM Mode I²S Compatible (BICK = 256fs)

128BICK

LRCKx

BICKx

32 BICK

SLOT1

32 BICK

SLOT2

32 BICK

SLOT3

32 BICK

SDIN1/SDOUT1

SLOT4

Figure 36. TDM Mode I²S Compatible (BICK = 128fs)

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5-5-2. MSB Justified Format

512BICK

LRCKx

BICKx

32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK

SDIN1/SDOUT1

SLOT1 SLOT2

SLOT4

SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

SLOT5 SLOT6 SLOT7 SLOT8

SLOT3

Figure 37. TDM Mode MSB Justified Format (BICK = 512fs)

256BICK

LRCKx

BICKx

32 BICK

SLOT1

32 BICK

SLOT2

32 BICK

SLOT3

32 BICK

SLOT4

32 BICK

SLOT5

32 BICK

SLOT6

32 BICK

SLOT7

32 BICK

SLOT8

SDIN1/SDOUT1

Figure 38. TDM Mode MSB Justified Format (BICK = 256fs)

128BICK

LRCKx

BICKx

32 BICK

SLOT1

32 BICK

SLOT2

32 BICK

SLOT3

32 BICK

SDIN1/SDOUT1

SLOT4

Figure 39. TDM Mode MSB Justified Format (BICK = 128fs)

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5-5-3. LSB Justified Format

512BICK

LRCKx

BICKx

32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK

SDIN1/SDOUT1

SLOT1 SLOT2

SLOT4

SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

SLOT5 SLOT6 SLOT7 SLOT8

SLOT3

Figure 40. TDM Mode LSB Justified Format (BICK = 512fs)

256BICK

LRCKx

BICKx

32 BICK

SLOT1

32 BICK

SLOT2

32 BICK

SLOT3

32 BICK

SLOT4

32 BICK

SLOT5

32 BICK

SLOT6

32 BICK

SLOT7

32 BICK

SLOT8

SDIN1/SDOUT1

Figure 41. TDM Mode LSB Justified Format (BICK = 256fs)

128BICK

LRCKx

BICKx

32 BICK

SLOT1

32 BICK

SLOT2

32 BICK

SLOT3

32 BICK

SDIN1/SDOUT1

SLOT4

Figure 42. TDM Mode LSB Justified Format (BICK = 128fs)

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5-5-4. PCM Short Frame Format

512BICK

LRCKx

BICKx

Don’t Care

SDIN1

SDOUTx

SLOT1 SLOT2 SLOT3 SLOT4

SLOT6 SLOT7 SLOT8 SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

SLOT5

Figure 43. TDM mode PCM Short Frame (BICK = 512fs, BCKP bit = “0”) (Note 45)

256BICK

LRCKx

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 SLOT8

Figure 44. TDM mode PCM Short Frame (BICK = 256fs, BCKP bit = “0”) (Note 45)

128BICK

LRCKx

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1

SLOT2

SLOT3

SLOT4

Figure 45. TDM mode PCM Short Frame (BICK = 128fs, BCKP bit = “0”) (Note 45)

Note 45. When BCKPx bit = “1”, a BICK rising edge “↑” corresponds to a LRCK rising edge “↑”.

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5-5-5. PCM Long Frame Format

512BICK

LRCKx(Master)

LRCKx(Slave)

Don’t Care

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1 SLOT2 SLOT3 SLOT4

SLOT6 SLOT7 SLOT8 SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

SLOT5

Figure 46. TDM mode PCM Long Frame (BICK = 512fs, BCKP bit = “0”) (Note 46)

256BICK

LRCKx(Master)

Don’t Care

LRCKx(Slave)

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 SLOT8

Figure 47. TDM mode PCM Long Frame (BICK = 256fs, BCKP bit = “0”) (Note 46)

128BICK

LRCKx(Master)

Don’t Care

LRCKx(Slave)

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1

SLOT2

SLOT3

SLOT4

Figure 48. TDM mode PCM Long Frame (BICK = 128fs, BCKP bit = “0”) (Note 46)

Note 46. When BCKPx bit = “1”, a BICK rising edge “↑” corresponds to a LRCK rising edge “↑”.

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5-5-6. Irregular I²S Format

512BICK

LRCKx(Master)

LRCKx(Slave)

Don’t Care

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT2 SLOT3 SLOT4

SLOT6 SLOT7 SLOT8 SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

SLOT1

SLOT5

Figure 49. TDM Mode Irregular I²S Format (BICK = 512fs)

256BICK

LRCKx(Master)

LRCKx(Slave)

Don’t Care

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 SLOT8

Figure 50. TDM Mode Irregular I²S Format (BICK = 256fs)

128BICK

LRCKx(Master)

LRCKx(Slave)

Don’t Care

BICKx

Don’t Care

SDIN1

SDOUT1

SLOT1

SLOT2

SLOT3

SLOT4

Figure 51. TDM Mode Irregular I²S Format (BICK = 128fs)

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[AK4601]

■ Power-up Sequence

１. Power-up Sequence

The AK4601 should be powered up when the PDN pin = “L”. Set the PDN pin to “H” to start the power

supply circuits for REF (reference voltage source) generator and digital circuits after all power supplies

are fed. By setting the PDN pin to “H”, control registers are initialized. Control register settings should be

made with an interval of 1ms or more after the PDN pin = “H”.

The PLL starts operation by a clock reset release (CKRESETN bit = “0” → “1”) and generates the

internal master clock after setting control registers. Therefore, necessary system clock must be input

before a clock reset release.

The system clock must not be stopped except during clock reset and power-down mode (PDN pin = “L”).

Power Supply

600ns

(min)

100 ms

PDN pin

Analog Input Charge

Analog Input

SI / SDApin

1ms

(min)

CONT

REG Setting

PMMB1 bit

PMMB2 bit

100 ms

MIC Power

Output

Stable MIC Power Output

CKRESETN bit

HRESETN bit

Start

Operation

Clock Determined

MCKI, BICKx pin

10 ms

PLL Internal

Master Clock

Period until PLL oscillation

Figure 52. Power-up Sequence

Note 47. The analog input charge period depends on the capacitance of AC coupling capacitor. It will be

100 msec if the capacitance is 1 µF.

Note 48. The output period of a stable microphone power depends on the capacitance of decoupling

capacitor at the MPREF pin. It will be 100 msec if the capacitance is 1 µF.

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[AK4601]

■ LDO (Internal Circuit Drive Regulator)

The AK4601 has a regulator for driving internal digital circuits (LDO). Connect a 2.2μF (±30%) capacitor

between the AVDRV pin and the DVSS2 pin. The LDO starts operation by releasing power-down mode,

and control register settings can be made 1ms after the power-down release (PDN pin=“H”).

The AK4601 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by

a short of the AVDRV pin to VSS and etc., and an overvoltage protection circuit to protect from exceeded

voltage when the voltage to the AVDRV pin gets too high. When these protection circuits perform,

internal circuits are powered down. The internal circuit will not return to a normal operation until being

reset by the PDN pin after removing the problems.

■ Power-down and Reset

1. AK4601 Power-down and Reset Statuses and Power Management

Power-down and power-down release of the AK4601 is controlled by the PDN pin. After power-down is

released, the power management and reset of the AK4601 are controlled by registers such as

CKRESETN bit (Clock Reset) and power management bits for each block.

There are two states for the AK4601 other than normal operation: Power-down and Clock Reset. The

power-down state means the status that the PDN pin is “L”. In this state, all blocks of the AK4601 stop

the operation.

The clock reset state means the status that the PDN pin is “H” and CKRESETN bit is “0”. In this state,

the ADC, DAC, blocks are not in operation because the PLL circuit and internal clocks are stopped.

Setting

State

PDN pin

CKRESETN bit

Power-down

Clock Reset

Clock Reset Release

(Note 49)

Table 30. Reset State Definitions of the AK4601 (x: Don’t Care)

Note 49. A stable clock should be supplied before releasing clock reset (CKRESETN bit = “1”).

2. Power-down

The AK4601 can be powered down by bringing the PDN pin = “L”. Output statuses of power-down mode

are shown in Table 3.

3. Power-down Release

The REF generation circuit (reference voltage source) and a power supply circuit for internal digital

circuit are powered-up by bringing the PDN pin to “H” from “L” after an interval of 600ns or more when

AVDD, LVDD, TVDD are powered up. Control register settings should be made with an interval of 1ms

or longer after setting the PDN pin = “H”.

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4. Clock Reset

When CKRESETN bit = “0” after power-down mode is released (PDN pin = “H”), the AK4601 is in clock

reset state. All blocks except the power supply circuits for REF generation and digital circuits are in

power-save mode. Even the internal PLL for master clock generation is powered down.

Control register settings should be made with an interval of 1ms (min) or more after releasing the

power-down mode.

Necessary system clocks (Table 4, Table 5) should be input before the clock reset is released. The

internal PLL starts operation and the master clock is generated when clock reset is released

(CKRESETN bit = “1”) (Figure 52). The AK4601 will be in operation by releasing power-down mode of

the blocks by setting each power-management bit.

System clocks must be changed during clock reset or in power-down mode (PDN pin = “L”). The PLL

and the internal clocks are stopped by this clock reset and the clock change can be done safely. Change

PLL starts operation by setting CKRESETN bit to “1”.

Clock operated blocks (ADC and DAC) must be powered down before executing clock reset. These

blocks can be powered down simultaneously by setting HRESETN bit to “0” from “1” (each PMAD and

PMDA bits settings are not necessary). Set HRESETN bit to “1” from “0” with an interval of 10ms for

stabilization of PLL after clock reset is released.

PLLREF Mode 1

PLLREF Mode 0

MCKI

BICK1

CSN

SCLK (Simplified)

00 29 87

C0 00 01 00

C0 00 84 00

C0 00

HRESETN bit

CKRESETN bit

PLL Stop

Input clock and clock mode can be changed

Blocks except PLL

are stopped

Resume

PLL Stabilize

Operation

Figure 53. Clock Mode Switching Sequence

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[AK4601]

■ STO Bit Status

PLL lock signal can be read out from the STO bit when PLLLOCKE bit = “1”.

PLLLOCKE bit

STO bit

No Error Detected: 1

Note

(default)

No Error Detected: 1

PLLLOCK Error Detected: 0

Table 31. STO Bit Status

■ μP Interface Setting and Pin Status

The AK4601 supports both SPI and I²C interfaces. When using SPI interface, release the power-down

state of the AK4601 while the CSN pin is “H”. After a power-down release, the AK4601 is set to I²C

interface mode. SPI interface mode become enabled by sending the dummy command mentioned

below.

Input “0xDE → 0xADDA → 0x7A” to the SI/I2CFIL pin while the CSN pin is “L” for the dummy command.

The data is in MSB first format.

CSN

SCLK

don’tcare

(L/H)

don’tcare

(L/H)

0x7A(8bit)

0xDE (8bit)

0xADDA (16bit)

Figure 54. Dummy Command Write Sequence

Statuses of the SO/SDA, SCLK/SCL and SI/I2CFIL pins are changed depending on the CSN and PDN

pins.

CSN pin PDN pin

SO/SDA pin

Hi-Z

function

SCLK/SCL pin

Input

SI/I2CFIL pin

Input

function

SPI Interface

I²C Interface

function

Input

“Hi-Z”→ pull-up

Input

L (I²C Fast Mode)

function

H (I²C Fast Mode Plus)

Table 32. μP Interface Setting

Note 50. The CSN pin and the SI/I2CFIL pin should be fixed to “L” or “H” when using I²C interface mode.

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[AK4601]

■ SPI Interface

1. Register Write

(1) Control Register Write

Field

Write data

(1) COMMAND Code

(2) ADDRESS

(3) ADDRESS

(4) DATA

0xC0

A15~A8

A7~A0

D7~D0

One byte of data may be written continuously for each address.

2. Register Read

(1) Control Register Read

Field

(1) COMMAND Code

(2) ADDRESS

(3) ADDRESS

(4) DATA

Write data

0x40

A15~A8

A7~A0

Readout data

D7~D0

One byte of data may be read continuously for each address.

Write Operation

CSN

SCLK

don’tcare

(L/H)

don’tcare

(L/H)

Data (write)

Command Code (8bit)

Address (16bit)

Low

Hi-Z

Figure 55. SPI Interface Timing (Write)

Read Operation

CSN

SCLK

don’tcare

(L/H)

don’tcare

(L/H)

Command Code (8bit)

Address (16bit)

Data (Read)

Low

Hi-Z

Figure 56. SPI Interface Timing (Read)

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[AK4601]

■ I²C Bus Interface (CSN = “H”)

Access to the AK4601 registers and RAM can be controlled by an I²C bus. The AK4601 supports

fast-mode I²C-bus (max: 400kHz) and fast-mode plus (max: 1MHz).

SI/I2CFIL pin

Bus Mode

Fast Mode

Fast Mode Plus

Table 33. I²C Bus Mode Setting

Note 51. The AK4601 does not support Hs mode (max: 3.4MHz).

1. Data Transfer

In order to access any IC devices on the I²C bus, input a start condition first, followed by one byte of

Slave address which includes the Device Address. IC devices on the BUS compare this Device address

with their own addresses and the IC device which has an identical address with the Device address

generates an acknowledgement. An IC device with the identical address then executes either a read or a

write operation. After the command execution, input a Stop condition.

1-1. Data Change

Change the data on the SDA line while the SCL line is “L”. The SDA line condition must be stable and

fixed while the clock is “H”. Change the Data line condition between “H” and “L” only when the clock

signal on the SCL line is “L”. Change the SDA line condition while the SCL line is “H” only when the start

condition or stop condition is input.

SCL

SDA

DATA LINE

STABLE :

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 57. Data Change (I²C)

1-2. Start Condition and Stop Condition

A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All

instructions are initiated by a Start condition. A stop condition is generated by the transition of “L” to “H”

on the SDA line while the SCL line is “H”. All instructions end by a Stop condition.

SCL

SDA

START CONDITION

STOP CONDITION

Figure 58. Start Condition and Stop Condition (I²C)

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1-3. Repeated Start Condition

When a Start condition is received again instead of a Stop condition, the bus changes to a Repeated

Start condition. A Repeated Start condition is functionally the same as a Start condition.

SCL

SDA

START CONDITION

Repeated Start CONDITION

Figure 59. Repeated Start Condition (I²C)

1-4. Acknowledge

The IC device that sends data releases the SDA line (“H”) after sending one byte of data. The IC device

that receives data then sets the SDA line to “L” at the next clock. This operation is called

“acknowledgement”, and it enables verification that the data transfer has been properly executed.

The AK4601 generates an acknowledgement upon receipt of a Start condition and a Slave address. For

a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. For a

read instruction, succeeded by generation of an acknowledgement, the AK4601 releases the SDA line

after outputting data at the designated address, and it monitors the SDA line condition. When the Master

side generates an acknowledgement without sending a Stop condition, the AK4601 outputs data at the

next address location. When no acknowledgement is generated, the AK4601 ends data output (not

acknowledged).

Clock pulse

for acknowledge

SCL FROM

MASTER

DATA

OUTPUT BY

TRANSMITTER

not acknowledge

acknowledge

DATA

OUTPUT BY

RECEIVER

START

CONDITION

Figure 60. Generation of Acknowledgement

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[AK4601]

1-5. The First Byte

The First Byte, which includes the Slave-address, is input after the Start condition is set, and a target IC

device that will be accessed on the bus is selected by the Slave-address.

The Slave-address is configured with the upper 7-bits and the data is “0010000”. When the

Slave-address is inputted, an external device that has the identical device address generates an

acknowledgement and instructions are then executed. The 8^thbit of the First Byte (lowest bit) is allocated

as the R/W Bit. When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the write

instruction is executed.

Note 52. In this document, there is a case that describes a “Write Slave-address assignment” when

both address bits match and a Slave-address at R/W Bit = “0” is received. There is a case that

describes “Read Slave-address assignment” when both address bits matches and a

Slave-address at R/W Bit = “1” is received.

R/W

Figure 61. First Byte Configuration (I²C)

1-6. The Second and Succeeding Bytes

The data format of the second and succeeding bytes of the AK4601 Transfer / Receive Serial data

(command code, address and data in microcontroller interface format) on the I²C BUS are all configured

with a multiple of 8-bits. When transferring or receiving those data on the I²C BUS, they are divided into

an 8-bit data stream segment and they are transferred / received with the MSB side data first with an

acknowledgement in-between.

Example)

When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:

(1) I²C format

(1) Microcomputer format

24BIT

8BIT

…Acknowledge

Figure 62. Division of Data (I²C)

Note 53. In this document, there is a case that describes a write instruction command code which is

received at the second byte as “Write Command”. There is a case that describes a read

instruction command code which is received at the second byte as “Read Command”.

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[AK4601]

2. Write Sequence

In the AK4601, when a “Write-Slave-address assignment” is received at the first byte, the write

command at the second byte, the address at the third and fourth bytes, and data at the fifth and

succeeding bytes are received. The number of write data bytes is fixed by the received command code.

R/W=”0”

Slave

Address

Command

Code

SDA

Address(1)

Data(0)

Data(n)

Address(0)

Data(1)

Figure 63. Write Sequence (I²C)

3. Read Sequence

In the AK4601, when a “write- slave-address assignment” is received at the first byte, the read command

at the second byte and the address at the third and fourth bytes are received. When the fourth byte is

received and an acknowledgement is transferred, the read command waits for the next restart condition.

When a “read slave-address assignment” is received at the first byte, data is transferred at the second

and succeeding bytes. The number of readable data bytes is fixed by the received read command.

After reading the last byte, assure that a “not acknowledged” signal is received. If this “not

acknowledged” signal is not received, the AK4601 continues to send data regardless whether data is

present or not, and since it did not release the BUS, the stop condition cannot be properly received.

R/W=”0”

R/W=”1”

Slave

Address

Slave

Address

Command

Code

SDA

Address(0)

Address(1)

Data(0)

Data(n)

Data(1)

A C

Figure 64. Read Sequence (I²C)

4. Limitation in use of I²C Interface

The I²C interface does not support the following features.

(1) No operation in Hs Mode (max: 3.4MHz).

The AK4601 Supports Fast mode (max: 400kHz) and Fast plus mode (max: 1MHz).

Note 54. Do not turn off the power of the AK4601 whenever the power supplies of other devices of the

same system are turned on. Pull-up resistors of SDA and SCL pins should be connected to

TVDD or less voltage. (The diodes against TVDD exist in the SDA and SCL pins.)

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[AK4601]

■ Mixer

The AK4601 has two stereo input mixers that have level adjustment function for overflow protection after

adding and data change function (Mixer A and Mixer B). Level adjustment is processed by shift

operation. Since the level adjustment function is only for avoiding overflow by adding, it can only shift

1bit to the right.

Mixer A is controlled by SFTA1[1:0] bits, SFTA2[1:0] bits, SWPA1[1:0] bits and SWPA2[1:0] bits.

Mixer B is controlled by SFTB1[1:0] bits, SFTB2[1:0] bits, SWPB1[1:0] bits and SWPB2[1:0] bits.

Serial Data

Bus

Serial Data

Bus

SWPx1[1:0]

SFTx1[1:0]

L(1’)

L(1)

R(1)

SELMIXxI1[5:0]

L(1’’)

R(1’’)

Shift

Stereo (1)

mute

R(1’)

L(Q)

R(Q)

Stereo (Q)

SWPx2[1:0]

SFTx2[1:0]

L(2’)

SELMIXxI2[5:0]

L(2)

R(2)

L(2’’)

R(2’’)

Shift

Stereo (2)

mute

R(2’)

x = A or B

Figure 65. Block Diagram of the Mixer

SFTA1[1:0] / SFTA2[1:0] bits

SFTB1[1:0] / SFTB2[1:0] bits

L(y’)

(y=1 or 2)

R(y’)

(y=1 or 2)

Mode

Shift Amount

No Shift

Comment

L(y)

R(y)

0dB

About -6dB

(x 1/2)

1 bit Right Shift L(y) >> 1

R(y) >>1

Mute

-∞dB

Table 34. Level Adjustment of the Mixer

SWPA1[1:0] / SWPA2[1:0] bits

SWPB1[1:0] / SWPB2[1:0] bits

L(y’’)

R(y’’)

Mode

Comment

(y=1 or 2) (y=1 or 2)

L(y’)

R(y’)

L(y’)

R(y’)

Through

Lin → Lout, Rout

Rin → Lout, Rout

Swap Signal

Lin → Rout

R(y’)

L(y’)

Rin → Lout

Table 35. Data Change Function of the Mixer

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[AK4601]

■ Vol

The AK4601 has three digital volume circuits (+12~-115dB, 0.5dB steps) that have independent Lch and

Rch.

VOL1 Lch

VOL1 Rch

VOL2 Lch

VOL2 Rch

VOL3 Lch

VOL3 Rch

Attenuation

Level

VOL1L[7:0] VOL1R[7:0] VOL2L[7:0] VOL2R[7:0] VOL3L[7:0] VOL3R[7:0]

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

+12.0dB

+11.5dB

+11.0dB

17h

18h

19h

17h

18h

19h

17h

18h

19h

17h

18h

19h

17h

18h

19h

17h

18h

19h

+0.5dB

0.0dB

-0.5dB

(default)

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

-114.5dB

-115.0dB

Mute (-∞)

Table 36. Digital Volume Settings

ATSPVOL bit controls transition time between setting values of the volume.

MODE ATSPVOL

ATT speed

4/fs

(default)

16/fs

Table 37. Volume Transition Time

When changing output levels, transitions are executed via soft changes; thus no switching noise occurs

during these transitions. In Mode 0, it takes 1020/fs (21.3ms@fs=48kHz) from 18H(0dB) to FFH(MUTE).

If the PDN pin goes to “L”, each channel of volume circuit is initialized to 18H.

00h ↔ FFh Transition Time

ATSPVOL

LRCK Cycle

fs=48kHz fs=44.1kHz

fs=8kHz

127.5ms

510.0ms

1020/fs

4080/fs

21.3ms

85.0ms

23.1ms

92.5ms

(default)

Table 38. Volume Transition Time between 00h and FFh

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[AK4601]

code dB

code DB

code dB

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah 7.0

0Bh 6.5

0Ch 6.0

0Dh 5.5

0Eh 5.0

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

12.0 20h -4.0

40h

41h

42h

43h

-20.0 60h -36.0 80h

-52.0 A0h -68.0 C0h -84.0 E0h -100.0

-52.5 A1h -68.5 C1h -84.5 E1h -100.5

-53.0 A2h -69.0 C2h -85.0 E2h -101.0

-53.5 A3h -69.5 C3h -85.5 E3h -101.5

-54.0 A4h -70.0 C4h -86.0 E4h -102.0

-54.5 A5h -70.5 C5h -86.5 E5h -102.5

-55.0 A6h -71.0 C6h -87.0 E6h -103.0

-55.5 A7h -71.5 C7h -87.5 E7h -103.5

-56.0 A8h -72.0 C8h -88.0 E8h -104.0

-56.5 A9h -72.5 C9h -88.5 E9h -104.5

-57.0 AAh -73.0 CAh -89.0 EAh -105.0

-57.5 ABh -73.5 CBh -89.5 EBh -105.5

11.5 21h

11.0 22h

10.5 23h

10.0 24h

-4.5

-5.0

-5.5

-20.5 61h

-21.0 62h

-21.5 63h

-22.0 64h

-22.5 65h

-23.0 66h

-23.5 67h

-24.0 68h

-24.5 69h

-36.5 81h

-37.0 82h

-37.5 83h

-38.0 84h

-38.5 85h

-39.0 86h

-39.5 87h

-40.0 88h

-40.5 89h

-.6.0 44h

9.5

9.0

8.5

8.0

7.5

25h

26h

27h

28h

29h

-6.5

-7.0

-7.5

-8.0

-8.5

45h

46h

47h

48h

49h

2Ah -9.0

2Bh -9.5

4Ah -25.0 6Ah -41.0 8Ah

4Bh -25.5 6Bh -41.5 8Bh

2Ch -10.0 4Ch -26.0 6Ch -42.0 8Ch -58.0 ACh -74.0 CCh -90.0 ECh -106.0

2Dh -10.5 4Dh -26.5 6Dh -42.5 8Dh -58.5 ADh -74.5 CDh -90.5 EDh -106.5

2Eh -11.0 4Eh -27.0 6Eh -43.0 8Eh

-59.0 AEh -75.0 CEh -91.0 EEh -107.0

-59.5 AFh -75.5 CFh -91.5 EFh -107.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

-11.5 4Fh

-12.0 50h

-12.5 51h

-13.0 52h

-13.5 53h

-14.0 54h

-14.5 55h

-15.0 56h

-15.5 57h

-16.0 58h

-16.5 59h

-27.5 6Fh

-28.0 70h

-28.5 71h

-29.0 72h

-29.5 73h

-30.0 74h

-30.5 75h

-31.0 76h

-31.5 77h

-32.0 78h

-32.5 79h

-43.5 8Fh

-44.0 90h

-44.5 91h

-45.0 92h

-45.5 93h

-46.0 94h

-46.5 95h

-47.0 96h

-47.5 97h

-48.0 98h

-48.5 99h

-60.0 B0h -76.0 D0h -92.0 F0h

-60.5 B1h -76.5 D1h -92.5 F1h

-61.0 B2h -77.0 D2h -93.0 F2h

-61.5 B3h -77.5 D3h -93.5 F3h

-62.0 B4h -78.0 D4h -94.0 F4h

-62.5 B5h -78.5 D5h -94.5 F5h

-63.0 B6h -79.0 D6h -95.0 F6h

-63.5 B7h -79.5 D7h -95.5 F7h

-64.0 B8h -80.0 D8h -96.0 F8h

-64.5 B9h -80.5 D9h -96.5 F9h

-108.0

-108.5

-109.0

-109.5

-110.0

-110.5

-111.0

-111.5

-112.0

-112.5

-0.5 39h

1Ah -1.0 3Ah -17.0 5Ah -33.0 7Ah -49.0 9Ah

1Bh -1.5 3Bh -17.5 5Bh -33.5 7Bh -49.5 9Bh

-65.0 BAh -81.0 DAh -97.0 FAh -113.0

-65.5 BBh -81.5 DBh -97.5 FBh -113.5

1Ch -2.0 3Ch -18.0 5Ch -34.0 7Ch -50.0 9Ch -66.0 BCh -82.0 DCh -98.0 FCh -114.0

1Dh -2.5 3Dh -18.5 5Dh -34.5 7Dh -50.5 9Dh -66.5 BDh -82.5 DDh -98.5 FDh -114.5

1Eh -3.0 3Eh -19.0 5Eh -35.0 7Eh -51.0 9Eh

1Fh -3.5 3Fh -19.5 5Fh -35.5 7Fh -51.5 9Fh

-67.0 BEh -83.0 DEh -99.0 FEh -115.0

-67.5 BFh -83.5 DFh -99.5 FFh Mute

Table 39. Digital Volume Level Setting of the VOL Circuit

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[AK4601]

■ Analog Input Blcok

1. Microphone Input Gain

The AK4601 has gain amplifiers for microphone input. The gain of L and R channels can be

independently selected by MGNL[3:0] and MGNR[3:0] bits (Table 40). The input impedance is typ.

20k@ADC1VL/R bit = “0” and typ. 25k@ADC1VL/R bit = “1”. This gain amplifier executes zero

crossing detection when changing the gain by setting MICLZCE bit = “1” / MICRZCE bit = “1”. Zero

crossing detection is executed independently for L and R channels. Zero crossing timeout period is

16ms@fs=48kHz. When MICLZCE bit = “0”/ MICRZCE bit = “0”, the volume is changed immediately by

When writing to MGNL/R[3:0] bits continuously, take an interval of zero crossing timeout period or more.

If the MGNL/R[3:0] bits are changed before zero crossing, the volume of Lch and Rch may differ. When

the volume level that is same as the present volume is set, the zero crossing counter is not reset and

time outs according to the previous writing timing. Therefore, in this case, writing to MGNL/R [3:0] bits

continuously is possible with a shorter interval of the zero crossing timeout period.

1-1. Microphone Input Selector

MGNL[3] MGNL[2] MGNL[1]

MGNR[3] MGNR[2] MGNR[1] MGNR[0]

MGNL[0]

Mode

Input Gain

0dB

2dB

4dB

6dB

8dB

10dB

12dB

14dB

16dB

18dB

21dB

24dB

27dB

30dB

33dB

36dB

(default)

Table 40. Microphone Input Gain

1-2. Zero Crossing Timeout

The microphone gain is changed independently on the timing of zero crossing detection or zero crossing

timeout.

PLL_MCLK

Zero Crossing Timeout Period

48kHz base

44.1kHz base 112.986MHz

122.880MHz

16.0ms

17.4ms

Table 41. Zero Crossing Timeout Period

1-3. Start-up Time of MIC Input Pin

The AK4601 starts to charge a DC cut capacitor when the PDN pin is set to “H” from “L”. Since the input

impedance is 25kΩ, the time constant will be 25ms if the DC cut capacitor is 1µF. A wait time of about

100ms should be taken before power up the ADC to charge the DC cut capacitor sufficiently. A click

noise may occur just after the ADC is powered up if this wait time is not enough.

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[AK4601]

2. Microphone Input Selector

The AK4601 has microphone input selectors. Each microphone amplifier input is selectable between

single-ended input and differential input by AD1LSEL bit or AD1RSEL bit.

AK4601

AIN1L / INP1 pin

ADC Lch

INN1 pin

MIC-Amp Lch

AD1LSEL bit

AIN1R / INP2 pin

ADC Rch

INN2 pin

MIC-Amp Rch

AD1RSEL bit

Figure 66. Microphone Input Selector

AD1LSEL bit

ADC Lch

AD1RSEL bit

ADC Rch

INP1/INN1 (default)

AIN1L

INP2/INN2 (default)

AIN1R

Table 42. Microphone Input Selector

3. Microphone Bias Output

The AK4601 has two lines of microphone bias outputs. The power supply of microphones are supplied

from the MPWR1 pin and the MPWR2 pin by setting PMMB1 bit = “1” and PMMB2 bit = “1”, respectively.

The output voltage is 2.5V (AVDD=3.3V) and the load resistance is min. 2kΩ.

PMMB1 bit

MPWR1 pin

Hi-Z

PMMB2bit

MPWR2 pin

Hi-Z

(default)

Output

Table 43. Microphone Bias Output

AK4601

PMB1 bit

PMB2 bit

MPWR1 pin

MPWR2 pin

PMB2 bit

MPWR2 pin

Microphone

INP1

INN1

AIN1L

0.1µF

MIC-Amp Lch

MIC-Amp Rch

0.1µF

Microphone

INP2

INN2

AIN1R

0.1µF

MIC-Amp Rch

0.1µF

Figure 67. MIC Block Circuit (Differential Input)

Figure 68. MIC Block Circuit (Single-end Input)

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■ ADC Block (ADC1, ADC2, ADCM)

1. ADC Block High Pass Filter

The AK4601 has a digital high pass filter (HPF) for DC offset cancelling of each ADC. The cut-off

frequency of the HPF is about 0.93Hz (fs=48kHz), depending on operation frequency.

48kHz

0.93Hz

44.1kHz

0.86Hz

8kHz

0.16Hz

Cut-off Frequency

Table 44. HPF Cut-off Frequency

2. ADC Digital Volume

The AK4601 has independent digital volume controls for Lch and Rch (256 levels, 0.5dB steps) of each

ADC.

ADC1

ADC2

ADCM

Attenuation

Level

VOLAD1L[7:0] VOLAD1R[7:0] VOLAD2L[7:0] VOLAD2R[7:0] VOLADM[7:0]

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

+24.0dB

+23.5dB

+23.0dB

2Fh

30h

31h

2Fh

30h

31h

2Fh

30h

31h

2Fh

30h

31h

2Fh

30h

31h

+0.5dB

0.0dB

-0.5dB

(default)

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

-102.5dB

-103.0dB

Mute (-∞)

Table 45. ADC Digital Volume Control Setting

The transition time between set values is selected by ATSPAD bit.

Mode

ATSPAD bit

ATT speed

4/fs

(default)

16/fs

Table 46. ADC Volume Level Transition Time

When changing output levels, transitions are executed via soft changes; thus no switching noise occurs

during these transitions. In Mode 0, it takes 1020/fs (21.3ms@fs=48kHz) from 00H(0dB) to FFH(MUTE).

If the PDN pin goes to “L”, each channel of the ADC is initialized to 30H.

00h ↔ FFh Transition Time

ATSPAD bit

LRCK Cycle

1020/fs

fs=48kHz

21.3ms

85.0ms

fs=44.1kHz

23.1ms

92.5ms

fs=8kHz

127.5ms

510.0ms

(default)

4080/fs

Table 47. ADC Volume Transition Time between 00h and FFh

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code

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

code

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

code

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

code

60h

61h

62h

63h

code

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

code

24.0

23.5

23.0

22.5

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

9.5

-8.0

-8.5

-9.0

-9.5

-10.0 64h

-10.5 65h

-11.0 66h

-11.5 67h

-12.0 68h

-12.5 69h

-13.0 6Ah

-13.5 6Bh

-24.0

-24.5

-25.0

-25.5

-26.0

-26.5

-27.0

-27.5

-28.0

-28.5

-40.0

-40.5

-41.0

-41.5

-42.0

-42.5

-43.0

-43.5

-44.0

-44.5

-45.0

-45.5

A0h -56.0 C0h -72.0 E0h

A1h -56.5 C1h -72.5 E1h

A2h -57.0 C2h -73.0 E2h

A3h -57.5 C3h -73.5 E3h

A4h -58.0 C4h -74.0 E4h

A5h -58.5 C5h -74.5 E5h

A6h -59.0 C6h -75.0 E6h

A7h -59.5 C7h -75.5 E7h

A8h -60.0 C8h -76.0 E8h

A9h -60.5 C9h -76.5 E9h

AAh -61.0 CAh -77.0 EAh

ABh -61.5 CBh -77.5 EBh

ACh -62.0 CCh -78.0 ECh

ADh -62.5 CDh -78.5 EDh

AEh -63.0 CEh -79.0 EEh

AFh -63.5 CFh -79.5 EFh

B0h -64.0 D0h -80.0 F0h

B1h -64.5 D1h -80.5 F1h

B2h -65.0 D2h -81.0 F2h

B3h -65.5 D3h -81.5 F3h

B4h -66.0 D4h -82.0 F4h

B5h -66.5 D5h -82.5 F5h

B6h -67.0 D6h -83.0 F6h

B7h -67.5 D7h -83.5 F7h

-88.0

-88.5

-89.0

-89.5

-90.0

-90.5

-91.0

-91.5

-92.0

-92.5

-93.0

-93.5

-94.0

-94.5

-95.0

-95.5

-96.0

-96.5

-97.0

-97.5

-98.0

-98.5

-99.0

-99.5

-29.0 8Ah

-29.5 8Bh

4Ch -14.0 6Ch -30.0 8Ch -46.0

4Dh -14.5 6Dh -30.5 8Dh -46.5

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

-15.0 6Eh

-15.5 6Fh

-16.0 70h

-16.5 71h

-17.0 72h

-17.5 73h

-18.0 74h

-18.5 75h

-19.0 76h

-19.5 77h

-20.0 78h

-20.5 79h

-21.0 7Ah

-21.5 7Bh

-31.0 8Eh

-47.0

-47.5

-48.0

-48.5

-49.0

-49.5

-50.0

-50.5

-51.0

-51.5

-52.0

-52.5

-53.0

-53.5

-31.5

-32.0

-32.5

-33.0

-33.5

-34.0

-34.5

-35.0

-35.5

-36.0

-36.5

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

-5.5

-.6.0

-6.5

-7.0

-7.5

B8h -68.0 D8h -84.0 F8h -100.0

B9h -68.5 D9h -84.5 F9h -100.5

BAh -69.0 DAh -85.0 FAh -101.0

BBh -69.5 DBh -85.5 FBh -101.5

BCh -70.0 DCh -86.0 FCh -102.0

BDh -70.5 DDh -86.5 FDh -102.5

BEh -71.0 DEh -87.0 FEh -103.0

-37.0 9Ah

-37.5 9Bh

5Ch -22.0 7Ch -38.0 9Ch -54.0

5Dh -22.5 7Dh -38.5 9Dh -54.5

5Eh

5Fh

9.0

8.5

-23.0 7Eh

-23.5 7Fh

-39.0 9Eh

-39.5 9Fh

-55.0

-55.5

BFh -71.5 DFh -87.5 FFh

Mute

Table 48. ADC Digital Volume Level Setting

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[AK4601]

3. ADC Soft Mute

The ADC block has a digital soft mute circuit. The soft mute operation is performed at digital domain.

The output signal is attenuated to -∞ in “ATT setting level x ATT transition time” from the current ADC

digital volume setting level by setting AD1MUTE bit, AD2MUTE bit or ADMMUTE bit to “1”. When the

AD1MUTE bit, AD2MUTE bit or ADMMUTE bit returns to “0”, the mute is cancelled and the output

attenuation level gradually changes to ATT setting level in “ATT setting level x ATT transition time”. If the

soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is

discontinued and the volume level returns to original volume setting level by the same cycle. The soft

mute is effective for changing the signal source without stopping the signal transmission.

The attenuation level transition takes 828/fs from 0dB to -∞ and from -∞ to 0dB. Soft mute function is

available when each ADC is in operation. The attenuation value is initialized by setting the PDN pin = “L”.

AD1MUTE, AD2MUTE,

ADMMUTE bit

Group Delay (GD)

0dB

Attenuation Level

828/fs

-∞dB

828/fs

Output Image

Figure 69. ADC Soft Mute

4. ADC Input Selector

ADC2 of the AK4601 has an input selector for 1 stereo differential input or 2 stereo single-ended inputs,

and 1 stereo semi-differential input. Differential or single-ended input can be selected for the ADCM.

These inputs are selected by AD2SEL[1:0] bits and ADMSEL bit. In the case that these registers are

changed during operation, mute output signal to reduce switching noise as needed.

Mode AD2SEL[1:0] bits

Selected Pins

AIN2LP, AIN2LN, AIN2RP, AIN2RN

AIN3L, AIN3R

(default)

AIN4L, AIN4R

AIN5L, AIN5R, GNDIN5

Table 49. ADC2 Input Select

Mode

ADMSEL bit

Selected Pins

Differential (AINMP, AINMN)

Single-ended (AINM)

(default)

Table 50. ADCM Input Select

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[AK4601]

4-1. Input Selector Switching Sequence

The input selector should be changed after enabling soft mute function to reduce the switching noise of

the input selector.

ADC2 Input selector switching sequence:

1) Enable Soft Mute Function before Changing Channel

2) Change Channel

3) Disable Soft Mute Function

AD2MUTE bit

(2)

(1)

DATT Level

Attenuation

Channel

(3)

-∞

IN3L/IN3R

IN4L/IN4R

Figure 70. ADC2 Input Channel Switching Sequence Example

The period of (1) varies according to the setting value of the DATT level. Transition time of attenuation

level from 0dB to - is shown below.

(1) Period (max)

ATSPAD

LRCK Cycle

fs=48kHz

fs=44.1kHz fs=8kHz

828/fs

828/fs x 4

17.25ms

69ms

18.78ms

75.10ms

103.5ms (default)

414ms

The input channel should be changed during the period (2). An interval around 200ms is needed before

releasing the soft mute after changing the channel (period (3)).

5. ADC Digital Filter Select

The AK4601 has four kinds of digital filters in ADC block. ADSD and ADSL bits select a digital filter.

Mode

ADSD bit

ADSL bit

Digital Filter

Sharp Roll-Off Filter

Slow Roll-Off Filter

Short Delay Sharp Roll-Off Filter

Short Delay Slow Roll-Off Filter

(default)

Table 51. ADC Digital Filter Select

6. ADC Full Scale Voltage

Single-ended input amplitude (differential input amplitude) of ADC1 L/Rch, ADC2 L/Rch and ADCM can

be switched between 2.3Vpp (±2.3Vpp) and 2.83Vpp (±2.83Vpp) by ADC1VL/R bit, ADC2VL/R bit and

ADCMV bit, respectively (Table 52).

Full Scale

Single-end Differential

ADC1VL, ADC1VR, ADC2VL,

ADC2VR, ADCMV

Mode

2.3Vpp

2.83Vpp

(default)

±2.3Vpp

±2.83Vpp

Table 52. ADC Input Voltage

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[AK4601]

■ DAC Block (DAC1, DAC2 and DAC3)

1. DAC Digital Volume

The AK4601 has channel-independent digital volume controls in DAC block. (256 levels, 0.5 steps)

DAC1 Lch

DAC1 Rch

DAC2 Lch

DAC2 Rch

DAC3 Lch

DAC3 Rch

Attenuation

Level

VOLDA1L[7:0] VOLDA1R[7:0] VOLDA2L[7:0] VOLDA2R[7:0] VOLDA3L[7:0] VOLDA3R[7:0]

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

00h

01h

02h

+12.0dB

+11.5dB

+11.0dB

17h

18h

19h

17h

18h

19h

17h

18h

19h

17h

18h

19h

17h

18h

19h

17h

18h

19h

+0.5dB

0.0dB

-0.5dB

(default)

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

-114.5dB

-115.0dB

Mute (-∞)

Table 53. DAC Digital Volume Setting

Transition time between set values can be selected by ATSPDA bit.

MODE

ATSPDA

ATT speed

4/fs

(default)

16/fs

Table 54. DAC Volume Transition Time Setting

When changing output levels, transitions are executed via soft changes; thus no switching noise occurs

during these transitions. In Mode 0, it takes 1020/fs (21.3ms@fs=48kHz) from 00H(0dB) to FFH(MUTE).

If the PDN pin goes to “L”, each channel of the DAC is initialized to 18H.

00h ↔ FFh Transition Time

ATSPDA

LRCK Cycle

fs=48kHz fs=44.1kHz fs=8kHz

1020/fs

4080/fs

21.3ms

85.0ms

23.1ms

92.5ms

127.5ms

510.0ms

(default)

Table 55. DAC Volume Transition Time between 00h and FFh

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[AK4601]

code dB

code DB

code dB

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah 7.0

0Bh 6.5

0Ch 6.0

0Dh 5.5

0Eh 5.0

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

12.0 20h -4.0

40h

41h

42h

43h

-20.0 60h -36.0 80h

-52.0 A0h -68.0 C0h -84.0 E0h -100.0

-52.5 A1h -68.5 C1h -84.5 E1h -100.5

-53.0 A2h -69.0 C2h -85.0 E2h -101.0

-53.5 A3h -69.5 C3h -85.5 E3h -101.5

-54.0 A4h -70.0 C4h -86.0 E4h -102.0

-54.5 A5h -70.5 C5h -86.5 E5h -102.5

-55.0 A6h -71.0 C6h -87.0 E6h -103.0

-55.5 A7h -71.5 C7h -87.5 E7h -103.5

-56.0 A8h -72.0 C8h -88.0 E8h -104.0

-56.5 A9h -72.5 C9h -88.5 E9h -104.5

-57.0 AAh -73.0 CAh -89.0 EAh -105.0

-57.5 ABh -73.5 CBh -89.5 EBh -105.5

11.5 21h

11.0 22h

10.5 23h

10.0 24h

-4.5

-5.0

-5.5

-20.5 61h

-21.0 62h

-21.5 63h

-22.0 64h

-22.5 65h

-23.0 66h

-23.5 67h

-24.0 68h

-24.5 69h

-36.5 81h

-37.0 82h

-37.5 83h

-38.0 84h

-38.5 85h

-39.0 86h

-39.5 87h

-40.0 88h

-40.5 89h

-.6.0 44h

9.5

9.0

8.5

8.0

7.5

25h

26h

27h

28h

29h

-6.5

-7.0

-7.5

-8.0

-8.5

45h

46h

47h

48h

49h

2Ah -9.0

2Bh -9.5

4Ah -25.0 6Ah -41.0 8Ah

4Bh -25.5 6Bh -41.5 8Bh

2Ch -10.0 4Ch -26.0 6Ch -42.0 8Ch -58.0 ACh -74.0 CCh -90.0 ECh -106.0

2Dh -10.5 4Dh -26.5 6Dh -42.5 8Dh -58.5 ADh -74.5 CDh -90.5 EDh -106.5

2Eh -11.0 4Eh -27.0 6Eh -43.0 8Eh

-59.0 AEh -75.0 CEh -91.0 EEh -107.0

-59.5 AFh -75.5 CFh -91.5 EFh -107.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

-11.5 4Fh

-12.0 50h

-12.5 51h

-13.0 52h

-13.5 53h

-14.0 54h

-14.5 55h

-15.0 56h

-15.5 57h

-16.0 58h

-16.5 59h

-27.5 6Fh

-28.0 70h

-28.5 71h

-29.0 72h

-29.5 73h

-30.0 74h

-30.5 75h

-31.0 76h

-31.5 77h

-32.0 78h

-32.5 79h

-43.5 8Fh

-44.0 90h

-44.5 91h

-45.0 92h

-45.5 93h

-46.0 94h

-46.5 95h

-47.0 96h

-47.5 97h

-48.0 98h

-48.5 99h

-60.0 B0h -76.0 D0h -92.0 F0h

-60.5 B1h -76.5 D1h -92.5 F1h

-61.0 B2h -77.0 D2h -93.0 F2h

-61.5 B3h -77.5 D3h -93.5 F3h

-62.0 B4h -78.0 D4h -94.0 F4h

-62.5 B5h -78.5 D5h -94.5 F5h

-63.0 B6h -79.0 D6h -95.0 F6h

-63.5 B7h -79.5 D7h -95.5 F7h

-64.0 B8h -80.0 D8h -96.0 F8h

-64.5 B9h -80.5 D9h -96.5 F9h

-108.0

-108.5

-109.0

-109.5

-110.0

-110.5

-111.0

-111.5

-112.0

-112.5

-0.5 39h

1Ah -1.0 3Ah -17.0 5Ah -33.0 7Ah -49.0 9Ah

1Bh -1.5 3Bh -17.5 5Bh -33.5 7Bh -49.5 9Bh

-65.0 BAh -81.0 DAh -97.0 FAh -113.0

-65.5 BBh -81.5 DBh -97.5 FBh -113.5

1Ch -2.0 3Ch -18.0 5Ch -34.0 7Ch -50.0 9Ch -66.0 BCh -82.0 DCh -98.0 FCh -114.0

1Dh -2.5 3Dh -18.5 5Dh -34.5 7Dh -50.5 9Dh -66.5 BDh -82.5 DDh -98.5 FDh -114.5

1Eh -3.0 3Eh -19.0 5Eh -35.0 7Eh -51.0 9Eh

1Fh -3.5 3Fh -19.5 5Fh -35.5 7Fh -51.5 9Fh

-67.0 BEh -83.0 DEh -99.0 FEh -115.0

-67.5 BFh -83.5 DFh -99.5 FFh Mute

Table 56. DAC Digital Volume Level Setting

2. DAC Soft Mute

The DAC block has a digital soft mute circuit. The soft mute operation is performed at digital domain.

The output signal is attenuated to -∞ in “ATT setting level x ATT transition time” from the current DAC

digital volume setting level by setting DA1MUTE bit, DA2MUTE bit or DA3MUTE bit to “1”. When the

DA1MUTE bit, DA2MUTE bit or DA3MUTE bit returns to “0”, the mute is cancelled and the output

attenuation level gradually changes to ATT setting level in “ATT setting level x ATT transition time”. If the

soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is

discontinued and the volume level returns to original volume setting level by the same cycle. The soft

mute is effective for changing the signal source without stopping the signal transmission.

The attenuation level transition takes 924/fs from 0dB to -∞ and from -∞ to 0dB. Soft mute function is

available when each DAC is in operation. The attenuation value is initialized by setting the PDN pin = “L”.

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DA1/2/3MUTE bit

Attenuation Level

924/fs

0dB

-∞dB

Group Delay (GD)

Output Image

Soft Mute Operation

Figure 71. DAC Sof Mute Operation

The analog output pin will be in a mode that outputs VCOM voltage by changing HRESETN pin to “0”

from “1” while PMDA bit = “1” when changing system clock during DAC operation. This mode can

prevent a click noise when the DAC resumes operation after changing the system clock (Figure 72,

CASE1). The analog output will be Hi-z state when changing HRESETN to “0” from “1” while PMDA bit =

“0”. A click noise may occur when resuming the DAC operation after the system clock is changed (Figure

72, CASE2).

HRESETN bit

CASE1

PMDAx bit

“1”

Analog Output

VCOM Output

CASE2

PMDAx bit

Analog Output

“0”

HiZ

VCOM Output

Figure 72. Analog Output in HUB Reset

3. DAC Digital Filter Select

The AK4601 has four kinds of digital filters in DAC block. DASD and DASL bits select a digital filter.

Mode

DASD bit

DASL bit

Digital Filter

Sharp Roll-Off Filter

Slow Roll-Off Filter

Short Delay Sharp Roll-Off Filter (default)

Short Delay Slow Roll-Off Filter

Table 57. DAC Digital Filter Select

4. De-emphasis Filter Control

The AK4601 has a digital de-emphasis filter (tc=50/15µs) which corresponds to three sampling

frequencies (32kHz, 44.1kHz, 48kHz) by IIR filter. It is enabled or disabled with the DEMx[1:0] bits

(x=1~3) (Table 58).

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DEMx[1] bit

DEMx[0] bit

Mode

44.1kHz

OFF

48kHz

32kHz

(default)

Table 58. De-emphasis Filter Control

The de-emphasis filer only corresponds to the frequencies shown in Table 58. DEMx[1:0] bits must be

set to the default setting “01” when the AK4601 is operated with other sampling frequencies.

• In the case that the AK4601 is operated with a sampling frequency other than shown in Table 58.

The frequency characteristics of the de-emphasis filter will track the sampling frequency of the actual

operation.

(e.g. The cut-off frequency exists around 1kHz in 48kHz mode, around 2kHz in 96kHz mode and

around 0.5kHz in 24kHz mode.)

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■ Register Map

Control registers can be initialized by a power-down release (PDN pin = “L” → “H”).

Do not write to registers in the address after 008CH and write "0" into 0 bits and write "1" into 1 bit.

Normal Registers

Addr

[Hex]

Default

System Clock Setting 1

System Clock Setting 2

REFSEL[2:0]

REFMODE[4:0]

FSMODE[4:0]

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

CKRESETN

Mic Bias Power Management PSW1N

PSW2N

PMMB1

PMMB2

Sync Domain 1 Setting 1

Sync Domain 1 Setting 2

Sync Domain 2 Setting 1

Sync Domain 2 Setting 2

Reserved

MSN1

MSN2

CKS1[2:0]

BDV1[8]

SDV1[2:0]

BDV1[7:0]

BDV2[8]

BDV2[7:0]

CKS2[2:0]

SDV2[2:0]

Reserved

CLKO Output Setting

Pin Setting

CLKOE

CLKOSEL[2:0]

0 MSELN

Sync Domain Select 1

Reserved

SDBCK1[2:0]

SDBCK2[2:0]

Sync Domain Select 3

Sync Domain Select 4

Reserved

EXBCK1[2:0]

EXBCK3[2:0]

EXBCK2[2:0]

Sync Domain Select 6

Sync Domain Select 7

Sync Domain Select 8

Sync Domain Select 9

Reserved

SDDO1[2:0]

SDDO3[2:0]

SDDO2[2:0]

SDVOL1[2:0]

SDVOL3[2:0]

SDVOL2[2:0]

Reserved

Sync Domain Select 15

Sync Domain Select 16

SDOUT1 TDM SLOT1-2 Data Select

SDOUT1 TDM SLOT3-4 Data Select

SDOUT1 TDM SLOT5-6 Data Select

SDOUT1 TDM SLOT7-8 Data Select

SDOUT1 TDM SLOT9-10 Data Select

SDOUT1 TDM SLOT11-12 Data Select

SDOUT1 TDM SLOT13-14 Data Select

SDOUT1 TDM SLOT15-16 Data Select

SDMIXA[2:0]

SDADC1[2:0]

SDMIXB[2:0]

SDCODEC[2:0]

SELDO1A[5:0]

SELDO1B[5:0]

SELDO1C[5:0]

SELDO1D[5:0]

SELDO1E[5:0]

SELDO1F[5:0]

SELDO1G[5:0]

SELDO1H[5:0]

SELDO2[5:0]

SELDO3[5:0]

SDOUT2 Output Data Select

SDOUT3 Output Data Select

Reserved

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Addr

[Hex]

Default

Reserved

DAC1 Input Data Select

DAC2 Input Data Select

DAC3 Input Data Select

VOL1 Input Data Select

VOL2 Input Data Select

VOL3 Input Data Select

Reserved

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

0040

0041

0042

0043

0044

0045

0046

0047

0048

0049

004A

004B

004C

004D

004E

004F

0050

0051

0052

0053

0054

0055

0056

0057

0058

0059

005A

005B

005C

005D

005E

005F

0060

0061

0062

0063

0064

0065

0066

0067

0068

0069

006A

SELDA1[5:0]

SELDA2[5:0]

SELDA3[5:0]

SELVOL1[5:0]

SELVOL2[5:0]

SELVOL3[5:0]

Reserved

Mixer A Ch1 Input Data Select

Mixer A Ch2 Input Data Select

Mixer B Ch1 Input Data Select

Mixer B Ch2 Input Data Select

Reserved

SELMIXAI1[5:0]

SELMIXAI2[5:0]

SELMIXBI1[5:0]

SELMIXBI2[5:0]

Reserved

Clock Format Setting 1

Reserved

BCKP1

DCF1[2:0]

BCKP2

DCF2[2:0]

Reserved

SDIN1 Digital Input Format

SDIN2 Digital Input Format

SDIN3 Digital Input Format

Reserved

DIEDGEN1

DIEDGEN2

DIEDGEN3

DISL1[1:0]

DILSBE1

DILSBE2

DILSBE3

DIDL1[1:0]

DISL2[1:0]

DISL3[1:0]

DIDL2[1:0]

DIDL3[1:0]

Reserved

SDOUT1 Digital Output Format

SDOUT2 Digital Output Format

SDOUT3 Digital Output Format

Reserved

DOEDGEN1

DOEDGEN2

DOEDGEN3

DOSL1[1:0]

DOSL2[1:0]

DOSL3[1:0]

DOLSBE1

DOLSBE2

DOLSBE3

DODL1[1:0]

DODL2[1:0]

DODL3[1:0]

Reserved

SDOUT Phase Setting

Reserved

SDOPH3 SDOPH2 SDOPH1

Reserved

Output Port Enable Setting

Reserved

SDOUT1E SDOUT2E SDOUT3E

Mixer A Setting

Mixer B Setting

MIC AMP Gain

SFTA2[1:0]

SFTB2[1:0]

SFTA1[1:0]

SFTB1[1:0]

SWPA2[1:0]

SWPB2[1:0]

SWPA1[1:0]

SWPB1[1:0]

MGNL[3:0]

ADC1VR ADC2VL

MGNR[3:0]

0 MICLZCE MICRZCE

Analog Input Gain Control

ADC1 Lch Digital Volume

ADC1 Rch Digital Volume

ADC2 Lch Digital Volume

ADC2 Rch Digital Volume

ADCM Digital Volume

Reserved

ADC1VL

ADC2VR

ADCMV

VOLAD1L[7:0]

VOLAD1R[7:0]

VOLAD2L[7:0]

VOLAD2R[7:0]

VOLADM[7:0]

Reserved

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Addr

[Hex]

Default

ADMSEL AD1LSEL AD1RSEL

AD1HPFN AD2HPFN ADMHPFN

Analog Input Select Setting

ADC Mute & HPF Control

DAC1 Lch Digital Volume

DAC1 Rch Digital Volume

DAC2 Lch Digital Volume

DAC2 Rch Digital Volume

DAC3 Lch Digital Volume

DAC3 Rch Digital Volume

DAC Mute & Filter Setting

DAC DEM Setting

VOL1 Lch Digital Volume

VOL1 Rch Digital Volume

VOL2 Lch Digital Volume

VOL2 Rch Digital Volume

VOL3 Lch Digital Volume

VOL3 Rch Digital Volume

Reserved

ADSD

ADSL

AD2SEL[1:0]

006B

006C

006D

006E

006F

0070

0071

0072

0073

0074

0075

0076

0077

0078

0079

007A

007B

007C

007D

007E

007F

0080

0081

0082

0083

0084

0085

0086

0087

0088

0089

008A

008B

008C

ATSPAD AD1MUTE AD2MUTE ADMMUTE

VOLDA1L[7:0]

VOLDA1R[7:0]

VOLDA2L[7:0]

VOLDA2R[7:0]

VOLDA3L[7:0]

VOLDA3R[7:0]

DA1MUTE

DA2MUTE

DA3MUTE

ATSPDA

DSMN

DEM2[1:0]

DASD

DASL

DEM3[1:0]

DEM1[1:0]

VOL1L[7:0]

VOL1R[7:0]

VOL2L[7:0]

VOL2R[7:0]

VOL3L[7:0]

VOL3R[7:0]

Reserved

VOL Setting

ATSPVOL

Reserved

STO Flag Setting 1

Reserved

PLLLOCKE

Reserved

Power Management 1

Reserved

PMAD1

PMAD2

PMADM

PMDA1

PMDA2

PMDA3

Reset Control

CRESETN

HRESETN

Read Only Registers

Read these registers after Clock reset is released (when PLL is stabilized).

Addr

[Hex]

0100

0101

0102

Default

Reserved

Status Read Out

STO

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■ Register Definitions

Normal Registers

Addr Register Name

0000 System Clock Setting 1

R/W

REFSEL[2:0]

R/W

REFMODE[4:0]

R/W

Default

000

00H

REFSEL[3:0]: PLL Reference Clock Input Pin Setting (Table 4)

Default: “000” (MCKI)

REFMODE[4:0]: PLL Reference Clock Frequency Setting (Table 5)

Default: 00H (256kHz)

Addr Register Name

0001 System Clock Setting 2 CKRESETN

FSMODE[4:0]

R/W

Default

R/W

R/W R/W

00H

CKRESETN: Clock Reset

0: Clock Reset

(default)

1: Clock Reset Release

FSMODE[4:0]: Operation Sampling Frequency Mode Setting for each Block (Table 12)

Default: 00H (8kHz)

Addr Register Name

Mic Bias Power Management

0002

PSW1N PSW2N

PMMB1 PMMB2

R/W

Default

R/W

PSW1N: Pull-down Setting for BICK1pin / LRCK1 pin (Table 2)

0: Pulled Down (46kΩ) (default)

1: Release

PSW2N: Pull-down Setting for BICK2 pin/ LRCK2 pin (Table 2)

0: Pulled Down (46kΩ) (default)

1: Release

PMMB1: Power Management Setting for MIC Bias Output 1

0: Power Save Mode (default)

1: Normal Operation

PMMB2: Power Management Setting for MIC Bias Output 2

0: Power Save Mode (default)

1: Normal Operation

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Addr Register Name

Sync Domain 1 Setting 1

0003

MSN1

CKS1[2:0]

BDV1[8]

SDV1[2:0]

Sync Domain 1 Setting 2

0004

BDV1[7:0]

R/W

Default

R/W

000

R/W

000

MSN1: Slave/Master Mode Setting for BICK1 pin/LRCK1 pin (Table 16)

0: Slave Mode (default)

1: Master Mode

CKS1[2:0]: MBICK1 Divider Reference Clock Setting of Clock Sync Domain 1 (Table 8)

Default: “000” (TieLow)

BDV1[8:0]: MBICK1 Divider Setting (Table 9)

Default: 000H (Divided by 1)

SDV1[2:0]: MLRCK1 Divider Setting (Table 10)

Default: “000” (Divided by 64)

Addr Register Name

Sync Domain 2 Setting 1

0005

MSN2

CKS2[2:0]

BDV2[8]

SDV2[2:0]

Sync Domain 2 Setting 2

0006

BDV2[7:0]

R/W

Default

R/W

000

R/W

000

MSN2: Slave/Master Mode Setting for BICK2 pin/LRCK2 pin (Table 16)

0: Slave Mode (default)

1: Master Mode

CKS2[2:0]: MBICK2 Divider Reference Clock Setting of Clock Sync Domain 2 (Table 8)

Default: “000” (TieLow)

BDV2[8:0]: MBICK2 Divider Setting (Table 9)

Default: 000H (Divided by 1)

SDV2[2:0]: MLRCK2 Divider Setting (Table 10)

Default: “000” (Divided by 64)

Addr Register Name

CLKO Output Setting

CLKOE

CLKOSEL[2:0]

000F

R/W

Default

R/W

000

CLKOE: CLKO pin Output Enable

0: CLKO pin = “L” (default)

1: CLKO Output Enable

CLKOSEL[2:0]: CLKO pin Output Clock Frequency Setting (Table 13)

Default: “000” (12.288MHz / 11.2896MHz)

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Addr Register Name

0010 Pin Setting

R/W

MSELN

R/W

Default

MSELN: BICK2/SDIN3 pin and LRCK2/SDOUT3 pin setting

0: BICK2 pin, LRCK2 pin (default)

1: SDIN3 pin, SDOUT3 pin

Addr Register Name

Sync Domain Select 1

Sync Domain Select 3

Sync Domain Select 4

Sync Domain Select 6

Sync Domain Select 7

Sync Domain Select 8

Sync Domain Select 9

Sync Domain Select 15

Sync Domain Select 16

SDBCK1[2:0]

SDBCK2[2:0]

EXBCK1[2:0]

EXBCK3[2:0]

SDDO2[2:0]

0011

0013

0014

0016

0017

0018

0019

001F

0020

EXBCK2[2:0]

SDDO1[2:0]

SDDO3[2:0]

SDVOL1[2:0]

SDVOL3[2:0]

SDMIXB[2:0]

SDCODEC[2:0]

SDVOL2[2:0]

SDMIXA[2:0]

SDADC1[2:0]

R/W

Default

R/W

000

R/W

000

SDxxxx[2:0]: Clock Sync Domain Setting for Input/Output Port (Table 20, Table 21)

Default: “000” (Not Assigned)

EXBCKx[2:0]: SDINx pin Symchronizing Clock Select (Table 15)

Default: “000” (Not Assigned)

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Addr Register Name

SDOUT1 TDM SLOT1-2 Data Select

SELDO1A[5:0]

SELDO1B[5:0]

SELDO1C[5:0]

SELDO1D[5:0]

SELDO1E[5:0]

SELDO1F[5:0]

SELDO1G[5:0]

SELDO1H[5:0]

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

0035

0036

0037

0038

0039

003A

0045

0046

0047

0048

SDOUT1 TDM SLOT3-4 Data Select

SDOUT1 TDM SLOT5-6 Data Select

SDOUT1 TDM SLOT7-8 Data Select

SDOUT1 TDM SLOT9-10 Data Select

SDOUT1 TDM SLOT11-12 Data Select

SDOUT1 TDM SLOT13-14 Data Select

SDOUT1 TDM SLOT15-16 Data Select

SDOUT2 Output Data Select

SDOUT3 Output Data Select

DAC1 Input Data Select

SELDO2[5:0]

SELDO3[5:0]

SELDA1[5:0]

DAC2 Input Data Select

SELDA2[5:0]

DAC3 Input Data Select

SELDA3[5:0]

VOL1 Input Data Select

SELVOL1[5:0]

SELVOL2[5:0]

SELVOL3[5:0]

SELMIXAI1[5:0]

SELMIXAI2[5:0]

SELMIXBI1[5:0]

SELMIXBI2[5:0]

VOL2 Input Data Select

VOL3 Input Data Select

Mixer A Ch1 Input Data Select

Mixer A Ch2 Input Data Select

Mixer B Ch1 Input Data Select

Mixer B Ch2 Input Data Select

R/W

Default

R/W

00H

SELxxx[5:0]: Data Source Select of Output Port (Table 21)

Default: 00H (ALL0)

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Addr Register Name

Clock Format Setting 1

BCKP1

DCF1[2:0]

BCKP2

DCF2[2:0]

004C

R/W

Default

R/W

000

R/W

000

BCKP1: Relationship of LRCK1 and BICK1 Edges (Table 23)

0: LRCK1 starts on a BICK1 falling edge (default)

1: LRCK1 starts on a BICK1 rising edge

DCF1[2:0]: LRCK1/BICK1 Clock Format Setting (Table 22)

Default: “000” (I²S Mode)

BCKP2: Relationship of LRCK2 and BICK2 Edges (Table 23)

0: LRCK2 starts on a BICK2 falling edge (default)

1: LRCK2 starts on a BICK2 rising edge

DCF2[2:0]: LRCK2/BICK2 Clock Format Setting (Table 22)

Default: “000” (I²S Mode)

Addr Register Name

SDIN1 Digital Input Format

DIEDGEN1

DISL1[1:0]

DILSBE1

DIDL1[1:0]

0050

R/W

Default

R/W

DIEDGEN1: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDIN1

0: LRCK Edge Basis (default)

1: Slot Length Basis

DISL1[1:0]: SDIN1 Data Slot Length Setting (Table 24)

Default: “00” (24bit)

DILSBE1: MSB/LSB Setting of Audio Data in Data Slot of SDIN1

0: MSB (default)

1: LSB

DIDL1[1:0]: Audio Data Word Length Setting of SDIN1 (Table 25)

Default: “00” (24bit)

Addr Register Name

SDIN2 Digital Input Format

DIEDGEN2

DISL2[1:0]

DILSBE2

DIDL2[1:0]

0051

R/W

Default

R/W

DIEDGEN2: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDIN2

0: LRCK Edge Basis (default)

1: Slot Length Basis

DISL2[1:0]: SDIN2 Data Slot Length Setting (Table 24)

Default: “00” (24bit)

DILSBE2: MSB/LSB Setting of Audio Data in Data Slot of SDIN2

0: MSB (default)

1: LSB

DIDL2[1:0]: Audio Data Word Length Setting of SDIN2 (Table 25)

Default: “00” (24bit)

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Addr Register Name

SDIN3 Digital Input Format

DIEDGEN3

DISL3[1:0]

DILSBE3

DIDL3[1:0]

0052

R/W

Default

R/W

DIEDGEN3: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDIN3

0: LRCK Edge Basis (default)

1: Slot Length Basis

DISL3[1:0]: SDIN3 Data Slot Length Setting (Table 24)

Default: “00” (24bit)

DILSBE3: MSB/LSB Setting of Audio Data in Data Slot of SDIN3

0: MSB (default)

1: LSB

DIDL3[1:0]: Audio Data Word Length Setting of SDIN3 (Table 25)

Default: “00” (24bit)

Addr Register Name

DOEDGEN1

DOSL1[1:0]

DOLSBE1

DODL1[1:0]

SDOUT1 Digital Output Format

0055

R/W

Default

R/W

DOEDGEN1: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDOUT1

0: LRCK Edge Basis (default)

1: Slot Length Basis

DOSL1[1:0]: SDOUT1 Data Slot Length Setting (Table 24)

Default: “00” (24bit)

DOLSBE1: MSB/LSB Setting of Audio Data in Data Slot of SDOUT1

0: MSB (default)

1: LSB

DODL1[1:0]: Audio Data Word Length Setting of SDOUT1 (Table 25)

Default: “00” (24bit)

Addr Register Name

DOEDGEN2

DOSL2[1:0]

DOLSBE2

DODL2[1:0]

SDOUT2 Digital Output Format

0056

R/W

Default

R/W

DOEDGEN2: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDOUT2

0: LRCK Edge Basis (default)

1: Slot Length Basis

DOSL2[1:0]: SDOUT2 Data Slot Length Setting (Table 24)

Default: “00” (24bit)

DOLSBE2: MSB/LSB Setting of Audio Data in Data Slot of SDOUT2

0: MSB (default)

1: LSB

DODL2[1:0]: Audio Data Word Length Setting of SDOUT2 (Table 25)

Default: “00” (24bit)

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Addr Register Name

DOEDGEN3

DOSL3[1:0]

DOLSBE3

DODL3[1:0]

SDOUT3 Digital Output Format

0057

R/W

Default

R/W

DOEDGEN3: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDOUT3

0: LRCK Edge Basis (default)

1: Slot Length Basis

DOSL3[1:0]: SDOUT3 Data Slot Length Setting (Table 24)

Default: “00” (24bit)

DOLSBE3: MSB/LSB Setting of Audio Data in Data Slot of SDOUT3

0: MSB (default)

1: LSB

DODL3[1:0]: Audio Data Word Length Setting of SDOUT3 (Table 25)

Default: “00” (24bit)

Addr Register Name

005A SDOUT Phase Setting

SDOPH3 SDOPH2 SDOPH1

R/W

Default

R/W

SDOPH3: High speed mode setting for SDOUT3 in slave mode (Note 41)

0: Normal Mode (default)

1: High speed mode

SDOPH2: High speed mode setting for SDOUT2 in slave mode (Note 41)

0: Normal Mode (default)

1: High speed mode

SDOPH1: High speed mode setting for SDOUT1 in slave mode (Note 41)

0: Normal Mode (default)

1: High speed mode

Addr Register Name

Output Port Enable Setting

SDOUT1E SDOUT2E SDOUT3E

005E

R/W

Default

R/W

SDOUT1E: SDOUT1 Output Enable

0: SDOUT1 pin = “L” (default)

1: SDOUT1 Output Enable

SDOUT2E: SDOUT2 Output Enable

0: SDOUT2 pin = “L” (default)

1: SDOUT2 Output Enable

SDOUT3E: SDOUT3 Output Enable

0: SDOUT3 pin = “L” (default)

1: SDOUT3 Output Enable

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Addr Register Name

Mixer A Setting

SFTA2[1:0]

SFTA1[1:0]

SWPA2[1:0]

SWPA1[1:0]

0060

R/W

Default

R/W

SFTA2[1:0]: Level Adjustment Function Setting for Input2 of Mixer A (Table 34)

Default: “00” (Not Shifted)

SFTA1[1:0]: Level Adjustment Function Setting for Input1 of Mixer A (Table 34)

Default: “00” (Not Shifted)

SWPA2[1:0]: Data Change Setting for Input 2 of Mixer A (Table 35)

Default: “00” (Through)

SWPA1[1:0]: Data Change Setting for Input 1 of Mixer A (Table 35)

Default: “00” (Through)

Addr Register Name

Mixer B Setting

SFTB2[1:0]

SFTB1[1:0]

SWPB2[1:0]

SWPB1[1:0]

0061

R/W

Default

R/W

SFTB2[1:0]: Level Adjustment Function Setting for Input2 of Mixer B (Table 34)

Default: “00” (Not Shifted)

SFTB1[1:0]: Level Adjustment Function Setting for Input1 of Mixer B (Table 34)

Default: “00” (Not Shifted)

SWPB2[1:0]: Data Change Setting for Input 2 of Mixer B (Table 35)

Default: “00” (Through)

SWPB1[1:0]: Data Change Setting for Input 1 of Mixer B (Table 35)

Default: “00” (Through)

Addr Register Name

MIC AMP Gain

MGNL[3:0]

MGNR[3:0]

0062

R/W

Default

R/W

0000

R/W

0000

MGNL[3:0]: MIC Input Lch Gain Setting (Table 40)

Default: 0H (0dB)

MGNR[3:0]: MIC Input Rch Gain Setting (Table 40)

Default: 0H (0dB)

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Addr Register Name

Analog Input Gain Control

ADC1VL

ADC2VR

ADCMV

ADC1VR ADC2VL

MICLZCE MICRZCE

0063

R/W

Default

R/W

ADC1VL: Lch Input Voltage Setting of ADC1 (Table 52)

Default: “0”(2.3Vpp(±2.3Vpp))

ADC1VR: Rch Input Voltage Setting of ADC1 (Table 52)

Default: “0”(2.3Vpp(±2.3Vpp))

ADC2VL: Lch Input Voltage Setting of ADC2 (Table 52)

Default: “0”(2.3Vpp(±2.3Vpp))

ADC2VR: Rch Input Voltage Setting of ADC2 (Table 52)

Default: “0”(2.3Vpp(±2.3Vpp))

ADCMV: Input Voltage Setting of ADCM (Table 52)

Default: “0”(2.3Vpp(±2.3Vpp))

MICLZCE: MIC Gain Zero Crossing Enable for Lch

0: Lch Zero Crossing Detection is OFF (default)

1: Lch Zero Crossing Detection is ON

MICRZCE: MIC Gain Zero Crossing Enable for Rch

0: Rch Zero Crossing Detection is OFF (default)

1: Rch Zero Crossing Detection is ON

Addr Register Name

ADC1 Lch Digital Volume

VOLAD1L[7:0]

0064

0065

0066

0067

0068

ADC1 Rch Digital Volume

ADC2 Lch Digital Volume

ADC2 Rch Digital Volume

ADCM Digital Volume

VOLAD1R[7:0]

VOLAD2L[7:0]

VOLAD2R[7:0]

VOLADM[7:0]

R/W

Default

R/W

30H

VOLAD1L[7:0]: Lch Digital Volume Setting of ADC1 (Table 45)

Default: 30H (0dB)

VOLAD1R[7:0]: Rch Digital Volume Setting of ADC1 (Table 45)

Default: 30H (0dB)

VOLAD2L[7:0]: Lch Digital Volume Setting of ADC2 (Table 45)

Default: 30H (0dB)

VOLAD2R[7:0]: Rch Digital Volume Setting of ADC2 (Table 45)

Default: 30H (0dB)

VOLADM[7:0]: Digital Volume Setting of ADCM (Table 45)

Default: 30H (0dB)

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Addr Register Name

Analog Input Select Setting

ADSD

ADSL

ADMSEL AD1LSEL AD1RSEL

AD2SEL[1:0]

006B

R/W

Default

R/W

ADSD, ADSL: ADC Digital Filter Select (Table 51)

00: Sharp Roll-Off Filter (default)

01: Slow Roll-Off Filter

10: Short Delay Sharp Roll-Off Filter

11: Short Delay Slow Roll-Off Filter

ADMSEL: ADCM Input Pin Select (Table 50)

0: AINMP, AINMN (default)

1: AINMP

AD1LSEL: ADC1 Lch Input Pin Select (Table 42)

0: INP1/INN1 (default)

1: AIN1L

AD1RSEL: ADC1 Rch Input Pin Select (Table 42)

0: INP2/INN2 (default)

1: AIN1R

AD2SEL[1:0]: ADC2 Input Pin Select (Table 49)

Default: “00” (AIN2LP, AIN2LN, AIN2RP, AIN2RN)

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Addr Register Name

ADC Mute & HPF Control

ATSPAD AD1MUTE AD2MUTE ADMMUTE

AD1HPFN AD2HPFN ADMHPFN

006C

R/W

Default

R/W

ATSPAD: ADC Digital Volume Transition Time Setting (Table 46)

0: 4/fs (default)

1: 16/fs

AD1MUTE: ADC1 Soft Mute Enable

0: Soft Mute Disable (default)

1: Soft Mute Enable

AD2MUTE: ADC2 Soft Mute Enable

0: Soft Mute Disable (default)

1: Soft Mute Enable

ADMMUTE: ADCM Soft Mute Enable

0: Soft Mute Disable (default)

1: Soft Mute Enable

AD1HPFN: ADC1 HPF Enable for DC Offset Cancelling

0: HPF Enable (default)

1: HPF Disable

AD2HPFN: ADC2 HPF Enable for DC Offset Cancelling

0: HPF Enable (default)

1: HPF Disable

ADMHPFN: ADCM HPF Enable for DC Offset Cancelling

0: HPF Enable (default)

1: HPF Disable

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Addr Register Name

DAC1 Lch Digital Volume

VOLDA1L[7:0]

VOLDA1R[7:0]

VOLDA2L[7:0]

VOLDA2R[7:0]

VOLDA3L[7:0]

VOLDA3R[7:0]

006D

006E

006F

0070

0071

0072

DAC1 Rch Digital Volume

DAC2 Lch Digital Volume

DAC2 Rch Digital Volume

DAC3 Lch Digital Volume

DAC3 Rch Digital Volume

R/W

Default

R/W

18H

VOLDA1L[7:0]: Lch Digital Volume Setting of DAC1 (Table 53)

Default: 18H (0dB)

VOLDA1R[7:0]: Rch Digital Volume Setting of DAC1 (Table 53)

Default: 18H (0dB)

VOLDA2L[7:0]: Lch Digital Volume Setting of DAC2 (Table 53)

Default: 18H (0dB)

VOLDA2R[7:0]: Rch Digital Volume Setting of DAC2 (Table 53)

Default: 18H (0dB)

VOLDA3L[7:0]: Lch Digital Volume Setting of DAC3 (Table 53)

Default: 18H (0dB)

VOLDA3R[7:0]: Rch Digital Volume Setting of DAC3 (Table 53)

Default: 18H (0dB)

Addr Register Name

DAC Mute & Filter Setting

DSMN

DASD

DASL

ATSPDA DA1MUTE DA2MUTE DA3MUTE

0073

R/W

Default

R/W

ATSPDA: DAC Digital Volume Transition Time Setting (Table 54)

0: 4/fs (default)

1: 16/fs

DA1MUTE: DAC1 Soft Mute Enable

0: Soft Mute Disable (default)

1: Soft Mute Enable

DA2MUTE: DAC2 Soft Mute Enable

0: Soft Mute Disable (default)

1: Soft Mute Enable

DA3MUTE: DAC3 Soft Mute Enable

0: Soft Mute Disable (default)

1: Soft Mute Enable

DSMN: Sampling Clock Setting for Delta Sigma Module of DAC

0: 12.288MHz / 11.2896MHz Fixed (default)

1: fs Based

DASD, DASL: DAC Digital Filter Select (Table 57)

00: Sharp Roll-Off Filter

01: Slow Roll-Off Filter

10: Short Delay Sharp Roll-Off Filter (default)

11: Short Delay Slow Roll-Off Filter

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Addr Register Name

DAC DEM Setting

DEM3[1:0]

DEM2[1:0]

DEM1[1:0]

0074

R/W

Default

R/W

DEM1[1:0]: De-emphasis Filter Setting of DAC1 (Table 58)

00: 44.1kHz

01: OFF (default)

10: 48kHz

11: 32kHz

DEM2[1:0]: De-emphasis Filter Setting of DAC2 (Table 58)

00: 44.1kHz

01: OFF (default)

10: 48kHz

11: 32kHz

DEM3[1:0]: De-emphasis Filter Setting of DAC3 (Table 58)

00: 44.1kHz

01: OFF (default)

10: 48kHz

11: 32kHz

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Addr

[Hex]

0075

0076

0077

0078

0079

007A

VOL1 Lch Digital Volume

VOL1 Rch Digital Volume

VOL2 Lch Digital Volume

VOL2 Rch Digital Volume

VOL3 Lch Digital Volume

VOL3 Rch Digital Volume

VOL1L[7:0]

VOL1R[7:0]

VOL2L[7:0]

VOL2R[7:0]

VOL3L[7:0]

VOL3R[7:0]

R/W

Default

R/W

18H

VOL1L[7:0]: Lch Digital Volume Setting of VOL1 (Table 36)

Default: 18H (0dB)

VOL1R[7:0]: Rch Digital Volume Setting of VOL1 (Table 36)

Default: 18H (0dB)

VOL2L[7:0]: Lch Digital Volume Setting of VOL2 (Table 36)

Default: 18H (0dB)

VOL2R[7:0]: Rch Digital Volume Setting of VOL2 (Table 36)

Default: 18H (0dB)

VOL3L[7:0]: Lch Digital Volume Setting of VOL3 (Table 36)

Default: 18H (0dB)

VOL3R[7:0]: Rch Digital Volume Setting of VOL3 (Table 36)

Default: 18H (0dB)

Addr Register Name

VOL Setting

ATSPVOL

007F

R/W

Default

R/W

ATSPVOL: Digital Volume Transition Speed Setting of VOL (Table 37)

0: 4/fs (default)

1: 16/fs

Addr Register Name

PLLLOCKE

STO Flag Setting 1

0083

R/W

Default

R/W

PLLLOCKE: STO bit Setting of PLL Lock Signal

0: Do Not Output to STO bit (default)

1: Output to STO bit

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Addr Register Name

Power Management 1

PMAD1

PMAD2

PMADM

PMDA1

PMDA2

PMDA3

008A

R/W

Default

R/W

PMAD1: ADC1 Power Management Setting

0: Power Save Mode (default)

1: Normal Operation

PMAD2: ADC2 Power Management Setting

0: Power Save Mode (default)

1: Normal Operation

PMADM: ADCM Power Management Setting

0: Power Save Mode (default)

1: Normal Operation

PMDAx(x=1~3): DAC1~3 Power Management Setting

0: Power Save Mode (default)

1: Normal Operation

Addr Register Name

CRESETN

HRESETN

Reset Control

008C

R/W

Default

R/W

CRESETN: ADC1 and CODEC Reset

0: ADC1 and CODEC Reset (default)

1: Reset Release

CODEC means ADC2, ADC, DAC1, DAC2 and DAC3.

HRESETN: HUB Reset

0: HUB Reset (default)

All ADC1/2, ADCM, DAC1/2/3 and Serial Signal Bus are Reset

1: HUB Reset Release

Read Only Registers

Addr

[Hex]

0102

STO

Status Read Out

Default

STO: STO bit Status Read

0: Error State

1: Normal Operation (default)

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13. Recommended External Circuits

■ Connection Diagram

1. I²C Interface

“H”

“H” or “L”

CSN

I2CFIL

MPREF

1

SDA

SCL

MPWR2

MPWR1

2kΩ

RESET

2kΩ

PDN

CONTROL

AIN1L/INP1

INN1

AIN1R/INP2

INN2

MCKI

SDIN1

SDIN2

CLOCK

2kΩ

SDOUT1

SDOUT2

LRCK1

1

AIN2LP/AIN3L

AIN2LN/AIN4L

AIN2RP/AIN3R

AIN2RN/AIN4R

BICK1

Audio I/F

1

LRCK2/SDOUT3

BICK2/SDIN3

CLKO

1

AIN5L

AIN5R

“L”

TESTI

GNDIN5

1

AK4601 _AINMP/AINM

AINMN

AOUT1L

AOUT1R

AOUT2L

AOUT2R

AOUT3L

AOUT3R

Digital IO 1.8～3.3V

10

TVDD

0.1

Analog +3.3V

AVDD

AVSS

10

0.1

Digital Core 3.3V

10

LVDD

0.1

VREFH

VREFL

10

AVDRV

2.2

6, 20

VCOM

DVSS1/DVSS2

2.2

Figure 73. I²C Interface Connection Example

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2. SPI Interface

CSN

MPREF

1

SCLK

MPWR2

MPWR1

2kΩ

RESET

2kΩ

PDN

CONTROL

AIN1L/INP1

INN1

AIN1R/INP2

INN2

MCKI

SDIN1

SDIN2

SDOUT1

SDOUT2

LRCK1

BICK1

LRCK2/SDOUT3

BICK2/SDIN3

CLKO

CLOCK

2kΩ

1

AIN2LP/AIN3L

AIN2LN/AIN4L

AIN2RP/AIN3R

AIN2RN/AIN4R

Audio I/F

1

AIN5L

AIN5R

“L”

TESTI

GNDIN5

1

AK4601_AINMP/AINM

AINMN

AOUT1L

AOUT1R

AOUT2L

AOUT2R

AOUT3L

AOUT3R

Digital IO 1.8～3.3V

10

TVDD

0.1

Analog +3.3V

AVDD

AVSS

10

0.1

Digital Core 3.3V

10

LVDD

0.1

VREFH

VREFL

10

AVDRV

2.2

6, 20

VCOM

DVSS1/DVSS2

2.2

Figure 74. SPI Interface Connection Example

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■ Peripheral Circuit

1. Ground

AVSS, DVSS1 and DVSS2 should be connected to the same ground. Decoupling capacitors, particularly

capacitors of small capacity, should be placed at positions as close as possible to the AK4601.

2. Reference Voltage

The AVDD voltage controls analog signal range. VCOM is a common voltage of this chip and the VCOM

pin outputs AVDD/2. A 2.2µF capacitor should be connected between the VCOM pin and AVSS.

Do not connect the VCOM pin to any external devices. Digital signal lines, especially clock signal line

should be kept away as far as possible from this pin in order to avoid unwanted coupling into the AK4601.

3. Analog Input

The analog input signal is input to the analog modulator of the AK4601. When AVDD = 3.3V and AVSS =

0.0V, the input voltage range at differential input pin is ±2.30Vpp or ±2.83Vpp (Typ.) and 2.30Vpp or

2.83Vpp (Typ.) at single-ended input pin. The output code format is 2's complements. The internal HPF

removes the DC offset.

After power-down is released, the internal operating point level AVDD/2 occurs on analog input pins of the

AK4601. Concerning the internal operating point formation circuit, each input pin has impedance of 25k

(typ). The pins that are connected to AC coupling capacitors require start-up time (time constant).

The AK4601 samples the analog inputs at 6.144MHz when fs=48kHz. Digital filters remove noise around

from 30kHz to 6.114MHz. The AK4601 includes an anti-aliasing filter (RC filter). This filter attenuates

noises around 6.114MHz ~ 6.144MHz, which are not removed by the digital filters. Therefore no external

low-pass filter is needed in front of the ADC since most of audio signals do not have a large noise around

6.114MHz. However, an external low-pass filter should be connected before the ADC for the signal which

has large out-of-band noise such as D/A converted signals.

The analog power supply to the AK4601 is +3.3V typical. Voltage of AVDD + 0.3V or larger, voltage of

AVSS - 0.3V or smaller, and current of 10mA or larger must not be applied to analog input pins. Excessive

current will damage the internal protection circuit and will cause latch-up, damaging the IC. Accordingly, if

the external analog circuit voltage is ±15V, the analog input pins must be protected from signals which are

equal or larger than absolute maximum ratings.

10k

68p

22u

2.30Vpp / 2.83Vpp

10k

+10V

-10V

10k

Signal

INP*

INN*

2.30Vpp / 2.83Vpp

Figure 75. Input Buffer Circuit Example at fs=48kHz (Differential Input)

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4. Analog Output

The analog output is single-ended and the output signal range is typically 0.86 x AVDD Vpp centered on

VCOM. The digital input data format is two’s compliment. Positive full-scale output corresponds to

7FFFFFFFH (@32bit) input code, Negative full scale is 80000000H (@32bit) and VCOM voltage ideally is

00000000H (@32bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma

modulator is attenuated by an integrated switched capacitor filter (SCF) and a continuous time filter

(CTF).

5. Connection to Digital Circuit

To minimize the noise from digital circuits, the digital output of the AK4601 must be connected to CMOS

or low voltage logic ICs such as 74HC and 74AC for CMOS and 74LV, 74LV-A, 74ALVC and 74AVC for

low voltage logic ICs.

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14. Package

■ Outline Dimensions

48-pin LQFP(Unit: mm)

1.70Max

9.0 ±0.2

7.0 ±0.2

0.13 0.13

1.40 0.05

0.09 0.20

0.5

0.22 0.08

0.10

0° 10°

0.10

0.30 ~ 0.75

■ Material and Lead Finish

Package: Epoxy

Lead frame: Copper

Terminal surface treatment: Soldering (Pb free) plate

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■ Marking

AK4601VQ

XXXXXXX

1) Pin #1 indication

2) Date Code: XXXXXXX(7 digits)

3) Marking Code: AK4601VQ

4) Asahi Kasei Logo

15. Ordering Guide

■ Ordering Guide

AK4601

AKD4601

-40  +85C

48-pin LQFP (0.5mm pitch)

Evaluation Board for the AK4601

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16. Revision History

Date (Y/M/D) Revision Reason

Page Contents

16/03/23

16/12/08

First Edition

Error Correction 5

Figure of PDN pin

I/O pin → Input pin

102

ATSPVOL: Digital Volume Transition Speed

Setting of VOL (Table 37)

0: 1/fs (default) → 4/fs (default)

1: 4/fs → 16/fs

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IMPORTANT NOTICE

0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in

this document without notice. When you consider any use or application of AKM product stipulated in this document

(“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the

Products.

1. All information included in this document are provided only to illustrate the operation and application examples of

AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the

information contained in this document nor grants any license to any intellectual property rights or any other rights of

AKM or any third party with respect to the information in this document. You are fully responsible for use of such

information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY

FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH

INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.

2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels

of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury,

serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities,

equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other

transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices,

elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use

Product for the above use unless specifically agreed by AKM in writing.

3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying

with safety standards and for providing adequate designs and safeguards for your hardware, software and systems

which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human

life, bodily injury or damage to property, including data loss or corruption.

4. Do not use or otherwise make available the Product or related technology or any information contained in this

document for any military purposes, including without limitation, for the design, development, use, stockpiling or

manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction

weapons). When exporting the Products or related technology or any information contained in this document, you

should comply with the applicable export control laws and regulations and follow the procedures required by such

laws and regulations. The Products and related technology may not be used for or incorporated into any products or

systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of

the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion

or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for

damages or losses occurring as a result of noncompliance with applicable laws and regulations.

6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document

shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner

whatsoever, any liability of AKM.

7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of

AKM.

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AK4601VQ [AKM]

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