AK7770EQ [AKM]
Audio DSP with Multi-Channel Audio CODEC; 音频DSP与多声道音频编解码器
| 型号： | AK7770EQ |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Audio DSP with Multi-Channel Audio CODEC |
| 文件： | 总22页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK7770]
AK7770EQ
Audio DSP with Multi-Channel Audio CODEC
GENERAL DESCRIPTION
The AK7770 is a digital signal processor with an integrated 4-channel audio ADC and a 6-channel audio
DAC, as well as an S/PDIF transmitter. It utilizes an enhanced dual bit architecture that results in wide
dynamic range for the ADC, and the advanced multi-bit architecture of the DAC enables wide dynamic
range and low out-of-band noise. Two sample-rate converters are integrated, allowing for operation at
48kHz sampling rate with input rates of 32kHz, 44.1kHz, or 48kHz. Volume control, compression, EQ and
sound processing are performed by the DSP. In addition, delay adjustment up to 70ms is possible for four
output channels through the integrated delay RAM. The AK7770 is packaged in a space-saving 80-pin
LQFP package.
FEATURES
■ DSP
- Data Width: 24-bit (Data RAM F20.4 floating Point)
- Processing Speed: 13.5 ns (1536step/fs; fs = 48kHz)
- Multiplication: 20 x 16 → 36-bit Double precision arithmetic available
- Program RAM: 1536 x 36-bit
- Coefficient RAM: 1536 x 16-bit
- Offset RAM: 64 x 14-bit
- DRAM: 14kword (1word = F16.4 floating point)
- Sample Rate: fs = 48kHz
- Master / Slave operation
■ 4:2 Selector with Input Pre-amp
■ 4ch 24-bit ADC
- 64-times oversampling
- Sample Rate: 48kHz
- S/(N+D): 84dB (fs = 48kHz)
- DR, S/N: 96dB (fs = 48kHz)
- Digital HPF for offset DC cancellation
- Channel independent Digital Volume control (+24/-103dB, 0.5dB step)
- Soft Mute
■ 6ch 24-bit DAC
- 128-times oversampling
- Sample Rate: 48kHz
- S/(N+D): 88dB (fs = 48kHz )
- DR, S/N: 100dB
- Channel independent Digital Volume control (+12/-115dB, 0.5dBstep)
- Soft Mute
- Digital de-emphasis
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[AK7770]
■ Stereo Headphone Amplifier with Volume Control
- DAC3 direct connection
- S/(N+D): 73dB (fs=48kHz)
- S/N: 86dB (fs=48kHz)
- Analog volume control (+0/-50dB,1.0/2.0/4.0dB per step)
- Output power: 22.5mW@16Ω
- No click noise at power ON/OFF
■ Headphone Detection Circuit (denounce circuit)
■ High Tolerance to Clock Jitter
■ Sample Rate Converter
- Dual 2ch SRC
- Input sample rate: 32kHz~48kHz
- Output sample rate: 48kHz fixed
■ DIT
- S/PDIF, IEC958, AES/EBU, EIAJ CP1201
- Output Selector (DIT or Through)
- 24 bit interface format
- 16 bit interface format
■ CMOS Level Digital I/F (for 3.3V)
■ Master Clock Input: 256fs (fs=48kHz)
■ Master Clock Output: 128fs, 192fs, 256fs, 384fs
■ Three Digital Audio Inputs
■ I²C µP I/F
■ Power Supply: +3.3V ±0.3V, +1.8V ±0.1V
■ Temperature Range: -10°C~70°C
■ Package: 80pin LQFP (0.5mm pitch)
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[AK7770]
■ Block Diagram
AOUTL1,AOUTR1 AOUTL2,AOUTR2
VCOM
2
2
HMUTEN
FROL2,FROR2
2
FRIL2,FRIR2
2
HPA
HPL,HPR
2
DAC2
DAC3
DAC1
VREF
HVCOM
HDT
SDINDA1
SDINDA2
SDINDA3
ASEL2[1:0]
ASEL1[1:0]
ADC2
HVDD
VSS2
AINL1,AINR1
2
AINL2,AINR2
2
SDOUTAD2
AVDD
3
3
AINL3,AINR3
2
SDOUTAD1
VSS1
AINL4,AINR4
2
ADC1
DVDD
DVDD18
VSS3
4
3
4
4
FRIL1,FRIR1
2
FROL1,FROR1
2
LFLT
XTO
pull down
Hi-z
Open Drain
XTI
CLKGEN
External system clock 0
internal system clock 0
Internal system clock 3
CLKOE
MCLKO
CLKO
SELCLK
BITCLKO
LRCLKOE
BITCLKO
MBITCLKO
LRCLKO
MLRCLK
O
1
0
SELCKDIT
SELDITI[1:0]
SDIN3
CLK3
3
2
1
DIT
DIT
SELTX[1:0]
DITO
0
0
1
2
3
MCLK3
TX
DIV
BITCLK3
LRCLK3
DOUT5
DIN4
DIN3
SELO3[1:0]
SELO2[1:0]
DOUT4
DOUT3
External system clock 3
3
2
1
0
OUT3
OUT2
SDOUT3
SDOUT2
3
2
1
0
SRCO2
SDIN2
CLK2
SRCI2
DIN2
SRCO2
DOUT2
DOUT1
SELO1[1:0]
SRC
SRCMCK2
3
2
1
0
OUT1
MCLK2
SDOUT1
TESTI3
DIV
BITCLK2
LRCLK2
SRCBICK2
SRCLRCK2
UNLOCK2
SO
External system clock 2
SDIN1
MICIF
SRCO1
CAD1
SCL
SRCO1
SRCI1
DIN1
CAD0
SDA
External system clock 1
CLK1
SRC
CLK0
*
MCLK1
SRCMCK1
HPEN
DIV
WDT
CRC
HPEN
BITCLK1
LRCLK1
DSP
SRCBICK1
Detect
WDTEN
HP
"L"
SRCLRCK1
UNLOCK1
STO
STATUS
CRCE
INITRSTN
LOCK2E
TESTI2
CKM[1:0]
TESTI
ROM
CONT
2
LOCK1E
Figure 1. Block Diagram
Figure 1shows a simplified diagram of the AK7770, which is not the perfect same as the actual circuit diagram.
MS0699-E-01-PB
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[AK7770]
DLP0,DLP1
DLRAM
CP0,CP1
DP0,DP1
OFREG
14kw × 20bit
DRAM
CRAM
64w X 14bit
1536w × 24bit
1536w × 16bit
CBUS(16bit)
DBUS(24bit)
Micon I/F
MPX16
X
MPX20
Control
Serial I/F
PRAM
Y
DEC
1536w × 36bit
Multiply
16bit×20bit→ 36bit
PC
Stack : 5level(max)
TMP 8×24bit
24bit
36bit
PTMP(LIFO) 6×24bit
MUL
DBUS
SHIFT
40bit
40bit
2×24bit
2×24bit
2×24bit
2×24bit
DIN4
A
B
DIN3
DIN2
DIN1
ALU
40bit
Overflow Margin: 4bit
40bit
~
DR0
3
2×24/20/16bit
2×24/20/16bit
2×24bit
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
40bit
Over Flow Data
Generator
2×24bit
2×24bit
Division
20÷20→20
Peak Detector
Figure 2. AK7770 DSP Block Diagram
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[AK7770]
■ Ordering Information
AK7770EQ
-10 ∼ +70°C
80pin LQFP (0.5mm pitch)
AKD7770
Evaluation board
■ Pin Assignment
SDA
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
AOUTR1
AOUTL1
DVDD18
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS1
AVDD
VSS3
DVDD
SCL
FRIR2
FROR2
CAD0
FROL2
FRIL2
CAD1
SDIN2
BITCLK2
CLK2
AINR1
AINL1
80 pin LQFP
AINR2
LRCLK2
SDIN1
BITCLK1
CLK1
AINL2
AINR3
AINL3
AINR4
AINL4
VSS1
(TOP VIEW)
LRCLK1
DVDD18
VSS3
DVDD
XTI
VCOM
AVDD
FROR1
XTO
pin
Input
Output
I/O
Power
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[AK7770]
PIN FUNCTION
No.
1
2
Pin name
FRIR1
FRIL1
I/O
I
I
Function
Rch Feedback Resistance Input Pin for ADC1
Lch Feedback Resistance Input Pin for ADC1
Lch Feedback Resistance Output Pin for ADC1
At initial reset, this pin goes Hi-Z.
Classification
Analog
3
FROL1
O
4
LFLT
O
Loop Filter Pin.
Connect a 10nF cap to AVDD. The output is AVDD at initial reset
Analog Power Supply Pin 3.3V (typ)
Analog Ground Pin 0V (connected to silicon substrate)
5
6
AVDD
VSS1
-
-
Analog power
supply
7
TESTI
I
Test Pin (Internal pull-down)
Connect to GND.
Test
Mode choice
8
CKM [0]
I
Clock Mode Selection Pin
Connect to GND.
9
10
HMUTEN
INITRSTN
I
I
Headphone Amplifier Mute Pin
Headphones
Reset
Reset Pin (for initialization)
Use to initialize the AK7770.
Test Pin
11
TEST2
I
Test
Connect to GND.
12
13
14
15
DVDD18
VSS3
DVDD
-
-
-
Digital Power Supply Pin 1.8V(typ)
Digital Ground Pin 0V
Digital Power Supply Pin 3.3V(typ)
Left/right Clock Output Pin
Digital power
supply
LRCLKO
O
System clock
The output in initial reset is “L”.
16
17
18
19
20
21
CLKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
XTO
O
O
O
O
O
O
Clock Output Pin
The output in initial reset is “L”.
Bit Clock Output Pin
The output in initial reset is “L”.
Serial Data Output 1 Pin
The output in initial reset is “L”.
Serial Data Output 2 Pin
The output in initial reset is “L”.
Serial Data Output 3 Pin
The output in initial reset is “L”.
Crystal Oscillator Output Pin
Serial data
A system clock
Connect a crystal oscillator between the XTI pin and XTO pin. Leave open
when using an external clock source. The output in initial reset is
undetermined.
22
XTI
I
Crystal Oscillator Input Pin
Connect a crystal oscillator between the XTI pin and XTO pin. Input an
external clock into the XTI pin when not using a crystal oscillator.
Digital Power Supply Pin 3.3V(typ)
23
24
25
DVDD
VSS3
-
-
-
Digital power
supply
Digital Ground Pin 0V
DVDD18
Digital Power Supply Pin 1.8V(typ)
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[AK7770]
No.
26
Pin name
LRCLK1
CLK1
I/O
Function
Classification
I
I
Left/Right Clock Input 1 Pin
Master Clock 1 Pin
System clock
27
28
29
30
BITCLK1
SDIN1
I
I
I
Bit Clock 1 Pin
Serial Data Input 1 Pin
Left/Right Clock Input 2 Pin
Serial data
LRCLK2
System clock
31
32
33
34
35
36
CLK2
BITCLK2
SDIN2
CAD1
I
I
I
I
I
I
Master Clock 2 Pin
Bit Clock 2 Pin
Serial Data Input 2 Pin
I2C Bus Address Pin 1
I2C Bus Address Pin 0
I2C Clock Pin
I2C interface
I2C interface
I2C interface
CAD0
SCL
37
38
DVDD
VSS3
-
-
-
Digital Power Supply Pin 3.3V(typ)
Digital Ground Pin 0V
Digital power
supply
39
40
DVDD18
SDA
Digital Power Supply Pin 1.8V(typ)
I/O I2C Bus Data Clock Pin
I2C interface
Headphones
Status
SDA goes to “Hi-Z” during initial reset.
41
42
HPEN
STO
O Headphone Detect Output Pin
Initial reset for headphone search is determined by the state of HDT
O Status Output Pin
When HDT = “H”, STO = “L”
When HDT = “L”, STO = “H”
The output in initial reset is “H”
S/PDIF transmitter Output Pin
43
TX
O
TX
S/PDIF data is output when SELTX [1:0] bit= “00”. “L” during initial rest.
44
45
46
47
48
49
50
DVDD
VSS3
-
-
-
I
I
I
I
Digital Power Supply Pin 3.3V(typ)
Digital Ground Pin 0V
Digital Power Supply Pin 1.8V(typ)
Serial Data Input 3 Pin
Bit Clock 3 Pin
Digital power
supply
DVDD18
SDIN3
Serial data
BITCLK3
CLK3
System clock
Master Clock 3 Pin
LRCLK3
Left/Right Clock 3 Pin
Clock Mode Selection Pin
Connect to GND.
Test Pin
51
52
CKM [1]
TESTI3
I
I
Mode selection
Test
This pin must be connected to DVDD.
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[AK7770]
No. Pin name I/O
Function
Classification
53
HDT
I
Headphone Detection Pin
Headphone Rch Output Pin
Output is VSS2 at initial reset
Headphones
54
HPR
O
Headphones
Analog power
supply
55
HVDD
-
Headphone Power Supply Pin 3.3V(typ)
Headphone Common Voltage Output Pin
56 HVCOM
O
Connect a of 1μF cap to VSS2. Do not use for an outside circuits. Output at Headphones
initial reset is VSS2
Analog power
57
58
VSS2
HPL
-
Headphone Ground Pin 0V
supply
Headphone Lch Output Pin
Output is VSS2 at initial reset
DAC2 Rch Output Pin
Output at initial reset is VSS1
DAC2 Lch Output Pin
Output at initial reset is VSS1
DAC1 Rch Output Pin
Headphone
output
O
O
O
O
O
-
59 AOUTR2
60 AOUTL2
61 AOUTR1
62 AOUTL1
Analog output
Output at initial reset is VSS1
DAC1 Lch Output Pin
Output at initial reset is VSS1
Analog power
supply
Analog power
supply
63
64
65
VSS1
AVDD
FROR2
Analog Ground Pin 0V (connected to silicon substrate)
Analog Power Supply Pin 3.3V (typ)
-
ADC2 Rch Feedback Resistance Output Pin
The output at initial reset is Hi-Z
O
Analog output
66
67
FRIR2
FRIL2
I
I
ADC2 Rch Feedback Resistance Input Pin
ADC2 Lch Feedback Resistance Input Pin
Analog input
Analog input
ADC2 Lch Feedback Resistance Input Pin
The output at initial reset is Hi-Z.
ADC Rch Single-ended Input 1 Pin
ADC Lch Single-ended Input 1 Pin
ADC Rch Single-ended Input 2 Pin
ADC Lch Single-ended Input 2 Pin
ADC Rch Single-ended Input 3 Pin
ADC Lch Single-ended Input 3 Pin
ADC Rch Single-ended Input 4 Pin
ADC Lch Single-ended Input 4 Pin
68
FROL2
O
Analog output
Analog input
69
70
71
72
73
74
75
76
AINR1
AINL1
AINR2
AINL2
AINR3
AINL3
AINR4
AINL4
I
I
I
I
I
I
I
I
Analog power
supply
77
VSS1
-
Analog Power Supply Pin 0.0V
Analog Common Voltage Output Pin
Output at initial reset is VSS1. Connect capacitors of 0.1uF and 2.2uF
between this pin and VSS1. No external circuits should be connected to
this pin.
78
VCOM
O
Analog output
Analog power
supply
79
80
AVDD
FROR1
-
Analog Power Supply Pin 3.3V (typ)
Rch Feedback Resistance Output Pin for ADC1
The output in initial reset is Hi-Z
O
Analog output
Note 1. Do not leave digital input pins floating.
Note 2. When analog input pins (AINL1-4 pins, AINR1-4) are not used, leave them open.
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[AK7770]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Pin Name
Setting
These pins should be open.
FRIR1-2, FRIL1-2, FROL1-2, FROR1-2, XTO,
AOUTL1-2, AOUTR1-2, AINL1-4, AINR1-4
LRCLKO,CLKO, BITCLKO, SDOUT1-3, HPEN, HPR, These pins should be open.
HPL
Digital
TESTI2, CLK1-3, BITCLK1-3, LRCLK1-3 SDIN1-3,
These pins should be connected to VSS3.
HDT
HMUTEN
This pin should be connected to DVDD.
ABSOLUTE MAXIMUM RATINGS
(VSS1 = VSS2 = VSS3=0V: Note 3)
Parameter
Power supply voltage
Analog
Symbol
min
max
Units
AVDD
HVDD
DVDD
DVDD18
IIN
-0.3
-0.3
-0.3
-0.3
-
4.3
4.3
4.3
2.5
±10
V
V
V
V
mA
Analog
Digital
Digital
Input current (except power supply pins)
Analog input voltage
AINL1~AINL4, AINR1~AINR4
FRIL1, FRIL2, FRIR1, FRIL2
Digital input voltage
Ambient operating temperature
Storage temperature
VINA
V
-0.3
AVDD+0.3
VIND
Ta
Tstg
-0.3
-10
-65
DVDD+0.3
V
°C
°C
70
150
Note 3. All voltages referred to ground. Connect VSS1, VSS2, VSS3 to the same ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OERATING CONDITIONS
(VSS1 = VSS2 = VSS3=0V: Note 3)
Parameter
Supply
voltage
Symbol
AVDD
HVDD
DVDD
DVDD18
min
3.0
3.0
3.0
1.7
typ
3.3
3.3
3.3
1.8
max
3.6
3.6
3.6
1.9
Units
V
V
V
V
Analog
Analog
Digital
Digital
Difference
Difference
Difference
HVDD-AVDD
HVDD-DVDD
AVDD-DVDD
-0.3
-0.3
-0.3
0
0
0
+0.3
+0.3
+0.3
V
V
V
Note 4. The power supply sequence for AVDD HVDD, DVDD, DVDD18 is not critical but all power supplies must be
On before start operating the AK7770.
Note 5. Do not turn off the power supply of the AK7770 with the power supply of the surrounding device turned on.
DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and
SCL pins.)
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
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[AK7770]
ANALOG CHARACTERISTICS
■ ADC1/2
(Ta=25 °C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V; Signal frequency = 1kHz;
Measurement bandwidth =20Hz~20kHz , fs=48kHz fs; SRC reset; unless otherwise specified)
Parameter
Pre-AMP
min
10
typ
max
30
Units
kΩ
dB
Feedback Resistance
S/(N+D)
(Note 6)
(Note 6)
99
105
S/N
(A-weighted)
dB
Load Capacitance
Resolution
20
24
pF
Bits
Pre-AMP Dynamic characteristics
S/(N+D) fs = 48kHz (-1dBFS)
Dynamic range fs = 48kHz (A-weighted)
74
88
84
96
dB
dB
+
ADC1
ADC2
(Note 7, Note 8)
S/N
fs = 48kHz (A-weighted)
(Note 7)
(Note 9)
85
85
96
100
dB
dB
Interchannel Isolation( (f=1kHz)
DC Accuracy
Gain mis-match between channels
Analog input
Input voltage
0.1
2.2
0.3
dB
ADC1
ADC2
2.05
2.35
Vp-p
Note 6. Value measured with an input resistance of 47kΩ and a feedback resistance of 16kΩ with a 2Vrms input voltage.
Note 7. The value measured through the pre-amp and ADC with an input resistance of 47kΩ and a feedback resistance of
16kΩ with a 2Vrms input voltage.
Note 8. S/(N+D) with an input signal of -60dBFS
Note 9. Isolation between AINL1-4, AINR1-4 with a -1dBFS input signal.
Note 10. When the SRC on DIT operate asynchronously, the performance may be degraded.
■ DAC1/2
(Ta= 25°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V;
Signal frequency = 1kHz; Measurement bandwidth =20Hz~20kHz, fs=48kHz fs; SRC reset; unless otherwise
specified)
Parameter
DAC1
min
typ
max
24
Units
Bits
Resolution
DAC2
Dynamic characteristics
S/(N+D)
(0 dBFS)
(Note 11)
78
92
92
90
88
dB
dB
dB
dB
Dynamic range (A-weighted)
S/N (A-weighted)
100
100
100
Interchannel Isolation (f=1kHz) (Note 12)
DC Accuracy
Gain mis-match between channels
Analog output
Output voltage
Load resistance
Load capacitance
0.2
0.5
2.34
30
dB
(Note 13)
2.02
5
2.18
Vp-p
kΩ
pF
Note 11. S/(N+D) with a -60dBFS input signal
Note 12. Isolation between Lch-Rch between each DAC
Note 13. Full scale output voltage
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[AK7770]
■ DAC3 + HP Amp
(Ta=25°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V;
Signal frequency = 1kHz; Measurement bandwidth =20Hz~20kHz , fs=48kHz fs; SRC reset; fs=48kHzs)
Parameter
min
typ
max
Units
Analog Volume Control Characteristics OPGA):
Gain
Maximum (OPGA[4:0] bits= “1FH”)
Minimum (OPGA[4:0] bits= “01H”)
+0dB ∼ -16dB
-16dB ∼ -38dB
-38dB ∼ -50dB
-
-
+0
-50
1
-
-
-
-
-
dB
dB
dB
dB
dB
Step size
0.1
0.1
-
2
4
Headphone-Amp Characteristics: DAC → HPL/HPR pins, RL=16Ω
Output Voltage
S/(N+D)
S/N
Inter channel Isolation
Inter channel Gain Mismatch
Load Resistance
1.53
1.7
73
86
80
0.1
-
1.87
-
-
-
0.5
-
Vpp
dB
dB
dB
dB
Ω
63
80
60
-
16
-
(−3dBFS)
(A-weighted)
(RL, Figure 3)
(C1, Figure 3)
Load Capacitance
Load Capacitance
-
-
30
300
pF
pF
(C2, Figure 3)
-
Measurement
Point
HPL pin
HPR pin
HP-Amp
47μF
−
+
+
C1
C2
0.22μF
10Ω
RL
Figure 3. Headphone amplifier output circuit
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[AK7770]
■ SRC (SRC1, SRC2)
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V;
Input signal frequency = 1kHz; measurement bandwidth = 20Hz to FSO/2, fs=48kHz)
Parameter
Resolution
Input Sample Rate
Output Sample Rate
Symbol
min
typ
max
Units
Bits
kHz
kHz
24
48
-
FSI
FSO
32
-
48
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/32kHz
-112
-112
dB
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/32kHz
113
113
dB
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=48kHz/32kHz
Ratio between Input and Output Sample Rate
115
dB
-
FSO/FSI
0.98
1.5
DC CHARACTERISTICS
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1 = VSS2 = VSS3=0V)
Parameter
High level input voltage
Low level input voltage
SCL, SDA high level input voltage
SCL, SDA low level input voltage
HDT high level input voltage
HDT low level input voltage
High level output voltage Iout=-100μA
Low level output voltage Iout=100μA
(Note 15)
Symbol
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
min
80%DVDD
typ
max
Units
(Note 14)
(Note 14)
V
V
V
V
V
V
V
V
20%DVDD
30%DVDD
45%HVDD
0.5
70%DVDD
85%HVDD
DVDD-0.5
SDA low level output voltage Iout=3mA
VOL
Iin
Iid
0.4
±10
V
Input leakage current
(Note 16)
μA
μA
μA
Input leakage current pull-down pin (Note 17)
Input leakage current XTI pin
22
26
Iix
Note 14. SCL, SDA and HDT pins are not included.
Note 15. The SDA pin is not included
Note 16. Pull-down pins and the XTI pin are not included.
Note 17. Pull-down pins (Typ 150k) and TESTI
[Description rule]
Regarding the input/output levels in the text, the low level will be represented as “L”, and the high level as “H”.
In principle, “0” and “1” will be used to represent the bus (serial/parallel) such as registers.
##h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)
MS0699-E-01-PB
2008/06
- 12 -
[AK7770]
POWER CONSUMPTION
(Ta=25°C; AVDD=HVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V); DVDD18=1.7~1.9V(typ=1.8V, max=1.9V);
VSS1= VSS2 = VSS3=0V)
Parameter
min
typ
max
Units
Power Supply
Power supply electric current
Normal Operation
AVDD
HVDD
DVDD
75
6
5
-
-
-
mA
mA
mA
mA
mA
DVDD18 (Note 18)
AVDD+HVDD+DVDD
Reset (INITRSTN pin = “L” reference data)
58
85
120
AVDD+HVDD+DVDD+DVDD18 (Note 19)
2
-
mA
Note 18. DVDD18 value varies with use frequency and DSP program contents.
Note 19. This is a reference value when using a crystal oscillator.
Since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly
according to the crystal type and the external circuit. This is a “reference data” only.
DIGITAL FILTER CHARACTERISTICS
■ ADC1/2
(Ta=-10°C ~70°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V; fs=48kHz; Note 20)
Parameter
PassBand (±0.1dB)
(-0.2dB)
(-3.0dB)
Stopband
Passband Ripple
Stop band attenuation
(Note 22, Note 23)
Group Delay deviation
Group Delay (Ts=1/fs)
Symbol
min
0
typ
max
18.9
Units
kHz
kHz
kHz
kHz
dB
(Note 21)
PB
20.0
23.0
SB
PR
28
68
(Note 21)
±0.04
0
SA
dB
∆GD
GD
μs
Ts
16
Digital filter + analog filter
Amplitude characteristic
20Hz~20.0kHz (Note 24)
±0.5
dB
Note 20. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high
pass filter is not included.
Note 21. The passband is from DC to 18.9kHz when fs=48kHz.
Note 22. Attenuation frequency is 48kHz to 3.044MHz when fs=48kHz.
Note 23. When fs = 48kHz, the analog modulator samples the input signal at 3.072MHz. There is no attenuation of an
input signal in band (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3…) of integer times the sampling frequency of the
digital filter.
Note 24. Value through Pre-Amp and ADC. External input resistance is 47kΩ, and feedback resistance is 16kΩ.
MS0699-E-01-PB
2008/06
- 13 -
[AK7770]
■ DAC1-3
(Ta=-10°C ~70°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V; fs=48kHz;
DEM=OFF)
Parameter
Passband (±0.05dB)
(-6.0dB)
Stopband
Passband ripple
Stopband Attenuation
Group delay (Ts=1/fs) (Note 26)
Digital filter + analog filter
Amplitude characteristic
20Hz~20.0kHz
Symbol
min
0
typ
max
21.7
Units
kHz
kHz
kHz
dB
(Note 25)
(Note 25)
PB
24
SB
PR
SA
GD
26.2
64
±0.01
dB
Ts
24
±0.5
dB
Note 25. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents
PB=0.4535 * fs (@ -0.05dB), and SB=0.5465 * fs, respectively.
Note 26. The digital filter’s delay is calculated as the time from setting data into the input register until an analog signal is
output.
■ SRC1/2
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V)
Parameter
Symbol
min
0
0.5417FSI
typ
max
0.4583FSI
Units
kHz
kHz
dB
PB
SB
PR
Passband -0.01dB
Stop Band
Passband ripple
(0.980≤FSO/FSI≤1.500)
(0.980≤FSO/FSI≤1.500)
± 0.01
Stop band attenuation
Group Delay (Ts=1/fs)
SA
GD
102.2
dB
Ts
(Note 27)
56
Note 27. SRC delay time is calculated from the start of SRCLRCK just after data input to the start of LRCLKO just after
data output, when there is no phase difference between SRCLRCK and LRCLKO.
MS0699-E-01-PB
2008/06
- 14 -
[AK7770]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V)
Parameter
Sysmbol
Min
typ
max
Units
XTI
a) with a crystal oscillator
fXTI
-
12.288
50
-
MHz
b) with an external clock
Duty cycle ratio
40
60
%
fXTI
fCK
11.0
12.4
MHz
2.0
40
256
8
12.288
50
50
60
MHz
%
CLK1, CLK2 Frequency
Duty cycle ratio
(Note 28)
Clock speed
1024
48.4
fs
fs
48
kHz
LRCLK1, LRCLK2 Frequency
(Note 29)
BITCLK1, BITCLK2 Frequency
High level width
tBCLKH
tBCLKL
150
150
ns
ns
Low level width
fCK
11.0
40
12.288
50
50
60
MHz
%
CLK3 Frequency
Duty cycle ratio
Clock speed
LRCLK3 Frequency
BITCLK3 Frequency
High level width
Low level width
(Note 28)
256
1024
fs
fs
43
48
48.4
kHz
(Note 29)
tBCLKH
tBCLKL
150
150
ns
ns
Note 28. CLKn and LRCLKn must occur in the same period, but phase matching is not critical.
Note 29. The sample rate must match LRCLK.
■ Reset
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V)
Parameter
Symbol
Min
typ
max
Units
INITRSTN
(Note 30)
tRST
600
ns
Note 30. Power supply must be up and a master clock must be present before initializing reset.
MS0699-E-01-PB
2008/06
- 15 -
[AK7770]
■ Audio System Interface
1. SDIN1~SDIN3, SDOUT1~SDOUT3
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Input
Delay time from BITCLKn “↑”to LRCLK
Delay time from LRCLKn to BITCLKn “↑”
Serial data entry latch setup time
(Note 31)
(Note 31)
tBLRD
tLRBD
tBSIDS
tBSIDH
20
20
80
80
ns
ns
ns
ns
Serial data entry latch hold time
Output
BITCLKO frequency
BITCLKO duty cycle ratio
Delay time from BITCLKO “↓” to LRCLKO
Delay time from LRCLKO to SDOUTn (Only MSB)
Delay time from BITCLKO to SDOUTn
fBCLK
64
50
fs
%
ns
ns
ns
tMBL
tLRD
tBSOD
-20
40
80
80
SDINn → SDOUTn
(Note 32)
Delay time from SDINn to SDOUTn
tIOD
50
ns
Note 31. BITCLKn “↑” must not occur at the same time as LRCKn edge
Note 32. SDIN1 → SDOUT1: control register setting SELO1[1:0]= “11”, OUT1E=1
SDIN2 → SDOUT2: control register setting SELO2[1:0]= “11”, OUT2E=1
SDIN3 → SDOUT3: control register setting SELO3[1:0]= “11”, OUT3E=1
MS0699-E-01-PB
2008/06
- 16 -
[AK7770]
■ Microcontroller Interface (I2CBUS Interface)
(Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1= VSS2 = VSS3=0V)
Parameter
Symbol
min
typ
max
Unit
I2C Timing
SCL clock frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first Clock pulse)
Clock Low Time
tBUF
tHD:STA
1.3
0.6
μs
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
0.9
0.1
0.3
0.3
tF
tSU:STO
0.6
0
Pulse Width of Spike Noise Suppress By Input Filter tSP
Capacitive load on bus Cb
50
400
Note 33. I2C is a registered trademark of Philips Semiconductors.
MS0699-E-01-PB
2008/06
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[AK7770]
■ Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
1/fs
1/fs
ts=1/fs
LRCLKn
VIH
VIL
n = 1, 2, 3
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
VIL
BITCLKn
n = 1, 2, 3
tBCLKH
tBCLKL
Figure 4. System Clock
INITRSTN
tRST
VIL
Figure 5. Reset
MS0699-E-01-PB
2008/06
- 18 -
[AK7770]
LRCLKn
LRCLKO
50%DVDD
tMBL tMBL
tLRBD
tBLRD
tLRD
BITCLKn
BITCLKO
50%DVDD
50%DVDD
50%DVDD
tBSOD
SDOUT*
tBSIDS
tBSIDH
SDIN*
SDIN*=SDIN1, SDIN2, SDIN3
SDOUT*=SDOUT1, SDOUT2, SDOUT3
Figure 6. Audio System Interface
VIH
VIL
SDA
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
VIL
SCL
tHD:STA
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
Stop
Figure 7. Microcontroller Interface (I2C bus)
MS0699-E-01-PB
2008/06
- 19 -
[AK7770]
PACKAGE
80-pin LQFP
(Unit: mm )
14.0±0.2
12.0±0.2
60
41
61
40
80
21
1
20
0° ~ 10°
0.20±0.1
M
0.50
0.08
1.25TYP
0.50±0.2
0.10
■ Materials and lead Specification
Package:
Epoxy
Copper
Soldering plate (Pb free)
Lead frame:
Lead-finish:
MS0699-E-01-PB
2008/06
- 20 -
[AK7770]
MARKING
AKM
AK7770EQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7digits)
3) Marking Code: AK7770EQ
4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
08/01/08
Revision Reason
Page
15
Contents
00
First Edition
SWITCHING CHARACTERISTICS
■System Clock
08/06/24
01
Error Correct
CLK1, CLK2 Frequency; 11.0 → 2.0
MS0699-E-01-PB
2008/06
- 21 -
[AK7770]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
Thank you for your access to AKEMD products information.
More detail product information is available, please contact our
sales office or authorized distributors.
MS0699-E-01-PB
2008/06
- 22 -
相关型号：
AK7832AB
Audio Amplifier, 2W, 2 Channel(s), 1 Func, PBGA24, 2.50 X 2.50 MM, 0.50 MM PITCH, WLCSP-24
AKM
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