AK8810A [AKM]
Color Signal Encoder, CMOS, PQFP44, PLASTIC, LQFP-44;
| 型号： | AK8810A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Color Signal Encoder, CMOS, PQFP44, PLASTIC, LQFP-44 编码器 商用集成电路 |
| 文件： | 总31页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHIKASEI
[AK8810A]
AK8810A
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The AK8810A Digital video encoder is suitable for a digital broadcasting STB and a DVD player.
ITU-R601 Format Y,Cb,Cr is converted into NTSC or PAL composite signal simultaneously with Y/C
(S-video). AK8810A supports Macrovision Copy Protection Rev.7.01 , Closed Captioning line 21 and
284 and NTSC line 20 Video Blanking ID. These functions are controlled by high speed I2C interface.
FEATURES
{ NTSC-M, PAL-B,D,G,H,I,M,N encoding.
{ Simultaneous Composite and S-Video output
{ CCIR-656 4:2:2 8-bit Parallel Input
{ EAV, SAV Decoding
{ Master/Slave Operation
{ Digital Field Sync I/O
{ Digital Vertical/Horizontal Sync I/O
{ Y filtering
{ C filtering
x2 oversampling
x4 oversampling & sin(x)/x correction
{ Single 27MHz Clock (The polarity could be inverted by SYSINV pin)
{ Triple 10 bit DAC
{ IIC Interface (400kHz)
{ Closed caption encoding (NTSC: line 21,284-SMPTE PAL: line 21,334-CCIR)
{ Supports Macrovision Copy Protection Rev. 7.01*
{ VBID, CGMS (EIAJ CPR-1024:)
{ On-chip Color Bar generator
{ 5V only, CMOS Monolithic
{ 44pin LQFP Package
AKM reserves the right to modify this product without notice.
This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual rights.
The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is
intended for home and other limited pay-per -view use only, unless otherwise authorized in written by Macrovision.
Reverse engineering or disassembly is prohibited.
M0036-E-00
1
1998/09
ASAHI KASEI
[AK8810A]
M0036-E-00
2
1998/09
ASAHI KASEI
44pin LQFP
[AK8810A]
PIN LAYOUT
M0036-E-00
3
1998/09
ASAHI KASEI
[AK8810A]
PIN/FUNCTION
Num
Pin Name
I/O
I
Description
1,2,3
4,6,7
8,9
D7 - D0
27MHz 8-Bit 4:2:2 multiplexed Y,Cb,Cr Data Input.
For CCIR-656 format, AK8810A decodes EAV and SAV.
For non-CCIR-656 format (without EAV/SAV) AK8810A
operates in Master or Slave mode.
30
SYSCLK
I
27MHz Clock Input. The polarity could be inverted by
SYSINV.
28
41
SYSINV
/RESET
I
I
Connects to “L “or “H”. “L” sets normal clock polarity.
After this pin becomes “L”, AK8810A starts the internal
initializing sequence at the rising edge of the first
SYSCLK. (Width of the reset pulse” L” needs minimum
10 SYSCLK cycles.)
After initializing sequence, AK8810A is set NTSC, CCIR-
656 decoding mode. All DAC Off.
16
15
FID
/VSYNC
I/O
I/O
Show the relation between MPEG stream and data.
Either of FID or VSYNC selected by the register.
For CCIR-656 decode mode, this pin is output .
For non-CCIR-656 decode mode, I/O depends on the
device operation mode.( Master or Slave)
FID shows that “L” is odd field and ”H” is even field.
HSYNC
Show the relation between MPEG stream and data.
For CCIR-656 decode mode, this pin is output.
For non-CCIR-656 decode mode, I/O depends on the
device operation mode.(Master or Slave)
10
11
SCL
I
I/O
I
Serial interface clock
SDA
SELA
Serial interface data
12
Connects to “L “or “H”. The slave address is following
“L”:40H “H”:42H
25
VREFOUT
O
Output of the Internal Vref. Terminate with 0.1F or more
capacitance.
26
27
I
VREFIN
IREF
Input of the Reference Voltage
O
The currents flow this pin adjusts the full-scale output
current of the DAC.
22
20
18
5
O
O
COMPOSITE
CHROMA
LUMA
Output of Composite Video signal
Output of the C signal
O
I
Output of Luminance Signal
Test pin. Grounded for normal operation
Analog +5V
TEST
19,24
AVDD
P
P
31,40
13
DVDD
PVDD
Digital +5V
21,23
17
AVSS,
BVSS
G
G
Analog Ground
Digital Ground
29,42
14
DVSS,
PVSS
*
PD[9:0]
NC Test pin. Left Open
4
Test pin * 32,33,34,35,36,37,38,39,43,44
M0036-E-00
1998/09
ASAHI KASEI
[AK8810A]
ELECTRICAL CHARACTERISTICS
Maximum Ratings
Parameter
Min
-0.3
Max
6.5
Units
V
Supply Voltage (VDD)
DVDD, PVDD, AVDD
Input Pin Voltage (Vin)
-0.3
VDD+0.3
±10
V
Input Pin Current (Iin)
Analog Reference Current (IREF)
Analog Output Current
Power Dissipation
-
-
-
mA
mA
mA
mW
°C
0.35
11
1000
125
Storage Temperature
-40
(Note) When all grand pins (DVSS,PVSS,BVSS,AVSS) are set to 0V.
Recommended Operating Conditions
Parameter
Min
4.5
-10
Typ.
5
Max
5.5
70
Units
V
Supply Voltage (VDD)
Operating Temperature
°C
M0036-E-00
5
1998/09
ASAHI KASEI
[AK8810A]
DC Characteristic
Parameter
(Power Supply:5V Temperature:25°C)
Symbol
Min
2.2
Typ
Max
Units
Conditions
VIH
VIL
IL
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input leak Current
Digital Output High Voltage
Note1)
Note1)
0.7
±10
µA
V
Note1)
VOH
2.8
2.5
IOH=-1mA Note 2)
IOL=2mA Note2)
VOL
VIH
0.4
V
V
Digital Output Low Voltage
IIC Input High Voltage
I2C(SDA,SCL)
IIC Input Low Voltage
I2C(SDA,SCL)
VIL
0.7
0.4
V
V
VOL
IIC(SDA) Output Voltage
IOL=4.5mA
Note1) D[9:0],FID/VSYNC, HSYNC, SYSCLK, RESET pin
Note2) FID/VSYNC, HSYNC pin
Note) Connected Test Pin to GND, SELA and SISINV Pin are desired polarity.
Analog Characteristic And Dissipation Current (Power Supply:5V Temperature:25°C)
Parameter
Resolution
Min
1.21
1.17
Typ
10
Max
Units
bit
Conditions
±0.3
±0.2
1.28
±1.5
±1
Integral linearity error
Differential linearity error
Output Full Scale Voltage
Output offset Voltage
DAC Unbalance
LSB
LSB
V
1.38
5.0
±5
Note1)
Note2)
mV
%
±1
50
Note3)
DAC Isolation
dB
1MHz Full Scale
1.235
50
1.33
V
Internal Reference Voltage
Internal Reference Drift
Digital Current
ppm/°C
mA
mA
µA
60
DAC Current
25
Note4)
Note5)
Note6)
DAC Current
10
Total Current
85
125
mA
Note 1) Under the condition of output load 220Ω, I REF pin with 6.8kΩ, using internal reference.
The output full-scale current Iout is calculated as Full scale output voltage (typ.
1.28V)/220Ω=typ. 5.8mA.
Note 2) DAC output when feeding code of 0(Decimal).
Note 3) Deviation between the DAC output when feeding 1V generating code of 800(Decimal).
Note 4) All DACs are operating.
Note 5) All DACs are off with no system clock.
Note 6) NTSC internal color-bar with 3ch DACs operation.
M0036-E-00
6
1998/09
ASAHI KASEI
[AK8810A]
AC Characteristic
1. Pixel Data Input
Pixel Data Input Timing
Parameter
SYSCLK
Symbol
fSYSCLK
tCLKH
tCLKL
tDS
Min
Typ
27
Max
Units
MHz
nsec
nsec
nsec
nsec
SYSCLK Pulse Width H
SYSCLK Pulse Width L
Data Setup Time
Data Hold Time
15
15
8
tDH
5
2. Synchronizing Signal (FID/VSYNC, HSYNC)
2-1 [Input Synchronizing Signal]
Input Synchronizing Signal Timing
Parameter
Data Setup Time
Symbol
tDS
Min
8
Typ.
Max
Units
nsec
nsec
Data Hold Time
tDH
5
M0036-E-00
7
1998/09
ASAHI KASEI
[AK8810A]
2-2 [Output Synchronizing Signal]
Output Synchronizing Signal Timing
Parameter
Symbol
Min
Typ.
Max
25
Units
nsec
Delay from SYSCLK
tDEL
3. Reset (Initialize)
Reset Timing
Parameter
Symbol
pRES
Min
10
Typ.
Max
Units
SYSCLK
/RESET Pulse Width
Note) System controlling pin, such as SELA SISINV are fixed before or after more than 10 SYSCLK
exclusively during reset initiation.
M0036-E-00
8
1998/09
ASAHI KASEI
[AK8810A]
4 I2C Bus
4-1 I2C Bus I/O Timing1 (SCL 400kHz cycle mode)
Parameter
Bus Free Time
Symbol
tBUF
tHD:STA
tLOW
Min
1.3
Max
Units
µsec
µsec
Vsec
nsec
nsec
µsec
µsec
Hold Time (Start Condition)
Clock Pulse Low Time
0.6
1.3
Bus Signal Rise Time
tR
20+0.1Cb*
20+0.1Cb*
0.6
300
300
Bus Signal Fall Time
tF
Setup Time(Start Condition)
tSU:STA
Setup Time(Stop Condition)
tSU:STO
0.6
*Cb is total load capacitance(Units of pF) of the I2C bus line. Minimum values are not tested.
4-2 I2C Bus I/O Timing2 (SCL 400kHz cycle mode)
Parameter
Data Setup Time
Symbol
tSU:DAT
tHD:DAT
tHIGH
tSP
Min
100 Note 1)
0.0
Max
Units
nsec
µsec
µsec
nsec
kHz
Hold Time (Start Condition)
Clock Pulse Low Time
Noise Suppression
0.9 Note 2)
0.6
50 Note 3)
SCL Frequency
fSCL
400
Note 1) When using under standard mode, the condition of tSU:DAT ≥ 250nsec must be
satisfied.
Note 2) When the system does not extend tLOW (tLOW= minimum standard), this condition
must be satisfied.
Note 3) Represents typical value. Not tested.
M0036-E-00
9
1998/09
ASAHI KASEI
[AK8810A]
I/O pin Capacitance
Parameter
Symbol
Min
Typ.
11
Max
Units
Input Pin Capacitance
pF
pF
Output Pin Capacitance
11
(Note) Sample value. Not tested.
*Condition f=1MHz
Parameter
Symbol
Min
Typ.
Max
Units
pF
11
11
I/O Pin Capacitance SDA pin
pF
Input Pin Capacitance SCL pin
(Note) Sample value. Not tested.
DAC Out Load Capacitance
Parameter
Symbol
Min
Typ.
Max
30
Units
pF
DAC Load Capacitance
(Note) Sample value. Not tested.
*Condition f=1MHz
M0036-E-00
10
1998/09
ASAHI KASEI
[AK8810A]
FUNCTIONAL DESCRIPTION
♦ Reset
When the reset pin /RESET set to “L”, AK8810A is put in reset state. After the reset, the video
outputs are in high-impedance. AK8810A starts in the internal initializing sequence at the rising
edge of the first SYSCLK after the reset pin is “L”. If there is no SYSCLK, AK8810A does not
start in the initializing sequence. All internal registers are set to be default value by this
initializing sequence.
♦ Master-Clock
AK8810A requires 27MHz clock at SYSCLK pin for operation. Video input data (CCIR-656) is
sampled at the rising edge of this 27MHz . When SYSINV pin is “H” , video input data is
sampled at the falling edge of 27 MHz.
♦ Video Signal Interface
AK8810A can interface with the video input data by the following 3 modes.
1. CCIR-656 Format
AK8810A decodes EAV in a data-line and manages an internal synchronization.
In this case, AK8810A outputs FID (odd : “L” even : “H”)/ VSYNC and HSYNC.
2. CCIR-656 like Format (4:2:2 YCbCr)
There are MASTER and SLAVE modes, for CCIR-656 like Format which does not include
EAV.
<Master Mode>
AK8810A provides FID/VSYNC and HSYNC to an external device according to the
AK8810A internal timing counter. AK8810A start to sample the input data at the fixed value
on the internal pixel counter.
<Slave Mode>
FID/VSYNC and HSYNC is supplied by an external device. AK8810A samples the data as
same manner of Master mode.
M0036-E-00
11
1998/09
ASAHI KASEI
[AK8810A]
♦ Video Signal Conversion
Video reconstruction module converts the multiplexed data (ITU-R601 Y,Cb,Cr) to the interlace
format of NTSC, PAL-M, PAL-B,D,G,H,I,N. The video reconstruction format is specified by the
register.
The frequency of Color Sub-carrier is changed automatically by the selected format.
(cf. : burst signal table) The frequency and the phase of Color Sub-carrier is also adjustable by
the register. The Sub-carrier has a free-running mode and a reset-mode. In the reset-mode, the
Sub-carrier is re-set automatically to the initial phase for every 4 fields (NTSC) or 8 fields (PAL).
♦ Video Filter
Luminance signal and chroma signal modulated by the Sub-carrier pass through the Type-A
filter that corrects the attenuation of the DAC’s aperture effect up to 5 MHz.
For the luminance component of composite signal, it is possible to select the narrow-band filter
Type-B to ease the Y/C separation.
Chroma signal (Cb,Cr) before modulation passes through the 1.3 MHz Low pass filter.
Fig.1 Filter Type A
Fig.2 Filter Type B
M0036-E-00
12
1998/09
ASAHI KASEI
[AK8810A]
♦ Color burst signal
Burst signal is made by the 24bit-adder (Digital Frequency Synthesizer). The Default frequency
of the color burst is selected automatically by the video reconstruction format.
Standard
NTSC-M
Sub-carrier Freq.
(MHz)
3.57954545
PAL-M
3.57561188
4.43361875
3.5820558
4.43361875
PAL-B,D,G,H,I
PAL-N(Arg.)
PAL-N(non-Arg.)
Burst Signal Table
The burst frequency and initial phase resolution are as follows.
Frequency resolution
SCH Phase resolution
0.8046Hz
360/256°C
♦ Video DAC
AK8810A has the three currents driven 10bits-DACs at 27MHz operation. The full-scale of DAC
is determined by the current that flow IREF pin. Typical output voltage is 1.28Vo-p under
condition of VREFIN 1.235V, 6.8KΩ at IREF pin and DAC load resistance of 220Ω. This full-
scale voltage is adjustable from –10% to +10% by adjusting the outer 6.8k resistance.
Each DAC output can be set individually “ON/OFF” by the register. If the DAC is “OFF”, then
the output is Hi-impedance. When three DACs are all “OFF”, then the internal Vref is also
“OFF”. When DAC is forced to be “ON”, AK8810A needs a delay-time for Vref rising time of
several mil-seconds.
♦ Use external Reference Voltage
In order to improve the accuracy of DAC output, external reference voltage is available. In this
case, unused Vrefout pin needs to be terminated with more than 0.1uF capacitance.
♦ Copy Protection
Macrovision Copy Protection ver7.01
Information about the Macrovision encoding functions of the AK8810A is available to
Macrovision licensees. Macrovision may be contacted at:
Macrovision Corporation
1341 Orleans Drive
Sunnyvale, California 904089
USA
Attention: ACP-PPV Technical Support
FAX: (408) 743 - 8610
M0036-E-00
13
1998/09
ASAHI KASEI
[AK8810A]
♦ Closed Caption and Extended Data
AK8810A supports both Closed Captioning and Extended Data. They are controlled “ON” or
”OFF” respectively by the register setting. Each data consists of 2 continuous bytes register, and
it is recognized as the data is renewed when the second byte is written in the register. After the
data is renewed, AK8810A encodes Closed Captioning and Extended Data at the designated
line. If the data isn’t renewed, AK8810A outputs “ASCII-NULL” code. The data is supposed as
Odd Parity and 7 bit US-ASCII code. Host should provide a parity bit.
*In PAL encoding mode, AK8810A outputs them at the same timing and same pattern as NTSC.
*The line where Closed Captioning data is encoded is as follows.
525/60 System (SMPTE)
21 Line default
625/50 System (CCIR)
21 Line default
Closed Caption
Extended Data
284 Line default
334 Line default
Fig. 3 Closed Captioning Wave form
M0036-E-00
14
1998/09
ASAHI KASEI
[AK8810A]
♦ Video ID
AK8810A supports Video ID (EIAJ tentative standard, CPR-1204) encoding for the distinction of
an aspect ratio, etc.
VBID Data Renewal Timing.
Fig. 4 VBID Data renewal Timing
VBID Data Layout
VBID is consists of 20 bits and its format is as follows.
AK8810A generates CRC code automaticaly and adds it to the data. Initial value of the
Polynomial is 1.
Fig. 5 VBID code assignment
M0036-E-00
15
1998/09
ASAHI KASEI
[AK8810A]
VBID Waveform
Fig. 6 VBID Wave Form
525/60 system
400
625/50 system
392
Amplitude(10bit code)
Encode Line
20/283
20/333
VBID parameter table
M0036-E-00
16
1998/09
ASAHI KASEI
[AK8810A]
♦ AK8810A Interface Timing(Part 1) Master mode
On CCIR-656 or master mode operation, AK8810A output HSYNC and FID or VSYNC
(selected by register).
When AK8810A receives CCIR-656 signal, the device decodes EAV for synchronization then
output the HSYNC. The HSYNC output is SYSCLK ↑ timing of data slot 32(24), which is
counted from the EAV start as below.(See also AC Characteristic 2-2[Input Synchronizing
Signal])
On master mode, front end device(MPEG Decoder) start to set Cb on 276(288) slot, after start
to count HSYNC ↓ as 32(24) slot.
FID/VSYNC is output synchronously with HSYNC at the timing of solid line as in Fig. 9. Video
Field.
Fig. 7 Interface Timing (CCIR-656 or Master mode)
M0036-E-00
17
1998/09
ASAHI KASEI
[AK8810A]
♦ AK8810A Interface Timing(Part 2) Slave mode
On slave mode operation, HSYNC and FIDorVSYNC (Selected by register) are fed to
AK8810A.
AK8810A monitor the transition of HSYNC on the SYSCLK ↑ timing. (Refer to AC
Characteristic 2-1. [Input Synchronizing Signal]) After confirm HSYNC to Low, AK8810A
recognize the 32(24) slot, internally. Then, start to sample the data as Cb on 276(288) slot.
Video field is recognized the transition timing between FID/VSYNC and HSYNC. (Fig.8.
Video Field) As in the figure, there is a margin of ±1/4H.
Fig. 8. Interfacing timing (Slave mode)
Fig. 9. Video Field
M0036-E-00
18
1998/09
ASAHI KASEI
[AK8810A]
♦ HSYNC FID/VSYNC Timing
M0036-E-00
19
1998/09
ASAHI KASEI
[AK8810A]
♦ Color Bars
AK8810A generates the Common Color Bar signal for NTSC and PAL internally. The
generated Color Bar is “100% Amplitude, 100% Saturation”.
MAGENTA
202
WHITE
128
235
YELLOW
16
CYAN
166
170
16
GREEN
54
145
RED
90
81
BLUE
240
41
BLACK
128
16
Cb
Y
Cr
210
146
106
222
128
34
240
110
128
M0036-E-00
20
1998/09
ASAHI KASEI
[AK8810A]
♦ IIC Control Sequence
AK8810A is controlled by IIC bus. The slave address can be selected as 40H or 42H by
selecting SELA pin.
SELA pull-down
Pull-up
40H
42H
Operation :
Write Sequence:
ý6 6ODYHý$GGUHVV : ý$ ý6XEý$GGUHVV ý$ ý'DWDBì ý$
ý'DWDBQ ý$î$ ý6WS
* Continuous data writing is capable for the all registers.
Sequential Read: (Only Sub Address of 24H, 25H, 26H could be read)
ý6 6ODYH
: ý$
6XEý$GGUHVVýëé+
ý$ U6 6ODYH
5 ý$
ý$ '$7$Bëç+
'$7$Bëé+ ý$ ý'$7$Bëè+
ý$ ý6WS
S : Start Condition
ýýE\ý+RVW
A : Acknowledge(SDA LOW)
A: Not Acknowledge(SDA HIGH)
Stp : Stop Condition
ýýE\ý$.ååìí
R/W:1: Read 0:Write
- It ignores the general call
M0036-E-00
21
1998/09
ASAHI KASEI
[AK8810A]
AK8810A REGISTER MAP
Sub
Name
default
Address
00H
01H
02H
03H
04H
05H
06H
07H
Interface Mode
Video Process 1
Video Process 2
Video Process 3
RESERVED
A4H
18H
00H
00H
DAC Mode
00H
00H
00H
Sub C. Freq.
Sub C. Phase
08H-15H RESERVED
16H
17H
18H
19H
1AH
1BH
Closed Caption R
00H
00H
00H
00H
00H
00H
Closed Caption R
Closed Caption R
Closed Caption R
Video ID Data
Video ID Data
1CH-23H RESERVED
24H
25H
26H
STS Data
Device ID
Device REV
-
21H
01H
27H-29H RESERVED
M0036-E-00
22
1998/09
ASAHI KASEI
[AK8810A]
Interface Mode Register (W only default A4H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
FID
bit 1
bit 0
00H
BLN4
BLN3
BLN2
BLN1
BLN0
MAS
CCIR
Symbol
BLN4 - BLN0
Value
*****
Description
Line Blanking No.
default
10100
FID
0
Select VSYNC
Select FID
Slave mode
Master mode When CCIR=0,it’s
valid
1
0
1
default
default
MAS
CCIR
0
1
CCIR656 non-decode
CCIR656 decode
default
Video Process 1 Register (W only default 18H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01H
CBG
SETUP
SCR
VM2
VM1
VM0
Symbol
Value
Description
CBG
SETUP
SCR
0
Video Encode
Generates color bar
No Set-up
7.5 IRE Set-up
Sub C. Phase Reset off
Standard Field Reset
default
default
1
0
1
0
1
default
default
VM2 - VM0
000 NTSC
001 PAL-M
100 PAL
101 PAL-N-Arg
110 PAL-N-nonArg
•
•
When SCR is “ON”, resets every 4 fields for NTSC, every 8 fields for PAL.
Even when SETUP is “ON”, there is no Set-up (Pedestal) during the blanking lines.
M0036-E-00
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1998/09
ASAHI KASEI
[AK8810A]
Video Process 2 Register (W only default 00H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
02H
CC284
CC21
VBID
Symbol
Value
Description
CC284
CC21
VBID
0
Extended Data OFF
ON
Closed Caption OFF
ON
Video ID OFF
ON
default
default
default
1
0
1
0
1
Video Process 3 Register (W only default 00H)
bit 7
bit 6
FLY
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
03H
SYD2
SYD1
SYD0
CYD2
CYD1
CYD0
Symbol
Value
Description
FLY
0
1
Y filter type B (for Composite)
Y filter type A
default
SYD2 - SYD0
CYD2 - CYD0
S-Video Y Component
delay no. from Chroma: 2's comp.
Composite Y Component
default
000
default
000
delay no. from Chroma: 2's comp.
•
•
“FLY” bit selects Y signal filter for Composite signal. Type-A filter is also used to
chroma signal, it compensates an aperture effect of DAC and keeps flat LPF
characteristic up to 5MHz.
S video and Y component of the composite signal can be shifted for the chroma signal
independently at ‘3 system clock (27MHz).
M0036-E-00
24
1998/09
ASAHI KASEI
[AK8810A]
DAC Mode Register (W only default 00H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
05H
OUTCP OUTC
OUTY
Symbol
OUTCP
Value
Description
0
Comp : OFF
Comp : ON
C : OFF
C : ON
Y : OFF
default
default
default
1
0
1
0
1
OUTC
OUTY
Y : ON
•
Video output of AK8810A (DAC) can be forced “OFF” independently.
The output of DAC which is forced “OFF” is Hi-impedance. When three DACs are
forced “OFF”, then the internal Vref is also forced “OFF”. In this case, it takes several
msec for the internal Vref to reach the necessary voltage after any DAC becomes
“ON”.
SubC Freq. Register (W only default 00H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
06H
SUBF7 SUBF6 SUBF5 SUBF4 SUBF3 SUBF2 SUBF1 SUBF0
Symbol
Value
Description
SUBF7-SUBF0
default 0
Adjustment of frequency: +127 -128
step of 0.8Hz
•
•
AK8810A generates the necessary sub-carrier frequency from a system clock by DFS
(Digital Frequency Synthesizer)
Frequency of default is adjustable by specifying this bit. This bit adjusts the default
frequency.
SubC Phase Register (W only default 00H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
07H
SUBP7 SUBP6 SUBP5 SUBP4 SUBP3 SUBP2 SUBP1 SUBP0
Symbol
Value
Description
SUBP7 – SUBP0
Step: (360°/256°)
default 0
•
Sub- carrier phase is adjustable by (360°/256°) step.
M0036-E-00
25
1998/09
ASAHI KASEI
[AK8810A]
bit 0
Closed Caption Register (W only default 00H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
16H
17H
18H
19H
CC1[7] CC1[6]
CC2[7] CC2[6]
CC3[7] CC3[6]
CC4[7] CC4[6]
CC1[5] CC1[4] CC1[3] CC1[2] CC1[1] CC1[0]
CC2[5] CC2[4] CC2[3] CC2[2] CC2[1] CC2[0]
CC3[5] CC3[4] CC3[3] CC3[2] CC3[1] CC3[0]
CC4[5] CC4[4] CC4[3] CC4[2] CC4[1] CC4[0]
Symbol
Description
CC1[7] - CC1[0] Line 21 –1
CC2[7] - CC2[0] Line 21 –2
Closed Caption
Extended Data
CC3[7] - CC3[0]
CC4[7] - CC4[0]
Line 284 -1
Line 284 -2
When the 2nd byte of Closed Caption Data and Extended Data is written in, AK8810A
judges as the data is renewed and encodes data in the video line. NULL is output
automatically in the line which is not renewed.
•
Video ID Data Register (W only default 00H)
bit 7
bit 6
bit 5
bit 1
bit 9
bit 4
bit 2
bit 10
bit 3
bit 3
bit 11
bit 2
bit 4
bit 12
bit 1
bit 5
bit 13
bit 0
bit 6
bit 14
1AH
1BH
bit 7
bit 8
•
•
Bit numbers correspond to Fig. 5 VBID code assignment. (p.15)
AK8810A generates CRC 6 bit data automatically.
M0036-E-00
26
1998/09
ASAHI KASEI
[AK8810A]
Followings are read only register
STATUS REGISTER (R only)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
24H
EN284
EN21
SYNC
STS2
STS1
STS 0
Symbol
Value
Description
EN284
0
1
0
1
0
Wait for the appointed video line to encode.
Ready for the C.C. data input to the register.
Wait for the appointed video line to encode.
Ready for the C.C. data input to the register.
Missing synchronization in slave mode.
Synchronization was achieved.
EN21
SYNC
1
STS2 - STS 0
***
Shows the processing field No.
•
•
•
Status Register become effective when SYNC bit turns to “1”. When in master mode
operation, this bit is ”1”.
STS2-STS2 holds the field number of processing. Some time lag is inevitable for the IIC
acquisition.
Closed caption data should be renewed after firm that the EN* flag is “1”. EN* flag bit is
cleared after the second byte( Sub address 17H,19H) was accessed.
Device ID (R only default 21H)
bit7
0
bit6
0
bit5
1
bit4
0
Bit3
0
bit2
0
bit1
0
bit0
1
25H
•
Represents device ID. AK8810A is assigned 21H.
Device REV (R only default 01H)
bit7
0
bit6
0
bit5
0
bit4
0
Bit3
0
bit2
0
bit1
0
bit0
1
26H
•
Represents device revision. Initial is 01H.
M0036-E-00
27
1998/09
ASAHI KASEI
[AK8810A]
SYSTEM CONNECTION EXAMPLE
M0036-E-00
28
1998/09
ASAHI KASEI
[AK8810A]
PACKAGE
44pin LQFP (Unit: mm)
Package & Lead frame material
Package molding compound:
Epoxy
Lead frame material:
Cu
Lead frame surface treatment:
Solder plate
M0036-E-00
29
1998/09
ASAHI KASEI
[AK8810A]
MARKING
1) Pin #1 indication
2) Date Code : XXXXXXX (7 digits)
3) Marketing Code : AK8810A
4) Country of Origin
5) Asahi Kasei Logo
M0036-E-00
30
1998/09
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
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