AK93C55BL [AKM]
1K / 2K / 4K / 8Kbit Serial CMOS EEPROM; 1K / 2K / 4K / 8Kbit串行CMOS EEPROM的
| 型号： | AK93C55BL |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 1K / 2K / 4K / 8Kbit Serial CMOS EEPROM |
| 文件： | 总14页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK93C45B/55B/65B/75B]
AK93C45B / 55B / 65B / 75B
1K / 2K / 4K / 8Kbit Serial CMOS EEPROM
Features
ꢀ ADVANCED CMOS EEPROM TECHNOLOGY
ꢀ READ/WRITE NON-VOLATILE MEMORY
ꢀ WIDE VCC OPERATION : VCC = 1.8V to 5.5V
ꢀ AK93C45B ・・1024 bits, 64 x 16 organization
AK93C55B ・・2048 bits, 128 x 16 organization
AK93C65B ・・4096 bits, 256 x 16 organization
AK93C75B ・・8192 bits, 512 x 16 organization
ꢀ SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
ꢀ LOW POWER CONSUMPTION
- 0.8µA Max. Standby
ꢀ High Reliability
- Endurance
: 100K cycles
- Data Retention : 10 years
ꢀ Automatic address increment (READ)
ꢀ Automatic write cycle time-out with auto-ERASE
ꢀ Busy/Ready status signal
ꢀ Software controlled write protection
ꢀ IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (MSOP, SON)
DO
DATA
REGISTER
16
16
R/W AMPS
AND
AUTO ERASE
INSTRUCTION
REGISTER
DI
EEPROM
INSTRUCTION
DECODE,
CONTROL
AND
93C45B=1024bit
93C55B=2048bit
93C65B=4096bit
93C75B=8192bit
CLOCK
ADD.
DECODER
GENERATION
BUFFERS
CS
VPP SW
SK
PE
VPP
GENERATOR
VREF
(AK93C55B/65B/75B)
Block Diagram
- 1 -
DAM04E-02
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
General Description
The AK93C45B/55B/65B/75B is a 1024/2048/4096/8192-bit serial CMOS EEPROM divided into
64/128/256/512 registers of 16 bits each. The AK93C45B/55B/65B/75B has 4 instructions such as
READ, WRITE, EWEN and EWDS. Those instructions control the AK93C45B/55B/65B/75B.
The AK93C45B/55B/65B/75B can operate full function under wide operating voltage range from
1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write
operation.
A serial interface of AK93C45B/55B/65B/75B, consisting of chip select (CS), serial clock (SK),
data-in (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard
microprocessors. AK93C45B/55B/65B/75B takes in the write data from data input pin (DI) to a
register synchronously with rising edge of input pulse of serial clock pin (SK). And at read
operation, AK93C45B/55B/65B/75B takes out the read data from a register to data output pin (DO)
synchronously with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data
output or Busy/Ready signal output.
x Software and Hardware controlled write protection
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before
WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable
state continues until EWDS instruction is executed or VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE,
EWEN and EWDS instructions. ・・AK93C55B/65B/75B
x Busy/Ready status signal
After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling
edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status
of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that
programming is still in progress. DO=logical "1" indicates that the register at the address specified
in the instruction has been written with the new data pattern contained in the instruction and the part
is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
Type of Products
Model
Memory size
1K bits
Temp. Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VCC
Package
AK93C45BH
AK93C45BL
AK93C55BH
AK93C55BL
AK93C65BH
AK93C65BL
AK93C75BH
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8pin Plastic MSOP
8pin Plastic SON
8pin Plastic MSOP
8pin Plastic SON
8pin Plastic MSOP
8pin Plastic SON
8pin Plastic MSOP
2K bits
4K bits
8K bits
DAM04E-02
2003/05
- 2 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Pin Arrangement
AK93C45BH
AK93C55BH/65BH/75BH
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
NC
PE
DO
GND
DO
GND
8pin MSOP
8pin MSOP
AK93C45BL
AK93C55BL/65BL
VCC
1
2
3
4
8
7
6
5
CS
VCC
1
2
3
4
8
7
6
5
CS
NC
NC
SK
DI
NC
PE
SK
DI
GND
DO
GND
DO
8pin SON
8pin SON
Pin Name
CS
Function
Chip Select
SK
DI
Serial Data Clock
Serial Data Input
DO
GND
PE
VCC
NC
Serial Data Output
Ground
Program Enable
Power Supply
Not Connected
(note) The PE is internally pulled up to VCC ( R = typ.2.5MΩ, VCC=5V ).
DAM04E-02
2003/05
- 3 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Functional Description
The AK93C45B/55B/65B/75B has 4 instructions such as READ, WRITE, EWEN and EWDS. A
valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory
Address location.
The CS pin must be brought low for a minimum of 250ns (Tcs) between each instruction when the
instruction is continuously executed.
Start Op
Instruction
Address
Data
Comments
Bit
Code
10
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
READ
WRITE
EWEN
EWDS
WRAL
1
A5-A0
A5-A0
11XXXX
00XXXX
01XXXX
D15-D0
D15-D0
1
1
1
1
01
00
00
00
D15-D0
X: Don't care
table1. Instruction Set for the AK93C45B
Start Op
Instruction
Address
Data
Comments
Bit
Code
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
READ
WRITE
EWEN
EWDS
WRAL
1
10
01
00
00
00
X A6-A0
X A6-A0
11XXXXXX
00XXXXXX
01XXXXXX
D15-D0
D15-D0
1
1
1
1
D15-D0
X: Don't care
table2. Instruction Set for the AK93C55B
Start Op
Instruction
Address
Data
Comments
Bit
Code
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
READ
WRITE
EWEN
EWDS
WRAL
1
10
01
00
00
00
A7-A0
A7-A0
11XXXXXX
00XXXXXX
01XXXXXX
D15-D0
D15-D0
1
1
1
1
D15-D0
X: Don't care
table3. Instruction Set for the AK93C65B
Start Op
Instruction
Address
Data
Comments
Bit
Code
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
READ
WRITE
EWEN
EWDS
WRAL
1
10
01
X A8-A0
X A8-A0
D15-D0
D15-D0
1
1
1
1
00 11XXXXXXXX
00 00XXXXXXXX
00 01XXXXXXXX D15-D0
X: Don't care
table4. Instruction Set for the AK93C75B
(Note) x The WRAL instruction are used for factory function test only.
User can't use the WRAL instruction.
x The AK93C45B/55B/65B/75B perceives the start bit in the logic"1" and also "01".
DAM04E-02
2003/05
- 4 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the
last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the
SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs).
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
CS
tCS
0
1
2
3
4
5
8
9
10
11
23
D2
24
D1
25
D0
SK
DI
0
1
0
1
A5
A4
A1
A0 D15 D14
Start Bit
Op code
Hi-Z
Busy
DO
Ready
AK93C45B output a logic "1" (Ready status),
if previous instruction is WRITE.
tE/W
WRITE (AK93C45B)
CS
SK
DI
tCS
0
1
2
3
4
5
10
A1
11
12
13
25
D2
26
D1
27
D0
X
0
1
0
1
/
A6
A0 D15 D14
A7
Start Bit
Op code
Hi-Z
Busy
DO
Ready
AK93C55B/65B output a logic "1" (Ready status),
if previous instruction is WRITE.
tE/W
X: Don't care
*Address bit A7 becomes a "don't care" for AK93C55B.
WRITE (AK93C55B/65B)
CS
SK
DI
tCS
0
1
2
3
4
5
12
A1
13
14
15
27
D2
28
D1
29
D0
0
1
0
1
X
A8
A0 D15 D14
Start Bit
Op code
Hi-Z
Busy
DO
Ready
AK93C75B output a logic "1" (Ready status),
if previous instruction is WRITE.
tE/W
X: Don't care
WRITE (AK93C75B)
DAM04E-02
2003/05
- 5 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
READ
The read instruction is the only instruction which outputs serial data on the DO pin.
Following the Start bit, first Op code and address are decoded, then the data from the selected
memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from
the selected memory location. The output data changes are synchronized with the rising edges of
the serial clock (SK).
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
When the highest address is reached, the address counter rolls over to address $00 or $000
allowing the read cycle to be continued indefinitely.
CS
0
1
2
3
4
5
8
9
10
11
25
26
40
41
SK
DI
0
1
1
0
A5
A4
A1
A0
Start bit
Op code
Hi-Z
0
D15 D14
D0 D15
D1
D0
DO
Dummy
AK93C45B output a logic "1" (Ready status),
if previous instruction is WRITE.
address[A5–A0]
address[A5–A0]+1
Bit
READ (AK93C45B)
CS
SK
DI
0
1
2
3
4
5
10
A1
11
A0
12
13
27
28
42
43
X
0
1
1
0
/
A6
A7
Start bit
Op code
Hi-Z
0
D15 D14
D0 D15
address[A6/A7–A0] address[A6/A7–A0]+1
X: Don't care
D1
D0
DO
Dummy
AK93C55B/65B output a logic "1" (Ready status),
if previous instruction is WRITE.
Bit
*Address bit A7 becomes a "don't care" for AK93C55B.
READ (AK93C55B/65B)
CS
SK
DI
0
1
2
3
4
5
12
A1
13
A0
14
15
29
30
44
45
0
1
1
0
X
A8
Start bit
Op code
Hi-Z
0
D15 D14
D0 D15
address[A8–A0]+1
X: Don't care
D1
D0
DO
Dummy
AK93C75B output a logic "1" (Ready status),
if previous instruction is WRITE.
address[A8–A0]
Bit
READ (AK93C75B)
- 6 -
DAM04E-02
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before
WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable
state continues until EWDS instruction is executed or VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
CS
0
1
2
3
4
5
6
7
8
9
SK
DI
0
1
0
0
X
X
X
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C45B output a logic "1" (Ready status),
if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C45B)
CS
SK
DI
0
1
2
3
4
5
6
7
8
9
10
11
0
1
0
0
X
X
X
X
X
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C55B/65B output a logic "1" (Ready status),
if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C55B/65B)
CS
SK
DI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
0
0
X
X
X
X
X
X
X
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C75B output a logic "1" (Ready status),
if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C75B)
DAM04E-02
2003/05
- 7 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Absolute Maximum Ratings
Parameter
Symbol
VCC
Min
Max
+7.0
Unit
V
Power Supply
-0.6
-0.6
All Input Voltages
VIO
VCC+0.6
V
with Respect to Ground
Ambient storage temperature
Tst
-65
+150
°C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter
Power Supply
Ambient Operating Temperature
Symbol
VCC
Ta
Min
1.8
-40
Max
5.5
+85
Unit
V
°C
DAM04E-02
2003/05
- 8 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
◇AK93C45B/55B/65B
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Paremeter
Current Dissipation
(WRITE)
Symbol
ICC1
ICC2
Condition
VCC=5.5V, tSKP=1.0µs, *1
Min.
Max.
4.0
Unit
mA
93C45B
93C55B/65B
1.5
2.0
0.5
0.2
0.1
0.8
mA
mA
mA
mA
mA
µA
VCC=1.8V,
tSKP=4µs,*1
ICC3
ICC4
ICC5
VCC=5.5V, tSKP=1.0µs, *1
VCC=2.5V, tSKP=2.0µs, *1
VCC=1.8V, tSKP=4.0µs, *1
Current Dissipation
(READ, EWEN, EWDS)
Current Dissipation
(Standby)
ICCSB VCC=5.5V
*2
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
2.0
VCC + 0.5
V
V
V
V
V
V
V
VCC=5.0V±10%
Input High Voltage
0.8 x VCC VCC + 0.5
0.8 x VCC VCC + 0.5
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
VCC=5.0V±10%
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
-0.1
-0.1
-0.1
2.2
0.8
0.15 x VCC
0.2 x VCC
Input Low Voltage
Output High Voltage VOH1
VCC=5.0V±10%
IOH=-0.4mA
VOH2
VOH3
0.8 x VCC
0.8 x VCC
V
V
2.5V ≤ VCC ≤ 5.5V
IOH=-0.1mA
1.8V ≤ VCC < 2.5V
IOH=-0.1mA
Output Low Voltage
VOL1
VOL2
VOL3
ILI
0.4
0.4
V
VCC=5.0V±10%
IOL=1.5mA
V
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
0.4
V
1.8V ≤ VCC < 2.5V
IOL=0.1mA
Input Leakage
VCC=5.5V, VIN=5.5V
*3
±1.0
±1.0
µA
µA
Output Leakage
ILO
VCC=5.5V,
VOUT=5.5V, CS=GND
*1 : VIN=VIH/VIL, DO=Open
*2 : VIN=VCC/GND, CS=GND, DO=Open, PE=Open(AK93C55B/65B)
*3 : CS, SK, DI pin
DAM04E-02
2003/05
- 9 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
◇AK93C75B
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Paremeter
Current Dissipation
(WRITE)
Symbol
ICC1
ICC2
ICC3
ICC4
Condition
VCC=5.5V, tSKP=1.0µs, *4
VCC=1.8V, tSKP=4.0µs, *4
VCC=5.5V, tSKP=1.0µs, *4
VCC=1.8V, tSKP=4.0µs, *4
Min.
Max.
4.0
2.0
0.4
0.1
0.8
Unit
mA
mA
mA
mA
µA
Current Dissipation
(READ, EWEN, EWDS)
Current Dissipation
(Standby)
ICCSB VCC=5.5V
*5
Input High Voltage
Input Low Voltage
VIH
VIL
0.8 x VCC VCC + 0.5
V
V
V
-0.1
0.2 x VCC
Output High Voltage VOH1
0.8 x VCC
2.5V ≤ VCC ≤ 5.5V
IOH=-0.1mA
VOH2
0.8 x VCC
V
V
1.8V ≤ VCC < 2.5V
IOH=-0.1mA
Output Low Voltage
VOL1
VOL2
ILI
0.4
0.4
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
V
1.8V ≤ VCC < 2.5V
IOL=0.1mA
Input Leakage
VCC=5.5V, VIN=5.5V
*6
±1.0
±1.0
µA
µA
Output Leakage
ILO
VCC=5.5V,
VOUT=5.5V, CS=GND
*4 : VIN=VIH/VIL, DO=Open
*5 : VIN=VCC/GND, CS=GND, DO=PE=Open
*6 : CS, SK, DI pin
DAM04E-02
2003/05
- 10 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Paremeter
SK Cycle Time
Symbol
tSKP1
Condition
4.5V ≤ VCC ≤ 5.5V
Min.
1.0
Max.
Unit
µs
tSKP2
tSKP3
tSKW1
tSKW2
tSKW3
tCSS
tCSH
tDIS
2.0
4.0
500
1.0
2.0
100
0
2.0V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.0V
4.5V ≤ VCC ≤ 5.5V
2.0V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.0V
µs
µs
ns
µs
µs
ns
ns
ns
ns
ns
µs
µs
ms
ms
ms
ns
ns
ns
ns
SK Pulse Width
CS Setup Time
CS Hold Time
Data Setup Time
Data Hold Time
200
200
tDIH
tPD1
tPD2
tPD3
tE/W1
tE/W2
tE/W3
tCS
tSV
tOZ1
tOZ2
500
1.0
2.0
10
8
4.5V ≤ VCC ≤ 5.5V
2.0V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.0V
93C45B/55B/65B
Output delay
*7
Selftimed
Programming Time
93C75B
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 4.5V
10
Min CS Low Time
CS to Status Valid
CS to Output High-Z
250
CL=100pF
500
100
250
2.0V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.0V
*7 : CL=100pF
DAM04E-02
2003/05
- 11 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Synchronous Data timing
CS
SK
DI
tCSS
tSKW
tSKW
tSKP
tDIS tDIH
1
0
tSV
Hi-Z
DO
AK93C45B/55B/65B/75B output a logical "1" (Ready status),
if previous instruction is WRITE.
The Start of Instruction
CS
SK
DI
tCSH
tPD
tPD
tPD
tOZ
Hi-Z
D3
D2
D1
D0
DO
The End of Instruction
DAM04E-02
2003/05
- 12 -
ASAHI KASEI
[AK93C45B/55B/65B/75B]
tCS
CS
SK
DI
tCSH
tDIS tDIH
D1
D0
tSV
Hi-Z
Busy
Ready
DO
tE/W
Busy/Ready Signal Output
DAM04E-02
2003/05
- 13 -
IMPORTANT NOTICE
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distributor concerning their current status.
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(b) A critical component is one whose failure to function or perform may reasonably be expected to
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