AKD4632_技术文档

ASAHI KASEI

[AK4632]

AK4632

∆Σ

16-Bit

Mono CODEC with ALC & MIC/SPK/Video-AMP

GENERAL DESCRIPTION

The AK4632 is a 16-bit mono CODEC with Microphone-Amplifier, Speaker-Amplifier and Video-

Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit.

Output circuits include a Speaker-Amplifier and Mono Line Output. Video circuits include a LPF and

Video-Amplifier. The AK4632 suits a moving picture of Digital Still Camera and etc. This

speaker-Amplifier supports a Piezo Speaker. The AK4632 is housed in a space-saving 32-pin QFN

package.

FEATURE

1. 16-Bit Delta-Sigma Mono CODEC

2. Recording Function

• 1ch Mono Input

• 1^stMIC Amplifier: 0dB, 20dB, 26dB or 32dB

• 2^ndAmplifier with ALC: -8dB ∼ +27.5dB, 0.5dB Step

• ADC Performance: S/(N+D): 80dB, DR, S/N: 85dB

3. Playback Function

• Digital Volume: +12dB ∼ -115dB, 0.5dB Step, Mute

• Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB

• Mono Speaker-Amp

- Speaker-Amp Performance: S/(N+D): 60dB, S/N: 90dB (150mW@ 8Ω)

- BTL Output

- ALC (Automatic Level Control) Circuit

- Output Power: 400mW @ 8Ω, SVDD=3.3V

3.0Vrms@SVDD=5V

• Beep Input

4. Power Management

5. Video Function

• A Composite Video Input

• Gain Control (-1.0dB ∼ +10.5dB, 0.5dB Step)

• Low Pass Filter

• A Video-Amp for Composite Video Signal(+6dB)

• DC Direct Output or Sag Compensation Output

6. Flexible PLL Mode:

• Frequencies:

11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)

1fs (FCK pin)

16fs, 32fs or 64fs (BICK pin)

7. EXT Mode:

• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)

8. Sampling Rate:

• PLL Slave Mode (FCK pin) : 7.35kHz ~ 26kHz

• PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz

• PLL Slave Mode (MCKI pin):

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

• PLL Master Mode:

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

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ASAHI KASEI

[AK4632]

• EXT Slave Mode:

7.35kHz ~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs)

9. Output Master Clock Frequency: 256fs

10. Serial µP Interface: 3-wire

11. Master / Slave Mode

12. Audio Interface Format: MSB First, 2’s compliment

• ADC: DSP Mode, 16bit MSB justified, I²S

• DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I²S

13. Ta = -10 ∼ 70°C

14. Power Supply

• CODEC: 2.6 ∼ 3.6V (typ. 3.3V)

• Speaker-Amp: 2.6 ∼ 5.25V (typ. 3.3V/5.0V)

• Video-Amp: 2.8 ∼ 5.25V (typ. 3.3V/5.0V)

15. Power Supply Current: 23.5 mA (All Power ON)

16. Package: 32pin QFN

17. Register Compatible with AK4631

Block Diagram

AVSS AVDD

VCOM

MICOUT

AIN

PMMIC

MPI

MIC

MIC Power

Supply

PMADC

DVDD

DVSS

ALC1

(IPGA)

MIC-AMP

ADC HPF

0dB or 20dB

or 26dB or 32dB

PDN

Audio

FCK

ALC1A

DACA

Interface

PMDAC

PMAO

BICK

SDTO

SDTI

AOUT

DAC

DVOL

BEEPA

DSP

and

uP

ALC1M

DACM

SVDD

SVSS

PMSPK

SPP

ALC2

CSN

SPK-

AMP

MIX

Control

Register

CCLK

CDTI

SPN

PMBP

BEEP

VOUT

PMPLL

MCKO

PMV

GCA

LPF

PLL

-1dB ~ +10.5dB

Step 0.5dB

+6dB

CLAMP

MCKI

VSAG

VCOC

MIN

MOUT

VIN

VVDD

Figure 1. AK4632 Block Diagram

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ASAHI KASEI

[AK4632]

Ordering Guide

AK4632VN

AKD4632

−10 ∼ +70°C

Evaluation board for AK4632

32pin QFN (0.5mm pitch)

Pin Layout

MOUT

AOUT

BEEP

AIN

DVDD

BICK

FCK

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

AK4632VN

SDTO

SDTI

CDTI

CCLK

CSN

Top View

MICOUT

MIC

MPI

VCOM

Compare with AK4632

Function

Video Function

Package

AK4631

No

28pin QFN (5.2mm x 5.2mm)

AK4632

Yes

32pin QFN (5.0mm x 5.0mm)

The audio function of the AK4632 is compatible with that of the AK4631. Since the register map of audio

function is the same as the AK4631’s, the software of the audio function can run on the ak4632 without any

change.

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ASAHI KASEI

No. Pin Name

[AK4632]

PIN/FUNCTION

I/O

O

Function

Output Pin for Loop Filter of PLL Circuit

1

VCOC

This pin should be connected to AVSS with one resistor and capacitor in series.

Analog Power Supply Pin

2

3

4

5

6

7

AVDD

AVSS

VVDD

VIN

-

Analog Ground Pin

-

Video Block Power Supply Pin.

I

Composite Video Signal Input Pin

Composite Video Signal Driver Pin

Composite Video Signal Output Feedback Input Pin

Power-Down Mode Pin

VOUT

VSAG

O

I

8

PDN

I

“H”: Power up, “L”: Power down reset and initialize the control register.

Chip Select Pin

9

CSN

I

10 CCLK

11 CDTI

12 SDTI

13 SDTO

14 FCK

Control Data Clock Pin

I

Control Data Input Pin

I

Audio Serial Data Input Pin

O

Audio Serial Data Output Pin

I/O Frame Clock Pin

15 BICK

16 DVDD

17 DVSS

18 MCKI

19 MCKO

20 SPN

I/O Audio Serial Data Clock Pin

-

Digital Power Supply Pin

Digital Ground Pin

I

External Master Clock Input Pin (Internal Pull Down 25kΩ@PDN pin =“L”)

Master Clock Output Pin

O

-

Speaker Amp Negative Output Pin

Speaker Amp Positive Output Pin

Speaker Amp Power Supply Pin

Speaker Amp Ground Pin

21 SPP

22 SVDD

23 SVSS

24 MIN

-

I

ALC2 Input Pin

25 MOUT

26 AOUT

27 BEEP

28 AIN

O

I

Mono Analog Output Pin

Mono Line Output Pin

Beep Signal Input Pin

I

IPGA (ALC1) Input Pin

29 MICOUT

30 MIC

O

I

Microphone Analog Output Pin

Microphone Input Pin (Mono Input)

MIC Power Supply Pin for Microphone

Common Voltage Output Pin. Common Voltage = 0.45 x AVDD

Bias voltage of ADC inputs and DAC outputs.

31 MPI

O

32 VCOM

O

Note : All input pins except analog input pins (MIC, AIN, MIN, BEEP and VIN pins) should not be left floating.

Note : The exposed pad on the bottom surface of the package must be open.

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ASAHI KASEI

[AK4632]

Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification

Pin Name

Setting

These pins should be open and each path

should be switched off.

Analog Input

MIC, AIN, BEEP, MIN, VSAG

Analog Output MICOUT, MPI, AOUT, MOUT, SPP, SPN, VOUT

These pins should be open.

These pins should be connected to DVSS.

MCKI, SDTI, FCK(when M/S bit = “0”),

BICK(when M/S bit = “0”)

Digital Input

These pins should be open.

MCKO, SDTO, FCK(when M/S bit = “1”),

BICK(when M/S bit = “1”)

Digital Output

ABSOLUTE MAXIMUM RATINGS

(AVSS, DVSS, SVSS=0V; Note 1)

Parameter

Symbol

AVDD

DVDD

SVDD

VVDD

∆GND1

∆GND2

IIN

min

max

Units

V

Power Supplies:

Analog

Digital

Speaker-Amp

Video

|AVSS – DVSS| (Note 2)

−0.3

-

6.0

0.3

V

|AVSS – SVSS|

(Note 2)

-

0.3

Input Current, Any Pin Except Supplies

Analog Input Voltage(Audio)

Analog Input Voltage(Video)

Digital Input Voltage

-

±10

mA

V

(Note 3)

(Note 4)

VINA

VINV

VIND

Ta

Tstg

Pd

−0.3

−10

−65

-

AVDD+0.3

VVDD+0.3

DVDD+0.3

70

V

Ambient Temperature (powered applied)

Storage Temperature

Maximum Power Dissipation (Note 5)

°C

mW

150

700

Note 1. All voltages with respect to ground.

Note 2. AVSS, DVSS and SVSS must be connected to the same analog ground plane.

Note 3. MIC, AIN, BEEP, MIN pins

Note 4. VIN pin

Note 5. In case that PCB wiring density is 100%. This power is the AK4632 internal dissipation that does not include

power of externally connected speaker.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

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ASAHI KASEI

[AK4632]

RECOMMENDED OPERATING CONDITIONS

(AVSS, DVSS, SVSS=0V; Note 1)

Parameter

Symbol

AVDD

DVDD

min

typ

3.3

max

3.6

Units

V

Power Supplies Analog

2.6

(Note 6)

Digital

Speaker-Amp (Note 7)

Video (Note 8)

Difference

SVDD

VVDD

AVDD-DVDD

2.6

3.3 / 5.0

0

5.25

0.3

V

2.8 or AVDD

-0.3

Note 1. All voltages with respect to ground

Note 6. The power up sequence between AVDD, DVDD and SVDD is not critical.

When the power supplies are partially powered OFF, the AK4632 must be reset by bringing PDN pin “L” after

these power supplies are powered ON again.

Note 7. SVDD = 2.6 ∼ 3.6V when 8Ω dynamic speaker is connected to the AK4632. If SVDD is more than 3.6V when

8Ω dynamic speaker is connected to the AK4632, the output of Speaker-Amp should be restricted in consideration

of maximum power dissipation as the following.

SPoMax : Maximum Output Power of SPK-Amp[mW]

SPKMPD : Maximum Power Dissipation of SPK-Amp[mW]

Rmin

: Minimum Impedance of speaker[Ω]

Vmax

: Maximum permission output voltage of SPK-Amp[Vrms]

SPKMPD = 700 – AVDD(max) x 17.5 – VVDD(max) x 12 – SVDD(max) x 27

A = 2 x sqrt(2) x SVDD(max) / π

B = A x A – 4 x Rmin x SPKMPD / 1000

Vmax= (A – sqrt(B)) / 2

SPoMax = 1000 x Vmax x Vmax / Rmin

Maximum Output Power of SPK-Amp at B < 0 : No limitation

Maximum Output Power of SPK-Amp at B ≥ 0: This power should be less than or equal to

SPoMax[mW].

Regardless of the condition of B, the distortion of output signal increases, when SPK-Amp output power

exceeds 240mW.

Note 8. Minimum value is higher value between 2.8V and AVDD[V].

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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ASAHI KASEI

[AK4632]

ANALOG CHRACTERISTICS

(Ta=25°C; AVDD, DVDD, SVDD, VVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal

Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; EXT Slave Mode; unless otherwise specified)

min

typ

max

Units

Parameter

MIC Amplifier

Input Resistance

Gain

20

30

0

20

26

32

40

kΩ

dB

(MGAIN1-0 bits = “00”)

(MGAIN1-0 bits = “01”)

(MGAIN1-0 bits = “10”)

(MGAIN1-0 bits = “11”)

-

MIC Power Supply: MPI pin

Output Voltage

Load Resistance

Load Capacitance

(Note 9)

2.22

2

-

2.47

-

2.72

-

30

V

kΩ

pF

Input PGA Characteristics:

Input Resistance (Note 10)

Step Size

5

0.05

−8

10

0.5

-

15

0.9

+27.5

kΩ

dB

Gain Control Range

ADC Analog Input Characteristics: MIC Æ IPGA Æ ADC, MIC Gain=20dB, IPGA=0dB, ALC1=OFF

Resolution

-

0.168

68

75

-

0.198

80

85

16

0.228

-

Bits

Vpp

dB

Input Voltage (MIC Gain=20dB, Note 11)

S/(N+D)

D-Range

S/N

(−1dBFS) (Note 12)

(−60dBFS)

DAC Characteristics:

Resolution

-

16

Bits

Mono Line Output Characteristics: AOUT pin, DAC → AOUT, R_L=10kΩ

Output Voltage (Note 13)

1.78

73

83

10

-

1.98

85

93

-

2.18

-

Vpp

dB

kΩ

pF

S/(N+D)

D-Range

S/N

(0dBFS) (Note 12)

(-60dBFS)

Load Resistance

Load Capacitance

-

30

Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ)

Note 10. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.

Note 11. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)

Note 12. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D) is 77dB (typ).

Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)

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ASAHI KASEI

[AK4632]

Units

min

typ

max

Parameter

Speaker-Amp Characteristics: SPP/SPN pins, MIN Æ SPP/SPN, ALC2=OFF, R_L=8Ω, BTL, SVDD=3.3V

Output Voltage

(Note 14)

S/(N+D)

2.47

3.10

20

-

80

8

-

3.09

4.00

60

50

20

90

-

3.71

4.80

-

30

Vpp

dB

Ω

SPKG1-0 bits = “00” (-0.5dBFS)

SPKG1-0 bits = “01” (-0.5dBFS)

at 150mW Output

at 240mW Output

at 400mW Output

S/N (Note 16)

Load Resistance

Load Capacitance

-

pF

Speaker-Amp Characteristics: MIN Æ SPP/SPN pins, ALC2=OFF, C_L=3µF, R_serial=10Ω x 2, BTL, SVDD=5.0V

Output Voltage

(Note 14)

-

6.80

-

20

80

50

-

6.72

8.50

60

50

80

-

Vpp

dB

Ω

SPKG1-0 bits = “10”

SPKG1-0 bits = “11”

SPKG1-0 bits = “10”

SPKG1-0 bits = “11”

10.20

-

90

-

3

S/(N+D) (Note 14)

(Note 15)

S/N (Note 15) (Note 16)

Load Impedance (Note 17)

Load Capacitance

-

µF

BEEP Input: BEEP pin, External Input Resistance= 20kΩ

Maximum Input Voltage (Note 18)

Output Voltage (Input Voltage=0.6Vpp)

BEEP Æ SPP/SPN (SPKG1-0 bits = “00”)

BEEP Æ AOUT

-

1.98

-

Vpp

0.74

0.3

1.48

0.6

2.22

0.9

Vpp

Mono Input: MIN pin

Maximum Input Voltage (Note 19)

-

12

2.18

24

-

36

Vpp

kΩ

Input Resistance

(Note 20)

Mono Output: MOUT pin, DAC→ MOUT

Output Voltage

Load Resistance

Load Capacitance

(Note 21)

1.78

10

-

1.98

-

2.18

-

30

Vpp

kΩ

pF

Note 14. The full scale of Input signal of MIN pin is 1.98Vpp.

Note 15. In case of measuring between SPP pin and SPN pin directly.

Note 16. There are no relations with the setup of SPKG1-0 bits, and it is the same value.

Note 17. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 35. Load

capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be

connected at both SPP and SPN pins, respectively.

Note 18. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance(Rin).

Vout = 0.6 x AVDD x Rin/20kΩ(max).

Note 19. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.66 x AVDD (max)

Note 20. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ.

Note 21. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)

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ASAHI KASEI

[AK4632]

Parameter

min

typ

max

Units

Y Input Characteristics:

Maximum Input Voltage (Note 22)

Pull Down Current

-

1.2

2.0

-

Vpp

µA

V Output Characteristics:

Output Gain

Maximum Output

Voltage

VIN=100kHz (GCA=0dB)

at DC output

5.0

2.4

-

6.0

2.52

2.4

7.0

-

dB

Vpp

at Sag Compensation Output

100µF+2.2 uF, VVDD ≥ 3.135 V

at Sag Compensation Output

47µF+1.0uF, VVDD ≥ 3.135 V

at DC output

-

2.4

-

Vpp

Clamp Voltage

S/N

Secondary Distortion VIN=3.58MHz, 1.0Vpp(Sin Wave)

-

0.15

66

-45

-

V

dB

BW=100kH ∼ 6MHz

(Note 23)

Load Resistance

Load Capacitance

140

-

150

-

15

400

Ω

pF

C1(See Figure 2)

C2(See Figure 2) (Note 24)

LPF

Frequency Response

Input=1.26Vpp, Sin Wave Response at 27MHz

(0dB at 100kHz)

-3.0

-

-0.5

-30

-

dB

Response at 6.75MHz

-20

Group Delay

-

10

100

0.9

nsec

dB

|GD3MHz −GD6MHz|

GCA Characteristics:

Step Size

0.1

0.5

GCA = -1.0dB ∼ +10.5dB

Power Supplies

Power Up (PDN = “H”)

All Circuit Power-up: (Note 25)

AVDD+DVDD

fs=8kHz

fs=48kHz

-

9

11.5

-

mA

17.5

SVDD: Speaker-Amp Normal Operation (SPPS bit = “1”, No Output)

SVDD=3.3V

SVDD=5.0V

-

7

9

-

27

mA

VVDD (Note 26)

VVDD=3.3V

VVDD=5.0V

-

7.5

8

-

12

mA

Power Down (PDN = “L”) (Note 27)

AVDD+DVDD+SVDD+VVDD

-

10

100

µA

Note 22. Input Voltage doesn’t depend on VVDD.

Note 23. In the case of using Sag Compensation Circuit with 47µF+ 1.0uF and SAGC1-0 bits = “10”

Note 24. R1 and C2 compose of Low Pass Filter(LPF) in Figure 2. The cut off frequency of LPF is 10.6MHz at C2 =

400pF.

R1

75 ohm

Video Signal Output

R2

75 ohm

C1

C2

Figure 2. Load Capacitance C1 and C2

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ASAHI KASEI

[AK4632]

Note 25. PLL Master Mode (MCKI=12.288MHz) and PMV=PMMIC = PMADC = PMDAC = PMSPK = PMVCM =

PMPLL = MCKO = PMAO = PMBP = MPWR = M/S =“1”. And output current from MPI pin is 0mA. When the

AK4632 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 7mA@fs=8kHz,

9.5mA@fs=48kHz).

Note 26. This is the case of SAGC bits = “00” and no load resistance and capacitance. When SAGC bits = “10” and Black

signal is output, this current is typ.8mA. In the case of DC Output, this current increases by DC voltage / 150 Ω.

DC Output Voltage is 0V at PMV bit = “0”, and then DC current doesn’t flow. When any signal isn’t input at

using Sag Compensation Circuit, PMV bit should be set to “0”.

Note 27. MCKI pin is fixed to DVSS and all digital inputs pins except MCKI pin are fixed to DVSS or DVSS.

FILTER CHRACTERISTICS

(Ta = 25°C; AVDD, DVDD = 2.6 ∼ 3.6V; SVDD =2.6 ∼ 5.25V; VVDD =2.8 ∼ 5.25V; fs=8kHz)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

±0.16dB

−0.66dB

−1.1dB

−6.9dB

PB

0

-

4.7

-

3.5

3.6

4.0

-

3.0

-

kHz

dB

Passband

(Note 28)

Stopband

Passband Ripple

(Note 28)

SB

PR

-

±0.1

Stopband Attenuation

SA

GD

∆GD

73

-

dB

1/fs

µs

Group Delay

(Note 29)

17.1

0

Group Delay Distortion

ADC Digital Filter (HPF):

Frequency Response (Note 28) −3.0dB

FR

-

0.62

1.81

3.99

-

Hz

−0.5dB

−0.1dB

DAC Digital Filter:

Passband

(Note 28) ±0.1dB

−0.7dB

PB

0

-

4.6

-

59

-

3.6

4.0

-

3.6

-

±0.01

-

kHz

−6.0dB

Stopband

Passband Ripple

Stopband Attenuation

Group Delay

(Note 28)

SB

PR

SA

GD

kHz

dB

(Note 29)

16.8

1/fs

DAC Digital Filter + Analog Filter:

Frequency Response: 0 ∼ 3.4kHz

FR

-

±1.0

-

dB

Note 28. The passband and stopband frequencies are proportional to fs (system sampling rate).

For example, ADC is PB=0.45*fs (@-1.1dB). A reference of frequency response is 1kHz.

Note 29. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the

16-bit data of a channel from the input register to the output register of the ADC. This time includes the group

delay of the HPF. For the DAC, this time is from setting the 16-bit data of a channel from the input register to the

output of analog signal.

DC CHRACTERISTICS

(Ta = 25°C; AVDD, DVDD = 2.6 ∼ 3.6V; SVDD =2.6 ∼ 5.25V)

Parameter

Symbol

min

typ

max

Units

V

High-Level Input Voltage

Low-Level Input Voltage

High-Level Output Voltage

Low-Level Output Voltage

Input Leakage Current

VIH

VIL

70%DVDD

-

30%DVDD

(Iout=−80µA)

(Iout= 80µA)

VOH

VOL

Iin

DVDD−0.4

-

V

-

0.4

±10

-

µA

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ASAHI KASEI

[AK4632]

SWITING CHARACTERISTICS

(Ta = 25°C; AVDD, DVDD = 2.6 ∼ 3.6V; SVDD =2.6 ∼ 5.25V ; VVDD =2.8 ∼ 5.25V; C_L=20pF)

Parameter

Symbol

min

typ

max

Units

PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 3)

MCKI Input: Frequency

Pulse Width Low

Pulse Width High

MCKO Output:

fCLK

tCLKL

tCLKH

11.2896

0.4/fCLK

-

27.0

MHz

ns

-

ns

Frequency

fMCK

dMCK

fFCK

dFCK

tBCK

dBCK

-

40

-

256 x fFCK

-

60

-

kHz

%

Duty Cycle except fs=29.4kHz, 32kHz

fs=29.4kHz, 32kHz (Note 30)

FCK Output: Frequency

Duty Cycle

50

33

-

%

8

-

48

-

kHz

%

50

BICK: Period (BCKO1-0 = “00”)

(BCKO1-0 = “01”)

-

1/16fFCK

1/32fFCK

1/64fFCK

50

-

ns

-

ns

(BCKO1-0 = “10”)

-

ns

Duty Cycle

-

%

Audio Interface Timing

DSP Mode: (Figure 4, Figure 5)

FCK “↑” to BICK “↑” (Note 31)

FCK “↑” to BICK “↓” (Note 32)

BICK “↑” to SDTO (BCKP = “0”)

BICK “↓” to SDTO (BCKP = “1”)

SDTI Hold Time

tDBF

tBSD

tSDH

tSDS

0.5 x tBCK -40

0.5 x tBCK

0.5 x tBCK + 40

ns

0.5 x tBCK -40

0.5 x tBCK

0.5 x tBCK +40

-70

50

-

70

-

SDTI Setup Time

50

-

Except DSP Mode: (Figure 6)

BICK “↓” to FCK Edge

FCK to SDTO (MSB)

tBFCK

tFSD

-40

-70

-

40

70

ns

(Except I²S mode)

BICK “↓” to SDTO

SDTI Hold Time

tBSD

tSDH

tSDS

-70

50

-

70

-

ns

SDTI Setup Time

50

-

MS0396-E-00

2005/06

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ASAHI KASEI

[AK4632]

Parameter

Symbol

min

typ

max

Units

PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 7, Figure 8)

FCK: Frequency

DSP Mode: Pulse Width High

Except DSP Mode: Duty Cycle

BICK: Period

fFCK

tFCKH

duty

7.35

tBCK-60

45

8

-

26

kHz

1/fFCK-tBFCK

ns

%

ns

55

tBCK

1/64fFCK

240

1/16fFCK

Pulse Width Low

Pulse Width High

tBCKL

tBCKH

-

240

PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 7, Figure 8)

FCK: Frequency

DSP Mode: Pulse width High

fFCK

tFCKH

duty

7.35

8

48

kHz

ns

tBCK-60

-

1/fFCK-tBFCK

Except DSP Mode: Duty Cycle

BICK: Period (PLL3-0 = “0001”)

(PLL3-0 = “0010”)

45

-

55

-

%

tBCK

tBCKL

tBCKH

-

1/16fFCK

ns

-

1/32fFCK

-

ns

(PLL3-0 = “0011”)

Pulse Width Low

-

1/64fFCK

-

ns

0.4 x tBCK

-

ns

Pulse Width High

-

ns

PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 9)

MCKI Input: Frequency

Pulse Width Low

Pulse Width High

MCKO Output:

fCLK

fCLKL

fCLKH

11.2896

0.4/fCLK

-

27.0

MHz

ns

-

ns

Frequency

fMCK

dMCK

fFCK

-

256 x fFCK

-

kHz

%

Duty Cycle except fs=29.4kHz, 32kHz

fs=29.4kHz, 32kHz (Note 30)

FCK: Frequency

40

-

50

33

-

60

-

%

8

48

kHz

ns

DSP Mode: Pulse width High

Except DSP Mode: Duty Cycle

BICK: Period

tFCKH

duty

tBCK-60

45

-

1/fFCK-tBFCK

-

55

%

tBCK

1/64fFCK

0.4 x tBCK

-

1/16fFCK

ns

Pulse Width Low

tBCKL

tBCKH

-

ns

Pulse Width High

-

ns

Audio Interface Timing

DSP Mode: (Figure 10,Figure 11)

FCK “↑” to BICK “↑” (Note 31)

FCK “↑” to BICK “↓” (Note 32)

BICK “↑” to FCK “↑” (Note 31)

BICK “↓” to FCK “↑” (Note 32)

BICK “↑” to SDTO (BCKP = “0”)

BICK “↓” to SDTO (BCKP = “1”)

SDTI Hold Time

tFCKB

tBFCK

tBSD

0.4 x tBCK

-

ns

0.4 x tBCK

-

0.4 x tBCK

-

80

-

tBSD

-

tSDH

50

SDTI Setup Time

tSDS

-

Except DSP Mode: (Figure 13)

FCK Edge to BICK “↑” (Note 33)

BICK “↑” to FCK Edge (Note 33)

FCK to SDTO (MSB) (Except I²S mode)

BICK “↓” to SDTO

tFCKB

tBFCK

tFSD

50

-

ns

80

-

tBSD

tSDH

tSDS

-

SDTI Hold Time

50

SDTI Setup Time

-

MS0396-E-00

2005/06

- 12 -

ASAHI KASEI

[AK4632]

Parameter

Symbol

min

typ

Max

Units

EXT Slave Mode (Figure 12)

MCKI Frequency: 256fs

512fs

fCLK

tCLKL

tCLKH

fFCK

1.8816

3.7632

7.5264

0.4/fCLK

7.35

2.048

12.288

MHz

ns

4.096

13.312

1024fs

8.192

13.312

Pulse Width Low

Pulse Width High

FCK Frequency (MCKI = 256fs)

(MCKI = 512fs)

(MCKI = 1024fs)

Duty Cycle

-

ns

8

-

48

26

13

55

-

kHz

%

fFCK

7.35

fFCK

7.35

duty

45

BICK Period

tBCK

tBCKL

tBCKH

312.5

130

-

ns

BICK Pulse Width Low

Pulse Width High

-

130

-

Audio Interface Timing (Figure 13)

FCK Edge to BICK “↑“ (Note 33)

BICK “↑“ to FCK Edge (Note 33)

FCK to SDTO (MSB) (Except I²S mode)

BICK “↓“ to SDTO

tFCKB

tBFCK

tFSD

50

-

ns

80

-

tBSD

tSDH

tSDS

-

SDTI Hold Time

50

SDTI Setup Time

-

Note 30. Duty Cycle = (the width of “L” ) / (the period of clock) × 100

Note 31. MSBS, BCKP bits = “00” or “11”

Note 32. MSBS, BCKP bits = “01” or “10”

Note 33. BICK rising edge must not occur at the same time as FCK edge.

Parameter

Symbol

min

typ

max

Units

Control Interface Timing:

CCLK Period

tCCK

tCCKL

tCCKH

tCDS

200

80

-

ns

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

80

40

tCDH

tCSW

tCSS

40

CSN “H” Time

CSN “↓“ to CCLK “↑“

CCLK “↑“ to CSN “↑“

150

50

tCSH

Reset Timing

PDN Pulse Width

(Note 34)

(Note 35)

tPD

150

-

ns

PMADC “↑“ to SDTO valid

tPDV

1059

1/fs

Note 34. The AK4632 can be reset by the PDN pin = “L”

Note 35. This is the count of FCK “↑“ from the PMADC = “1”.

MS0396-E-00

2005/06

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ASAHI KASEI

[AK4632]

Timing Diagram

1/fCLK

VIH

VIL

MCKI

tCLKH

dFCK

tCLKL

dFCK

1/fFCK

50%DVDD

FCK

1/fMCK

MCKO

50%DVDD

tMCKOH

tMCKOL

dMCK = tMCKOL x fMCK x 100

Figure 3. Clock Timing (PLL Master mode)

FCK

50%DVDD

tBCK

tDBF

dBCK

BICK

(BCKP = "0")

50%DVDD

BICK

(BCKP = "1")

tBSD

SDTO

50%DVDD

MSB

tSDH

tSDS

VIH

VIL

SDTI

MSB

Figure 4. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = “0”)

MS0396-E-00

2005/06

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ASAHI KASEI

[AK4632]

FCK

50%DVDD

tBCK

tDBF

dBCK

BICK

(BCKP = "1")

50%DVDD

BICK

(BCKP = "0")

tBSD

SDTO

50%DVDD

MSB

tSDH

tSDS

VIH

VIL

SDTI

MSB

Figure 5. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = “1”)

50%DVDD

FCK

tBFCK

dBCK

BICK

SDTO

SDTI

50%DVDD

tFSD

tBSD

tSDS

tSDH

VIH

VIL

Figure 6. Audio Interface Timing (PLL Master mode & Except DSP mode)

MS0396-E-00

2005/06

- 15 -

ASAHI KASEI

[AK4632]

1/fFCK

VIH

VIL

FCK

tFCKH

tBCKH

tBFCK

tBCK

VIH

VIL

BICK

(BCKP = "0")

tBCKL

VIH

VIL

BICK

(BCKP = "1")

Figure 7. Clock Timing (PLL Slave mode; PLL Reference clock = FCK or BICK pin & DSP mode; MSBS = 0)

1/fFCK

VIH

FCK

VIL

tFCKH

tBCKH

tBFCK

tBCK

VIH

VIL

BICK

(BCKP = "1")

tBCKL

VIH

VIL

BICK

(BCKP = "0")

Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1)

MS0396-E-00

2005/06

- 16 -

ASAHI KASEI

[AK4632]

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fFCK

VIH

VIL

FCK

tFCKH

tFCKL

tBCK

VIH

VIL

BICK

tBCKH

tBCKL

1/fMCK

50%DVDD

MCKO

tMCKOH

tMCKOL

dMCK = tMCKOL x fMCK x 100

Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)

MS0396-E-00

2005/06

- 17 -

ASAHI KASEI

[AK4632]

tFCKH

VIH

VIL

FCK

tFCKB

VIH

VIL

BICK

(BCKP = "0")

VIH

VIL

BICK

(BCKP = "1")

tBSD

SDTO

SDTI

50%DVDD

MSB

tSDH

tSDS

VIH

VIL

MSB

Figure 10. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)

tFCKH

VIH

FCK

VIL

tFCKB

VIH

VIL

BICK

(BCKP = "1")

VIH

VIL

BICK

(BCKP = "0")

tBSD

SDTO

50%DVDD

MSB

tSDS

tSDH

VIH

VIL

SDTI

MSB

Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)

- 18 -

MS0396-E-00

2005/06

ASAHI KASEI

[AK4632]

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fFCK

VIH

VIL

FCK

tFCKH

tBCKH

tFCKL

tBCKL

tBCK

VIH

VIL

BICK

Figure 12. Clock Timing (EXT Slave mode)

VIH

FCK

VIL

tBFCK

tFCKB

VIH

VIL

BICK

SDTO

SDTI

tFSD

tBSD

50%DVDD

MSB

tSDS

tSDH

VIH

VIL

Figure 13. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode)

MS0396-E-00

2005/06

- 19 -

ASAHI KASEI

[AK4632]

VIH

CSN

VIL

tCSS

tCCKL

tCCKH

VIH

VIL

CCLK

CDTI

tCCK

tCDH

tCDS

VIH

VIL

C1

C0

R/W

Figure 14. WRITE Command Input Timing

tCSW

VIH

VIL

CSN

tCSH

VIH

VIL

CCLK

CDTI

VIH

VIL

D2

D1

D0

Figure 15. WRITE Data Input Timing

VIH

VIL

CSN

tPDV

SDTO

50%DVDD

Figure 16. Power Down & Reset Timing 1

tPD

PDN

VIL

Figure 17. Power Down & Reset Timing 2

MS0396-E-00

2005/06

- 20 -

ASAHI KASEI

[AK4632]

OPERATION OVERVIEW

System Clock

There are the following four clock modes to interface with external devices. (See Table 1 and Table 2)

Mode

PMPLL bit M/S bit

PLL3-0 bit

See Table 4

MCKPD bit

0

Figure

Figure 19

PLL Master Mode

PLL Slave Mode 1

(PLL Reference Clock: MCKI pin)

PLL Slave Mode 2

(PLL Reference Clock: FCK or BICK pin)

1

0

See Table 4

0

1

Figure 20

1

0

Figure 21

EXT Slave Mode

Invalid state (Note 36)

0

1

X

0

X

Figure 22

-

Table 1. Clock Mode Setting (X: Don’t care)

Note 36. If this mode is selected, the invalid clocks are output from MCKO, FCK and BICK pins.

Mode

MCKO bit

MCKO pin

MCKI pin

BICK pin

FCK pin

Master Clock

Input for PLL

(Note 37)

0

1

16fs/32fs/64fs

Output

1fs

Output

“L” Output

PLL Master Mode

256fs Output

Master Clock

Input for PLL

(Note 37)

0

1

“L” Output

PLL Slave Mode 1

(PLL Reference Clock: MCKI pin)

16fs/32fs/64fs

Input

1fs

Input

256fs Output

PLL Slave Mode 2

(PLL Reference Clock: FCK or BICK pin)

16fs/32fs/64fs

Input

1fs

Input

0

GND

“L” Output

256fs/

512fs/

1024fs

Input

1fs

Input

≥ 32fs

Input

EXT Slave Mode

Note 37. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz

Table 2. Clock pins state in Clock Mode

[Pull-down resistor of MCKI pin]

When the master clock is input, MCKPD bit should be “0”. When the MCKI pin is floating, the pin should be pulled-down

by internal 25kΩ resistor at MCKPD bit = “1”(Default).

MCKI

MCKPD bit ="0"

25kΩ

AK4632

Figure 18. Pull-down resistor of MCKI pin

MS0396-E-00

2005/06

- 21 -

ASAHI KASEI

[AK4632]

Master Mode/Slave Mode

The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the

AK4632 is power-down mode (PDN pin = “L”) and exits reset state, the AK4632 is slave mode. After exiting reset state,

the AK4632 goes master mode by changing M/S bit = “1”.

When the AK4632 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and

BICK pins of the AK4632 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating

state.

M/S bit

Mode

0

1

Slave Mode

Master Mode

Default

Table 3. Select Master/Salve Mode

PLL Mode

When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the

PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4632 is supplied to a stable clocks after

PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.

1) Setting of PLL Mode

PLL

Reference

Clock Input

R and C of

VCOC pin

PLL Lock

Time

(max)

PLL3 PLL2 PLL1 PLL0

Input

Frequency

Mode

bit

C[F]

R[Ω]

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FCK pin

BICK pin

MCKI pin

N/A

1fs

16fs

32fs

6.8k

10k

220n

4.7n

10n

160ms

2ms

Default

64fs

2ms

11.2896MHz

12.288MHz

12MHz

24MHz

13.5MHz

27MHz

40ms

12

13

Others

1

10n

Others

Table 4. Setting of PLL Mode (*fs: Sampling Frequency)

2) Setting of sampling frequency in PLL Mode.

When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS2-0 bits as

defined in Table 5.

Mode

0

1

2

3

4

5

6

7

10

11

14

15

Others

FS3 bit

FS2 bit

FS1 bit

FS0 bit

Sampling Frequency

8kHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Default

12kHz

16kHz

24kHz

7.35kHz

11.025kHz

14.7kHz

22.05kHz

32kHz

48kHz

29.4kHz

44.1kHz

N/A

Others

Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”

MS0396-E-00

2005/06

- 22 -

ASAHI KASEI

[AK4632]

When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3,

FS1-0 bits. (See Table 6)

Mode

FS3 bit

FS2 bit

FS1 bit

FS0 bit

Sampling Frequency Range

0

1

Don’t care

0

1

0

1

0

1

0

1

2

3

6

7

0

1

Default

7.35kHz ≤ fs ≤ 8kHz

8kHz < fs ≤ 12kHz

12kHz < fs ≤ 16kHz

16kHz < fs ≤ 24kHz

24kHz < fs ≤ 32kHz

32kHz < fs ≤ 48kHz

N/A

Others

Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”

PLL Unlock State

1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

In this mode, irregular frequency clocks are output from FCK, BICK and MCKO pins after PMPLL bit = “0” Æ “1” or

sampling frequency is changed. After that PLL is unlocked, BICK and FCK pins output “L” for a moment, and invalid

frequency clock is output from MCKO pin at MCKO bit = “1”. If MCKO bit is “0”, MCKO pin is output to “L”. (See

Table 7)

After the PLL is locked, a first period of FCK and BICK may be invalid clock, but these clocks return to normal state after

a period of 1/fs.

MCKO pin

MCKO bit = “0” MCKO bit = “1”

PLL State

BICK pin

FCK pin

Invalid

256fs Output

Invalid

“L” Output

See Table 9

Invalid

“L” Output

1fs Output

After that PMPLL bit “0” Æ “1”

PLL Unlock

PLL Lock

“L” Output

Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

In this mode, an invalid clock is output from MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is changed.

After that, 256fs is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is

unlocked. For DAC, the output signal should be muted by writing “0” to DACA and DACM bits in Addr=02H.

MCKO pin

PLL State

MCKO bit = “0”

“L” Output

MCKO bit = “1”

Invalid

After that PMPLL bit “0” Æ “1”

PLL Unlock

Invalid

“L” Output

PLL Lock

256fs Output

“L” Output

Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

MS0396-E-00

2005/06

- 23 -

ASAHI KASEI

[AK4632]

PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

When an external clock (11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the

MCKO, BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs,

the output is enabled by MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (See Table 9)

When BICK output frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode).

11.2896MHz, 12MHz, 12.288MHz

13.5MHz, 24MHz, 27MHz

AK4632

DSP or P

µ

MCKI

256fs

16fs, 32fs, 64fs

1fs

MCKO

BICK

FCK

MCLK

BCLK

FCK

SDTI

SDTO

SDTI

SDTO

Figure 19. PLL Master Mode

BICK Output

Frequency

Mode

BCKO1

BCKO0

0

1

2

3

0

1

0

1

0

1

16fs

32fs

64fs

N/A

Default

Table 9. BICK Output Frequency at Master Mode

MS0396-E-00

2005/06

- 24 -

ASAHI KASEI

[AK4632]

PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

A reference clock of PLL is selected among the input clocks to MCKI, BICK or FCK pin. The required clock to the

AK4632 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency

is 16fs, the audio interface format supports only Mode 0 (DSP Mode).

a) PLL reference clock: BICK or FCK pin

In the case of using BICK as PLL reference clock, the sampling frequency corresponds to 7.35kHz to 48kHz by

changing FS3-0 bits. In the case of using FCK, the sampling frequency corresponds to 7.35kHz to 26kHz. (SeeTable

6)

AK4632

MCKO

DSP or P

µ

MCKI

BICK

FCK

16fs, 32fs, 64fs

1fs

BCLK

FCK

SDTI

SDTO

SDTI

SDTO

Figure 20. PLL Slave Mode 1 (PLL Reference Clock: FCK or BICK pin)

b) PLL reference clock: MCKI pin

BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK dose not

matter. Sampling frequency can be selected by FS3-0 bits. (See Table 5)

11.2896MHz, 12MHz, 12.288MHz

13.5MHz, 24MHz, 27MHz

AK4632

DSP or P

µ

MCKI

256fs

16fs, 32fs, 64fs

1fs

MCKO

BICK

FCK

MCLK

BCLK

FCK

SDTI

SDTO

SDTI

SDTO

Figure 21. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin)

The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation

(PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4632 may draw excess current and it is

not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present,

the ADC and DAC should be in the power-down mode (PMADC bit =PMDAC bit = “0”).

MS0396-E-00

2005/06

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ASAHI KASEI

[AK4632]

EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

When PMPLL bit is “0”, the AK4632 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit

is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI

(256fs, 512fs or 1024fs), FCK (fs) and BICK (32fs∼). The master clock (MCKI) should be synchronized with FCK. The

phase between these clocks does not matter. The input frequency of MCKI is selected by FS3-0 bits. (See Table 10)

Mode

FS3-2 bits

FS1 bit

FS0 bit

MCKI Input

Frequency

256fs

Sampling Frequency

Range

Don’t care

0

1

0

1

Default

0

1

2

3

0

1

7.35kHz ≤ fs ≤ 48kHz

7.35kHz < fs ≤ 13kHz

7.35kHz < fs ≤ 48kHz

7.35kHz < fs ≤ 26kHz

1024fs

256fs

512fs

Table 10. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

External Slave Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.

The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.

When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output

through AOUT amp at fs=8kHz is shown in Table 11.

S/N

MCKI

(fs=8kHz, 20kHzLPF + A-weight)

256fs

512fs

1024fs

83dB

93dB

Table 11. Relationship between MCKI and S/N of AOUT

The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation

(PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4632 may draw excess current and it is

not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present,

the ADC and DAC should be in the power-down mode (PMADC bit = PMDAC bit = “0”).

AK4632

MCKO

DSP or P

µ

256fs, 512fs or 1024fs

MCKI

BICK

FCK

MCLK

BCLK

FCK

32fs, 64fs

1fs

SDTI

SDTO

SDTI

SDTO

Figure 22. EXT Slave Mode

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ASAHI KASEI

[AK4632]

Audio Interface Format

Four types of data formats are available and are selected by setting the DIF1-0 bits. (See Table 12) In all modes, the serial

data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and

BICK are output from AK4632 in master mode, but must be input to AK4632 in slave mode.

In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.

Mode

DIF1

DIF0

SDTO (ADC)

DSP Mode

SDTI (DAC)

DSP Mode

MSB justified

BICK

≥ 16fs

≥ 32fs

Figure

See Table 13

Figure 27

Figure 28

Figure 29

0

1

2

3

0

1

0

1

0

1

MSB justified

Default

I²S compatible I²S compatible

Table 12. Audio Interface Format

In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.

When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK.

When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK.

MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK.

MSBS bit BCKP bit

Audio Interface Format

Figure 23

0

1

0

1

0

1

Default

Figure 24

Figure 25

Figure 26

Table 13. Audio Interface Format in Mode 0

If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at

8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and

this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit

data.

System Reset

Upon power-up, reset the AK4632 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their

initial values.

The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle

time is 1059/fs, or 133ms@fs=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are

forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete.

The DAC does not require an initialization cycle.

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ASAHI KASEI

[AK4632]

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

15

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

Don’t Care

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 23. Mode 0 Timing (BCKP = “0”, MSBS = “0”)

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

15

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

Don’t Care

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 24. Mode 0 Timing (BCKP = “1”, MSBS = “0”)

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ASAHI KASEI

[AK4632]

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

15

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

Don’t Care

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 25. Mode 0 Timing (BCKP = “0”, MSBS = “1”)

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

15

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

Don’t Care

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 26. Mode 0 Timing (BCKP = “1”, MSBS = “1”)

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ASAHI KASEI

[AK4632]

FCK

0

1

2

3

8

9

10 11

12

13 14

15

0

1

2

3

8

9

10 11

12

13 14

15

0

1

BICK(32fs)

SDTO(o)

15 14

8

7

6

5

4

3

2

1

0

15

13

SDTI(i)

15 14

5

2

13

Don’t Care

0

1

2

3

14

15 16

17

18

31

0

1

2

3

14

15 16

17

18

31

0

1

BICK(64fs)

SDTO(o)

15 14 13

2

1

0

15

Don’t Care

15:MSB, 0:LSB

15 14

1

0

Don’t Care

SDTI(i)

Data

1/fs

Figure 27. Mode 1 Timing

FCK

0

1

2

8

9

10 11

12

13 14

15

0

1

2

8

9

10 11

12

13 14

15

0

1

BICK(32fs)

SDTO(o)

15 14

8

7

6

5

4

3

2

1

0

15

SDTI(I)

15 14

5

2

Don’t Care

0

1

2

3

14

15 16

17

18

31

0

1

2

3

14

15 16

17

18

31

0

1

BICK(64fs)

SDTO(o)

15 14 13 13

2

1

0

15

SDTI(i)

15 14 13 13

15:MSB, 0:LSB

Don’t Care

Data

1/fs

Figure 28. Mode 2 Timing

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ASAHI KASEI

[AK4632]

FCK

0

1

2

3

4

9

10 11

12

13 14

15

0

1

2

3

4

9

10 11

12

13 14

15

0

1

BICK(32fs)

SDTO(o)

15

13

7

6

5

4

3

2

1

0

14

SDTI(i)

15 14 13

6

3

0

1

2

3

4

14

15 16

17

18

31

0

1

2

3

4

14

15 16

17

18

31

0

1

BICK(64fs)

SDTO(o)

15 14

2

1

0

13

15 14 13

15:MSB, 0:LSB

Don’t Care

SDTI(i)

Data

1/fs

Figure 29. Mode 3 Timing

Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.25Hz

(@fs=8kHz) and scales with sampling rate (fs).

MIC Gain Amplifier

The AK4632 has a Gain Amplifier for Microphone input. This gain is 0dB, +20dB, +26dB or +32dB, selected by the

MGAIN1-0 bit. The typical input impedance is 30kΩ.

MGAIN1 bit MGAIN0 bit

Input Gain

0dB

+20dB

+26dB

+32dB

0

1

0

1

0

1

Default

Table 14. Input Gain

MIC Power

The MPI pin supplies power for the Microphone. This output voltage is typically 0.75 x AVDD and the load resistance is

minimum 2kΩ. No capacitor must not be connected directly to MPI pin. (See Figure 30)

MIC Power

MPI pin

≥ 2k Ω

Microphone

MIC pin

MIC-Amp

Figure 30. MIC Block Circuit

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ASAHI KASEI

[AK4632]

Manual Mode

The AK4632 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below.

1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc)

2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed.

For example; When the change of the sampling frequency.

3. When IPGA is used as a manual volume.

When IPGA6-0 bits are written at manual mode, the counter for zero cross time out is reset and restart. The IPGA6-0 bits

value are reflected to IPGA at zero cross or zero cross time out. The time of zero cross time out is set by ZTM1-0 bits.

When writing to IPGA6-0 bits continually, the control register should be written by an interval of more than zero crossing

timeout.

MIC-ALC Operation

The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”.

[1] ALC1 Limiter Operation

When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value

is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically.

When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done

continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after completing

the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH.

When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation

function so that the IPGA value is attenuated at the zero-detect points of the waveform.

[2] ALC1 Recovery Operation

The ALC1 recovery refers to the amount of time that the AK4632 will allow a signal to exceed a predetermined limiting

value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait

period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery Waiting

Counter Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this operation

up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero

crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery

operation starts.

During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the

ALC1 recovery operation changes immediately into an ALC1 limiter operation.

In the case of “(Recovery waiting counter reset level) ≤ IPGA Output Level < Limiter detection level” during the ALC1

recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of “(Recovery waiting

counter reset level) > IPGA Output Level”, the wait timer for the ALC1 recovery operation starts.

The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation

becomes faster than a normal recovery operation.

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ASAHI KASEI

[AK4632]

[3] Example of ALC1 Operation

Table 15 shows the example of the ALC1 setting. In case of this example, ALC1 operation starts from 0dB.

fs=8kHz

Operation

fs=16kHz

Data Operation

Register Name Comment

Data

1

00

0

LMTH

LTM1-0

ZELM

Limiter detection Level

-4dBFS

Don’t use

Enable

1

00

0

-4dBFS

Don’t use

Enable

Limiter operation period at ZELM = 1

Limiter zero crossing detection

Zero crossing timeout period

Recovery waiting period

ZTM1-0

00

16ms

01

16ms

WTM1-0

*WTM1-0 bits should be the same data

as ZTM1-0 bits

00

16ms

01

16ms

REF6-0

IPGA6-0

LMAT1-0

RATT

Maximum gain at recovery operation

IPGA gain at the start of ALC1 operation

Limiter ATT Step

Recovery GAIN Step

ALC1 Enable bit

47H

10H

00

0

+27.5dB

0dB

1 step

Enable

47H

10H

00

0

+27.5dB

0dB

1 step

Enable

ALC1

1

Table 15. Examples of the ALC1 Setting

The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1

operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.

• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits

When setting IPGA gain at the start of ALC1 operation, IPGA6-0 bits should be set while PMMIC bit is “1” and ALC1 bit

is “0”. When PMMIC bit = “1”, IPGA6-0 bits value aren’t reflected to IPGA. When ALC1 bit is changed from “1” to “0”,

IPGA holds the last gain value set automatically by ALC1 operation.

Example:

Limiter = Zero crossing Enable

Recovery Cycle = 16ms @ fs= 8kHz

Limiter and Recovery Step = 1

Maximum Gain = +27.5dB

Limiter Detection Level = -4dBFS

Manual Mode

ALC2 bit = “1” (default)

WR (ZTM1-0, WTM1-0, LTM1-0)

WR (REF6-0)

(1) Addr=06H, Data=00H

(2) Addr=08H, Data=47H

(3) Addr=09H, Data=10H

(4) Addr=07H, Data=61H

* The value of IPGA should be

the same or smaller than REF’s

WR (IPGA6-0)

WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)

ALC1 Operation

Note : WR : Write

Figure 31. Registers set-up sequence at the ALC1 operation

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ASAHI KASEI

[AK4632]

Digital Output Volume

The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVOL7-0 bits. The

volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with MUTE. This

volume has a soft transition function. It takes 1061/fs or 256/fs from 00H to FFH.

DVOL7-0

00H

01H

02H

•

Gain

+12.0dB

+11.5dB

+11.0dB

•

18H

0dB

Default

•

FDH

FEH

FFH

−114.5dB

−115.0dB

MUTE (−∞)

Table 16. Digital Output Volume Code Table

The transition time from 00H to FFH of DVOL7-0 bits

DVTM bit

Transition Time

1061/fs

fs=8kHz

133msec

32msec

fs=22.05kHz

48msec

0

1

256/fs

12msec

Table 17.Setting of transition time

BEEP Input

When the PMBP bit is set to “1”, the beep input is powered-up. And when the BEEPS bit is set to “1”, the input signal

from the BEEP pin is output to Speaker-Amp. When the BEEPA bit is set to “1”, the input signal from the BEEP pin is

output to the mono line output amplifier. The external resister Ri adjusts the signal level of BEEP input. The gains are

shown in Table 18, when Ri = 20kΩ. These gain are in inverse proportion to Ri.

Rf

Ri

-

+

BEEP

Figure 32. Block Diagram of BEEP pin

SPKG1-0 bits

BEEP Æ SPP/SPN Gain

+7.89dB

BEEP Æ AOUT Gain

00

01

10

11

0dB

+9.93dB

+14.11dB

+16.15dB

Table 18. Beep input gain at R_i= 20kΩ

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ASAHI KASEI

[AK4632]

MONO LINE OUTPUT (AOUT pin)

A signal of DAC is output from AOUT pin. When the DACA bit is “0”, this output is OFF. The load resistance is

10kΩ(min). When PMAO bit is “0” and AOPSN bit is “0”, the mono line output enters power-down and is pulled down by

100Ω(typ). If PMAO bit is controlled at AOPSN bit = “1”, POP noise will be reduced at power-up and down. Then, this

line should be pulled down by 20kΩ of resister after C-coupling shown in Figure 33. This rising and falling time is max

300 ms at C=1.0µF . When PMAO bit is “1” and AOPSN bit is “0”, the mono line output enters power-up state.

1µF

220Ω

AOUT

20kΩ

Figure 33. AOUT external circuit in case of using POP Reduction function.

AOUT Control Sequence in case of using POP Reduction Circuit

(2 )

(5 )

P M A O b it

(1 )

(3 )

(4 )

(6 )

A O P S N b it

A O U T p in

N o rm a l O u tp u t

≥ 3 0 0 m s

≥

3 0 0 m s

Figure 34. Mono Line Output Control Sequence in case of using POP Reduction function..

(1) Set AOPSN bit = “1”. Mono line output enters the power-save mode.

(2) Set PMAO bit = “1”. Mono line output exits the power-down mode.

AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF.

(3) Set AOPSN bit = “0” after AOUT pin rises up. Mono line output exits the power-save mode.

Mono line output is enabled.

(4) Set AOPSN bit = “1”. Mono line output enters power-save mode.

(5) Set PMAO bit = “1”. Mono line output enters power-down mode.

AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1µF.

(6) Set AOPSN bit = “0” after AOUT pin falls down. Mono line output exits the power-save mode.

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ASAHI KASEI

[AK4632]

Speaker Output

The power supply voltage for Speaker-Amp SVDD can be set to from 2.6V to 5.25V. However, SVDD should be set to

from 2.6V to 3.6V, when the load resistance is less than 50Ω(ex. a dynamic speaker).

The output signal from DAC is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output

controlled by BTL and a gain of the Speaker-Amp is set by SPKG1-0 bit. In the case of ALC2 OFF, the output voltage

depends on AVDD and SPKG1-0 bits. In the case of ALC2 ON, the output voltage depends on SVDD and SPKG1-0 bits.

The output level of ALC2 is proportional to SVDD.

SPKG1-0 bits

Gain

0dB

+2.04dB

+6.22dB

+8.26dB

00

01

10

11

(Note) These Gain from the level at SPKG1-0bits= “00”.

Table 19. Gain of Speaker-Amp at ALC2 OFF

Output Voltage from Speaker-Amp

Output Voltage from

SPKG1-0 bits

AVDD

3.3V

SVDD

3.3V

5.0V

at ALC2 OFF and DAC Input=0dBFS

Speaker-Amp at ALC ON

00

01

10

11

00

01

10

11

3.27Vpp, 167mW@8Ω

4.15Vpp, 269mW@8Ω

6.91Vpp (Note)

8.50Vpp (Note)

3.27Vpp

3.09Vpp, 150mW@8Ω

3.92Vpp, 240mW@8Ω

Not Available

6.34Vpp

4.15Vpp

6.91Vpp

8.50Vpp

8.02Vpp

(Note) This output voltage is assumed that the signal is not clipped. In actual, the signal will be clipped when DAC

outputs 0dBFS signal. The output power is 400mW@8Ω, SVDD=3.3V.

Table 20. Speaker-Amp Output Voltage

[Caution for using Piezo Speaker]

When a piezo speaker (load capacitance > 30pF) is used, resistances more than 10Ω should be inserted between SPP/SPN

pins and speaker in series, respectively, as shown in Figure 35. Zener diodes should be inserted between speaker and

GND as shown in Figure 35, in order to protect SPK-Amp of AK4632 from the power that the piezo speaker outputs

when the speaker is pressured. Zener diodes of the following Zener voltage should be used.

92% of SVDD ≤ Zener voltage of Zener diodo(ZD of Figure 35) ≤ SVDD+0.3V

Ex) In case of SVDD = 5.0V : 4.6V ≤ ZD ≤ 5.3V

For example, Zener diode which Zener voltage is 5.1V(Min :4.97V, Max 5.24V) can be used.

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ASAHI KASEI

[AK4632]

ZD

SPK-Amp

≥10Ω

SPP

SPN

≥10Ω

ZD

Figure 35. Circuit of Speaker Output(Load Capacitance > 30pF)

Speaker blocks (MOUT, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the

PMSPK bit is “0”, the MOUT, SPP and SPN pins are placed in a Hi-Z state.

When the PMSPK bit is “1” and SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is

placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. And then the Speaker output gradually changes to the

SVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4632 is powered-down, pop noise can be

also reduced by first entering power-save-mode.

PMSPK bit

SPPS bit

SPP pin

SPN pin

Hi-Z

SVDD/2

>0

Hi-Z

>t1(Note)

Figure 36. Power-up/Power-down Timing for Speaker-Amp

(Note)

“t1” depends on the time constant of input resistance of MIN and capacitor between MOUT pin and MIN pin. If

Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur.

Ex) C of MOUT pin – MIN pin = 0.1 µF, Input resistance of MIN pin = 36kΩ(Max) : t1 = 5τ = 18ms

C of MOUT pin – MIN pin and the Input resistance(Rin) of MIN pin compose of HPF which cut off

frequency(fc) are the followings.

fc = 66Hz@Rin=24kΩ(typ), 133Hz@Rin=12kΩ(min), 44Hz@Rin=36kΩ(max)

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ASAHI KASEI

[AK4632]

SPK-ALC Operation

The ALC (Automatic Level Control) operation of speaker output is done by ALC2 block when ALC2 bit is “1”. Input

resistance of the ALC2 is 24kΩ (typ) and centered around VCOM voltage. The ALC2 level diagram is shown in Figure

37 ~Figure 40.

The limiter detection level is proportional to SVDD voltage. The output level is limited by the ALC2 circuit when the

input signal exceeds –7.1dBV (@SPKG1 bit = “0”, SVDD=3.3V or @SPKG1 bit = “1”, SVDD = 5V). When a

continuous signal of –7.1dBV or greater is input to the ALC2 circuit, the change period of the ALC2 limiter operation is

250µs (=2/fs@fs=8kHz) and the attenuation level is 0.5dB/step.

The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the

input level of the Speaker-amp goes to –9.1dBV (@SPKG1 bit = “0”, SVDD=3.3V or @SPKG1 bit = “1”, SVDD = 5V).

Maximum gain of the ALC2 recovery operation is set by RFS5-0 bits.

When the input signal is between –9.1dBV and –7.1dBV, the ALC2 limiter or recovery operations are not done.

When the PMSPK bit changes from “0” to “1”, the initilization cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”) starts.

The ALC2 is disabled (The ALC2 gain is fixed to “-3.5dB”.) during the initilization cycle and the ALC2 starts from

“–2dB” after completing the initilization cycle. The ROTM bit and RFS5-0 bits set during the PMSPK bit = “0”.

When the ALC2 is disable, a gain of the ALC2 block is fixed to -3.5dB. Therefore, a gain of internal speaker block is

shown in Table 22.

Parameter

ALC2 Limiter operation

−5.2dBV

ALC2 Recovery operation

−7.2dBV

Operation Start Level

fs=8kHz

Period

2/fs = 250µs

2/fs = 125µs

No

512/fs=64ms

fs=16kHz

Zero-crossing Detection

ATT/GAIN

512/fs=32ms

Yes (Timeout = Period Time)

1dB step

0.5dB step

Table 21. Limiter /Recovery of ALC2 (ROTM bit = “0”)

SPKG1-0 bits

Gain

00

01

10

11

+4.4dB

+6.4dB

+10.6dB

+12.7dB

Table 22. Gain of Speaker-Amp at ALC2 OFF(Full-differential Output)

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[AK4632]

0.8dBV

0dBV

+7.9dB

FS-4.0dB = -7.1dBV

-3.1dBV

-1.2dBV

+7.9dB

Full-differential

Single-ended

FS

-4.0dB

+2.0dB

-5.2dBV

+1.9dB

-8dB

-10dBV

-11.1dBV

-15.1dBV

FS-6.0dB = -9.1dBV

FS-12dB

-15.1dBV

+6.0dB

+14.0dB

-20dBV

-30dBV

-8dB

-23.1dBV

DVOL

DAC

ALC2

SPK-AMP

(AVDD=3.3V, SVDD=3.3V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “00”,) * FS = Full Scale

Figure 37. Speaker-Amp Output Level Diagram

10dBV

Full-differential

2.8dBV

FS-4dB = -7.1dBV

+9.9dB

0.8dBV

0dBV

+9.9dB

-3.2dBV

-3.1dBV

Single-ended

FS

+3.9dB

-4.0dB

+2.0dB

-8dB

-10dBV

-20dBV

-30dBV

-11.1dBV

-15.1dBV

FS-6.0dB = -9.1dBV

FS-12dB

+6.0dB

+14.0dB

-15.1dBV

-8dB

-23.1dBV

DVOL

DAC

ALC2

SPK-AMP

(AVDD=3.3V, SVDD=3.3V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “01”,) * FS = Full Scale

Figure 38. Speaker-Amp Output Level Diagram

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[AK4632]

10dBV

7.0dBV

Full-differential

5.0dBV

1.0dBV

+14.1dB

Single-ended

0dBV

-3.1dBV

FS-4dB = -7.1dBV

-4.0dB

+2.0dB

+8.1dB

FS

-8dB

-10dBV

-20dBV

-30dBV

-11.1dBV

-15.1dBV

FS-6.0dB = -9.1dBV

FS-12dB

+6.0dB

+14.0dB

-15.1dBV

-8dB

-23.1dBV

DVOL

DAC

ALC2

SPK-AMP

(AVDD=3.3V, SVDD=5.0V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “10”,) * FS = Full Scale

Figure 39. Speaker-Amp Output Level Diagram

10dBV

9.1dBV

+16.2dB

Full-differential

7.1dBV

3.1dBV

Single-ended

0dBV

+10.2dB

-3.1dBV

FS-4dB = -7.1dBV

-4.0dB

+2.0dB

FS

-8dB

-10dBV

-20dBV

-30dBV

-11.1dBV

-15.1dBV

FS-6.0dB = -9.1dBV

FS-12dB

+6.0dB

+14.0dB

-15.1dBV

-8dB

-23.1dBV

DVOL

DAC

ALC2

SPK-AMP

(AVDD=3.3V, SVDD=5.0V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “11”,) * FS = Full Scale

Figure 40. Speaker-Amp Output Level Diagram

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ASAHI KASEI

[AK4632]

Video Block

Video-Amp has a drivability for a load resistance of 150Ω. The AK4632 has a composite input and output. A Low Pass

Filter(LPF) and Gain Control Amp(GCA) are integrated and both DC output and Sag Compensation circuit are supported

as shown in Figure 41 and Figure 42. The capacitance for Sag Compensation circuit is 100µ F+2.2µ F or 47µ F+1.0µ F.

When DC output is used, VOUT pin and VSAG pin must be shorted. The output clamp voltage is 150mV(typ) at DC

output. SAGC1-0 bits and VVDD voltage should be set as shown in Table 23. Table 25 shows the gain and step of the

gain control. The gain is set by VGCA4-0 bits. PMV bit controls the power up and down of the video block. VOUT pin

outputs AVSS level at PMV bit = “1”.

C1

75Ω

YIN

CLAMP

LPF

GCA

VOUT

VSAG

+6dB

-1dB ~ +10.5dB

Step 0.5dB

C2

(C1=100µ F, C2=2.2µ F) or (C1=47µ F, C2=1.0µ F)

Figure 41. Video block (using Sag Compensation circuit)

75Ω

YIN

CLAMP

LPF

GCA

VOUT

VSAG

+6dB

-1dB ~ +10.5dB

Step 0.5dB

Figure 42. Video block (at DC Output))

VVDD voltage

SAGC1 bit

SAGC0 bit

Output Circuit

DC output

0

1

0

1

0

1

Default

2.8 V ≤ VVDD ≤ 3.6V

Not Available

Sag compensation

2.85V ≤ VVDD < 4.75V

4.5 V ≤ VVDD < 5.25V

Table 23. Setting of VVDD and video output circuit.

Output Circuit

VVDD voltage

GCA setting

0dB

-1dB (Note)

0dB

DC output

2.8 V ≤ VVDD ≤ 3.6V

3.135 V ≤ VVDD ≤ 5.25V

2.85V ≤ VVDD < 3.135 V

3.135 V ≤ VVDD ≤ 5.25V

2.85V ≤ VVDD < 3.135 V

Sag compensation

100µ F+2.2µ F

47µ F+1.0µ F

Sag compensation

-1dB (Note)

Note : When the sag compensation circuit is used at less than 3.135V of VVDD, the GCA should be set to -1dB in

order to avoid clipping of output video signal. Note that the video will become dark at that time.

Table 24. Gain compensation

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[AK4632]

VGCA4-0 bits

GAIN(dB)

STEP

0.5dB

17H

16H

15H

:

+10.5dB

+10.0dB

+9.5dB

:

04H

03H

02H

01H

00H

+1.0dB

+0.5dB

0.0dB

Default

-0.5dB

-1.0dB

Table 25. Setting of GCA

Serial Control Interface

Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface

consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address (MSB first, 5bits) and

Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the

falling edge. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = “L”.

CSN

2

6

7

8

9

10 11

12 13 14 15

0

1

3

4

5

CCLK

CDTI

R/W

C1 C0

A4 A3 A2 A2 A0 D7 D6 D5 D4 D3 D2 D1 D0

“1” “0” “1”

C1-C0: Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”

R/W: READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”

A4-A0: Register Address

D7-D0: Control data

Figure 43. Serial Control I/F Timing

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ASAHI KASEI

[AK4632]

Register Map

Addr

Register Name

D7

0

PMV

SPPS

D6

PMVCM

0

BEEPS

AOPSN

PLL2

0

ROTM

ALC2

REF6

IPGA6

DVOL6

0

D5

PMBP

0

ALC2S

MGAIN1

PLL1

D4

PMSPK

0

DACA

SPKG1

PLL0

MSBS

ZTM0

ZELM

REF4

D3

PMAO

M/S

D2

D1

D0

00H Power Management 1

01H Power Management 2

02H Signal Select 1

PMDAC

MCKPD

MPWR

BEEPA

BCKO0

FS2

WTM0

LMAT0

REF2

PMMIC

MCKO

MICAD

ALC1M

DIF1

PMADC

PMPLL

MGAIN0

ALC1A

DIF0

DACM

SPKG0

BCKO1

BCKP

WTM1

LMAT1

REF3

IPGA3

DVOL3

RFS3

03H Signal Select 2

0

04H Mode Control 1

05H Mode Control 2

06H Timer Select

07H ALC Mode Control 1

08H ALC Mode Control 2

09H Input PGA Control

0AH Digital Volume Control

0BH ALC2 Mode Control

0CH Video Mode Control

PLL3

0

DVTM

FS3

FS1

FS0

ZTM1

ALC1

REF5

IPGA5

DVOL5

RFS5

LTM1

RATT

REF1

IPGA1

DVOL1

RFS1

LTM0

LMTH

REF0

IPGA0

DVOL0

RFS0

0

IPGA4

DVOL4

RFS4

IPGA2

DVOL2

RFS2

DVOL7

0

SAGC1

SAGC0

VGCA4

VGCA3

VGCA2

VGCA1

VGCA0

The PDN pin = “L” resets the registers to their default values.

Note: Unused bits must contain a “0” value.

Note: Only write to address 00H to 0CH.

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[AK4632]

Register Definitions

Addr Register Name

D7

0

D6

PMVCM

0

D5

PMBP

0

D4

PMSPK

0

D3

PMAO

0

D2

D1

D0

00H

Power Management 1

Default

PMDAC PMMIC PMADC

0

PMADC: ADC Block Power Control

0: Power down (Default)

1: Power up

When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz) starts. After

initializing, digital data of the ADC is output.

PMMIC: MIC In Block (MIC-Amp and ALC1) Power Control

0: Power down (Default)

1: Power up

PMDAC: DAC Block Power Control

0: Power down (Default)

1: Power up

PMAO: Mono Line Out Power Control

0: Power down (Default)

1: Power up

PMSPK: Speaker Block Power Control

0: Power down (Default)

1: Power up

PMBP: BEEP In Power Control

0: Power down (Default)

1: Power up

Even if PMBP bit is “0”, the path is still connected between BEEP and AOUT/SPK-Amp. BEEPS and BEEPA

bits should be set to “0” to disconnect these paths.

PMVCM: VCOM Block Power Control

0: Power down (Default)

1: Power up

Each block can be powered-down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are

powered-down.

When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down. Though the IPGA

resisters are initialized, the other registers remain unchanged. (refer to the IPGA6-0 bits description)

When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and MCKO bits and all

bits in 00H address are “0”, PMVCM bit can write to “0”.

When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin Æ SPP/SPN pins) or Mono Lineout-Amp

(Signal path: BEEP pin Æ AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in

operation, the clocks must always be present.

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[AK4632]

Addr

01H

Register Name

Power Management 2

Default

D7

PMV

0

D6

0

D5

0

D4

0

D3

M/S

0

D2

MCKPD

1

D1

MCKO

0

D0

PMPLL

0

PMPLL: PLL Block Power Control Select

0: PLL is Power down and External is selected. (Default)

1: PLL is Power up and PLL Mode is selected.

MCKO: Master Clock Output Enable

0: “L” Output (Default)

1: 256fs Output

MCKPD: MCKI pin pull down control

0: Master Clock input enable

1: Pull down by 25kΩ (typ.) (Default)

M/S: Select Master / Slave Mode

0: Slave Mode (Default)

1: Master Mode

PMV: Video Block Power Control

0: Power down (Default)

1: Power up

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[AK4632]

Addr Register Name

D7

SPPS

0

D6

BEEPS

0

D5

ALC2S

0

D4

DACA

0

D3

DACM

0

D2

MPWR

0

D1

MICAD

0

D0

MGAIN0

1

02H

Signal Select 1

Default

MGAIN1-0 : 1^stMIC-amp Gain control(See Table 26)

MGAIN 1 bit is located at D6 bit of 03H

MGAIN1 bit MGAIN0 bit

Input Gain

0dB

+20dB

+26dB

+32dB

0

1

0

1

0

1

Default

Table 26. Input Gain

MICAD: Switch Control from MIC In to ADC.

0: OFF (Default)

1: ON

When MICAD bit is “1”, the ALC1 output signal is input to ADC.

MPWR: Power Supply Control for Microphone

0: OFF (Default)

1: ON

When PMMIC bit is “1”, MPWR bit is enabled.

DACM: Switch Control from DAC to mono amp.

0: OFF (Default)

1: ON

When PMSPK bit is “1”, DACM bit is enabled. When PMSPK bit is “0”, MOUT pin is Hi-Z state.

DACA: Switch Control from DAC to mono line amp

0: OFF (Default)

1: ON

When PMAO bit is “1”, DACA bit is enabled. When PMAO bit is “0”, the AOUT pin is AVSS.

ALC2S: ALC2 output to Speaker-Amp Enable

0: OFF (Default)

1: ON

When ALC2S bit is “1”, the ALC2 output signal is input to Speaker-Amp.

BEEPS: BEEP pin to Speaker-Amp Enable

0: OFF (Default)

1: ON

When BEEPS bit is “1”, the beep signal is input to Speaker-Amp.

SPPS: Speaker-amp Power-Save-Mode

0: Power Save Mode (Default)

1: Normal Operation

When SPPS bit is “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is

set to SVDD/2 voltage. When the PMSPK bit = “1”, this bit is valid. After the PDN pin changes from “L” to

“H”, the PMSPK bit is “0”, which powers down Speaker-amp.

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[AK4632]

D0

Addr Register Name

D7

0

D6

0

D5

MGAIN1

0

D4

D3

D2

BEEPA

0

D1

03H

Signal Select 2

Default

SPKG1 SPKG0

ALC1M ALC1A

0

ALC1A: Switch Control from ALC1 output signal to mono line output amp.

0: OFF (Default)

1: ON

When PMAO bit is “1”, ALC1A bit is enabled. When PMAO bit is “0”, the AOUT pin is AVSS.

ALC1M: Switch Control from ALC1 output signal to mono amp.

0: OFF (Default)

1: ON

When PMSPK bit is “1”, ALC1M is enabled. When PMSPK bit is “0”, the MOUT pin goes Hi-Z state.

BEEPA: Switch Control from beep signal to mono line output amp.

0: OFF (Default)

1: ON

When PMAO bit is “1”, BEEPA is enabled. When PMAO bit is “0”, the AOUT pin is AVSS.

SPKG1-0: Select Speaker-Amp Output Gain (See Table 27)

SPKG1-0 bits

Gain

0dB

+2.2dB

+4.4dB

+8.7dB

00

01

10

11

Table 27. Gain of Speaker-Amp

MGAIN1: Mic-Amplifier Gain Control(See Table 26)

ALC1M

DACM

IPGA

DAC

ALC2S

MIX

ALC2

SPK

BEEPS

BEEP

ALC1A

DACA

AOUT

BEEPA

Figure 44. Speaker and Mono Lineout-Amps switch control

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[AK4632]

AOPSN: Mono Line Output Power-Save Mode

0: Normal Operation

1: Power-Save Mode (Default)

Power-save mode is enable at AOPSN bit = “1”. POP noise at power-up/down can be reduced by changing

at AOPSN bit = “1”. (See Figure 34)

Addr Register Name

D7

PLL3

0

D6

PLL2

0

D5

PLL1

0

D4

PLL0

0

D3

D2

D1

DIF1

1

D0

DIF0

0

04H

Mode Control 1

Default

BCKO1 BCKO0

0

DIF1-0: Audio Interface Format (See Table 28)

Mode DIF1 bit DIF0 bit SDTO (ADC)

SDTI (DAC)

DSP Mode

LSB justified

BICK

Figure

See Table 34

Figure 27

Figure 28

Figure 29

0

1

2

3

0

1

0

1

0

1

DSP Mode

MSB justified

MSB justified MSB justified

I²S compatible I²S compatible

Table 28. Audio Interface Format

≥ 16fs

≥ 32fs

Default

BCKO1-0: Select BICK output frequency at Master Mode (See Table 29)

BICK Output

Frequency

16fs

Mode

BCKO1 bit

BCKO0 bit

0

1

2

3

0

1

0

1

0

1

Default

32fs

64fs

N/A

Table 29. BICK Output Frequency at Master Mode

PLL3-0: Select input frequency at PLL mode (See Table 30)

PLL3

bit

PLL2

bit

PLL1

bit

PLL0

bit

PLL Reference

Clock Input Pin

Input

Frequency

Mode

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FCK pin

BICK pin

MCKI pin

N/A

1fs

16fs

32fs

64fs

Default

11.2896MHz

12.288MHz

12MHz

24MHz

13.5MHz

27MHz

12

13

Others

1

Others

Table 30. Setting of PLL Mode (*fs: Sampling Frequency)

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[AK4632]

Addr Register Name

D7

0

D6

0

D5

FS3

0

D4

MSBS

0

D3

BCKP

0

D2

FS2

0

D1

FS1

0

D0

FS0

0

05H

Mode Control 2

Default

FS3-0: Setting of Sampling Frequency (See Table 31 and Table 32) and MCKI Frequency (See Table 33)

These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode.

Mode

0

1

2

3

4

5

6

7

10

11

14

15

Others

FS3 bit

FS2 bit

FS1 bit

FS0 bit

Sampling Frequency

8kHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Default

12kHz

16kHz

24kHz

7.35kHz

11.025kHz

14.7kHz

22.05kHz

32kHz

48kHz

29.4kHz

44.1kHz

N/A

Others

Table 31. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”

Mode

FS3 bit

FS2 bit

FS1 bit

FS0 bit

Sampling Frequency Range

0

1

Don’t care

0

1

0

1

0

1

0

1

2

3

6

7

0

1

Default

7.35kHz ≤ fs ≤ 8kHz

8kHz < fs ≤ 12kHz

12kHz < fs ≤ 16kHz

16kHz < fs ≤ 24kHz

24kHz < fs ≤ 32kHz

32kHz < fs ≤ 48kHz

N/A

Others

Table 32. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”

Mode

FS3-2 bits

FS1 bit

FS0 bit

MCKI Input

Frequency

Sampling Frequency

Range

Don’t care

0

1

0

1

256fs

1024fs

256fs

512fs

Default

0

1

2

3

0

1

7.35kHz ≤ fs ≤ 48kHz

7.35kHz < fs ≤ 13kHz

7.35kHz < fs ≤ 48kHz

7.35kHz < fs ≤ 26kHz

Table 33. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

BCKP, MSBS: “00” (Default) (See Table 34)

MSBS bit BCKP bit

Audio Interface Format

Figure 23

0

1

0

1

0

1

Default

Figure 24

Figure 25

Figure 26

Table 34. Audio Interface Format in Mode 0

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[AK4632]

Addr Register Name

D7

DVTM

0

D6

ROTM

0

D5

ZTM1

0

D4

ZTM0

0

D3

WTM1

0

D2

WTM0

0

D1

LTM1

0

D0

LTM0

0

06H

Timer Select

Default

LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (See Table 35)

The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done

by the period specified by the LTM1-0 bits. Default is “00” (0.5/fs).

ALC1 Limiter Operation Period

LTM1 bit LTM0 bit

8kHz

63µs

125µs

250µs

500µs

16kHz

31µs

63µs

125µs

250µs

0

1

0

1

0

1

0.5/fs

1/fs

2/fs

Default

4/fs

Table 35. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit=“1”)

WTM1-0: ALC1 Recovery Waiting Period (See Table 36)

A period of recovery operation when any limiter operation does not occur during the ALC1 operation.

Default is “00” (128/fs).

ALC1 Recovery Operation Waiting Period

WTM1 bit WTM0 bit

8kHz

16ms

32ms

64ms

128ms

16kHz

8ms

16ms

32ms

64ms

0

1

0

1

0

1

128/fs

256/fs

512/fs

1024/fs

Default

Table 36. ALC1 Recovery Operation Waiting Period

ZTM1-0: ALC1 Zero crossing timeout Period (See Table 37)

When the IPGA perform zero crossing or timeout, the IPGA value is changed by the µP WRITE operation,

ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”). Default is “00” (128/fs).

Zero Crossing Timeout Period

ZTM1 bit ZTM0 bit

8kHz

16ms

32ms

64ms

128ms

16kHz

8ms

16ms

32ms

64ms

0

1

0

1

0

1

128/fs

256/fs

512/fs

1024/fs

Default

Table 37. Zero Crossing Timeout Period

ROTM: Period time for ALC2 Recovery operation, ALC2 Zero Crossing Timeout and ALC2 initializing cycle.

0: 512/fs (Default)

1: 1024/fs

The ROTM bit is set during the PMSPK bit = “0”.

DVTM :Digital Volume Soft Transition Time Control

0: 1061/fs (Default)

1: 256/fs

This is the time to FFH from 00H of DVOL7-0 bits.

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ASAHI KASEI

[AK4632]

Addr Register Name

D7

0

D6

ALC2

1

D5

ALC1

0

D4

ZELM

0

D3

D2

D1

RATT

0

D0

LMTH

0

07H

ALC Mode Control 1

Default

LMAT1 LMAT0

0

LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (See Table 38 )

The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.

Default is “0”.

LMTH bit

ALC1 Limiter Detection Level

ADC Input ≥ −6.0dBFS

ADC Input ≥ −4.0dBFS

ALC1 Recovery Waiting Counter Reset Level

−6.0dBFS > ADC Input ≥ −8.0dBFS

−4.0dBFS > ADC Input ≥ −6.0dBFS

0

1

Default

Table 38. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level

RATT: ALC1 Recovery GAIN Step (See Table 39)

During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For

example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the

ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value

exceeds the reference level (REF6-0 bits), the IPGA value does not increase.

RATT bit

GAIN STEP

0

1

2

Default

Table 39. ALC1 Recovery Gain Step Setting

LMAT1-0: ALC1 Limiter ATT Step (See Table 40)

During the ALC1 limiter operation, when IPGA output signal exceeds the ALC1 limiter detection level set by

LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current

IPGA value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter

operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation

value exceeds IPGA = “00” (−8dB), it clips to “00”.

LMAT1 bit LMAT0 bit

ATT STEP

0

1

0

1

0

1

2

3

4

Default

Table 40. ALC1 Limiter ATT Step Setting

ZELM: Enable zero crossing detection at ALC1 Limiter operation

0: Enable (Default)

1: Disable

When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently

and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1

recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately.

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ASAHI KASEI

[AK4632]

ALC1: ALC1 Enable

0: ALC1 Disable (Default)

1: ALC1 Enable

When ALC1 bit is “1”, the ALC1 operation is enabled.

ALC2: ALC2 Enable

0: ALC2 Disable

1: ALC2 Enable (Default)

After completing the initializing cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”), the ALC2 operation is

enabled. When the PMSPK bit changes from “0” to “1” or PDN pin changes from “L” to “H”, the initilization

cycle starts.

Addr Register Name

08H ALC Mode Control 2

Default

D7

0

D6

REF6

0

D5

REF5

1

D4

REF4

1

D3

REF3

0

D2

REF2

1

D1

REF1

1

D0

REF0

0

REF6-0: Reference value at ALC1 Recovery Operation (See Table 41)

During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation,

then the IPGA does not become larger than the reference value. For example, when REF7-0 = “30H”, RATT =

2step, IPGA = 2FH, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset

Level”, the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”.

DATA (HEX)

GAIN (dB)

+27.5

+27.0

+26.5

:

STEP

47

46

45

:

36

:

+19.0

:

Default

10

:

+0.0

:

0.5dB

06

05

04

03

02

01

00

−5.0

−5.5

−6.0

−6.5

−7.0

−7.5

−8.0

Table 41. Setting Reference Value at ALC1 Recovery Operation

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ASAHI KASEI

[AK4632]

Addr Register Name

D7

0

D6

IPGA6

0

D5

IPGA5

0

D4

IPGA4

1

D3

IPGA3

0

D2

IPGA2

0

D1

IPGA1

0

D0

IPGA0

0

09H

Input PGA Control

Default

IPGA6-0: Input Analog PGA (See Table 42)

Default: “10H” (0dB)

When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”.

IPGA6-0 bits should be set at 2/fs(250µs@fs=8kHz) after PMMIC bit is set to “1”. IPGA gain is reset when

PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC bit is changed to “1”.

When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set automatically by ALC1

operation.

In a manual mode, IPGA can be set to any values in Table 42.The ZTM1-0 bits set zero crossing timeout

period when IPGA value is changed. When the control register is written from the µP, the zero crossing

counter is reset and its counter starts. When the signal zero crossing or zero crossing timeout, the written value

from the µP becomes valid.

DATA (HEX)

GAIN (dB)

+27.5

+27.0

+26.5

:

STEP

47

46

45

:

36

:

+19.0

:

10

:

+0.0

:

Default

0.5dB

06

05

04

03

02

01

00

−5.0

−5.5

−6.0

−6.5

−7.0

−7.5

−8.0

Table 42. Input Gain Setting

Addr Register Name

0AH Digital Volume Control

Default

D7

DVOL7

0

D6

DVOL6

0

D5

D4

D3

D2

D1

D0

DVOL5 DVOL4 DVOL3 DVOL2 DVOL1 DVOL0

0

1

0

DVOL7-0: Output Digital Volume (See Table 43)

The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The gain can be set by the DVOL7-0

bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB

with MUTE. This volume has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) or 256/fs

(=32ms @ fs = 8kHz) from 00H to FFH. Soft Transition Time is set by DVTM bit.

DVOL7-0

00H

01H

02H

•

Gain

+12.0dB

+11.5dB

+11.0dB

•

18H

0dB

Default

•

FDH

FEH

FFH

−114.5dB

−115.0dB

MUTE (−∞)

Table 43. Digital Volume Code Table

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ASAHI KASEI

[AK4632]

Addr Register Name

0BH ALC2 Mode Control

Default

D7

0

D6

0

D5

RFS5

1

D4

RFS4

1

D3

RFS3

1

D2

RFS2

1

D1

RFS1

0

D0

RFS0

0

RFS6-0: Reference value at ALC2 Recovery Operation (See Table 44)

REFS5-0 bits

Volume[dB]

+19.5

+19.0

+18.5

+18.0

:

Step

3F

3E

3D

3C

:

Default

0.5dB

19

18

17

:

+0.5

+0.0

-0.5

:

03

02

01

00

-10.5

-11.0

-11.5

-12.0

Table 44. Setting Reference Value at ALC2 Recovery Operation

Addr Register Name

0CH Video Mode Control

Default

D7

0

D6

SAGC1

0

D5

D4

D3

D2

D1

D0

SAGC0 VGCA4 VGCA3 VGCA2 VGCA1 VGCA0

0

1

0

VGCA4-0: Gain Control of Video output(See Table 25)

SAGC1-0: Select Video Output Circuit (See Table 23)

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ASAHI KASEI

[AK4632]

SYSTEM DESIGN

Figure 45 shows the system connection diagram. An evaluation board [AKD4632] is available which demonstrates the

optimum layout, power supply arrangements and measurement results.

20k

C

2.2k

0.22µ

220

1µ

0.1µ

R

0.1µ

10µ

Cp Rp

1

2

3

4

5

6

7

8

VCOC

AVDD

AVSS

VVDD

VIN

24

23

MIN

0.1µ

10µ

Analog Supply

2.6∼3.6V

SVSS

+

0.1µ

10µ

Analog Supply

2.6∼5.25V

+

SVDD 22

SPP 21

Analog Supply

2.8∼5.25V

R2

+

Top View

Speaker

0.1u

Cv

SPN 20

R1

75

ZD2

ZD1

MCKO 19

MCKI 18

DVSS 17

VOUT

VSAG

PDN

Cs

SAGC1-0 bits = “00”

Cv : Short

Cs : Short

SAGC1-0 bits = “10” or “11”

Cv=100µF & Cs=2.2µF

or

Dynamic SPK :

R1,R2 : Short

ZD1,ZD2 : Open

Peizo SPK :

R1,R2 : 10Ω

ZD1,ZD2 : Required

Cv=47µF & Cs=1.0µF

0.1µ

10

+

10µ

DSP or µP

Figure 45. Typical Connection Diagram

Notes:

- AVSS, DVSS and SVSS of the AK4632 should be distributed separately from the ground of external

controllers.

- The exposed pad on the bottom surface of the package must be open.

- All digital input pins except pull-down pin should not be left floating.

- Value of R and C of BEEP pin should depend on system.

- When the AK4632 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.

- When the AK4632 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 45.

- Input resistance of AIN pin and Capacitance between MICOUT pin and AIN pin compose of HPF. When the

capacitance is 0.22µF, the cut off frequency is typ.72Hz(typ)(min. 48Hz, max. 145Hz).

Rp and Cp of

VCOC pin

PLL Lock

Time

(max)

PLL3 PLL2 PLL1 PLL0 PLL Reference

Input

Frequency

Mode

bit

Clock Input Pin

Cp[F]

Rp[Ω]

6.8k

10k

Default

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FCK pin

BICK pin

MCKI pin

N/A

1fs

16fs

32fs

220n

4.7n

10n

160ms

2ms

64fs

2ms

11.2896MHz

12.288MHz

12MHz

24MHz

13.5MHz

27MHz

40ms

12

13

Others

1

10n

Others

Table 45. Setting of PLL Mode (*fs: Sampling Frequency)

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ASAHI KASEI

[AK4632]

1. Grounding and Power Supply Decoupling

The AK4632 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, SVDD and VVDD

are usually supplied from the system’s analog supply. If AVDD, DVDD, SVDD and VVDD are supplied separately, the

correct power up sequence should be observed. AVSS, DVSS and SVSS of the AK4632 should be connected to the

analog ground plane. System analog ground and digital ground should be connected together near to where the supplies

are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4632 as possible, with the

small value ceramic capacitor being the nearest.

2. Voltage Reference

VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached

to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All

signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the

AK4632.

3. Analog Inputs

The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic

input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD).

Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4632 can accept

input voltages from AVSS to AVDD.

4. Analog Outputs

The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and

a negative full scale for 8000H(@16bit). Mono output from the MOUT pin and Mono Line Output from the AOUT pin

are centered at 0.45 x AVDD (typ). The Speaker-Amp output is centered at SVDD/2.

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ASAHI KASEI

[AK4632]

CONTROL SEQUENCE

Clock Set up

When ADC, DAC, ALC1, ALC2 and IPGA are used, the clocks must be supplied.

1. In case of PLL Master Mode.

Power Supply

Example:

(1)

Audio I/F Format: DSP Mode, BCKP = MSBS = “0”

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 11.2896MHz

MCKO : Enable

PDN pin

(2)

(3)

PMVCM bit

(Addr:00H, D6)

Sampling Frequency:8kHz

(4)

MCKPD bit

(Addr:01H, D2)

(1) Power Supply & PDN pin = “L” Æ “H”

(5)

MCKO bit

(Addr:01H, D1)

(2)Addr:01H, Data:0CH

Addr:04H, Data:48H

Addr:05H, Data:00H

PMPLL bit

(Addr:01H, D0)

(6)

MCKI pin

Input

(3)Addr:00H, Data:40H

(4)Addr:01H, Data:0BH

M/S bit

(Addr:01H, D3)

40msec(max)

(7)

BICK pin

FCK pin

Output

(8)

1msec (max)

MCKO, BICK and FCK output

40msec(max)

(9)

(10)

MCKO pin

Figure 46. Clock Set Up Sequence (1)

(1) After Power Up, PDN pin = “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4632.

(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.

(3) Power UpVCOM: PMVCM bit = “0” → “1”

VCOM should first be powered-up before the other block operates.

(4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0”

(5) In case of using MCKO output: MCKO bit = “1”

In case of not using MCKO output: MCKO bit = “0”

(6) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external

source.

(7) The AK4632 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of

the block which a clock is necessary for becomes possible.

(8) The invalid frequencies are output from FCK and BICK pins during this period.

(9) The invalid frequency is output from MCKO pin during this period.

(10) The normal clock is output from MCKO pin after the PLL is locked.

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ASAHI KASEI

[AK4632]

2. When the external clocks (FCK or BICK pin) are used in PLL Slave Mode.

Example:

Audio I/F Format : DSP Mode, BCKP = MSBS = “0”

PLL Reference clock: BICK

Power Supply

PDN pin

BICK frequency: 64fs

Sampling Frequency: 8kHz

(1)

(2)

(3)

4fs of

(1) Power Supply & PDN pin = “L” Æ “H”

PMVCM bit

(Addr:00H, D6)

(4) "H"

MCKPD bit

(Addr:01H, D2)

(2) Addr:04H, Data:30H

Addr:05H, Data:00H

PMPLL bit

(Addr:01H, D0)

(3) Addr:00H, Data:40H

(4) Addr:01H, Data:05H

BICK and FCK input

FCK pin

BICK pin

Input

(5)

Internal Clock

(6)

Figure 47. Clock Set Up Sequence (2)

(1)After Power Up: PDN pin “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4632.

(2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period.

(3)Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered up before the other block operates.

(4)Pull down of the MCKI pin: MCKPD bit = “1”

(5)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (FCK or BICK pin) is supplied.

PLL lock time is 160ms(max) when FCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK

is a PLL reference clock.

(6)Normal operation stats after the PLL is locked.

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ASAHI KASEI

[AK4632]

3. When the external clock (MCKI pin) is used in PLL Slave Mode.

Example:

Audio I/F Format: DSP Mode, BCKP = MSBS = “0”

Power Supply

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 11.2896MHz

MCKO : Enable

(1)

Sampling Frequency:8kHz

PDN pin

(2)

(3)

PMVCM bit

(Addr:00H, D6)

(1) Power Supply & PDN pin = “L” Æ “H”

(4)

MCKPD bit

(Addr:01H, D2)

(2)Addr:01H, Data:04H

Addr:04H, Data:48H

Addr:05H, Data:00H

(5)

MCKO bit

(Addr:01H, D1)

PMPLL bit

(Addr:01H, D0)

(3)Addr:00H, Data:40H

(4)Addr:01H, Data:03H

MCKO output start

(6)

MCKI pin

Input

40msec(max)

(7)

MCKO pin

(8)

Output

Input

(9)

BICK pin

FCK pin

BICK and FCK input start

Figure 48. Clock Set Up Sequence (3)

(1) After Power Up: PDN pin “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4632.

(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.

(3) Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered up before the other block operates.

(4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0”

(5) Enable MCKO output: MCKO bit = “1”

(6) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL

lock time is 40ms(max).

(7) The normal clock is output from MCKO after PLL is locked.

(8) The invalid frequency is output from MCKO during this period.

(9) BICK and FCK clocks should be synchronized with MCKO clock.

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ASAHI KASEI

4. EXT Slave Mode

Power Supply

[AK4632]

Example

Audio I/F Format:MSB justified (ADC and DAC)

Input MCKI frequency: 1024fs

Sampling Frequency:8kHz

MCKO: Disable

(1)

PDN pin

(1) Power Supply & PDN pin = “L” Æ “H”

(2)

(3)

PMVCM bit

(Addr:00H, D6)

(2) Addr:04H, Data:02H

Addr:05H, Data:01H

MCKPD bit

(Addr:01H, D2)

(4)

"L"

(3) Addr:00H, Data:40H

(4) Addr:01H, Data:00H

MCKI, BICK and FCK input

PMPLL bit

(Addr:01H, D0)

(5)

MCKI pin

Input

FCK pin

BICK pin

Figure 49. Clock Set Up Sequence (4)

(1)After Power Up: PDN pin “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4632.

(2)DIF1-0 and FS1-0 bits should be set during this period.

(3)Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered up before the other block operates.

(4)Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0”

Power down PLL: PMPLL bit = “0”

(5)Normal operation starts after the MCKI, FCK and BICK are supplied.

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ASAHI KASEI

[AK4632]

MIC Input Recording

Example:

PLL Master Mode

Audio I/F Format:DSP Mode, BCKP=MSBS=“0”

Sampling Frequency:8kHz

Pre MIC AMP:+20dB

FS3-0 bits

XXXX

XXX

(Addr:05H,

MIC Power On

D5,D2-0)

ALC1 setting:Refer to Figrure 29

ALC2 bit=“1”(default)

(1)

MIC Control

001

X1X

(1) Addr:05H, Data:00H

(2) Addr:02H, Data:07H

(Addr:02H, D2-0)

(2)

ALC1 Control 1

XXH

00H

47H

(Addr:06H)

(3)

ALC1 Control 2

XXH

(3) Addr:06H, Data:00H

(4) Addr:08H, Data:47H

(5) Addr:07H, Data:61H

(6) Addr:00H, Data:43H

Recording

(Addr:08H)

(4)

ALC1 Control 3

61H or 21H

(Addr:07H)

(5)

ALC1 State

ALC1 Disable

ALC1 Enable

PMADC bit

(Addr:00H, D0)

(6)

(7)

PMMIC bit

(Addr:00H, D1)

1059 / fs

ADC Internal

State

Power Down

Normal State Power Down

Initialize

(7) Addr:00H, Data:40H

Figure 50. MIC Input Recording Sequence

This sequence is an example of ALC1 setting at s=8kHz. If the parameter of the ALC1 is changed, please refer to

“Figure 31. Registers set-up sequence at the ALC1 operation“

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bit). When the AK4632 is PLL mode, MIC and ADC should be powered-up

in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up MIC input (Addr: 02H)

(3) Set up Timer Select for ALC1 (Addr: 06H)

(4) Set up REF value for ALC1 (Addr: 08H)

(5) Set up LMTH, RATT, LMAT1-0 and ALC1 bits (Addr: 07H)

(6) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0” → “1”

The initialization cycle time of ADC is 1059/fs=133ms@fs=8kHz.

After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts from IPGA default

value (0dB).

(7) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1” → “0”

When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1 operation

is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also changed

when the sampling frequency is changed, it should be done after the AK4632 goes to the manual mode (ALC1 bit

= “0”) or MIC block is powered-down (PMMIC bit = “0”). IPGA gain is reset when PMMIC bit is “0”, and then

IPGA operation starts from the default value when PMMIC bit is changed to “1”.

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ASAHI KASEI

[AK4632]

Speaker-amp Output

Example:

PLL, Master Mode

Audio I/F Format :DSP Mode, BCKP=MSBS= “0”

Sampling Frequency: 8kHz

Digital Volume: -8dB

FS2-0 bits

XXXX

(Addr:05H,

D5, D2-0)

(1)

(8)

ALC2 : Enable

DACM bit

(1) Addr:05H, Data:00H

(2) Addr:02H, Data:28H

(Addr:02H, D3)

(2)

ALC2S bit

(Addr:02H, D5)

ALC2 bit

0

(3) Addr:07H, Data:40H

(4) Addr:0AH, Data:28H

(5) Addr:00H, Data:54H

(6) Addr:02H, Data:A8H

Playback

X

(Addr:07H, D6)

(3)

DVOL7-0 bits

0001100

XXXXXXX

(Addr:0AH, D7-0)

(4)

(9)

PMDAC bit

(Addr:00H, D2)

(5)

PMSPK bit

(Addr:00H, D4)

(6)

SPPS bit

(Addr:02H, D7)

(7)

SPP pin

Hi-Z

Normal Output

Hi-Z

(7) Addr:02H, Data:28H

(8) Addr:00H, Data:40H

SPN pin

Hi-Z

SVDD/2 Normal Output SVDD/2 Hi-Z

Figure 51. Speaker-Amp Output Sequence

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Speaker-Amp should be

powered-up in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up the path of “DAC Æ SPK-Amp”

DACM = ALC2S bit: “0” → “1”

(3) Set up the ALC2 Enable/Disable

(4) Set up the digital volume (Addr: 0AH)

After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by

the soft transition.

(5) Power Up of DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “0” → “1”

When ALC2 bit = “1”, the ALC2 is disabled (ALC2 gain is fiexed to “–2dB”) during the initilization cycle

(512/fs = 64ms @ fs=8kHz, ROTM bit = “0”) and the ALC2 starts from “–2dB” after completing the

initilization cycle.

(6) Exit the power-save-mode of Speaker-Amp: SPPS bit = “0” → “1”

“(6)” time depends on the time constant of input impedance of MIN pin and capacitor between MIN pin and

MOUT pin. If Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur.

e.g. Input Impedance of MIN pin =36kΩ (max), C=0.1µF: Recommended wait time is more than 5τ = 18ms.

(7) Enter the power-save-mode of Speaker-Amp: SPPS bit = “1” → “0”

(8) Disable the path of “DAC Æ SPK-Amp”

DACM = ALC2S bit: “1” → “0”

(9) Power Down DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “1” → “0”

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[AK4632]

BEEP signal output from Speaker-Amp

Clocks can be stopped.

CLOCK

Example:

(1) Addr:07H, Data:00H

ALC2 bit

(Addr:07H, D6)

0 or 1

0

(1)

(2) Addr:00H, Data:70H

(3) Addr:02H, Data:60H

(4) Addr:02H, Data:E0H

BEEP Signal Output

PMBP bit

(Addr:00H, D2)

(2)

(6)

PMSPK bit

(Addr:00H, D4)

ALC2S bit

(Addr:02H, D5)

0 or 1

0

(3)

(7)

BEEPS bit

(Addr:02H, D6)

(4)

SPPS bit

(Addr:02H, D7)

(5) Addr:02H, Data:60H

(5)

SPP pin

SPN pin

Hi-Z

Normal Output

Hi-Z

(6) Addr:00H, Data:40H

(7) Addr:02H, Data:00H

Hi-Z

SVDD/2 Normal Output SVDD/2 Hi-Z

Figure 52. “BEPP-Amp Æ Speaker-Amp” Output Sequence

The clocks can be stopped when only BEEP-Amp and Speaker-Amp are operating. However ALC2 must be

disabled.

(1) ALC2 Disable: ALC2 bit = “0”

(2) Power Up BEEP-Amp and Speaker-Amp: PMBP bit = PMSPK bit = “0” → “1”

(3) Disable the path of “ALC2 Æ SPK-Amp”: ALC2S bit = “0”

Enable the path of “BEEP Æ SPK-Amp”: BEEPS bit = “0” → “1”

(4) Exit the power-save-mode of Speaker-Amp: SPPS bit = “0” → “1”

“(4)” time depends on the time constant of external resistor and capacitor connected to BEEP pin. If

Speaker-Amp output is enabled before input of BEEP-Amp becomes stable, pop noise may occur.

e.g. R=20k, C=0.1µF: Recommended wait time is more than 5τ = 10ms.

(5) Enter the power-save-mode of Speaker-Amp: SPPS bit = “1” → “0”

(6) Power Down BEEP-Amp and Speaker-Amp: PMBP bit = PMSPK bit = “1” → “0”

(7) Disable the path of “BEEP Æ SPK-Amp”: BEEPS bit = “1” → “0”

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[AK4632]

MONO LINEOUT

1. In case of using an external mute circuit.(Compatible with AK4536/AK4630)

Example:

PLL, Master Mode

Audio I/F Format :DSP Mode, BCKP=MSBS= “0”

Sampling Frequency: 8kHz

Digital Volume: -8dB

FS3-0 bits

(Addr:05H,

D5,D2-0)

XXXX

(1) Addr:05H, Data:00H

(2) Addr:02H, Data:10H

(1)

(6)

DACA bit

(Addr:02H, D4)

(2)

(3)

DVOL7-0 bits

(3) Addr:0AH, Data:28H

(4) Addr:00H, Data:4CH

Playback

00011000

XXXXXXX

(Addr:0AH, D7-0)

PMDAC bit

(Addr:00H, D2)

(5)

(4)

PMAO bit

(Addr:00H, D3)

AOUT pin

Hi-Z

Normal Output

(5) Addr:00H, Data:40H

(6) Addr:02H, Data:00H

Figure 53. Mono Lineout Sequence

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Mono Line Amp should

be powered-up in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up the path of “DAC Æ Mono Line Amp”

DACA bit: “0” → “1”

(3) Set up the digital volume (Addr: 0AH)

After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by

the soft transition.

(4) Power Up of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “0” → “1”

When DAC and Mono Line Amp are powered-up, the pop noise occurs from AOUT pin. Therefore AOUT pin

should be muted by external circuit.

(5) Power Down of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “1” → “0”

When DAC and Mono Line Amp are powered-down, the pop noise occurs from AOUT pin. Therefore AOUT

pin should be muted by external circuit.

(6) Disable the path of “DAC Æ Mono Line Amp”

DACA bit: “1” → “0”

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[AK4632]

2. In case of using POP reduction circuit of AK4632.

Example:

PLL, Master Mode

Audio I/F Format :DSP Mode, BCKP=MSBS= “0”

Sampling Frequency: 8kHz

Digital Volume: -8dB

MGAIN1=SPKG1=SPKG0=BEEPA=ALC1M

=ALC1A= “0”

(1) Addr:05H, Data:00H

(2) Addr:02H, Data:10H

(3) Addr:0AH, Data:28H

(4) Addr:03H, Data:40H

(5) Addr:00H, Data:4CH

(6) Addr:03H, Data:00H

Playback

FS2-0 bits

XXXX

(Addr:05H,

D5,D2-0)

(1)

(9)

DACA bit

(Addr:02H, D4)

(2)

(3)

DVOL7-0 bits

(Addr:0AH, D7-0)

00011000

XXXXXXX

PSAON bit

(Addr:03H, D6)

(4)

(6)

(7)

(10)

PMDAC bit

(Addr:00H, D2)

(7) Addr:03H, Data:40H

(8) Addr:00H, Data:40H

(9) Addr:02H, Data:00H

(10) Addr:03H, Data:00H

(5)

(8)

PMAO bit

(Addr:00H, D3)

>300 ms

Normal Output

AOUT pin

Figure 54. Mono Lineout Sequence

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Mono Line Amp should

be powered-up in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up the path of “DAC Æ Mono Line Amp” : DACA bit: “0” → “1”

(3) Set up the digital volume (Addr: 0AH)

After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by

the soft transition.

(4) Enter power-save mode of Mono Line Amp: AOPSN bit = “0” → “1”

(5) Power Up of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “0” → “1”

AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF.

(6) Exit power-save mode of Mono Line Amp after AOUT pin rises up. : AOPSN bit = “1” → “0”

Mono Line Amp goes to normal operation.

(7) Enter power-save mode of Mono Line Amp: AOPSN bit = “0” → “1”

(8) Power Down of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “1” → “0”

AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1µF.

(9) Disable the path of “DAC Æ Mono Line Amp” : DACA bit: “1” → “0”

(10)Exit power-save mode of Mono Line Amp after AOUT pin falls down. : AOPSN bit = “1” → “0”

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[AK4632]

Video Signal Input and Output

Example:

Clocks

Clocks can be stopped, if only video output is enable.

1

Audio Function :No use

PLL Master Mode

VIDEO Output : DC Output

VGCA : 0dB

PMVCM bit

(Addr:00H, D6)

X

(1)

(2)

(1) Addr:00H, Data:45H

(2) Addr:0CH, Data:02H

(3) Addr:01H, Data:8BH

SAGC1-0 bits

(Addr:0CH, D6-5)

X X

VGCA4-0 bits

(Addr:0CH, D4-0)

X X X X X

(4)

(3)

PMV bit

(Addr:01H, D7)

Video Output

VOUT pin

AVSS

Normal Output

(4) Addr:01H, Data:0BH

Figure 55. Video Output Sequence

When the only video function is used, the clocks are not needed to input.

(1) Power Up of VCOM : PMVCM bit = “0” → “1”

(2) Set up the output circuit(SAGC1-0bits) and GCA(VGCA4-0 bits)

(3 ) Power Up of Video-Amp : PMV bit = “0” → “1”

The video signal that is input to VIN pin starts output from VOUT pin.

(4) Power Down of Video-Amp : PMV bit = “1” → “0”

The output from VOUT pin stops. VOUT pin goes to AVSS.

If any audio functions are not used, VCOM can be powered-down(PMVCM bit =“0”)

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[AK4632]

Stop of Clock

Master clock can be stopped when ADC, DAC, ALC1, ALC2 and IPGA don’t operate.

1. In case of PLL Master Mode

Example:

(1)

Audio I/F Format: DSP Mode, BCKP = MSBS = “0”

BICK frequency at Master Mode : 64fs

Input Master Clock Select at PLL Mode : 11.2896MHz

Sampling Frequency:8kHz

PMPLL bit

(Addr:01H,D0)

(2)

MCKO bit

"H"or"L"

(1) (2) (3) Addr:01H, Data:0CH

Stop an external MCKI

(Addr:01H,D1)

(3)

MCKPD bit

(Addr:01H,D2)

(4)

External MCKI

Input

Figure 56. Clock Stopping Sequence (1)

(1) Power down PLL: PMPLL bit = “1” → “0”

(2) Stop MCKO clock: MCKO bit = “1” → “0”

(3) Pull down the MCKI pin: MCKPD bit = “0” → “1”

When the external master clock becomes Hi-Z, MCKI pin should be pulled down.

(4) Stop an external master clock.

2. When an external clocks (FCK or BICK pins) are used in PLL Slave Mode.

Example

Audio I/F Format : DSP Mode, BCKP = MSBS = “0”

(1)

PLL Reference clock: BICK

BICK frequency: 64fs

PMPLL bit

(Addr:01H,D0)

Sampling Frequency: 8kHz

(2)

External BICK

External FCK

Input

(1) Addr:01H, Data:04H

(2) Stop the external clocks

Figure 57. Clock Stopping Sequence (2)

(1) Power down PLL: PMPLL bit = “1” → “0”

(2) Stop the external BICK and FCK clocks

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[AK4632]

3. When an external clock (MCKI pin) is used in PLL Slave Mode.

(1)

PMPLL bit

(Addr:01H,D0)

(1)

Example

MCKO bit

(Addr:01H,D1)

Audio I/F Format : DSP Mode, BCKP = MSBS = “0”

PLL Reference clock: MCKI

BICK frequency: 64fs

Sampling Frequency: 8kHz

(1)

MCKPD bit

(Addr:01H,D2)

(1) Addr:01H, Data:04H

(2)

External MCKI

Input

(2) Stop the external clocks

Figure 58. Clock Stopping Sequence (3)

(1) Power down PLL: PMPLL bit = “1” → “0”

Stop MCKO output: MCKO bit = “1” → “0”

Pull down the MCKI pin: MCKPD bit = “0” → “1”

When the external master clock becomes Hi-Z, MCKI pin should be pulled down.

(2) Stop the external master clock.

4. EXT Slave Mode

Example

Audio I/F Format :MSB justified(ADC and DAC)

Input MCKI frequency:1024fs

Sampling Frequency:8kHz

(1)

MCKPD bit

(Addr:01H,D2)

(2)

(1) Addr:01H, Data:04H

External MCKI

External BICK

External FCK

Input

(2)

(2) Stop the external clocks

Figure 59. Clock Stopping Sequence (4)

(1) Pull down the MCKI pin: MCKPD bit = “0” → “1”

When the external master clock becomes Hi-Z, MCKI pin should be pulled down.

(2) Stop the external MCKI, BICK and FCK clocks.

Power down

If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are

powered-down and a master clock stops. The AK4632 is also powered-down by PDN pin = “L”. When PDN pin = “L”,

the registers are initialized.

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[AK4632]

PACKAGE

32pin QFN (Unit: mm)

5.00 ± 0.10

4.75 ± 0.10

0.40 ± 0.10

24

17

25

16

B

Exposed

Pad

9

32

1

C0.42

1

8

A

3.5

+0.07

0.23 ^-0.05

0.50

AB

M

0.10

C

0.08

Note) The exposed pad on the bottom surface of the package must be open.

Material & Lead finish

Package molding compound:

Lead frame material:

Epoxy

Cu

Lead frame surface treatment:

Solder (Pb free) plate

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[AK4632]

MARKING

4632

XXXX

1

XXXX : Date code identifier (4 digits)

Revision History

Date (YY/MM/DD) Revision Reason

05/06/01 00 First Edition

Page

Contents

IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering

any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or

authorized distributor concerning their current status.

• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the

application or use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license

or other official approval under the law and regulations of the country of export pertaining to customs

and tariffs, currency exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to any

such use, except with the express written consent of the Representative Director of AKM. As used

here:

a. A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its

failure to function or perform may reasonably be expected to result in loss of life or in significant

injury or damage to person or property.

b. A critical component is one whose failure to function or perform may reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or

system containing it, and which must therefore meet very high standards of performance and

reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or

otherwise places the product with a third party to notify that party in advance of the above content

and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability

for and hold AKM harmless from any and all claims arising from the use of said product in the

absence of such notification.

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型号：	AKD4632
厂家：	ASAHI KASEI MICROSYSTEMS
描述：	16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP 16位ΔΣ单声道编解码器与ALC ＆ MIC / SPK /视频- AMP 解码器编解码器
文件：	总70页 (文件大小：619K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AKD4632 [AKM]

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