ALD500PC [ALD]
PRECISION INTEGRATING ANALOG PROCESSOR; 精密积分模拟处理器
| 型号： | ALD500PC |
| 厂家： | 
ADVANCED LINEAR DEVICES |
| 描述： | PRECISION INTEGRATING ANALOG PROCESSOR |
| 文件： | 总11页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED
LINEAR
DEVICES, INC.
ALD500AU/ALD500A/ALD500
PRECISION INTEGRATING ANALOG PROCESSOR
BENEFITS
APPLICATIONS
• 4 1/2 digits to 5 1/2 digits plus sign measurements
• Precision analog signal processor
• Precision sensor interface
• High accuracy DC measurement functions
• Portable battery operated instruments
• Computer peripheral
• Wide dynamic signal range
• Very high noise immunity
• Low cost, simple functionality
• Automatic compensation and cancellation of
error sources
• Easy to use to acquire true 18 bit,17 bit, or
16 bit conversion and noise performance
• Inherently linear and stable with temperature
and component variations
• PCMCIA
GENERAL DESCRIPTION
The ALD500AU/ALD500A/ALD500 are integrating dual slope analog
processors, designed to operate on ±5V power supplies for building
precision analog-to-digital converters. The ALD500AU/ALD500A/
ALD500 feature specifications suitable for 18 bit/17 bit/16 bit resolution
conversion, respectively. Together with three capacitors, one resistor,
a precision voltage reference, and a digital controller, a precision
Analog to Digital converter with auto zero can be implemented. The
digital controller can be implemented by an external microcontroller,
under either hardware (fixed logic) or software control. For ultra high
resolutionapplications,upto23bitconversioncanbeimplementedwith
an appropriate digital controller and software.
FEATURES
• Resolution up to 18 bits plus sign bit
and over-range bit
• Accuracy independent of input source
impedances
• High input impedance of 1012
Ω
• Inherently filters and integrates any
external noise spikes
• Differential analog input
• Wide bipolar analog input voltage
range ±3.5V
The ALD500 series of analog processors accept differential inputs and
the external digital controller first counts the number of pulses at a fixed
clock rate that a capacitor requires to integrate against an unknown
analog input voltage, then counts the number of pulses required to
deintegrate the capacitor against a known reference voltage. This
unknown analog voltage can then be converted by the microcontroller
to a digital word, which is translated into a high resolution number,
representing an accurate reading. This reading, when ratioed against
thereferencevoltage,yieldsanaccurate,absolutevoltagemeasurement
reading.
• Automatic zero offset compensation
• Low linearity error - as low as 0.002%
• Fast zero-crossing comparator - 1µs
• Low power dissipation - 6mW typical
• Automatic internal polarity detection
• Low input current - 2pA typical
• Microprocessor controlled conversion
• Optional digital control from a microcon-
troller, an ASIC, or a dedicated digital circuit
• Flexible conversion speed versus resolution
trade-off
TheALD500analogprocessorsconsistofon-chipdigitalcontrolcircuitry
to accept control inputs, integrating buffer amplifiers, analog switches,
and voltage comparators. It functions in four operating modes, or
phases, namely auto zero, integrate, deintegrate, and integrator zero
phases. At the end of a conversion, the comparator output goes from
high to low when the integrator crosses zero during deintegration.
ALD500 analog processors also provide direct logic interface to CMOS
logic families.
PIN CONFIGURATION
ALD500
+
V
1
2
3
4
5
6
7
8
C
16
15
14
13
12
11
10
9
INT
-
DGND
V
C
AZ
UF
C
OUT
ORDERING INFORMATION
Operating Temperature Range *
B
B
A
0°C to +70°C
0°C to +70°C
0°C to +70°C
AGND
16-Pin
Plastic Pin
Package
16-Pin
Small Outline
Package (SOIC)
16-Pin Wide Body
Small Outline
Package (SOIC)
-
C
+
V
REF
IN
+
-
V
C
REF
REF
IN
-
+
V
V
REF
ALD500PC (16 bit)
ALD500APC (17 bit)
ALD500AUPC (18 bit)
ALD500SC (16 bit)
ALD500ASC (17 bit)
ALD500AUSC (18 bit) ALD500AUSWC (18 bit)
ALD500SWC (16 bit)
ALD500ASWC (17 bit)
PC, SC, SWC PACKAGE
* Contact factory for industrial temperature range
Rev. 1.02 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286
http://www.aldinc.com
FIGURE 1. ALD 500 Functional Block Diagram
R
INT
C
INT
C
REF
C
AZ
+
-
C
INT
(1)
+
V
V
-
C
C
REF
REF
(8)
BUF
(4)
C
AZ
(3)
REF
(7)
REF
(6)
(9)
SW
SW
SW
R
R
-
SW
IN
Buffer
+
Integrator
-
+
V
IN
(11)
+
-
+
SW
R
R
+
-
Comp1
-
Level
Shift
Comp2
+
C
OUT
(14)
SW
AZ
+
-
SW
SW
SW
S
R
R
SW
SW
Az
IN
Polarity
Detection
DGND
(15)
AGND
(5)
SW
G
-
V
Analog
IN
(10)
Phase
Decoding
Logic
Switch
Control
Signals
V
SS
(2)
V
DD
(16)
A
B
(12) (13)
Control Logic
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles of Operation
The basic principle of dual-slope integrating analog to digital
c. Offset voltage values of the analog components, such
as VX, are cancelled out and do not affect accuracy.
d. Accuracyofthesystemdependsmainlyontheaccuracy
converter is simple and straightforward. A capacitor, CINT, is and the stability of the voltage reference value.
charged with the integrator from a starting voltage, VX, for a
fixed period of time at a rate determined by the value of an
unknown input voltage, which is the subject of measurement.
Then the capacitor is discharged at a fixed rate, based on an
e. Very high resolution, high accuracy measurements
can be achieved simply and at very low cost.
external reference voltage, back to VX where the discharge Aninherentbenefitofthedualslopeconvertersystemisnoise
time, or deintegration time, is measured precisely. Both the immunity. The input noise spikes are integrated (averaged to
integration time and deintegration time are measured by a
digital counter controlled by a crystal oscillator. It can be
near zero) during the integration periods. Integrating ADCs
are immune to the large conversion errors that plague
demonstrated that the unknown input voltage is determined successiveapproximationconvertersandotherhighresolution
by the ratio of the deintegration time and integration time, and converters and perform very well in high-noise environments.
isdirectlyproportionaltothemagnitudeoftheexternalreference
voltage.
Theslowconversionspeedoftheintegratingconverterprovides
inherentnoiserejectionwithatleasta20dB/decadeattenuation
rate. Interferencesignalswithfrequenciesatintegralmultiples
The major advantages of a dual-slope converter are:
a. Accuracy is not dependent on absolute values of oftheintegrationperiodare,theoretically,completelyremoved.
integration time tINT and deintegration time tDINT, but is Integrating converters often establish the integration period to
dependent on their relative ratios. Long-term clock frequency
variations will not affect the accuracy. A standard crystal
reject 50/60Hz line frequency interference signals.
controlledclockrunningdigitalcountersisadequatetogenerate The relationship of the integrate and deintegrate (charge
very high accuracies.
and discharge) of the integrating capacitor values are
shown below:
b. Accuracy is not dependent on the absolute values of
RINT and CINT. as long as the component values do not vary
through a conversion cycle, which typically lasts less than 1
second.
. .
VINT = VX - (VIN tINT / RINT CINT)
2
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
(integrate cycle)
VX = VINT - (VREF
(1)
(2)
(3)
Phase, internal analog switches connect VIN to the buffer
input where it is maintained for a fixed integration time period
(tINT). This fixed integration period is generally determined by
a digital counter controlled by a crystal oscillator. The
application of VIN causes the integrator output to depart 0V at
a rate determined by VIN and a direction determined by the
polarity of VIN.
.
.
tDINT / RINT CINT)
(deintegrate cycle)
Combining equations 1 and 2 results in:
IN / VREF = -tDINT / tINT
where:
V
The Reference Voltage Deintegration Phase is initiated
immediately after tINT, within 1 clock cycle. During Reference
VoltageDeintegrationPhase,internalanalogswitchesconnect
a reference voltage having a polarity opposite that of VIN to
the integrator input. Simultaneously the same digital counter
controlled by the same crystal oscillator used above is used to
start counting clock pulses. The Reference Voltage
DeintegrationPhaseismaintaineduntilthecomparatoroutput
Vx = An offset voltage used as starting voltage
VINT = Voltage change across CINT during tINT and
during tDINT (equal in magnitude)
VIN = Average, or an integrated, value of input voltage
to be measured during tINT (Constant VIN)
tINT = Fixed time period over which unknown voltage is insidethedualslopeanalogprocessorchangesstate,indicating
integrated
the integrator has returned to 0V. At that point the digital
counter is stopped. The Deintegration time period (tDINT), as
measured by the digital counter, is directly proportional to the
magnitude of the applied input voltage.
tDINT = Unknown time period over which a known
reference voltage is integrated
VREF = Reference Voltage
CINT = Integrating Capacitor value
RINT = Integrating Resistor value
After the digital counter value has been read, the digital
counter, the integrator, and the auto zero capacitor are all
Actual data conversion is accomplished in two phases: Input reset to zero through an Integrator Zero Phase and an Auto
SignalIntegrationPhaseandReferenceVoltageDeintegration Zero Phase so that the next conversion can begin again. In
Phase.
practice, this process is usually automated so that analog-to-
digital conversion is continuously updated. The digital control
The integrator output is initialized to 0V prior to the start of ishandledbyamicroprocessororadedicatedlogiccontroller.
InputSignalIntegrationPhase. DuringInputSignalIntegration The output, in the form of a binary serial word, is read by a
microprocessor or a display adapter when desired.
C
INT
INTEGRATOR
-
R
INT
ANALOG
INPUT
V
INT
COMPARATOR
+
-
C
OUT
(V
)
IN
+
S1
POLARITY
DETECTION
PHASE
CONTROL
VOLTAGE
REFERENCE
SWITCH DRIVER
REF
SWITCHES
CONTROL
LOGIC
POLARITY CONTROL
A
B
V
INT
= 4.1V MAX
V
V
IN ≈ FULL SCALE
V
V
IN ≈ 1/2 FULL SCALE
MICROCONTROLLER
(CONTROL LOGIC
+ COUNTER)
V
X ≈ 0
t
DINT
t
t
INT
DINT
Figure 2. Basic Dual-Slope Converter
Figure 2. Basic Dual-Slope Converter
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
3
ABSOLUTE MAXIMUM RATINGS
+
Supply voltage, V
13.2V
-0.3V to V +0.3V
600 mW
+
Differential input voltage range
Power dissipation
Operating temperature range PC, SC, SWC package
Storage temperature range
Lead temperature, 10 seconds
0°C to +70°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
+
-
T
= 25°C V = +5.0V V = -5.0V (V
= ±5.0 V) unless otherwise specified; C = C
AZ
= 0.47µf
REF
A
SUPPLY
500AU
500A
Typ
500
Typ
Parameter
Symbol
Min
15
Typ
Max
Min
30
Max
Min
60
Max
Unit
Test Conditions
Resolution
30
60
µV
Note 1
Zero-Scale
Error
Z
0.0025
0.003
0.003
0.005
0.005
0.008
%
%
SE
0°C to 70°C
End Point
Linearity
E
0.005
0.007
0.005 0.010
0.015
0.005
0.003
0.015
0.020
%
%
Notes 1, 2
0°C to +70°C
NL
Best Case
Straight Line
Linearity
N
0.0025
0.004
0.6
0.003 0.005
0.008
0.008
0.015
0.7
Notes 1, 2
0°C to +70°C
0°C to +70°C
Note 1
L
Zero-Scale
Temperature
Coefficient
TC
ZS
0.3
0.15
0.3
0.15
0.7
0.3
0.15
0.01
0.012
1.3
µV/°C
ppm/°C
%
0.3
0.35
0.35
Full-Scale
Symmetry Error
(Rollover Error)
S
YE
0.005
0.008
1.3
0.008
0.010
1.3
%
0°C to 70°C
Full-Scale
TC
FS
ppm/°C
0°C to +70°C
Temperature
Coefficient
Input
Current
I
2
2
2
pA
V
V
IN
= 0V
IN
-
+
-
+
-
+
Common-Mode CMVR V +1.5
Voltage Range
V -1.5 V +1.5
V -1.5 V +1.5
V -1.5
-
+
-
+
-
+
Integrator
VINT
V +0.9
V -0.9 V +0.9
V -0.9 V +0.9
V -0.9
V
Output Swing
-
+
-
+
-
+
Analog Input
Signal Range
VIN
V +1.5
V -1.5 V +1.5
V -1.5 V +1.5
V -1.5
V
AGND = 0V
-
+
-
+
-
+
Voltage
Reference
Range
VREF
V +1
V -1
V +1
V -1
V +1
V -1
V
4
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
DC ELECTRICAL CHARACTERISTICS
+
-
T
= 25°C V = +5.0V V = -5.0V (V
= ±5.0 V) unless otherwise specified; C = C
= 0.47µf
REF
A
SUPPLY
AZ
500AU
Typ
500A
Typ
500
Typ
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Test Conditions
+
Supply Current
I
0.6
1.0
0.6
1.0
0.6
1.0
mA
V
V
= 5V , A =1,B=1
S
Power Dissipation
P
10
10
10
mW
V
= ±5V
D
SUPPLY
Positive Supply Range
V
4.5
-4.5
4
5.5
4.5
-4.5
4
5.5
4.5
5.5
Note 4
Note 4
+S
Negative Supply Range
V
-5.5
0.4
1
-5.5
0.4
1
-4.5
4
-5.5
0.4
1
V
V
V
V
V
-S
Comparator Logic 1,
Output High
V
I
I
= 400µA
SOURCE
OH
Comparator Logic 0,
Output Low
V
= 1.1mA
SINK
OL
Logic 1, Input High
Voltage
V
3.5
3.5
3.5
IH
Logic 0, Input Low
Voltage
V
IL
Logic Input Current
Comparator Delay
I
t
0.01
1
0.01
1
0.01
1
µA
L
µsec
Note 5
D
NOTES:
~
1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., V
INT
= 4V, V = 2.0V Full Scale
IN
Resolution = V
INT
/integrate time/clock period
2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.
3. Rollover Error also depends on C , C , C characteristics.
INT REF AZ
4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V.
5. Recommended selection of clock periods of one of the following:
t clk = 0.27µsec, 0.54µsec, or 1.09µsec
which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
Figure 3. ALD500 TIMING DIAGRAM
1 Conversion Cycle
123,093
123,093
0.5416 µs
Clock Pulses
Clock Pulses
~
~
1.8432 MHz Clock
A INPUT
66.667 msec.
66.667 msec.
B INPUT
COUT
NOT VALID
NOT VALID
Positive Input Signal
COUT
Negative Input Signal
Auto Zero
Phase
Input Signal
Integration
Phase
Reference
Voltage
Deintegration
Phase
Integrator Zero
Phase
Auto Zero
Phase
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed period of
approx.1 msec.
Variable
number of
clock pulses.
Fixed number
of clock pulses
by design.
At VIN MAX,
max. number of
clock pulses
Stop counter upon
detection of comparator
output going from high
to low state.
START
REPEAT
CONVERSION
CYCLE
CONVERSION
CYCLE
~
= 246,185
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
START INTEGRATOR ZERO CYCLE
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
5
PIN DESCRIPTION
Pin No.
Symbol
Description
1
C
Integrator capacitor connection.
INT
-
2
V
C
Negative power supply.
3
The Auto-zero capacitor connection.
The Integrator resistor buffer connection.
This pin is analog ground.
AZ
4
BUF
5
AGND
-
6
C
C
V
Negative reference capacitor connection.
Positive reference capacitor connection.
External voltage reference (-) connection.
External voltage reference (+) connection.
Negative analog input.
REF
+
7
REF
-
8
REF
REF
IN
+
9
V
V
V
A
B
-
10
11
12
13
14
+
Positive analog input.
IN
Converter phase control MSB Input.
Converter phase control LSB Input.
C
Comparator output. C
OUT
is LOW when a negative input voltage is being integrated. A HIGH-to-LOW transition on C
that the Deintegrate phase is completed. C
time the Integrator Zero phase.
is HIGH during the Integration phase when a positive input voltage is being integrated and
signals the processor
is undefined during the Auto-Zero phase. It should be monitored to
OUT
OUT
OUT
15
16
DGND
Digital ground.
+
V
Positive power supply.
Table 1. Conversion Phase and Control Logic Internal Analog Switch Functions
Switch Functions
Input
Connect
Reference Input Auto Zero
Polarity
Reference
Sample
V
=AGND
System
Offset
IN
Conversion Control
Phase
Logic
+
-
SW
R
SW
SW
SW
AZ
SW
SW
SW
S
IN
R or
R
G
Auto Zero
A = 0, B = 1
A = 1, B = 0
Open
Open
Open
Closed
Open
Closed
Open
Closed
Open
Open
Open
Input Signal
Integration
Closed
Reference Voltage A = 1, B = 1
Deintegration
Open
Open
Closed*
Open
Open
Open
Open
Closed
Closed
Open
Integrator
A = 0, B = 0
Closed
Closed
Output Zero
+
-
R
*SW would be closed for a positive input signal. SW would be closed for a negative input signal.
R
6
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
ALD500AU/ALD500A/ALD500 CONVERSION CYCLE
value selections. The total number of clock pulses or clock
counts, during integration phase determine the resolution of
The ALD500AU/ALD500A/ALD500 conversion cycle takes the conversion. For high resolution applications, this total
place in four distinct phases, the Auto Zero Phase, the Input number of clock pulses should be maximized. The basic unit
SignalIntegrationPhase,theReferenceVoltageDeintegration of resolution is in µV/count. Before the end of this phase,
Phase,andtheIntegratorZeroPhase.Atypicalmeasurement
comparator output is sampled by the microcontroller. This
cycle uses all four phases in an order sequence as mentioned phaseisterminatedbychanginglogicinputsABfrom10to11.
above. The internal analog switch status for each of these
phases is summarized in Table 1.
Reference Voltage Deintegration Phase ( DINT Phase)
The following is a detailed description of each one of the four
phases of the conversion cycle.
At the end of the Input Signal Integration Phase, Reference
Voltage Deintegration Phase begins. The previously charged
reference capacitor is connected with the proper polarity to
ramp the integrator output back to zero. The ALD500AU/
ALD500A/ALD500 analog processors automatically selects
the proper logic state to cause the integrator to ramp back
Auto Zero Phase (AZ Phase)
The analog-to-digital conversion cycle begins with the Auto
Zero Phase, when the digital controller applies low logic level toward zero at a rate proportional to the reference voltage
to input A and high logic level to input B of the analog stored on the reference capacitor. The time required to return
processor. During this phase, the reference voltage is stored to zero is measured by the counter in the digital processor
on reference capacitor CREF, comparator offset voltage and using the same crystal oscillator. The phase is terminated by
the sum of the buffer and integrator offset voltages are stored
the comparator output after the comparator senses when the
on auto zero capacitor CAZ. During the Auto Zero Phase, the integrator output crosses zero. The counter contents are then
comparator output is characterized by an indeterminate transferred to the register. The resulting time measurement
waveform.
is proportional to the magnitude of the applied input voltage.
During the Auto Zero Phase, the external input signal is
The duration of this phase is precisely measured from the
disconnected from the internal circuitry of the ALD500AU/ transition of AB from 10 to 11 to the falling edge of the
ALD500A/ALD500 by opening the two SWIN analog switches comparator output, usually with a crystal controlled digital
and connecting the internal input nodes internally to analog counter chain. The comparator delay contributes some error
ground. A feedback loop, closed around the integrator and in this phase. The typical comparator delay is 1µ . The
sec
comparator, charges the CAZ capacitor with a voltage to
comparator delay and overshoot will result in error timing,
compensate for buffer amplifier, integrator and comparator which translates into error voltages. This error can be zeroed
offset voltages.
and minimized during Integrator Output Zero Phase and
corrected in software, to within ±1 count of the crystal clock
This is the system initialization phase, when a conversion is (which is equivalent to within ± 1 LSB, when 1 clock pulse = 1
ready to be initiated at system turn-on. In practice the
converter can be operated in continuous conversion mode,
LSB).
whereAZphasemustbelongenoughforthecircuitconditions Integrator Zero Phase ( INTZ Phase)
to settle out any system errors. Typically this phase is set to
be equal to tINT
.
This phase guarantees the integrator output is at 0V when the
Auto Zero phase is entered, and that only system offset
voltages are compensated. This phase is used at the end of
thereferencevoltagedeintegrationandisusedforapplications
Input Signal Integration Phase (INT Phase)
DuringtheInputSignalIntegrationPhase(INT),theALD500AU/ with high resolutions. If this phase is not used, the value of the
ALD500A/ALD500 integrates the differential voltage across Auto-Zero capacitor (CAZ) must be much greater than the
+
-
the (V IN) and (V IN) inputs. The differential voltage must be
value of the integration capacitor (CINT) to reduce the effects
within the device's common-mode voltage range CMVR. The of charge-sharing. The Integrator Zero phase should be
integrator charges CINT for a fixed period of time, or counts a programmed to operate until the Output of the Comparator
fixed number of clock pulses, at a rate determined by the returns "HIGH". A typical Integrator Zero Phase lasts 1msec.
magnitude of the input voltage. During this phase, the analog
inputs see only the high impedance of the noninverting
The comparator delay and the controller's response latency
operationalamplifierinputofthebuffer. Theintegratorresponds may result in Overshoot causing charge buildup on the
only to the voltage difference between the analog input integrator at the end of a conversion. This charge must be
terminals, thus providing true differential analog inputs.
removed or performance will degrade. The Integrator Output
Zero phase should be activated (AB = 00) until COUT goes
high. Atthispoint,theintegratoroutputisnearzero. AutoZero
The input signal polarity is determined by software control at
the end of this phase: COUT = 1 for positive input polarity; Phase should be entered (AB = 01) and the ALD500AU/
OUT = 0 for negative input polarity. The value is, in effect, the ALD500A/ALD500isheldinthisstateuntilthenextconversion
C
sign bit for the overall conversion result.
cycle.
The duration of this phase is selected by design to be a fixed
time and depends on system parameters and component
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
7
+
-
Differential Inputs (V IN,V IN)
(+) or (-) input voltages will cause a roll-over error. This error
can be minimized by using a large reference capacitor in
The ALD500AU/ALD500A/ALD500 operates with differential comparison to the stray capacitance.
voltages within the input amplifier common-mode voltage
range. Theamplifiercommon-moderangeextendsfrom1.5V Phase Control Inputs (A, B)
below positive supply to 1.5V above negative supply. Within
thiscommon-modevoltagerange, common-moderejectionis The A and B logic inputs select the ALD500AU/ALD500A/
typically 95dB.
ALD500 operating phase. The A and B inputs are normally
driven by a microprocessor I/O port or external logic, using
The integrator output also follows the common-mode voltage. CMOS logic levels. For logic control functions of A and B logic
When large common-mode voltages with near full-scale inputs, see Table 1.
differential input voltages are applied, the input signal drives
the integrator output to near the supply rails where the Comparator Output (COUT
)
integrator output is near saturation. Under such conditions,
linearity of the converter may be adversely affected as the By monitoring the comparator output during the Input Signal
integrator swing can be reduced. The integrator output must Integration Phase, which is a fixed signal integrate time
notbeallowedtosaturate. Typically, theintegratoroutputcan period, the input signal polarity can be determined by the
swing to within 0.9V of either supply rails without loss of microcontroller controlling the conversion. The comparator
linearity.
output is HIGH for positive signals and LOW for negative
signals during the Input Signal Integration Phase. The state of
the comparator should be checked by the microcontroller at
the end of the Input Signal Integration Phase, just before
Analog Ground
AnalogGroundisV-IN duringAutoZeroPhaseandReference transition to the Reference Voltage Deintegration Phase. For
Voltage Deintegration Phase. If V- is different from analog very low level input signals noise may cause the comparator
ground, a common-mode voltage exists at the inputs. This output state to toggle between positive and negative states.
common mode signal is rejected by the high common mode For the ALD500AU/ALD500A/ALD500, this noise has been
rejection ratio of the converter. In most applications, V
set at a fixed known voltage (i.e., power supply ground). All
other ground connections should be connected to digital At the start of the Reference Voltage Deintegration Phase,
IN
-
is minimized to typically within one count.
IN
ground in order to minimize noise at the inputs.
comparator output is set to HIGH state. During the Reference
VoltageDeintegrationPhase,themicrocontrollermustmonitor
the comparator output to make a HIGH-to-LOW transition as
the integrator output ramp crosses zero relative to analog
+
-
Differential Reference (V REF, V REF
)
The reference voltage can be anywhere from 1V of the power ground. This transition indicates that the conversion is
supply voltage rails of the converter. Roll-over error is caused complete. The microcontroller then stops and records the
by the reference capacitor losing or gaining charge due to the pulsecount. Theinternalcomparatordelayis1µsec,typically.
straycapacitanceonitsnodes. Thedifferenceinreferencefor The comparator output is undefined during the Auto Zero
Phase.
Positive Input Signal (VIN
)
0V
Negative Input Signal (VIN
)
ANALOG INPUT
REFERENCE
DEINTEGRATE
INTEGRATE
ANALOG INPUT
INTEGRATE
REFERENCE
DEINTEGRATE
INTEGRATOR
OUTPUT
INTEGRATOR
OUTPUT
(V
)
INT
ZERO
CROSSING
ZERO
CROSSING
(V
)
INT
EXTERNAL INPUT
EXTERNAL INPUT
POLARITY DETECTION
POLARITY DETECTION
COMPARATOR
OUTPUT
COMPARATOR
OUTPUT
(C
)
(C
)
OUT
OUT
Figure 4. Comparator Output
8
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
APPLICATIONS AND DESIGN NOTES
where:
V
IN MAX = Maximum input voltage desired
Determination and Selection of System Variables
(full count voltage)
RINT
= Integrating Resistor value
Theprocedureoutlinedbelowallowstheusertodeterminethe
valuesforthefollowingALD500AU/ALD500A/ALD500system
design variables:
For minimum noise and maximum linearity, RINT should be in
the range of between 50kΩ to 150kΩ .
(1) Determine Input Voltage Range
(2) Clock Frequency and Resolution Selection
(3) Input Integration Phase Timing
(4) Integrator Timing Components (RINT, CINT
(5) Auto Zero and Reference Capacitors
(6) Voltage Reference
Integrating Capacitor (CINT
)
)
The integrating capacitor should be selected to maximize
integrator output voltage swing VINT, for a given integration
time, without output level saturation. For +/-5V supplies,
recommended VINT range is between +/- 3 Volt to +/-4 Volt.
Using the 20µA buffer maximum output current, the value of
the integrating capacitor is calculated as follows:
System Timing
Figure 3 and Figure 4 show the overall timing for a typical
system in which ALD500AU/ALD500A/ALD500 is interfaced
toamicrocontroller. ThemicrocontrollerdrivestheA, Binputs
-6
.
C
INT = (tINT) (20 x 10 ) / VINT
with I/O lines and monitors the comparator output, COUT
,
where: tINT
VINT
=
=
Input Integration Phase Period
Maximum integrator output
voltage swing
using an I/O line or dedicated timer-capture control pin. It may
be necessary to monitor the state of the comparator output in
additiontohavingitcontrolatimerdirectlyduringtheReference
Deintegration Phase.
It is critical that the integrating capacitor must have a very low
dielectricabsorption, aschargelossorgainduringconversion
directlyconvertsintoanerrorvoltage. Polypropylenecapacitors
are recommended while Polyester and Polybicarbonate
capacitors may also be used in less critical applications.
There are four critical timing events: sampling the input
polarity;capturingthedeintegrationtime;minimizingovershoot
and properly executing the Integrator Output Zero Phase.
Selecting Input Integration Time
Reference (CREF) and Auto Zero (CAZ) Capacitors
For maximum 50/60 cycle noise rejection, Input Integration
Time must be picked as a multiple of the period of line
frequency. For example, tINT times of 33msec, 66msec and
100 msec maximize 60Hz line rejection, and 20msec, 40
msec, 80msec, and 100 msec maximize 50Hz line rejection.
Note that tINT of 100 msec maximizes both 60 Hz and 50Hz
line rejection.
CREF and CAZ must be low leakage capacitors (e.g.
polypropylene types). The slower the conversion rate, the
larger the value CREF must be. Recommended capacitor
values for CREF and CAZ are equal to CINT. Larger values for
CAZ and CREF may also be used to limit roll-over errors.
Calculate VREF
INT and DINT Phase Timing
The reference deintegration voltage is calculated using:
. .
REF = (VINT) (CINT) (RINT) / 2(tINT)
V
The duration of the Reference Deintegrate Phase (DINT) is a
function of the amount of voltage charge stored on the
integrator capacitor during INT phase, and the value of VREF
.
Converter Noise
The DINT phase must be initiated immediately following INT
phaseandterminatedwhenanintegratoroutputzero-crossing
is detected. In general, the maximum number of counts
chosenforDINT phaseistwicetothreetimesthatofINTphase
with VREF chosen as a maximum voltage relative to VIN. For
example, VREF = VIN(max)/2 would be a good reference
voltage.
The converter noise is the total algebraic sum of the integrator
noise and the comparator noise. This value is typically 14 µV
peak to peak. The higher the value of the reference voltage,
the lower the converter noise. Such sources of noise errors
canbereducedbyincreasedintegrationtimes,whicheffectively
filter out any such noise. If the integration time periods are
selected as multiples of 50/60Hz frequencies, then 50/60Hz
noise is also rejected, or averaged out. The signal-to-noise
ratio is related to the integration time (tINT) and the integration
time constant (RINT) (CINT) as follows:
Integrating Resistor (RINT
)
The desired full-scale input voltage and amplifier output
current capability determine the value of RINT. The buffer and
integrator amplifiers each have a full-scale current of 20µA.
-6
.
.
S/N (dB) = 20 Log ((VINT / 14 x 10 ) tINT /(RINT CINT))
The value of RINT is therefore directly calculated as follows:
This converter noise can also be reduced by using multiple
samples and mathematically averaged. For example, taking
16samplesandaveragingthereadingsresultinamathematical
(by software) filtering of noise to less than 4µV.
RINT
= VIN MAX / 20 µA
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
9
DESIGN EXAMPLES
We now apply these equations in the following
design examples.
EQUATIONS AND DERIVATIONS
Dual Slope Analog Processor equations and derivations
are as follows:
t
INT
.
.
1
V
t
(1)
REF DINT
∫
V
IN
(t)dt =
Design Example 1:
.
R
C
INT
0
INT
R
C
INT
INT
For V (t) = V (constant):
IN
IN
1. Pick resolution = 16 bit.
1
2. Pick t
= 4x
= 4 x 16.6667 msec.
= 66.6667ms
INT
.
V
t
1
.
REF DINT
60Hz
(2)
.
t
V
=
IN
INT
.
C
INT
R
.
C
INT
R
INT
INT
= 0.0666667 sec.
t
t
DINT
(2a)
(3)
.
. .
V
IN
= V
REF
3. Pick clock period = 1.08507 µs and number of counts
INT
0.0666667
= 61440
over t
INT
=
.
t
I
INT
B
-6
C
=
1.08507x10
INT
V
INT
4. Pick V MAX value, e.g., V MAX = 2.0 V
IN
I MAX = 20µA
IN
At V MAX, the current I is also at a maximum level,
IN
B
2.0
for a given R
value:
INT
R
INT
=
= 100 kΩ
B
-6
20x10
V
IN
I
B
V
MAX
IN
(4)
R
=
=
INT
5. Applying equation (3) to calculate C
-6
INT:
I MAX
B
C
INT
= (0.0666667)(20x10 )/4 where V
= 4.0V
INT
From equation (2a),
~
0.33 µF
=
.
V
t
IN INT
(5a)
(5b)
~
~
0.33 µF
V
=
6. Pick C
and C ≥ C : C
C
AZ
=
REF
REF
AZ
INT
REF
=
t
DINT
OR
7. Pick t
= 2 x t
INT
= 133.3334 msec
DINT
.
t
V
MAX
IN
INT
MAX
V
=
REF
.
.
R
INT
V
INT
MAX
C
INT
t
DINT
=
8. Calculate V
V
REF
t
MAX
DINT
Rearranging equations (3) and (4):
.
-6
3
C
V
INT
4 x 0.33 x 10 x 100 x 10
INT
t
=
(6)
(7)
INT
=
V
-3
I
133.3334 x 10
B
and
V
MAX
IN
= 0.99V
~
I MAX =
B
R
INT
1.00V
=
At V
V
MAX, equation (6) becomes:
INT = INT
.
Design Example 2:
C
=
V
MAX
INT
INT
t
INT
(6a)
I MAX
B
1. Select resolution of 17 bit. Total number of
counts during t
is131,072.
INT
Combining (6a) and (7):
.
.
R
INT
.
C
V
MAX
INT
INT
MAX
. .
(8)
t
=
2. We can pick t
of 16.6667 msec. x 5 = 83.3333 msec.
INT
INT
V
IN
In equation (5b), substituting equation (8) for t
or alternately, pick t
equal
INT
16.6667 msec. x 6 = 100.00 msec.
(for 60 Hz rejection)
:
INT
.
.
R
INT
C
INT
V
INT
MAX
which is t
= 20.00 msec. x 5
INT
.
V
MAX
V
IN
MAX
IN
(9)
= 100.00 msec. (for 50 Hz rejection)
V
=
=
REF
t
MAX
DINT
MAX
.
.
Therefore, using t
= 100 msec. would achieve
C
V
R
INT
INT
INT
INT
both 50 Hz and 60 Hz cycle noise rejection. For this
example, the following calculations would assume
t
MAX
DINT
t
of 100 msec. Now select period equal to
For t
MAX = 2 x t
,
INT
0.5425 µsec. (clock frequency of 1.8432 MHz)
DINT
INT
equation (9) becomes:
.
.
R
INT
C
INT
V
MAX
INT
2t
(10)
V
=
REF
INT
10
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
3. Pick V MAX = ±2V
IN
Design Example 4:
Objective: 5 1/2 digit + sign +over-range measurement.
For I MAX = 20µA, applying equation (4),
B
1. Pick t
= 133.333 msec. for 60Hz noise rejection.
INT
2
R
=
= 100 KΩ
INT
(16.6667 msec. x 8 cycles)
Frequency = 1.8432 MHz
clock period = 0.5425 µsec.
-6
20x10
4. Calculate, using equation (3) for C
-6
:
INT
C
= (0.1) x (20 x 10 /4)
~
INT
During Input Integrate Phase,
(assume V MAX = 4V)
= 0.5 µF
INT
-3
133.333 x 10
total count =
-6
0.5425 x 10
Use C
INT
0.47µF as the closest practical value.
= 245776
5. Pick C
and C = 0.47 µF
AZ
REF
For V
= 4.0V, the basic resolution is
INT
6. Pick t
= 2 x t
= 200 msec.
INT
DINT
4
or 16.276 µV/count
245776
7. Calculate the value for V
, from equation (10):
REF
For V MAX = 2.00V, the input resolution is
IN
.
.
V
REF
=
C
V
MAX
R
INT
V
MAX
INT
INT
IN
16.276
x
= 8.138 µV/count
V MAX
INT
t
MAX
DINT
-6
3
0.5 x 10 x 4 x 100 x 10
2. Pick V range = ± 2V
IN
=
-3
200 x 10
2
= 100 KΩ
For I = 20 µA, R
INT
=
B
= 1.00V
-6
20 x 10
~
-6
= (0.133333) x (20 x 10 )/4 = 0.67 µF
3. Calculate C
INT
Design Example 3:
4. Pick C
REF
= C = 0.67 µF
AZ
1. Pick resolution of 18 bit. Total number of counts during
t
is 262,144.
5. Select t
DINT
= 2 x t
= 266.667 msec.
INT
INT
2. Pick t
= 16.66667 msec. x 10 cycles
= 0.1666667 sec.
6. Calculate V
as shown in Design Example 1,
INT
REF
substituting the appropriate values:
.
.
R
INT
C
V
MAX
INT
INT
MAX
V
=
This t
allows clock period of 0.5425 µsec.
REF
INT
and still achieve 18 bits resolution.
t
DINT
~
= 1.005V
3. Again, as shown from previous example, pick V MAX = ±2V
IN
2
For I MAX = 20 µA,
R
=
INT
= 100 KΩ
B
-6
20x10
4. Next, we calculate C
INT:
-6
C
INT
= (0.1666667) x (20 x 10 )/4
~
(V MAX = 4.0V)
INT
= 0.83 µF
In this case, use CINT = 1.0 µF to keep
V
INT
< 4.0V
5. Pick C
and C = 1.0 µF
AZ
REF
6. Select t
DINT
= 2 x t
= 333.333 msec.
INT
7. Calculate V
as shown in the previous examples
REF
= 1.00V
and V
REF
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
11
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