A1245LLHLX-I2-T [ALLEGRO]
Chopper-Stabilized, Two Wire Hall-Effect Latch;型号: | A1245LLHLX-I2-T |
厂家: | ALLEGRO MICROSYSTEMS |
描述: | Chopper-Stabilized, Two Wire Hall-Effect Latch |
文件: | 总13页 (文件大小:567K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
A1245
Chopper-Stabilized, Two Wire Hall-Effect Latch
FEATURES AND BENEFITS
DESCRIPTION
• High speed, 4-phase chopper stabilization
□ Low switchpoint drift throughout temperature range
□ Low sensitivity to thermal and mechanical stresses
• On-chip protection
□ Supply transient protection
□ Reverse battery protection
• On-board voltage regulator
The A1245 is a two-wire Hall-effect latch. The device is
producedontheAllegro™ advancedBiCMOSwaferfabrication
process,whichimplementsapatentedhighfrequency,4-phase,
chopper-stabilization technique. This technique achieves
magnetic stability over the full operating temperature range,
and eliminates offsets inherent in devices with a single Hall
element that are exposed to harsh application environments.
□ 3.0 to 24 V operation
• Solid-state reliability
• Industry leading ISO 7637-2 performance through use of
proprietary, 40 V clamping structures
Two-wirelatchesareparticularlyadvantageousincost-sensitive
applications because they require one less wire for operation
versus the more traditional open-collector output switches.
Additionally, the system designer inherently gains diagnostics
because there is always output current flowing, which should
be in either of two narrow ranges.Any current level not within
these ranges indicates a fault condition.
PACKAGES:
Not to scale
The Hall-effect latch will be in the high output current state
in the presence of a magnetic south polarity field of sufficient
magnitude and will remain in this state until a sufficient north
polarity field is present.
Approximate
footprints
The device is offered in two package styles. The LH is a
SOT-23W style, miniature low profile package for surface-
mount applications. The UA is a 3-pin ultra-mini single inline
packages (SIP) for through-hole mounting. Both packages are
lead (Pb) free, with 100% matte tin leadframe plating.
3-pin SOT23-W
2 × 3 × 1 mm
(suffix LH)
3-pin ultramini SIP
1.5 × 4 × 3 mm
(suffix UA)
VCC
V+
Regulator
Clock/Logic
Amp
To all subcircuits
Schmitt
Trigger
Low-Pass
Filter
Polarity
GND
UA package only
GND
Functional Block Diagram
A1245-DS, Rev. 1
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
Selection Guide
Operating Ambient Tem-
perature, TA
Supply Current
at ICC(L)
Part Number
Packing*
Package
(°C)
(mA)
A1245LLHLX-I1-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1245LLHLX-I2-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40 to 150
–40 to 150
–40 to 150
–40 to 150
5 to 6.9
2 to 5
A1245LUA-I1-T
A1245LUA-I2-T
Bulk, 500 pieces/bag
Bulk, 500 pieces/bag
3-pin SIP through hole
3-pin SIP through hole
5 to 6.9
2 to 5
*Contact Allegro for additional packing options
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic
Symbol
VCC
Notes
Rating
28
Unit
V
Forward Supply Voltage
Reverse Supply Voltage
Magnetic Flux Density
VRCC
B
–18
V
Unlimited
–40 to 150
165
G
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
Range L
ºC
ºC
ºC
TJ(max)
Tstg
–65 to 170
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
Pin-out Diagrams and Terminal List Table
3
NC
2
3
2
1
1
LH Package, 3-pin
SOT23W Pin-out
UA Package, 3-pin SIP
Pin-out
Terminal List Table
Number
Name
LH
Function
UA
VCC
NC
1
2
1
Connects power supply to chip
N/A
2, 3
No connection (tie to GND; improved thermal characteristics) or float
Ground (Tie both to GND for improved thermal characteristics, or float
unused GND pin)
GND
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
ELECTRICAL CHARACTERISTICS: valid at TA = –40°C to 150°C; TJ < TJ(max); for LH and UA: CBYP = 0.01 µF; through oper-
ating supply voltage range; unless otherwise noted
Characteristics
Supply Voltage1,2
Symbol
Test Conditions
Min.
3.0
5
Typ.
Max.
24
6.9
5
Unit
V
VCC
Operating
-I1
–
–
–
–
–
B < BRP
B < BRP
mA
mA
mA
V
ICC(L)
Supply Current
-I2
2
ICC(H)
B > BOP
12
28
17
–
Supply Zener Clamp Voltage
Supply Zener Clamp Current
Reverse Supply Current
Output Slew Rate3
VZ(sup)
ICC(L)(max) + 3 mA, TA = 25°C
VZ(sup) = 28 V
ICC(L)(max)
+ 3 mA
IZ(sup)
IRCC
–
–
–
–
–
mA
mA
VRCC = –18 V
–1.6
–
No external bypass capacitor, capacitance of
probe CS = 20 pF
dI/dt
90
mA/µs
Chopping Frequency5
Power-Up Time2,4,5
Power-Up State4,6,7
fc
–
–
–
700
–
–
25
–
kHz
µs
–
ton
VCC ≥ VCC(min)
POS
ton < ton(max), VCC slew rate > 25 mV/µs
ICC(H)
1 VCC represents the generated voltage between the VCC pin and the GND pin.
2 The VCC slew rate must exceed 600 mV/ms from 0 to VCC(min). A slower slew rate through this range can affect device performance.
3 Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change.
4 Power-Up Time is measured with and without an external bypass capacitor of 0.01 µF, B < BRP – 10 G. Adding a larger bypass capacitor would cause longer Power-Up
Time.
5 Guaranteed by characterization and design.
6 Power-Up State as defined is true only with a VCC slew rate of 25 mV/µs or greater.
7 Power-Up State is defined during the power-on phase (t < tON) until the device has fully powered-on (tON), after which the output will correspond to the magnetic field level
seen by the sensor. For t > ton and BRP < B < BOP, Power-Up State is not defined.
MAGNETIC CHARACTERISTICS1: valid at TA = –40°C to 150°C; TJ < TJ(max); for LH and UA: CBYP = 0.01 µF; through oper-
ating supply voltage range; unless otherwise noted
Characteristics
Magnetic Operating Point
Magnetic Release Point
Hysteresis
Symbol
BOP
Test Conditions
Min.
5
Typ.
–
Max.
40
Unit2
G
BRP
–40
15
–
–5
G
BHYS
BOP – BRP
40
65
G
1Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore
greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
2 1 G (gauss) = 0.1 mT (millitesla).
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value Units
Package LH, 1-layer PCB with copper limited to solder pads
228
110
165
ºC/W
ºC/W
ºC/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side connected by
thermal vias
Package Thermal Resistance
RθJA
Package UA, 1-layer PCB with copper limited to solder pads
*Additional thermal information available on Allegro Web site.
Power Derating Curve
25
24
23
V
CC(max)
22
21
20
19
18
17
16
LH, 2-layer PCB
(RqJA = 110 ºC/W)
15
14
13
12
11
10
9
UA, 1-layer PCB
(RqJA = 165 ºC/W)
8
7
6
LH, 1-layer PCB
5
(RqJA = 228 ºC/W)
4
3
V
CC(min)
2
20
40
60
80
100
120
140
160
180
Temperature (ºC)
Maximum Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
CHARACTERISTIC PERFORMANCE
Average Supply Current (Low) vs. Temperature
Average Supply Current (Low) vs. Supply Voltage
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
3 V
-40°C
24 V
25°C
150°C
-50
0
50
100
150
200
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
Average Supply Current (High) vs. Supply Voltage
Average Supply Current (High) vs. Temperature
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
3 V
-40°C
24 V
25°C
150°C
-50
0
50
100
150
200
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
Average BOP vs. Temperature
Average BOP vs. Supply Voltage
40.0
35.0
30.0
25.0
20.0
15.0
10.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
3 V
-40°C
25°C
24 V
150°C
5.0
-50
0
50
100
150
200
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
Average BRP vs. Supply Voltage
Average BRP vs. Temperature
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40°C
25°C
3 V
24 V
150°C
-40.0
-50
0
50
100
150
200
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
Average BHYS vs. Supply Voltage
Average BHYS vs. Temperature
65.0
60.0
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
65.0
60.0
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
-40°C
25°C
3 V
24 V
150°C
15.0
-50
0
50
100
150
200
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
FUNCTIONAL DESCRIPTION
The A1245 output, ICC, switches high after the magnetic field
at the Hall sensor IC exceeds the operate point threshold, BOP
When the magnetic field is reduced to below the release point
threshold, BRP, the device output goes low. This is shown in
Figure 1.
The difference between the magnetic operate and release points
is called the hysteresis of the device, BHYS. This built-in hyster-
esis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
.
I+
ICC(H)
ICC(L)
0
B–
B+
BHYS
Figure 1: Hysteresis for the A1245
On the horizontal axis, the B+ direction indicates increasing south
polarity magnetic field strength, and the B– direction indicates
decreasing south polarity field strength (including the case of
increasing north polarity).
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
RSENSE
V+
V+
VCC
VCC
A1245
A1245
CBYP
CBYP
0.01 µF
0.01 µF
GND
GND
RSENSE
(A) Low Side Sensing
(B) High Side Sensing
LH and UA Packages
Figure 2: Typical Application Circuits
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. The chopper stabilization technique uses a 350 kHz
high frequency clock. For demodulation process, a sample and
hold technique is used, where the sampling is performed at twice
the chopper frequency. This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall out-
put voltages and precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sample-
and-hold circuits.
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
patented Allegro technique, namely Dynamic Quadrature Offset
Cancellation, removes key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
Regulator
Clock/Logic
Low-Pass
Filter
Hall Element
Amp
Figure 3: Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation)
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
Power Derating
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA and TA.
Example: Reliability for VCC at TA=150°C, package LH, using a
low-K PCB.
Observe the worst-case ratings for the device, specifically:
RθJA=110 °C/W, TJ(max) =165°C, VCC(max)= 24 V, and
ICC(max) = 17 mA.
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165°C–150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD(max) = ΔTmax ÷RθJA =15°C÷110 °C/W=136mW
Finally, invert equation 1 with respect to voltage:
V
CC(est) = PD(max) ÷ ICC(max)= 136mW÷17 mA= 8 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est)
PD = VIN
I
(1)
(2)
(3)
×
IN
ꢀ
ꢀ
ΔT = PD
R
θJA
×
.
TJ = TA + ΔT
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
and VCC(max) is reliable under these conditions.
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 9 mA, and RθJA = 110 °C/W, then:
PD = VCC
I
= 12 V 9 mA = 108 mW
CC
×
×
ΔT = PD
R
= 48 mW 110 °C/W = 11.9°C
θJA
×
×
TJ = TA + ΔT = 25°C + 11.9°C = 36.9°C
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
Package Outline Drawings
For Reference Only – Not for Tooling Use
(Reference DWG-2840)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98
–0.08
D
1.49
4° 4°
A
3
+0.020
0.180
–0.053
0.96
D
D
+0.19
–0.06
+0.10
1.91
2.40
2.90
–0.20
0.70
1.00
0.25 MIN
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Gauge Plane
Branded Face
PCB Layout Reference View
B
8X 10°
REF
1.00 0.13
+0.10
NNN
0.05
–0.05
0.95 BSC
0.40 0.10
C Standard Branding Reference View
N
= Last three digits of device part number
A
B
Active Area Depth, 0.28 mm
Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances
C
D
Branding scale and appearance at supplier discretion
Hall elements, not to scale
Figure 4: Package LH, 3-Pin SOT23W
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
For Reference Only – Not for Tooling Use
(Reference DWG-9013)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
45°
B
+0.08
–0.05
4.09
1.52 0.05
E
C
2.04
2 X 10°
1.44
E
E
Mold Ejector
Pin Indent
+0.08
–0.05
3.02
45°
Branded
Face
A
1.02 MAX
0.79 REF
1
2
3
+0.05
–0.07
+0.03
–0.06
0.43
0.41
1.27 NOM
NNN
14.99 0.25
1
D
Standard Branding Reference View
= Supplier emblem
N
= Last three digits of device part number
A
B
C
D
Dambar removal protrusion (6X)
Gate and tie bar burr area
Active Area Depth, 0.50 mm REF
Branding scale and appearance at supplier discretion
Hall element, not to scale
E
Figure 5: Package UA, 3-Pin SIP
Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two Wire
Hall-Effect Latch
A1245
Revision History
Revision
Date
December 17, 2014 Initial Release
July 13, 2015 Corrected LH package Active Area Depth value
Change
–
1
Copyright ©2013-15, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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