A1365LKTTN-5-T_技术文档

A1365

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

FEATURES AND BENEFITS

DESCRIPTION

• Proprietary segmented linear temperature compensation

(TC) technology provides a typical accuracy of 1% over

the full operating temperature range

The A1365 linear output Hall-effect sensor IC is specifically

designed to provide a highly accurate output with improved

resolution at high bandwidth for use in current-sensing

applications. This device employs a segmented, linearly

interpolated temperature compensation technology, which

provides greater accuracy in sensitivity and offset voltage

trimming and hence virtually zero temperature drift. This

improvementgreatlyreducesthetotalerrorofthedeviceacross

the operating temperature range.

• 120 kHz nominal bandwidth achieved via proprietary

packaging and chopper stabilization techniques

• Over Field Fault signal with 6-bit programmable trigger

levels, 2-bit programmable hysteresis, and latching or

non-latching behavior

• Over Field Fault response time < 4.5 μs (typ)

• Extremely low noise and high resolution achieved via

proprietary Hall element and low-noise amplifier circuits

• Customer-programmable, high-resolution offset and

sensitivity trim

The highly programmable Over Field Fault signal (FAULT

pin) can be used to detect a high magnetic field condition.

Broken ground wire detection, undervoltage lockout for V_CC

belowspecification,anduser-selectableoutputvoltageclamps

are also included, which are important for high reliability in

automotive applications. The sensor accuracy and diagnostic

capability make it ideally suited for automotive sockets such

as HEV inverter and DC-to-DC converter applications.

• Available in a 1-mm-thick SIP through-hole package

• Factory-programmed sensitivity and quiescent

output voltage TC with extremely stable temperature

performance

Continued on the next page…

The A1365 Hall-effect sensor IC is extremely sensitive, fast,

and temperature-stable. The accuracy and flexibility of this

device is enhanced by user programmability, performed via

the V_CCsupply and the output pins, which allows the device

to be optimized in the application.

PACKAGE:

4-Pin SIP (suffix KT)

ThisratiometricHall-effectsensorICprovidesavoltageoutput

thatisproportionaltotheappliedmagneticfield.Thequiescent

outputvoltageisuser-adjustablearound50%(bidirectional)of

Continued on the next page…

Not to scale

V +

(Programming)

VCC

Programming

Control

6-Bit Programmable Window Comparator

V_REF(High)

0.88 × V_CCto 0.72 × V_CC

COMP_IN

–

+

Internal

Pull-Up

6 bits

Temperature

Sensor

EEPROM and

Control Logic

FAULT

–

+

V_REF(Low)

C_BYPASS

Sensitivity Control

Offset Control

0.12 × V_CCto 0.28 × V_CC

VOUT

Signal Recovery

GND

(Programming)

Functional Block Diagram

A1365-GS-DS

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

FEATURES AND BENEFITS (CONTINUED)

DESCRIPTION (CONTINUED)

• Selectable sensitivity range between 0.6 and 14 mV/G through the supply voltage, V_CC. The device sensitivity is adjustable within

use of coarse sensitivity program bits

• Ratiometric sensitivity, quiescent voltage output, and

clamps enable simple interface with application A-to-D

converter (ADC)

• Output voltage clamps provide short-circuit diagnostic

capabilities

• Open-circuit detection on ground pin (broken wire)

• Undervoltage lockout for V_CCbelow specification

• Wide ambient temperature range: –40°C to 150°C

the range of 0.6 to 14 mV/G.

The A1365 incorporates a highly sensitive Hall element with a

BiCMOS interface integrated circuit that employs temperature-

compensation circuitry to reduce the intrinsic sensitivity and offset

driftoftheHallelement.TheICalsoincludesasmall-signalhigh-gain

amplifier, a clamped low-impedance output stage, and a proprietary

high-bandwidth dynamic offset cancellation technique.

Devicespecificationsapplyacrossanextendedambienttemperature

range: –40°C to 150°C. The A1365 sensor IC is provided in an

extremely thin case (1 mm thick), 4-pin SIP (single inline package,

suffix KT) that is lead (Pb) free, with 100% matte-tin leadframe

plating.Thethinpackageallowsforbettermagneticcouplingbecause

the smaller the air gap in the core is, the higher the coupling from

current to magnetic field will be.

Selection Guide

Sensitivity Range²

(mV/G)

Part Number

Package

Packing¹

A1365LKTTN-1-T

A1365LKTTN-2-T

A1365LKTTN-5-T

A1365LKTTN-10-T

4-pin SIP

4000 pieces per 13-in. reel

0.6 to 1.3

1.3 to 2.9

2.9 to 6.4

6.4 to 14

¹Contact Allegro for additional packing options.

²Allegro recommends against changing Coarse Sensitivity settings when programming devices that will be used in production.

Each A1365 has been factory temperature compensated at a speciﬁc sensitivity range, and changing the coarse bits setting could

cause sensitivity drift through temperature range (ΔSens_TC) to exceed speciﬁed limits.

Table of Contents

Specifications

Absolute Maximum Ratings

Thermal Characteristics

Pinout Diagram and Terminal List Table

Operating Characteristics

Characteristic Performance Data

Characteristic Definitions

Functional Description

Programming Sensitivity and Quiescent

Voltage Output

Coarse Sensitivity

Memory-Locking Mechanisms

Power-On Reset (POR) and Undervoltage

Lockout (UVLO) Operation

Detecting Broken Ground Wire

Over Magnet Field Fault

3

4

5

9

13

19

Programming Serial Interface

24

25

26

27

28

29

30

Transaction Types

Writing the Access Code

Writing to Volatile Memory

Writing to EEPROM

Reading from EEPROM or Volatile Memory

Error Checking

Serial Interface Reference

Serial Interface Message Structure

V_CCLevels During Manchester Communication

Shadow Mode

EEPROM Margining

EEPROM Cell Organization

EEPROM Error Checking and Correction (ECC) 30

Detecting ECC Error

19

20

21

22

30

31

Package Outline Drawing

Allegro MicroSystems, LLC

115 Northeast Cutoff

2

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

SPECIFICATIONS

Absolute Maximum Ratings

Characteristic

Symbol

V_CC

Notes

Rating

6

Unit

V

Forward Supply Voltage

Reverse Supply Voltage

Forward Output Voltage

Reverse Output Voltage

Forward Fault Voltage

Reverse Fault Voltage

Output Source Current

Output Sink Current

V_RCC

–0.1

25

V

V_OUT

V

V_ROUT

–0.1

6

V

V_{¯¯¯¯ ¯¯¯¯¯}

V

FA U LT

V_{RFA U LT}

¯¯¯¯ ¯¯¯¯¯

–0.1

2.8

10

V

I_OUT(source)

I_OUT(sink)

VOUT to GND

VCC to VOUT

mA

Maximum Number of EEPROM Write

Cycles

EEPROM_w(max)

100

cycles

Operating Ambient Temperature

Storage Temperature

T_A

T_stg

L temperature range

–40 to 150

–65 to 165

165

ºC

Maximum Junction Temperature

T_J(max)

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions*

Value

Unit

Package Thermal Resistance

R_θJA

On 1-layer PCB with exposed copper limited to solder pads

174

ºC/W

*Additional thermal information available on the Allegro website

Power Dissipation versus Ambient Temperature

900

800

700

600

500

400

300

200

(R

qJA

=

174

ºC/W)

100

0

20

40

60

80

100

120

140

160

180

Temperature, TA (°C)

Allegro MicroSystems, LLC

115 Northeast Cutoff

3

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Pinout Diagram and Terminal List Table

Terminal List Table

Number

Name

Function

Input Power Supply, use bypass capacitor to connect to ground;

also used for programming

1

VCC

2

3

4

VOUT

Output Signal, also used for programming

Over Field Fault Detection Flag

Ground

¯¯¯¯ ¯¯¯¯¯

FA U LT

GND

1

2 3 4

KT Package Pinout Diagram

(Ejector pin mark on opposite side)

Allegro MicroSystems, LLC

115 Northeast Cutoff

4

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

OPERATING CHARACTERISTICS: valid through the full operating temperature range T_A, C_BYPASS= 0.1 µF, and V_CC= 5 V,

unless otherwise speciﬁed

Characteristic

Electrical Characteristics

Supply Voltage

Symbol

Test Conditions

Min.

Typ.

Max.

Unit¹

V_CC

I_CC

t_PO

t_TC

4.5

–

5

5.5

15

V

¯¯¯¯ ¯¯¯¯¯

No load on VOUT, FA U LT pin in high-

Supply Current

impedance state, connected through a 10 kΩ

resistor to VCC

10

mA

Power-On Time²

T_A= 25°C, C_BYPASS= open, C_L= 1 nF

–

100

90

–

µs

Temperature Compensation

Power-On Time²

V_UVLOH

V_UVLOL

V_CCrising and device function enabled

V_CCfalling and device function disabled

–

4

4.3

–

V

Undervoltage Lockout (UVLO)

Threshold²

3.05

3.2

T_A= 25°C, C_BYPASS= open, C_L= 1 nF,

V_CCfall time (5 V to 3 V) = 1.5 μs

t_UVLOE

t_UVLOD

–

67

6

–

µs

UVLO Enable/Disable Delay Time²

T_A= 25°C, C_BYPASS= open, C_L= 1 nF,

V_CCrecover time (3 V to 5 V) = 1.5 μs

V_PORH

V_PORL

t_PORR

V_z

T_A= 25°C, V_CCrising

T_A= 25°C, V_CCfalling

T_A= 25°C, V_CCrising

T_A= 25°C, I_CC= 30 mA

Small signal –3 dB, C_L= 1 nF, T_A= 25°C

T_A= 25°C

–

2.9

2.5

85

–

V

Power-On Reset Voltage²

Power-On Reset Release Time²

Supply Zener Clamp Voltage

Internal Bandwidth

–

µs

V

6.5

–

7.5

120

500

BW_i

f_C

kHz

Chopping Frequency³

–

V

_OUTCharacteristics

T_A= 25°C, step magnetic field of 400 G,

C_L= 1 nF, Sens = 2 mV/G

Propagation Delay Time²

Rise Time²

t_pd

t_r

t_RESPONSE

t_CLP

–

2.2

3.6

3.7

10

–

µs

T_A= 25°C, step magnetic field of 400 G,

C_L= 1 nF, Sens = 2 mV/G

T_A= 25°C, step magnetic field of 400 G,

C_L= 1 nF, Sens = 2 mV/G

Response Time²

Delay to Clamp^2,4

T_A= 25°C, step magnetic field from 160 to

240 G, C_L= 1 nF, Sens = 10 mV/G

V_CLP(HIGH)T_A= 25°C, R_L(PULLDWN)= 10 kΩ to GND

4.55

0.15

4.8

–

4.85

0.45

–

V

Output Voltage Clamp⁵

Output Saturation Voltage²

Broken Wire Voltage²

V_CLP(LOW)

V_SAT(HIGH)

V_SAT(LOW)

T_A= 25°C, R_L(PULLUP)= 10 kΩ to VCC

T_A= 25°C, R_L(PULLDWN)= 10 kΩ to GND

T_A= 25°C, R_L(PULLDWN)= 10 kΩ to VCC

V

–

300

–

mV

V_BRK(HIGH)T_A= 25°C, R_L(PULLUP)= 10 kΩ to VCC

–

V_CC

200

1.1

V

V_BRK(LOW)

T_A= 25°C, R_L(PULLDWN)= 10 kΩ to GND

T_A= 25°C, CL = 1 nF

–

mV

mG/√(Hz)

–

T_A= 25°C, CL = 1 nF, Sens = 2 mV/G,

bandwidth = BW_i

–

6.3

1

mV_p-p

–

Noise⁶

V_N

T_A= 25°C, CL = 1 nF, Sens = 2 mV/G,

bandwidth = BW_i

mV_RMS

–

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

5

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range T_A, C_BYPASS= 0.1 µF,

and V_CC= 5 V, unless otherwise speciﬁed

Characteristic

V_OUTCharacteristics (continued)

DC Output Resistance

Symbol

Test Conditions

Min.

Typ.

Max.

Unit¹

R_OUT

T_A= 25°C

–

< 10

–

Ω

R_L(PULLUP)VOUT to VCC

R_L(PULLDWN)VOUT to GND

4.7

–

1

kΩ

nF

Output Load Resistance

–

Output Load Capacitance⁷

Output Slew Rate⁸

C_L

VOUT to GND

10

Sens = 2 mV/G, C_L= 1 nF, T_A= 25°C;

step magnetic field of 400 G

SR

–

230

–

V/ms

Over Field Fault Characteristics

Fault Switchpoint Programming Bits

FAULT_

THRESH

–

6

–

bit

V

Positive Field Fault Switchpoint

Range⁹

T_A= 25°C, programmable using FAULT_

THRESH bits

V_FPSP

V_FNSP

0.72 × V_CC

0.12 × V_CC

0.88 × V_CC

0.28 × V_CC

Negative Field Fault Switchpoint

Range⁹

T_A= 25°C, programmable using FAULT_

THRESH bits

V

T_A= 25°C, Average Fault Switchpoint step

size, V_CC= 5 V

Fault Switchpoint Step Size

Step_FAULT

–

16

2

–

mV

bit

Fault Hysteresis Programming Bits

FAULT_HYST

T_A= 25°C, FAULT_HYST = 0 (decimal),

FAULT_THRESH = 0, no hysteresis

0

mV

T_A= 25°C, FAULT_HYST = 1 (decimal),

FAULT_THRESH = 0, V_CC= 5 V

–

30

60

–

mV

Fault Hysteresis Level Range⁹

V_FHYST

T_A= 25°C, FAULT_HYST = 2 (decimal),

FAULT_THRESH = 0, V_CC= 5 V

T_A= 25°C, FAULT_HYST = 3 (decimal),

FAULT_THRESH = 0, maximum hysteresis

value, V_CC= 5 V

–

120

1

–

mV

bit

FAULT_

LATCH

Enable Latched Fault Bit

DC Fault Switchpoint Error

FAULT_THRESH = 0 (decimal), R_F(PULLUP)

=

¯¯¯¯ ¯¯¯¯¯

Err_DFS

10 kΩ from FA U LT to VCC; measured under

DC conditions, V_FHYST= 60 mV

±40

mV

FAULT_THRESH = 0 (decimal), R_F(PULLUP)

=

¯¯¯¯ ¯¯¯¯¯

DC Fault Switchpoint Symmetry Error

Err_DFSS

10 kΩ from FA U LT to VCC; measured under

–

±60

–

mV

V

DC conditions, V_FHYST= 60 mV

¯¯¯¯ ¯¯¯¯¯

R_F(PULLUP)= 10 kΩ from FA U LT to VCC

FA U LT Pin Low Output Voltage

V_{¯¯¯¯ ¯¯¯¯¯}

0.3

FA U LTL

¯¯¯¯ ¯¯¯¯¯

R_F(PULLUP)= 10 kΩ from FA U LT to VCC,

C_F= Open, FAULT_THRESH = 0, VOUT

step from V_OUT(Q)to V_OUT= 1.3 × (V_FPSP

V_OUT(Q)) + V_OUT(Q)

Transient Fault Response Time¹⁰

Transient Fault Release Time

Continued on the next page…

t_TFR

–

4.5

2.5

–

µs

-

¯¯¯¯ ¯¯¯¯¯

R_F(PULLUP)= 10 kΩ from FA U LT to VCC,

C_F= Open, FAULT_THRESH = 0, V_FHYST

0 mV, VOUT step from VOUT = 1.1 × (V_FPSP

- V_OUT(Q)) + V_OUT(Q)

=

t_TFRL

Allegro MicroSystems, LLC

115 Northeast Cutoff

6

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, T_A, C_BYPASS= 0.1 µF,

and V_CC= 5 V, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit¹

Fault Characteristics (continued)

Fault Delay Due to Load Capacitance

External Pull-Up Supply Voltage

¯¯¯¯ ¯¯¯¯¯

t_FDC

R_F(PULLUP)= 10 kΩ from FA U LT to VCC

–

1.65

4.7

–

0.5

V_CC

–

V_CC

–

µs/nF

V

V_F(PULLUP)

R_F(PULLUP)

C_F

¯¯¯¯ ¯¯¯¯¯

External FA U LT Pull-Up Resistor

kΩ

¯¯¯¯ ¯¯¯¯¯

External FA U LT Capacitance

–

10

–

nF

¯¯¯¯ ¯¯¯¯¯

Internal FA U LT Pull-Up Resistor

R_IF(PULLUP)

I_IF(PULLUP)

–

10

40

kΩ

¯¯¯¯ ¯¯¯¯¯

Internal FA U LT Pull-Up Current

–

µA

2

Quiescent Voltage Output (V_OUT(Q)

)

Initial Unprogrammed Quiescent

Voltage Output^2,11

V_OUT(Q)init

V_OUT(Q)PR

QVO

T_A= 25°C

2.4

2.3

–

2.5

–

2.6

2.7

–

V

Quiescent Voltage Output

Programming Range^2,5,12

Quiescent Voltage Output

Programming Bits¹³

9

bit

mV

Average Quiescent Voltage Output

Programming Step Size^2,14,15

Step_VOUT(Q)T_A= 25°C

Err_PGVOUT(Q)T_A= 25°C

1.9

–

2.3

2.8

–

Quiescent Voltage Output

Programming Resolution^2,16

±0.5 ×

Step_VOUT(Q)

Sensitivity (Sens)²

SENS_COARSE = 00, T_A= 25°C

–

1

2.2

4.7

9.6

–

mV/G

SENS_COARSE = 01, T_A= 25°C

SENS_COARSE = 10, T_A= 25°C

SENS_COARSE = 11, T_A= 25°C

SENS_COARSE = 00, T_A= 25°C

SENS_COARSE = 01, T_A= 25°C

SENS_COARSE = 10, T_A= 25°C

SENS_COARSE = 11, T_A= 25°C

Initial Unprogrammed Sensitivity¹¹

Sens_init

–

0.6

1.3

2.9

6.4

1.3

2.9

6.4

14

–

Sensitivity Programming Range^5,12

Sens_PR

–

Coarse Sensitivity Programming

Bits¹⁷

SENS_

COARSE

–

2

–

bit

Fine Sensitivity Programming Bits¹³

SENS_FINE

–

2.4

5

9

–

bit

SENS_COARSE = 00, T_A= 25°C

SENS_COARSE = 01, T_A= 25°C

SENS_COARSE = 10, T_A= 25°C

SENS_COARSE = 11, T_A= 25°C

3.2

6.6

14.2

29

4.1

8.5

18

38

µV/G

Average Fine Sensitivity and

Temperature Compensation

Programming Step Size^2,14,15

Step_SENS

11

22

Sensitivity Programming

Resolution^2,16

±0.5 ×

Step_SENS

Err_PGSENST_A= 25°C

–

µV/G

Factory-Programmed Sensitivity Temperature Coefﬁcient

T_A=150°C,T_A= –40°C,calculated relative to

25°C

Sensitivity Temperature Coefficient²

TC_SENS

–

0

–

%/°C

T_A= 25°C to 150°C

T_A= –40°C to 25°C

–2.5

–3

–

2.5

3

%

Sensitivity Drift Through Temperature

Range^2,12,18,23

ΔSens_TC

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

7

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, T_A, C_BYPASS= 0.1 µF,

and V_CC= 5 V, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit¹

Factory-Programmed Quiescent Voltage Output Temperature Coefﬁcient

Quiescent Voltage Output

Temperature Coefficient²

T_A= 150°C, T_A= –40°C, calculated relative

to 25°C

TC_QVO

–

0

–

mV/°C

mV

SENS_COARSE = 00, SENS_COARSE = 01,

or SENS_COARSE = 10, T_A= 25°C to 150°C

–10

10

Quiescent Voltage Output Drift

Through Temperature Range^2,12,18

ΔV_OUT(Q)TC

SENS_COARSE = 11, T_A= 25°C to 150°C

–15

–30

–

15

30

mV

T_A= –40°C to 25°C

Average Quiescent Voltage

Output Temperature Compensation

Step Size

Step_QVOTC

EELOCK

–

2.3

1

–

mV

bit

Lock Bit Programming

EEPROM Lock Bit

Error Components

Linearity Sensitivity Error^2,19

Symmetry Sensitivity Error²

Lin_ERR

–1

< ±0.25

1

%

Sym_ERR

–0.5

0.5

Ratiometry Quiescent Voltage Output

Error^2,20

Rat_ERRVOUT(Q)Relative to V_CC= 5 V ±5%

–0.3

0

0.3

%

Ratiometry Sensitivity Error^2,20

Ratiometry Clamp Error^2,21

Rat_ERRSensRelative to V_CC= 5 V ±5%

–1

–

< ±0.5

< ±1

1

–

%

Rat_ERRCLPT_A= 25ºC, Relative to V_CC= 5 V ±5%

Sensitivity Drift Due to Package

Hysteresis²

T_A= 25°C, after temperature cycling, 25°C to

150°C and back to 25°C

-1.25

±1.25

ΔSens_PKG

–

%

T_A= 25°C, shift after AEC Q100 grade 0

qualification testing

Sensitivity Drift Over Lifetime²²

ΔSens_LIFE

±1%

¹1 G (gauss) = 0.1 mT (millitesla).

²See Characteristic Deﬁnitions section.

³f_Cvaries up to approximately ±5% over the full operating ambient temperature range, T_A.

⁴If the programmed Fault Switchpoint exceeds the clamp voltage, Fault operation will have priority over clamp operation.

⁵Sens, V_OUT(Q), V_CLP(LOW), and V_CLP(HIGH)scale with V_CCdue to ratiometry.

⁶Noise, measured in mV_PPand in mV_RMS, is dependent on the sensitivity of the device.

⁷Output stability is maintained for capacitive loads as large as 10 nF.

⁸High-to-low transition of output voltage is a function of external load components and device sensitivity.

⁹Fault Switchpoint and Fault Hysteresis are ratiometric.

¹⁰Refer to Fault Characteristics section for the impact of load circuit and different Fault switchpoint settings on Transient Fault

Response Time.

¹¹Raw device characteristic values before any programming.

¹²Exceeding the speciﬁed ranges will cause sensitivity and Quiescent Voltage Output drift through the temperature range to deteriorate beyond the speciﬁed values.

¹³Refer to Functional Description section.

¹⁴Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Deﬁnitions section.

¹⁵Non-ideal behavior in the programming DAC can cause the step size at each signiﬁcant bit rollover code to be greater than twice the maximum speciﬁed value of

Step_VOUT(Q)or Step_SENS

.

¹⁶Overall programming value accuracy. See Characteristic Deﬁnitions section.

¹⁷Each A1365 part number is factory-programmed and temperature compensated at a different coarse sensitivity setting. Changing coarse bits setting could cause sensitiv-

ity drift through temperature range ,ΔSens_TC, to exceed speciﬁed limits.

¹⁸Allegro will be testing and temperature compensating each device at 150°C. Allegro will not be testing devices at –40°C. Temperature compensation codes will be applied

based on characterization data.

¹⁹Linearity applies to output voltage ranges of ±2 V from the quiescent output for bidirectional devices.

²⁰Percent change from actual value at V_CC= 5 V, for a given temperature, through the supply voltage operating range.

²¹Percent change from actual value at V_CC= 5 V, T_A= 25°C, through the supply voltage operating range.

²²Based on characterization data obtained during standardized stress test for Qualiﬁcation of Integrated Circuits. Cannot be guaranteed. Drift is a function of customer ap-

plication conditions. Contact Allegro MicroSystems for further information.

²³Includes sensitivity drift due to package hysteresis after exposing the sensor to a temperature of 150ºC for 60 seconds during test.

Allegro MicroSystems, LLC

115 Northeast Cutoff

8

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

CHARACTERISTIC PERFORMANCE DATA

Response Time (t_RESPONSE

)

400 G Excitation Signal with 10% - 90% rise time = 1 µs

Sensitivity = 2 mV/G, C_BYPASS= 0.1 µF, C_L= 1 nF

Output (V_OUT, mV)

Input = 400 G Excitation Signal

80% of Input

80% of Output

t_RESPONSE= 3.64 µs

C1

FLT DC1M C1

1.00 V/div

-3.0100 V

3.0681 V

FLT DC1M

Trigger

C1 DC

830 mV

Positive

Timebase -6.96 µs

200 mV/div

-3.10600 V

2.49230 V

3.13220 V

2.00 µs/div Stop

2.5 GS/s Edge

DX =

3.6444 µs

50.0 ks

X1 =

467.6 ns

X2 = 4.1120 µs 1/DX = 274.390 kHz

11/6/2013 10:23:51 AM

3.8212 V

Propagation Delay (t_PD

)

400 G Excitation Signal with 10% - 90% rise time = 1 µs

Sensitivity = 2 mV/G, C_BYPASS= 0.1 µF, C_L= 1 nF

Output (V_OUT, mV)

Input = 400 G Excitation Signal

t_PD= 2.1 µs

20% of Output

20% of Input

C1

FLT DC1M C2

1.00 V/div

-3.0100 V

767.5 V

FLT DC1M

200 mV/div

-3.10600 V

2.50227 V

2.65287 V

Trigger

C1 DC

830 mV

Timebase -6.96 µs

2.00 µs/div Stop

50.0 ks

2.5 GS/s Edge

DX =

Positive

X1 =

-33.2 ns

2.0216 µs

X2 = 1.9884 µs 1/DX = 494.66 kHz

3.7877 V

11/6/2013 10:22:47 AM

Allegro MicroSystems, LLC

115 Northeast Cutoff

9

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Rise Time (t_r)

400 G Excitation Signal with 10% - 90% rise time = 1 µs

Sensitivity = 2 mV/G, C_BYPASS= 0.1 µF, C_L= 1 nF

Output (V_OUT, mV)

Input = 400 G Excitation Signal

90% of Output

t_R= 3.15 µs

10% of Input

C1

FLT DC1M C2

FLT DC1M

200 mV/div

-3.10600 V

2.57280 V

3.21215 V

Trigger

C1 DC

830 mV

Timebase -6.96 µs

1.00 V/div

-3.0100 V

3.7602 V

3.8268 V

2.00 µs/div Stop

50.0 ks

2.5 GS/s Edge

Positive

DX =

X2 = 4.7764 µs 1/DX = 317.99 kHz

X1 = 1.6316 µs

3.1448 µs

11/6/2013 10:21:02 AM

Power-On Time (t_PO

)

400 G Constant Excitation Signal with V_CC10% - 90% rise time = 1 µs

Sensitivity = 2 mV/G, C_BYPASS= Open, C_L= 1 nF

Supply (V_CC, V)

V_CC(min)

Output (V_OUT, V)

90% of Output

t_PO= 97 µs

Trigger

50.0 µs/div Stop

C1 DC

3.13 V

Positive

F BwL DC1M

C2

C1

Timebase -120 µs

1.00 V/div

-3.0000 V

4.5241 V

4.9957 V

1.00 V/div

-3.0000 V

63.4 mV

3.0335 V

2.9701 V

10.0 ks

20 MS/s Edge

DX =

96.75 µs

X1 =

1.05 µs

X2 = 97.80 µs 1/DX = 10.336 kHz

Dy

471.6 mV Dy

Allegro MicroSystems, LLC

115 Northeast Cutoff

10

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Temperature Compensation Power-On Time (t_TC

)

400G Constant Excitation Signal, with V_CC10%-90% rise time = 1.5 μs

Sensitivity = 2mV/G, C_BYPASS= Open, C_L= 1 nF

Supply (V_CC, V)

Output (V_OUT, V)

90% of Temperature

Compensated Output

90% of Output

t_TC= 89 µs

Trigger

50.0 µs/div Stop

C1 DC

3.13 V

Positive

F BwL DC1M

C2

C1

Timebase -120 µs

1.00 V/div

-3.0000 V

4.9957 V

5.0019 V

1.00 V/div

-3.0000 V

3.0335 V

3.4127 V

379.2 mV

10.0 ks

20 MS/s Edge

DX =

X2 = 186.25 µs 1/DX = 11.306 kHz

X1 = 97.80 µs

88.45 µs

Dy

6.2 mV Dy

UVLO Enable Time (t_UVLOE

)

VCC 5 V - 3 V fall time = 1.5 µs

Sensitivity = 2 mV/G, C_BYPASS= Open, C_L= 1 nF

Supply (V_CC, V)

t_UVLOE= 67 µs

V_UVLOL

Output (V_OUT, V)

Output = 0 V

Trigger

20.0 µs/div Stop

C1 DC

F BwL DC1M

C2

C1

Tbase -2.5628 ms

3.54 V

1.00 V/div

-3.0000 V

3.5134 V

3.0227 V

1.00 V/div

-3.0000 V

2.6689 V

12.7 mV

10.0 ks

Positive

50 MS/s Edge

DX =

X1 = 2.50062 ms

X2 = 2.56728 ms 1/DX = 15.002 kHz

66.66 µs

Dy

-490.6 mV Dy

-2.6561 V

Allegro MicroSystems, LLC

115 Northeast Cutoff

11

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

UVLO Disable Time (t_UVLOD

)

VCC 3.2 V - 5 V Recovery Time = 1.5 µs

Sensitivity = 2 mV/G, C_BYPASS= Open, C_L= 1 nF

Supply (V_CC, V)

V_CC(min)

t_UVLOD= 6 µs

Output (V_OUT, V)

90% of Output

Trigger

C1 DC

3.54 V

Positive

A

F

B DC1M

A F B DC1M

C1

C2

Timebase

-6.4 µs

5.00 µs/div Stop

200 MS/s Edge

1.00 V/div

-3.0000 V

539 #

4.5048 V

5.0297 V

524.9 mV

1.00 V/div

-3.0000 V

539 #

92.6 mV

2.2821 V

2.1895 V

10.0 ks

DX =

6.000 µs

1/DX = 166.7 kHz

X1 = -2.285 µs

X2 = 3.715 µs

Dy

Allegro MicroSystems, LLC

115 Northeast Cutoff

12

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

CHARACTERISTIC DEFINITIONS

Power-On Time (t_PO)

V

V_CC

V_CC(typ)

90% V_OUT

When the supply is ramped to its operating voltage, the device

requires a finite time to power its internal components before

responding to an input magnetic field.

V_OUT

Power-On Time (t_PO) is defined as: the time it takes for the

output voltage to settle within ±10% of its steady-state value

under an applied magnetic field, after the power supply has

reached its minimum specified operating voltage (V_CC(min)) as

shown in Figure 1.

V_CC(min)

t_PO

t₁

t₂

t₁= time at which power supply reaches

minimum specified operating voltage

Temperature Compensation Power-On Time

(t_TC)

t₂= time at which output voltage settles

within ±10% of its steady-state value

under an applied magnetic field

After Power-On Time (t_PO) elapses, t_TCis also required before a

valid temperature compensated output.

0

+t

Propagation Delay (t_pd)

Figure 1: Power-On Time Deﬁnition

The time interval between a) when the applied magnetic field

reaches 20% of its final value, and b) when the output reaches

20% of its final value (see Figure 2).

Applied Magnetic Field

(%)

90

Rise Time (t_r)

Transducer Output

The time interval between a) when the sensor IC reaches 10% of

its final value, and b) when it reaches 90% of its final value (see

Figure 2). Both t_rand t_RESPONSEare detrimentally affected by

eddy current losses observed in the conductive IC ground plane.

Rise Time, t

r

20

10

0

Response Time (t_RESPONSE

)

The time interval between a) when the applied magnetic field

reaches 80% of its final value, and b) when the sensor reaches

80% of its output corresponding to the applied magnetic field

(see Figure 3).

t

Propagation Delay, t

pd

Figure 2: Propagation Delay and Rise Time Deﬁnitions

Delay to Clamp (t_CLP

)

Applied Magnetic Field

(%)

80

A large magnetic input step may cause the clamp to overshoot

its steady-state value. The Delay to Clamp (t_CLP) is defined

as: the time it takes for the output voltage to settle within

steady-state clamp voltage ±1% of Clamp Voltage Dynamic

Range, after initially passing through its steady-state voltage, as

shown in Figure 4. Clamp Voltage Dynamic Range is defined as

Transducer Output

Response Time, t

RESPONSE

V_{CLP(HIGH)(min)}– V_{CLP(LOW)(max)}

.

0

t

Figure 3: Response Time Deﬁnition

Allegro MicroSystems, LLC

115 Northeast Cutoff

13

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Quiescent Voltage Output (V_OUT(Q)

)

V_{OUT(Q)maxcode}– V_{OUT(Q)mincode}

(1)

,

Step_VOUT(Q)

=

In the quiescent state (no significant magnetic field: B = 0 G),

the output (V_OUT(Q)) has a constant ratio to the supply voltage

(V_CC) throughout the entire operating ranges of V_CCand ambient

temperature (T_A).

2ⁿ– 1

where n is the number of available programming bits in the trim range,

9 bits, V_{OUT(Q)maxcode}is at decimal code 255, and V_{OUT(Q)mincode}is at

decimal code 256.

Initial Unprogrammed Quiescent Voltage

Output (V_OUT(Q)init

)

Quiescent Voltage Output Programming

Resolution (Err_PGVOUT(Q)

)

Before any programming, the Quiescent Voltage Output

(V_OUT(Q)) has a nominal value of V_CC/2, as shown in Figure 5.

The programming resolution for any device is half of its pro-

gramming step size. Therefore, the typical programming resolu-

tion will be:

Quiescent Voltage Output Programming

Range (V_OUT(Q)PR

)

The Quiescent Voltage Output (V_OUT(Q)) can be programmed

within the Quiescent Voltage Output Range limits: V_{OUT(Q)PR(min)}

and V_{OUT(Q)PR(max)}. Exceeding the specified Quiescent Voltage

Output Range will cause Quiescent Voltage Output Drift Through

Temperature Range ΔV_OUT(Q)TCto deteriorate beyond the speci-

fied values, as shown in Figure 5.

Err_PGVOUT(Q)(typ) = 0.5 × Step_VOUT(Q)(typ)

(2)

Quiescent Voltage Output Temperature Coef-

ficient (TC_QVO

)

Device V_OUT(Q)changes as temperature changes, with respect to

its programmed Quiescent Voltage Output Temperature Coeffi-

cient, TC_QVO. TC_QVOis programmed at 150°C and is calculated

relative to the nominal V_OUT(Q)programming temperature of

25°C. TC_QVO(mV/°C) is defined as:

Average Quiescent Voltage Output Program-

ming Step Size (Step_VOUT(Q)

)

The Average Quiescent Voltage Output Progamming Step Size

(Step_VOUT(Q)) is determined using the following calculation:

TC_QVO= [V_OUT(Q)T2– V_OUT(Q)T1][1/(T2 – T1)]

(3)

where T1 is the nominal V_OUT(Q)programming temperature of

25°C, and T2 is the TC_QVOprogramming temperature of 150°C.

The expected V_OUT(Q)through the full ambient temperature range

(V_{OUT(Q)EXPECTED(TA)}) is defined as:

Magnetic Input

V_OUT

V

V_CLP(HIGH)

t_CLP

t₁

t₂

V_{OUT(Q)EXPECTED}(T_A) = V_OUT(Q)T1+ TC_QVO(T_A– T1)

(4)

t₁= time at which output voltage initially

reaches steady-state clamp voltage

V_OUT(Q)PR(max)

value

V_OUT(Q)PR(min)

value

V_OUT(Q)

t₂= time at which output voltage settles to

steady-state clamp voltage ±1% of the

clamp voltage dynamic range, where

clamp voltage dynamic range =

Programming range

(specified limits)

V_CLP(HIGH)(min) – V_CLP(LOW)(max)

Note: Times apply to both high clamp

(shown) and low clamp.

Distribution of values

resulting from maximum

programming code

(QVO programming bits

set to decimal code 255)

Typical initial value before

customer programming

V_OUT(Q)init

(QVO programming

bits set to code 0)

resulting from minimum

programming code

(QVO programming bits

set to decimal code 256)

0

t

Figure 4: Delay to Clamp Deﬁnition

Figure 5: Quiescent Voltage Output Range Deﬁnition

Allegro MicroSystems, LLC

115 Northeast Cutoff

14

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

V_{OUT(Q)EXPECTED(TA)}should be calculated using the actual

measured values of V_OUT(Q)T1and TC_QVOrather than program-

ming target values.

Initial Unprogrammed Sensitivity (Sens_init

)

Before any programming, Sensitivity has a nominal value that

depends on the SENS_COARSE bits setting. Each A1365 variant

has a different SENS_COARSE setting.

Quiescent Voltage Output Drift Through Tem-

perature Range (ΔV_OUT(Q)TC

)

Sensitivity Programming Range (Sens_PR)

Due to internal component tolerances and thermal considerations,

the Quiescent Voltage Output (V_OUT(Q)) may drift from its

nominal value through the operating ambient temperature (T_A).

The Quiescent Voltage Output Drift Through Temperature Range

(Δ_VOUT(Q)TC) is defined as:

The magnetic sensitivity (Sens) can be programmed around its

initial value within the sensitivity range limits: Sens_PR(min) and

Sens_PR(max). Exceeding the specified Sensitivity Range will

cause Sensitivity Drift Through Temperature Range ΔSens_TCto

deteriorate beyond the specified values. Refer to the Quiescent

Voltage Output Range section for a conceptual explanation of

how value distributions and ranges are related.

D_VOUT(Q)TC= V_OUT(Q)(TA)– V_{OUT(Q)EXPECTED(TA)}

(5)

∆V_OUT(Q)TCshould be calculated using the actual measured

Average Fine Sensitivity Programming Step

values of ∆V_OUT(Q)(TA)and ∆V_{OUT(Q)EXPECTED(TA)}rather than

programming target values.

Size (Step_SENS

)

Refer to the Average Quiescent Voltage Output Programming

Step Size section for a conceptual explanation.

Sensitivity (Sens)

The presence of a south polarity magnetic field, perpendicular

to the branded surface of the package face, increases the output

voltage from its quiescent value toward the supply voltage rail.

The amount of the output voltage increase is proportional to the

magnitude of the magnetic field applied.

Sensitivity Programming Resolution (Err_PGSENS

)

Refer to the Quiescent Voltage Output Programming Resolution

section for a conceptual explanation.

Sensitivity Temperature Coefficient (TC_SENS

)

Conversely, the application of a north polarity field decreases the

output voltage from its quiescent value. This proportionality is

specified as the magnetic sensitivity, Sens (mv/G), of the device,

and it is defined as:

Device sensitivity changes as temperature changes, with respect

to its programmed sensitivity temperature coefficient, TC_SENS

TC_SENSis programmed at 150°C, and calculated relative to the

nominal sensitivity programming temperature of 25°C. TC_SENS

(%/°C) is defined as:

.

V_OUT(BPOS)– V_OUT(BNEG)

Sens =

,

(6)

BPOS – BNEG

Sens_T2– Sens

Sens_T1

1

TC_SENS

=

^T1× 100%

,

(7)

T2–T1

where BPOS and BNEG are two magnetic fields with opposite

polarities.

where T1 is the nominal Sens programming temperature of 25°C,

and T2 is the TC_SENSprogramming temperature of 150°C. The

expected value of Sens over the full ambient temperature range,

Sens_EXPECTED(TA), is defined as:

Branded

Face

Mold Ejector

Pin Indent

TC_SENS(T –T1)

A

Sens_EXPECTED(TA)= Sens_T1× 100% +

(8)

100

Magnetic Flux

Direction Causing the

Output to Increase

Sens_EXPECTED(TA)should be calculated using the actual measured

values of Sens_T1rather than programming target values.

Figure 6: Magnetic Flux Polarity

Allegro MicroSystems, LLC

115 Northeast Cutoff

15

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

and BPOSx and BNEGx are positive and negative magnetic

fields, with respect to the quiescent voltage output such that

|BPOS2| = 2 × |BPOS1| and |BNEG2| = 2 × |BNEG1|.

Sensitivity Drift Through Temperature Range

(ΔSens_TC

)

Second-order-sensitivity temperature-coefficient effects cause the

magnetic sensitivity, Sens, to drift from its expected value over

the operating ambient temperature range (T_A). The Sensitivity

Drift Through Temperature Range (∆Sens_TC) is defined as:

Then:

Lin_ERRmax(Lin_ERRPOS, Lin_ERRNEG

)

.

=

(13)

Symmetry Sensitivity Error (Sym_ERR

)

Sens_TA– Sens_EXPECTED(TA)

∆Sens_TC

.

100%

=

×

The magnetic sensitivity of an A1365 device is constant for any

two applied magnetic fields of equal magnitude and opposite

polarities. Symmetry Error, Sym_ERR(%), is measured and

defined as:

(9)

Sens_EXPECTED(TA)

Sensitivity Drift Due to Package Hysteresis

(ΔSens_PKG

)

Package stress and relaxation can cause the device sensitivity at

T_A= 25°C to change during and after temperature cycling. The

sensitivity drift due to package hysteresis (∆Sens_PKG) is defined

as:



Sens_BPOS

Sens_BNEG







1–

Sym_ERR

,

100%

=

×

(14)







where Sens_Bxis as defined in equation 12, and BPOSx and

BNEGx are positive and negative magnetic fields such that

|BPOSx| = |BNEGx|.

Sens_(25°C)2– Sens_(25°C)1

,

100%

∆Sens_PKG

=

×

(10)

Sens_(25°C)1

Ratiometry Error (Rat_ERR

)

where Sens_(25°C)1is the programmed value of sensitivity at T_A= 25°C,

and Sens_(25°C)2is the value of sensitivity at T_A= 25°C, after tempera-

ture cycling T_Aup to 150°C and back to 25°C.

The A1365 device features ratiometric output. This means that

the Quiescent Voltage Output (V_OUT(Q)) magnetic sensitivity,

Sens, and Output Voltage Clamp (V_CLP(HIGH)and V_CLP(LOW)) are

proportional to the Supply Voltage (V_CC). In other words, when

the supply voltage increases or decreases by a certain percent-

age, each characteristic also increases or decreases by the same

percentage. Error is the difference between the measured change

in the supply voltage relative to 5 V, and the measured change in

each characteristic.

Linearity Sensitivity Error (Lin_ERR

)

The A1365 is designed to provide a linear output in response to

a ramping applied magnetic field. Consider two magnetic fields,

B1 and B2. Ideally, the sensitivity of a device is the same for both

fields, for a given supply voltage and temperature. Linearity error

is present when there is a difference between the sensitivities

measured at B1 and B2.

The ratiometric error in Quiescent Voltage Output,

Rat_ERRVOUT(Q)(%), for a given supply voltage (V_CC) is defined

as:

Linearity Error

Linearity error is calculated separately for the positive

(Lin_ERRPOS) and negative (Lin_ERRNEG) applied magnetic fields.

Linearity Error (%) is measured and defined as:



V_OUT(Q)(VCC)/ V





^OUT(Q)(5V)

1–

Rat_ERRVOUT(Q)

=

100%

×

(15)





V_CC/ 5 V











Sens



The ratiometric error in magnetic sensitivity, Rat_ERRSens(%), for

a given Supply Voltage (V_CC) is defined as:



^BPOS2

1–

Lin_ERRPOS

,

=

100%

×



Sens_BPOS1





Sens_(VCC)/ Sens

V_CC/ 5 V



Sens









^(5V)



^BNEG2

=

(11)

(12)

1–

Rat_ERRSens

.

100%

1–

Lin_ERRNEG

×

(16)





Sens

^BNEG1







The ratiometric error in the clamp voltages, Rat_ERRCLP(%), for a

given supply voltage (V_CC) is defined as:

where:

|V_OUT(Bx)

V

|

–

OUT(Q)

Sens_Bx

,

=

B_x

Allegro MicroSystems, LLC

115 Northeast Cutoff

16

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

or to V_BRK(LOW)if a load resistor is connected to GND.



V_CLP(VCC)/ V





^CLP(5V)

1–

Rat_ERRCLP

,

=

100%

×





(17)

V_CC/ 5 V

DC Fault Switchpoint Error (Err_DFS

)





The Over Field Fault Switchpoint is user-programmable with a

step size of Step_FAULT. DC Fault Switchpoint Error is a deviation

from the user-programmed value that occurs over the operating

temperature range.

where V_CLPis either V_CLP(HIGH)or V_CLP(LOW)

.

Power-On Reset Voltage (V_POR

)

On power-up, to initialize to a known state and avoid current

spikes, the A1365 is held in Reset state. The Reset signal is

DC Fault Switchpoint Symmetry Error

disabled when V_CCreaches V_UVLOHand time t_PORRhas elapsed,

allowing the output voltage to go from a high-impedance state

into normal operation. During power-down, the Reset signal is

enabled when V_CCreaches V_PORL, causing the output voltage to

go into a high-impedance state. (Note that a detailed description

of POR and UVLO operation can be found in the Functional

Description section).

(Err_DFSS

)

Writing FLT_THRESH bits sets the DC Fault Switchpoint for

positive and negative magnetic fields as follows:

Positive Field Fault Switchpoint (V_FPSP) = Xpos × V_CCand

Negative Field Fault Switchpoint (V_FNSP) = Xneg × V_CCwhere

Xpos + Xneg = 1. For example, programming V_FPSP= 0.8 × V_CC

should automatically set V_FNSP= 0.2 × V_CC. For a measured

V_FPSP,the DC Fault Switchpoint Symmetry error is the delta

between the expected V_FNSPand the measured one.

Power-On Reset Release Time (t_PORR

)

When V_CCrises to V_PORH, the Power-On Reset Counter starts.

The A1365 output voltage will transition from a high-impedance

state to normal operation only when the Power-On Reset Counter

Transient Fault Response Time (t_TFR

)

has reached t_PORRand V_CChas exceeded V_UVLOH

.

The time interval between a) when the input crosses the DC Fault

Switchpoint and b) when the FAULT pin reaches 20% of its final

value.

Undervoltage Lockout Threshold (V_UVLO

)

If V_CCdrops below V_UVLOL, the output voltage will be pulled to

GND. If V_CCstarts rising, the A1365 will come out of this lock

DC Fault

Switchpoint

V_FAULT

Applied magnetic Field

state when V_CCreaches V_UVLOH

.

(%)

UVLO Enable/Disable Delay Time (t_UVLO

)

When a falling V_CCreaches V_UVLOL, time t_UVLOEis required to

engage the Undervoltage Lockout state. When V_CCrises above

V_UVLOH, time t_UVLODis required to disable UVLO and to have a

valid output voltage.

Transducer Output

Output Saturation Voltage (V_SAT

)

20

When output voltage clamps are disabled, the output voltage

can swing to a maximum of V_SAT(HIGH)and to a minimum of

t

Transient Fault

Response Time

V_SAT(LOW)

.

(t_TFR

)

Broken Wire Voltage (V_BRK

)

Figure 7: Transient Fault Response Time (t_TFR

)

If the GND pin is disconnected (broken wire event), output volt-

age will go to V_BRK(HIGH)if a load resistor is connected to VCC,

Allegro MicroSystems, LLC

115 Northeast Cutoff

17

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

(%)

Transient Fault Release Time (t_TFRL

)

80

As the Over Field Fault condition goes away, t_TFRLis the time

interval between a) when the recovering input crosses the DC

Fault Switchpoint and when the FAULT pin reaches 80% of its

final value. Note that the DC Fault Switchpoint will be impacted

by the programmed Fault Hysteresis Level (V_FHSYT).

V_FAULT

DC Fault

Switchpoint

Transducer Output

Applied

Magnetic

Field

t

Transient Fault

Release Time

(t_TFRL

)

Figure 8: Transient Fault Release Time (t_TFRL

)

Allegro MicroSystems, LLC

115 Northeast Cutoff

18

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

FUNCTIONAL DESCRIPTION

Programming Sensitivity and Quiescent Volt-

age Output

Memory-Locking Mechanisms

The A1365 is equipped with two distinct memory-locking

mechanisms:

Sensitivity and V_OUT(Q)can be adjusted by programming

SENS_FINE and QVO bits, as illustrated in Figures 7 and 8.

Users should not program sensitivity or V_OUT(Q)beyond the

maximum or minimum programming ranges specified in the

Operating Characteristics table. Exceeding the specified limits

will cause the sensitivity and V_OUT(Q)drift over the temperature

range (ΔSens_TCand ΔV_OUT(Q)TC) to deteriorate beyond the

specified values.

•

Default Lock At power-up, all registers of the A1365 are

locked by default. EEPROM and volatile memory cannot be

read or written. To disable Default Lock, a specific 30-bit

customer access code has to be written to address 0x24 within

Access Code Timeout (t_ACC= 8 ms) from power-up. After

doing so, registers can be accessed. If VCC is power-cycled,

the Default Lock will automatically be re-enabled. This

ensures that during normal operation, memory content will not

be altered due to unwanted glitches on VCC or the output pin.

Programming sensitivity might cause a small drift in V_OUT(Q). As

a result, Allegro recommends programming sensitivity first, then

V_OUT(Q)

.

Coarse Sensitivity

•

Lock Bit After EEPROM has been programmed by the user,

the EELOCK bit can be set high and VCC power-cycled to

permanently disable the ability to read or write any register.

This will prevent the ability to disable Default Lock using the

method described above. Note that after the EELOCK bit is

set high and the VCC pin is power-cycled, you will not have

the ability to clear the EELOCK bit or read/write any register.

Each A1365 variant is programmed to a different coarse sensitiv-

ity setting. Devices are tested, and temperature compensation is

factory-programmed under that specific coarse sensitivity setting.

If the coarse sensitivity setting is changed, by programming

SENS_COARSE bits, Allegro cannot guarantee the specified

sensitivity drift through temperature range limits (ΔSens_TC).

Quiescent Voltage Output,

V_OUT(Q)(mV)

Sensitivity, Sens (mV/G)

Max Specified

V_OUT(Q)PR

Max Specified

Sens_PR

Specified V_OUT(Q)

Specified Sensitivity

Programming Range

Mid Range

Min Specified

V_OUT(Q)PR

Min Specified

Sens_PR

255 256

0

511

0

511

SENS_FINE Code

QVO Code

Figure 9: Device Sensitivity versus SENS_FINE

Programmed Value

Figure 10: Device V_OUT(Q)versus QVO

Programmed Value

Allegro MicroSystems, LLC

115 Northeast Cutoff

19

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

go to V_CC/ 2 after t_UVLOD[4].

Power-On Reset (POR) and Undervoltage

Lockout (UVLO) Operation

•

V_CCdrops below V_CC(min)= 4.5 V If V_CCdrops below

V

_UVLOL[4', 5], the UVLO Enable Counter starts counting. If

_CCis still below V_UVLOLwhen the counter reaches t_UVLOE

The descriptions in this section assume: T_A= 25°C, no output

load (R_L, C_L), and no significant magnetic field is present.

,

the UVLO function will be enabled and the ouput will be

pulled near GND [6]. If V_CCexceeds V_UVLOLbefore the

UVLO Enable Counter reaches 64 µs [5'], the output will

continue to be V_CC/2.

•

Power-Up At power-up, as V_CCramps up, the output is in a

high-impedance state. When V_CCcrosses V_PORH(location

[1] in Figure 11 and [1'] in Figure 12), the POR Release

counter starts counting for t_PORR. At this point, if V_CCexceeds

V_UVLOH[2'], the output will go to V_CC/ 2 after t_UVLOD[3']. If

V_CCdoes not exceed V_UVLOH[2], the output will stay in the

high-impedance state until V_CCreaches V_UVLOH[3] and then

•

Coming out of UVLO While UVLO is enabled [6], if V_CC

exceeds V_UVLOH[7], UVLO will be disabled after t_UVLOD

and the output will be V_CC/ 2 [8].

,

Power-Down As V_CCramps down below V_UVLOL[6’, 9], the

V_CC

11

10

1

2

3

9

6

5

7

4

8

5.0

V_UVLOH

V_UVLOL

V_PORH

V_PORL

t_UVLOE

GND

V_OUT

Time

Slope =

V_CC/ 2

2.5

t_PORR

t_UVLOD

GND

Time

High Impedance

Figure 11: POR and UVLO Operation – Slow Rise Time Case

V_CC

1’ 2’

4’ 5’

7’

6’

3’

5.0

V_UVLOH

V_UVLOL

V_PORH

V_PORL

< t_UVLOE

GND

V_OUT

Time

t_PORR

Slope =

V_CC/ 2

< 64 µs

Slope =

V_CC/ 2

2.5

t_UVLOD

GND

Time

High Impedance

Figure 12: POR and UVLO Operation – Fast Rise Time Case

Allegro MicroSystems, LLC

115 Northeast Cutoff

20

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

UVLO Enable Counter will start counting. If V_CCis higher

than V_PORLwhen the counter reaches t_UVLOE, the UVLO

function will be enabled and the ouput will be pulled near

GND [10]. The output will enter a high-impedance state as

V_CCgoes below V_PORL[11]. If V_CCfalls below V_PORLbefore

the UVLO Enable Couner reaches t_UVLOE, the output will

transition directly into a high-impedance state [7'].

A1365

V_F(PULLUP)

R_F(PULLUP)

VCC VOUT

GND FAULT

V+

C

F

C

L

Detecting Broken Ground Wire

(Optional)

C

BYPASS

If the GND pin is disconnected, node A becoming open (see

Figure 12), the VOUT pin will go to a high-impedance state.

The output voltage will go to V_BRK(HIGH)if a load resistor

R_L(PULLUP)is connected to V_CCor to V_BRK(LOW)if a load resistor

R_L(PULLDWN)is connected to GND. The device will not respond

to any applied magnetic field.

Figure 13: Typical Application Drawing

If the ground wire is reconnected, the A1365 will resume normal

operation.

V

CC

R

L(PULLUP)

VOUT

VCC

VOUT

V

F(PULLUP)

R

A1365

R

F(PULLUP)

R

F(PULLUP)

L(PULLDWN)

FAULT

GND

A

Connecting VOUT to R

L(PULLDWN)

L(PULLUP)

Figure 14: Connections for Detecting Broken Ground Wire

Allegro MicroSystems, LLC

115 Northeast Cutoff

21

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

The A1365 offers a 6-bit programmable Ratiometric Fault as well

as a 2-bit programmable Ratiometric Fault Hysteresis.

Over Magnetic Field Fault

¯¯¯¯¯¯¯¯¯

During normal operation, the FAULT pin is in a high-impedance

Figure 17 illustrates the impact of programming 60 mV of Fault

Hysteresis on the Fault Switchpoint:

state. The combination of an internal pull-up resistance with an

¯¯¯¯¯¯¯¯¯

internal current source enables the FAULT pin to be pulled high.

¯¯¯¯¯¯¯¯¯

shut down.

After the FAULT pin reaches V_SAT(HIGH), the current source is

• FAULT_THRESH = 0, setting Positive and Negative Field

Fault Switchpoint (V_FPSP, V_FNSP) to the middle of their

programmable range.

¯¯¯¯¯¯¯¯¯

The user could install an external pull-up resistor on the FAULT

¯¯¯¯¯¯¯¯¯

pin to reduce the amount of time required by the FAULT pin to

• FAULT_HYST = 2, setting Fault Hysteresis Level to 60 mV.

reach V_SAT(HIGH)after a fault event passes. An external pull-up

resistor can be connected to a voltage (V_F(PULLUP)) different

from VCC as long as it remains within the V_F(PULLUP)limits. If

V_F(PULLUP)is less than VCC, the current provided by the internal

current source, I_IF(PULLUP), will flow through the external pull-up

resistance causing a small voltage drop.

The Fault Switchpoint is not affected by the selected Fault

Hysteresis Level.

The speed and accuracy with which a fault is triggered are

characterized by the Transient Fault Response Time (t_TFR), the

DC Fault Switchpoint Error (err_DFS), and the Fault Delay Due to

Load Capacitance (t_FDC).

Fault

Switchpoint (V)

V

FAULT

(V)

Max Speciﬁed

Switchpoint

5.0

V

Speciﬁed Fault

Switchpoint Range

FHYST

Mid Range

FPSP

0.1

3940

4000

Min Speciﬁed

Switchpoint

V

OUT

(mV)

0

31 32

63

FLT_THRESH

Figure 17: Fault Hysteresis Behavior at FAULT_

THRESH = 0, FAULT_HYST = 2

Figure 16: Fault Switchpoint Programming Proﬁle

V_CC

A1365

I_IF(PULLUP)

R_IF(PULLUP)

GND

V_F(PULLUP)

VCC VOUT

V+

FAULT

R_F(PULLUP)

C

F

C

L

(Optional)

C

BYPASS

Figure 18: Fault Functional Circuit

Allegro MicroSystems, LLC

115 Northeast Cutoff

22

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

A Fault Overstep is defined as the amount by which the output

voltage exceeds the delta between V_OUT(Q)and the DC Fault

Switchpoint (V_FPSPand V_FNSP). The larger the overstep caused

by an input magnetic field is, the faster t_TFRwill be. When V_FPSP

and V_FNSPare programmed near their limits, the maximum Fault

Overstep will be limited because V_OUTwill be reaching satura-

tion levels (see Figure 19).

Faults can be latched by setting the FAULT_LATCH bit high.

¯¯¯¯¯¯¯¯¯

After a fault occurs, the FAULT pin will be held low. To reset the

¯¯¯¯¯¯¯¯¯

FAULT pin, the A1365 must be powered down.

Over Magnetic Field Fault can be disabled by setting the

FLT_DIS bit.

0.75

5.5

11

9

Worst Process Corner

when V_FNSP= 0.1 × V_CC

Worst Process Corner

when V_FPSP= 0.9 × V_CC

7

Worst Process Corner

when V_FNSP> 0.17 × V_CC

and V_FPSP< 0.87 × V_CC

5

Typical Process Corner

when V_FNSP> 0.2 × V_CC

and V_FPSP< 0.8 × V_CC

2

0

5

10

15

20

V_FaultOverstep(%)

Figure 19: Transient Fault Response Time versus Fault Overstep Voltage at V_CC= 5 V, C_F= 0 F, R_L= Open.

Allegro MicroSystems, LLC

115 Northeast Cutoff

23

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

PROGRAMMING SERIAL INTERFACE

The A1365 incorporates a serial interface that allows an external

controller to read and write registers in the EEPROM and volatile

memory. The A1365 uses a point-to-point communication pro-

tocol, based on Manchester encoding per G. E. Thomas (a rising

edge indicates 0 and a falling edge indicates 1), with address and

data transmitted MSB first.

Writing the Access Code

In order for the external controller to write or read from the

A1365 memory during the current session, it must establish serial

communication with the A1365 by sending a Write command

including the Access Code within Access Code Timeout (t_ACC

from power-up. If this deadline is missed, all write and read

access is disabled until the next power-up.

)

Transaction Types

Each transaction is initiated by a command from the controller;

the A1365 does not initiate any transactions. Three commands

are recognized by the A1365: Write Access Code, Write, and

Read. One response frame type is generated by the A1365, Read

Acknowledge. If the command is Read, the A1365 responds by

transmitting the requested data in a Read Acknowledge frame. If

the command is any other type, the A1365 does not acknowledge.

As shown in Figure 20, the A1365 receives all commands via the

VCC pin. It responds to Read commands via the VOUT pin. This

implementation of Manchester encoding requires the communica-

tion pulses be within a high (V_MAN(H)) and low (V_MAN(L)) range

of voltages for the VCC line and the VOUT line. The Write

command to EEPROM is supported by two high-voltage pulses

on the VOUT line.

Writing to Volatile Memory

In order for the external controller to write to volatile memory,

a Write command must be transmitted on the VCC pin. Succes-

sive Write commands to volatile memory must be separated by

t_WRITE. The required sequence is shown in Figure 21.

VCC

Write

to Register R#

t

t_WRITE

Figure 21: Writing to Volatile Memory

Write/Read Command

–

Manchester Code

Controller

V

CC

VCC

High Voltage pulses to

activate EEPROM cells

R

F(PULLUP)

A1365

FAULT

V

OUT

Read Acknowledge

– Manchester Code

Figure 20: Top-Level Programming Interface

Allegro MicroSystems, LLC

115 Northeast Cutoff

24

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

responding to the magnetic field and the Read Acknowledge

frame will be transmitted on the VOUT line. The Read Acknowl-

edge frame contains Read data.

Writing to EEPROM

In order for the external controller to write to non-volatile

EEPROM, a Write command must be transmitted on the VCC

pin. The controller must also send two Programming pulses,

long high-voltage strobes, via the VOUT pin. These strobes are

detected internally, allowing the A1365 to boost the voltage on

the EEPROM gates. The required sequence is shown in figures

22 and 23.

After the Read Acknowledge frame has been received from the

A1365, the VOUT line resumes normal operation after time

t_READ. The required sequence is shown in Figure 24.

Error Checking

The serial interface uses a cyclic redundancy check (CRC) for

data-bit error checking (synchronization bits are ignored during

the check). The CRC algorithm is based on the polynomial g(x)

= x3 + x + 1, and the calculation is represented graphically in

Figure 25. The trailing 3 bits of a message frame comprise the

CRC token. The CRC is initialized at 111. If the serial interface

receives a command with a CRC error, the command is ignored.

To ensure EEPROM integrity over lifetime, EEPROM should not

be exposed to more than 100 Write cycles.

Reading from EEPROM or Volatile Memory

In order for the external controller to read from EEPROM or

volatile memory, a Read command must be transmitted on

the VCC line. Within time t_{start_read}, the VOUT line will stop

VCC

Write

to Register R#

EEPROM

Programming

Pulses

VOUT

High

Impedance

Normal Operation

VOUT

t

t_sPULSE(E)

t_WRITE(E)

Figure 22: Writing to EEPROM

Figure 23: EEPROM Programming Pulses

VCC

Read from

Register R#

Input Data

C0

C1

C2

Normal Operation

VOUT

Read Acknowledge

R#

1x⁰

1x¹

0x²

1x³= x³+ x + 1

t

t_{start_read}

t_READ

Figure 24: Reading from EEPROM or Volatile Memory

Figure 25: CRC Calculation

Allegro MicroSystems, LLC

115 Northeast Cutoff

25

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Serial Interface Reference

Required timing parameters for successful serial communication with A1365 device are given in table below.

Required Serial Interface Timing Parameters

Characteristics

Symbol

Note

Min.

Typ.

Max.

Unit

Input/Output Signal Timing

Customer Access Code should be fully entered

Access Code Timeout

Bit Rate

t_ACC

in less than t_ACC, measured from when V_CC

–

8

ms

crosses V_UVLOH

.

Defined by the input message bit rate sent from

the external controller

t_BITR

32

80

kbps

Bit Time

t_BIT

Data bit pulse width at 70 kbps

13.6

–11

14.3

–

15

µs

%

Bit Time Error

err_TBIT

Deviation in t_BITduring one command frame

+ 11

Required delay from the trailing edge of certain

Write command frames to the leading edge of a

following command frame

Volatile Memory Write Delay

Non-Volatile Memory Write Delay

Read Acknowledge Delay

t_WRITE

2 × t_BIT

–

µs

Required delay from the trailing edge of the

t_WRITE(E)second EEPROM Programming pulse to the

leading edge of a following command frame

Required delay from the trailing edge of a Read

Acknowledge frame to the leading edge of a

following command frame

t_READ

Delay from the trailing edge of a Read

t_{start_read}command frame to the leading edge of the Read

Acknowledge frame

25 μs –

0.25 ×

t_BIT

50 μs

–0.25 ×

t_BIT

150 μs

– 0.25 ×

t_BIT

Read Delay

EEPROM Programming Pulse

Setup Time

Delay from last edge of write command to start

t_sPULSE(E)

40

–

μs

of EEPROM programming pulse

Input/Output Signal Voltage

Applied to VCC line

5.1

–

V

Manchester Code High Voltage

V_MAN(H)

V_CC

0.2 V

–

Read from VOUT line

Applied to VCC line

V_MAN(L)

–

3.9

0.2

15

V

Manchester Code Low Voltage

Manchester Level to VCC Delay

Read from VOUT line

t_{MAN_VCC}

µs

Allegro MicroSystems, LLC

115 Northeast Cutoff

26

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Serial Interface Message Structure

Read/Write

Synchronize

Memory Address

Data

CRC

The general format of a command message frame is shown in

Figure 26. Note that, in the Manchester coding used, a bit value

of one is indicated by a falling edge within the bit boundary, and

a bit value of zero is indicated by a rising edge within the bit

boundary.

0

0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1

MSB

V_CCLevels During Manchester Communica-

tion

Manchester Code per G. E. Thomas

Bit boundaries

0 0 1 1 0

For all devices with UVLO functionality, after power-up, it

is important that the VCC pin be held at V_CCuntil the first

Synchronization pulse of a read/write transaction is sent (see

Figure 27). During the transaction, the VCC pin varies between

V_MAN(H)and V_MAN(L), but after the last CRC bit has been sent,

the controller must bring the VCC pin back to the V_CClevel in

less than t_{MAN_VCC}. This is important in order to avoid triggering

the UVLO functionality during EEPROM read/write.

Figure 26: General Format for Serial Interface

Commands

Read/Write

Memory Address

Data

CRC

0/1

Synchronize

0

0 0/1

V

MAN(H)

V

CC(V)

V

MAN(L)

0 V

0

1

0

t

MAN_VCC

Bit boundaries

Figure 27: V_CCLevels During Manchester Communication

Serial Interface Command General Format

Quantity

of Bits

Parameter Name

Values

Description

2

Synchronization

00

0

Used to identify the beginning of a serial interface command

[As required] Write operation

1

Read/Write

1

[As required] Read operation

6

30

3

Address

Data

0/1

[Read/Write] Register address (volatile memory or EEPROM)

24 data bits and 6 ECC bits

CRC

Incorrect value indicates errors

Allegro MicroSystems, LLC

115 Northeast Cutoff

27

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Read (Controller to A1365)

Read/Write

Synchronize

Data

(30 bits maximum)

The fields for the Read command are:

Memory Address

CRC

• Sync (2 zero bits)

0

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1

MSB MSB

• Read/Write (1 bit, must be 1 for read)

• Address (6 bits) (ADDR[5] is 0 for EEPROM, 1 for register)

• CRC (3 bits)

Figure 30: Write Sequence

Write Access Code (Controller to A1365)

Figure 28 shows the sequence for a Read command.

The fields for the Access Code command are:

Read/Write

• Sync (2 zero bits)

Memory Address

CRC

Synchronize

• Read/Write (1 bit, must be 0 for write)

• Address (6 bits) (Address 0X24 for Customer Access)

• Data (30 bits) (0x2781_1F77 for Customer Access)

• CRC (3 bits)

0

1

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

MSB

Figure 28: Read Sequence

Read Acknowledge (A1365 to Controller)

The fields for the data return frame are:

Figure 31 shows the sequence for an Access Code command.

Read/Write

Data

• Sync (2 zero bits)

Memory Address

(30 bits)

CRC

Synchronize

• Data (30 bits: [29:26] Don’t Care, [25:24] ECC Pass/Fail,

[23:0] Data)

0

1

0

1

0

0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1

MSB

• CRC (3 bits)

Figure 31: Access Code Write Sequence

Figure 29 shows the sequence for a Read Acknowledge. Refer to

the Detecting ECC Error section for instructions on how to detect

and ECC failure.

The controller must open the serial communication with the

A1365 device by sending an Access Code. It must be sent within

Access Code Timeout (t_ACC) from power-up or the device will

be disabled for read and write access.

Data

(30 bits maximum)

CRC

Synchronize

Access Codes Information

0

0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1 0/1

MSB

Name

Serial Interface Format

Register Address

Data (Hex)

Figure 29: Read Acknowledge Sequence

Write (Controller to A1365)

(Hex)

The fields for the Write command are:

• Sync (2 zero bits)

Customer

0x24

0x2781_1F77

Shadow Mode

• Read/Write (1 bit, must be 0 for write)

For faster programming, Shadow Mode puts the sensor in a try

mode where one can write to the EEPROM registers as if they

are volatile registers. This is especially useful when searching

for Sensitivity, QVO, and Over Field Fault codes. Once the

desired codes are identified, the user should exit Shadow Mode

and execute an EEPROM Write. If a power-cycle is executed

during Shadow Mode, the registers will reset to their initial state.

SHADOW_ENABLE bit should be set to enter Shadow Mode.

• Address (6 bits) (ADDR[5] is 0 for EEPROM, 1 for register;

refer to the address map)

• Data (30 bits: [29:24] Don’t Care, [23:0] Data)

• CRC (3 bits)

Figure 30 shows the sequence for a Write command. Bits [29:24]

are Don’t Care because the A1365 automatically generates 6 ECC

bits based on the content of bits [23:0]. These ECC bits will be

stored in EEPROM at locations [29:24].

Allegro MicroSystems, LLC

115 Northeast Cutoff

28

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

change the EEPROM margin setting. EEPROM registers that

EEPROM Margining

were written by the user should be read and compared to the

user-programmed value. The procedure should be repeated using

VREAD = “10”. It is not mandatory for the user to execute

EEPROM Margining.

Allegro factory-tests the capacity of each EEPROM bit to retain

a “0” or a “1” state. After the user has completed EEPROM

programming, the two VREAD bits could be set to “01” to

Memory Address Map

Register Name

FAC_LOT_NUM

Address

Description

Factory Lot (uses 3rd to 7th digits of the lot number)

Factory Wafer (stores up to 64 wafers)

Factory use only

r/w

w

Bits

16

6

Location

15:0

21:16

23:22

7:0

WAFER_NUM

SCRATCH

X_DIE_LOC

Y_DIE_LOC

SCRATCH

SENS_FINE

SENS_COARSE

QVO

0x00*

2

Customer Read-

Only EEPROM

8 bits X die location (accommodates up to 256 die in X)

8 bits Y die location (accommodates up to 256 die in Y)

Factory use only

8

0x01*

0x02

8

15:8

23:16

8:0

8

Sensitivity

9

Coarse Sensitivity

2

10:9

19:11

20

Quiescent Output Voltage

Factory use only

9

FACTORY_RES1

POL

1

Reverses output polarity

1

21

CLAMP_EN

EELOCK

Clamp Enable

1

22

EEPROM LOCK

1

23

Customer R/W

EEPROM

Sets the DC Fault Switchpoint, two’s complement

DAC profile

FLT_THRESH

FLT_HYST

r/w

6

2

5:0

7:6

Fault Hysteresis Adjust, [00] = 0 V, [01] = 30 mV,

[10] = 60 mV, [11] = 120 mV

0x03

FLT_LATCH

FLT_DIS

Enables Fault Latch

r/w

1

8

9

Disables Fault

Misc(x)

Reserved for factory use; do not change default state

Factory-reserved (unused)

11

3

20:10

23:21

23:0

0

MISC3_1

CUSTOMER_RES

Disable Analog Output

0x04*

Customer-reserved

24

1

Sets the output pin to a high-impedance state

Enables register shadowing to bypass shadowed

EEPROM registers

SHADOW_ENABLE

CUSTOMER_ACCESS

Factory Reserved

r/w

r

1

2

1

2

Customer write access enabled

Reserved for factory use. Do not change default

state.

r/w

4:3

Volatile Memory

Customer Debug

Register

0x10

0 = No Over Field Fault

1 = Over Field Fault occurred, clears on read

OVERF_FLT

r

1

2

5

Factory Reserved

Reserved for factory use; do not change default state.

r/w

8:7

Change EEPROM read voltage for margining;

[00] = 1.2 V (default), [01] = 0 V, [10] = 4.3 V,

[11] = undefined

VREAD

–

r/w

n/a

2

10:9

Reserved for factory use (unused)

Customer code (not addressable)

13

30

23:11

29:0

ACCESS_CODE

0x24

*EEPROM registers or bits that are not shadowed.

Allegro MicroSystems, LLC

115 Northeast Cutoff

29

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

EEPROM Cell Organization

Programming coefficients are stored in non-volatile EEPROM,

which is separate from the digital subsystem, and accessed by the

digital subsystem EEPROM Controller module. The EEPROM

is organized as 30-bit-wide words, each word is made up of 24

data bits and 6 ECC (Error Checking and Correction) check bits,

stored as shown in figure below.

EEPROM Bit

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Contents

C5

C4

C3

C2

C1

C0 D23 D22 D21 D20 D19 D18 D17 D16 D15

14

D14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

External EEPROM Word Bit Sequence; C# – Check Bit, D# – Data Bit

EEPROM Error Checking and Correction

(ECC)

Detecting ECC Error

If an uncorrectable error has occurred, bits 25:24 are set to 10, the

VOUT pin will go to a high-impedance state, and the device will

not respond to the applied magnetic field. Output voltage will go

to V_BRK(HIGH)if a load resistor R_L(PULLUP)is connected to V_CC

or to V_BRK(LOW)if a load resistor R_L(PULLDWN)is connected to

GND.

Hamming code methodology is implemented for EEPROM

checking and correction. The device has ECC enabled after

power-up.

The device always returns 30 bits.

The message received from controller is analyzed by the device

EEPROM driver and ECC bits are added. The first 6 received bits

from device to controller are dedicated to ECC.

EEPROM ECC Errors

Bits

Name

Description

No meaning

00 = No error

29:26

–

01 = Error detected and message corrected

25:24

23:0

ECC

10 = Uncorrectable error

11 = No meaning

D[23:0]

EEPROM data

Allegro MicroSystems, LLC

115 Northeast Cutoff

30

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

PACKAGE OUTLINE DRAWING

For Reference Only - Not for Tooling Use

(Reference DWG-9202)

Dimensions in millimeters - NOT TO SCALE

Dimensions exclusive of mold ﬂash, gate burs, and dambar protrusions

Exact case and lead conﬁguration at supplier discretion within limits shown

B

10°

+0.08

–0.05

+0.08

–0.05

1.00

5.21

E

2.60

F

1.00

F

Mold Ejector

Pin Indent

+0.08

3.43

–0.05

Branded

Face

F

1

2

3

4

0.89 MAX

0.54 REF

A

NNNN

YYWW

+0.08

–0.05

+0.08

–0.05

0.41

0.20

12.14 0.05

D

Standard Branding Reference View

1.27 NOM

N

Y

= Device part number

= Last two digits of year of manufacture

W = Week of manufacture

A

Dambar removal protrusion (16X)

Gate and tie burr area

0.54 REF

B

C

Branding scale and appearance at supplier discretion

0.89 MAX

D

E

F

Thermoplastic Molded Lead Bar for alignment during shipment

Active Area Depth, 0.37 mm REF

+0.08

1.50

–0.05

D

Hall element, not to scale

+0.08

–0.05

+0.08

–0.05

1.00

5.21

Figure 32: Package KT, 4-Pin SIP

Allegro MicroSystems, LLC

115 Northeast Cutoff

31

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator

A1365

Revision History

Current

Revision

Description of Revision

Revision Date

–

January 7, 2016

Initial release

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, LLC

115 Northeast Cutoff

32

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com


型号：	A1365LKTTN-5-T
厂家：	ALLEGRO MICROSYSTEMS
描述：	Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
文件：	总32页 (文件大小：996K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A1365LKTTN-5-T [ALLEGRO]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E