A3942 [ALLEGRO]
Quad High-Side Gate Driver; 四通道高边栅极驱动器
| 型号： | A3942 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Quad High-Side Gate Driver |
| 文件： | 总20页 (文件大小：501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3942
Quad High-Side Gate Driver
for Automotive Applications
Features and Benefits
▪ Drives four N-channel high-side MOSFETS
▪ Charge pump for 100% duty cycle operation
▪ Serial and discrete inputs
▪ SPI port for control and fault diagnostics
▪ 4.5 to 60 V input voltage range
▪ Sleep function for minimum power drain
▪ Thin profile 38-lead TSSOP with internally fused leads for
enhanced thermal dissipation
▪ Lead (Pb) free
▪ Device protection features:
▫ Short-to-ground detection (latched)
▫ Short-to-battery protection (latched)
▫ Open load detection (latched)
▫ VDD undervoltage lockout
Description
The A3942 is a highly-integrated gate driver IC that can drive
up to four N-Channel MOSFETs in a high-side configuration.
The device is designed to withstand the harsh environmental
conditions and high reliability standards of automotive
applications.
SerialPeripheralInterface(SPI)compatibilitymakesthedevice
easily integrated into existing applications. The MOSFETs in
such applications are typically used to drive gasoline or diesel
engine management actuators, transmission actuators, body
control actuators and other general-purpose automotive or
industrial loads. In particular, the A3942 is suited for driving
glow plugs, valves, solenoids, and other inductive loads in
engine management and transmission systems.
▫ VCP undervoltage lockout
▫ Thermal monitor
The device is available in a 38-lead thin (1.20 mm maximum
overall height) TSSOP package with six pins that are fused
internally to provide enhanced thermal dissipation (package
LG). It is lead (Pb) free with 100% matte tin leadframe
plating.
Package: 38 pin TSSOP (suffix LG)
Approximate Scale 1:1
Typical Application
CP1 CP2 CP3 CP4
VCP
VBB
VDD
VBAT
VDD
IREF
VREG
D1
FAULTZ
SDO
SDI
A3942
G1
S1
D2
System
Control
Logic
CSZ
G2
S2
SCLK
RESETZ
ENB
IN1
D3
G3
S3
IN2
IN3
D4
G4
IN4
GNDGNDGNDGNDGNDGND S4
3942-DS, Rev. 5
Quad High-Side Gate Driver
for Automotive Applications
A3942
Selection Guide
Part Number
Packing
A3942KLGTR-T
4000 pieces per reel
Absolute Maximum Ratings*
Characteristic
Symbol
Notes
Rating
Units
VBB, CP1, CP3 Pins Voltage
–0.3 to 60
V
VBB – 6 V
to VBB + 0.5 V
Dx (Drain Detect) Pins Voltage
VDx
VSx
V
Sx (Output Source) Pins Voltage
VCP, CP2, CP4, Gx Pins Voltage
All Other Pins
–10 to 60
–0.3 to 74
–0.3 to 7
–40 to 125
150
V
V
V
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
TJ(max)
Tstg
Range K
ºC
ºC
ºC
V
–55 to 150
2500
ESD Rating, Human Body Model
ESD Rating, Charged Device Model
AEC-Q100-002, all pins
AEC-Q100-011, all pins
1050
V
*With respect to ground. Exceeding maximum ratings may cause permanent damage. Correct operation is not guaranteed when absolute
maximum conditions are applied.
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
Rating
Units
Package Thermal Resistance, Junction
to Ambient
4-layer PCB based on JEDEC standard, with no
thermal vias
RθJA
47
ºC/W
*For additional information, refer to the Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
Functional Block Diagram
CP4
CP3
CP2
CP1
VCP
CDD
C34
C12
VDD
IREF
Charge
Pump
Reference
Current
VDD
UVLO
Thermal
Warning
CREF
60.4 kΩ
VCP UVLO
CCP
CBB2 CBB1
FAULTZ
VBB
Fault
Monitor
U
V
L
Internal
Regulator
SDO
SDI
VREG
O
CREG
VDD
CSZ
SCLK
RESETZ
ENB
IN1
Voltage to VBB pin
and to Qx MOSFETs
must come from
the same supply
One of Four
Control
Logic
High-Side Drivers
RDx
Vds
Monitor
Dx
VCP
High
Side
Driver
RGx
Gx
Sx
Qx
IN2
IN3
Open
Load
Detect
IN4
L
L
GND
GND
GND
GND
GND
GND
Name
Suitable Characteristics
Representative Device
C12, C34 0.33 μF or 0.47 μF, 25 V, X7R ceramic
CBB1
CBB2
CCP
47 μF, 63 V, electrolytic
EGXE630ELL470MJC5S
0.22 μF, 100 V, X7R ceramic
1 μF, 16V, X7R ceramic
0.47 μF, 16 V, X7R ceramic
47 pF, 16 V, X7R ceramic
0.22 μF, 16 V, X7R ceramic
CDD
CREF
CREG
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
ELECTRICAL CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF, RREF = 60.4 kΩ, and
VBB within limits, unless otherwise noted
Characteristics
Supplies and Regulators
Operating Voltage
Symbol
Test Conditions
Min. Typ. Max. Units
VBB
4.5
–
–
–
–
–
–
60
10
8
V
VBB = 60 V
mA
mA
μA
μA
Charge pump on,
outputs disabled
VBB = 36 V
–
Quiescent Current
IBB(Q)
VBB = 36 V
–
15
1
Sleep mode
VBB = 36 V, TJ = 25°C
–
Logic Supply (voltage supplied to
logic circuits)
VDD
IDD
3
–
5.5
V
VDD = 5.5 V, serial port switching
–
–
–
–
3
mA
mA
Logic Supply Current
VDD = 5.5 V, device quiescent or in sleep mode
0.5
VDD falling, FAULTZ pin held active (low) for
1.5 V ≤ VDD ≤ VDDUV
Logic Supply UVLO Threshold
VDD(UV)
2.6
–
2.9
V
Logic Supply UVLO Hysteresis
VDD(hys)
fCP
100
–
150
100
–
200
–
mV
kHz
V
Charge Pump Switching Frequency
V
BB = 12 V, ICP = 10 mA
10
10
7
13
13
11
Measured relative to
VBB pin
Charge Pump Output Voltage
VCP
VBB = 6.0 V, ICP = 5 mA
VBB = 4.5 V, ICP = 5 mA
–
V
–
V
Charge Pump UVLO
Internal Regulator Voltage
Regulator Voltage UVLO
Regulator Voltage UVLO Hysteresis
Control Circuits
VCP(UV)
VREG
VREG(UV)
VREG(hys)
Relative to VBB pin, VCP falling
CREG = 0.22 μF
5.1
–
–
5.8
–
V
4
V
VREG falling
3
–
3.8
400
V
100
–
mV
Current Reference Source Voltage
Master Reset Pulse
VREF
tRESET
tSLEEP
tWAKE
1.14
0.3
20
1.2
–
1.26
V
RESETZ pin pulsed low
5
–
2
μs
μs
ms
Sleep Command
RESETZ pin held low
–
Wake-Up Delay
RESETZ pin held high; CCP = 1 μF
–
–
Logic I/O
0.7 ×
VDD
Logic Input Voltage, High
Logic Input Voltage, Low
VIH
VIL
–
–
VDD
V
V
0.3 ×
VDD
0
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF,
RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted
Characteristics
Logic Input Hysteresis
Symbol
Test Conditions
Min. Typ. Max. Units
0.1 ×
Vhys
–
–
V
VDD
CSZ pin
–
–
–
–
–
–
–
10
5
μA
μA
μA
μA
μA
μA
II(HI)
SDI and SCLK Pins
All other pins
VI = VDD = 5.5 V
–
–
100
–100
–5
Logic Input Current1
CSZ pin
–
II(LO)
SDI and SCLK Pins
All other pins
VI = 0 V
–
–
–10
VDD
– 0.5
VOUT(HI)
VOUT(LO)
IOUT = –1 mA
IOUT = 1 mA
–
VDD
V
Logic Output Voltage, SDO Pin
(CMOS push-pull circuit)
–
–
–
–
–
–
0.4
0.4
10
V
V
FAULTZ Pin Active (Low) Voltage
FAULTZ Pin Inactive (High) Current
Drivers
VFAULTZ(LO) IFAULTZ = 1 mA, VDD = 1.5 V, VBB = 4.5 V
IFAULTZ(HI) VFAULTZ = 5 V
μA
Measured relative to Sx pin, capacitive load–fully
charged
VCP
– 1
Gate Voltage, High
Gate Voltage, Low
VG(HI)
–
–
VCP
0.1
V
V
Measured relative to Sx pin, capacitive load–fully
discharged
VG(LO)
–
VBB = 4.5 V, VCP = 9 V
–10
–15
10
25
–
–
–
–
–
mA
mA
mA
mA
μs
RG = 0 Ω, 1 V ≤ VGS
4 V, VSx = VBB
≤
IG(HI)
VBB ≥ 9 V, VCP = 13 V
Peak Gate Current1,2
Propagation Delay
RG = 0 Ω, VGS = 1 V, VSx = 0 V
RG = 0 Ω, 2 V ≤ VGS ≤ 4 V, VSx = 0 V
From 90% VINx to VGx – VSx = 200 mV
From 10% VINx to VCP – VGx = 200 mV
RESETZ pin held low; VGSZ = 10 V
IG = 2 mA
–
–
IG(LO)
–
–
tp(on)
tp(off)
0.6
0.6
500
–
–
–
–
μs
Gate-to-Source Resistance
RGS
300
15
–
800
18
10
5
kΩ
V
Gate-to-Source Zener Diode Voltage
VGS(Z)
RESETZ pin held low, VBB = VDx = 60 V
–
μA
μA
μA
Drain Leakage Current
IDlkg
TJ = 150°C
TJ = 25°C
–
–
RESETZ pin held low,
BB = VDx = 36 V
V
–
–
1
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF,
RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min. Typ. Max. Units
Driver Fault Detection
VBB = 60 V
VBB = 36 V
75
85
100
100
125
120
μA
μA
Drain Fault Detect Current
IDx
VBB
– 3
VBB
+ 0.2
VBB ≥ 9 V
–
–
–
V
V
V
VBB
+ 0.2
Drain Fault Detect Voltage3
VDx
VBB = 6 V
5
4
VBB
+ 0.2
V
BB = 4.5 V
Open Load Detect Source Current1
Open Load Detect Voltage
IOL
VSx = 1.35 V; 4.5 V ≤ VBB ≤ 36 V
–48
1.4
–
–82
1.6
μA
VOL
1.5
V
Active (when an open load fault is active),
VBB ≤ 36 V
VCLAMP
–
–
5
V
Open Load VSx Clamp
ICLAMP
tON(00)
tON(01)
tON(10)
tON(11)
tOFF
Current limit in short-to-battery; VSx =VBB = 36 V
–
–
–
200
3.4
5.9
11.2
22.3
–
μA
μs
μs
μs
μs
μs
2.5
3.7
5.6
8.9
–
–
Turn-On Blank Time
Turn-Off Blank Time
tON(00) is the default, TJ = 150°C
–
–
tON
Short-to-Ground Fault Detect Filter
Delay
tSTG
From VSx < VDx to 90% VFAULTZ
–
1
1.2
μs
STB Comparator Offset Voltage
STG Comparator Offset Voltage
Temperature Monitor
VOS(STB)
VOS(STG)
–
–
–
–
60
45
mV
mV
Thermal Warning Threshold4
TWARN
Temperature rising
155
–
165
15
175
–
°C
°C
Thermal Warning Hysteresis
TWARN(hys)
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2For IG(HI), VCP relative to VBB
.
3Minimum values of VDx are specified only to avoid short-to-battery nuisance faults. For more information, refer to the Open Load Fault Level topic in
the Applications Information section.
4
Minimum and maximum not tested; guaranteed by design.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C and VBB and VDD within
limits, unless otherwise noted
Characteristics
Transfer Frequency
Symbol
f
Test Conditions
Min. Typ. Max. Units
–
375
50
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
8
–
MHz
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup Lead Time
tlead
Setup Lag Time
tlag
–
Setup Time Before Read
Access Time Before Write
Chip Selection Inactive Time
Delay Before Output Disabled
Serial Clock Period
tsu
–
ta
CSDO = 100 pF
CSDO = 0 pF
340
–
tCSZN
tdis
2
–
100
–
TSCLK
tw(HI)
tw(LO)
th(SCLK)
th(SDI)
th(SDO)
125
50
50
300
20
0
Serial Clock Pulse Width, High
Serial Clock Pulse Width, Low
Serial Clock Hold Time
Serial Data In Hold Time
Serial Data Out Hold Time
–
–
–
–
CSDO = 0 pF
–
CSDO = 100 pF, VDD = 3 V
–
120
80
Serial Data Out Time Before Valid
State
tvs
CSDO = 100 pF, VDD = 4.75 V
–
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
Serial Peripheral Interface (SPI) Timing Diagram
tCSZN
CSZ
TSCLK
th(SCLK)
tlag
tlead
tw(HI)
tw(LO)
SCLK
SDO
SDI
tvs
tdis
ta
th(SDO)
HI-Z
DON’T
CARE
D7
D6
D0
th(SDI)
tsu
D7
D6
D0
Fault System Block Diagram
VBB
Short to
Battery
Gx Off
8 V
FAULTZ
RDx
IDx
Dx
VCP
Short to
Ground
Gx On
Gx
On
RGx
Gx
Logic
Gx
On
VDS
Delay
Gx
Off
Sport
OSC
Mask
RGS
IOL
Clear
Serial
Sx
VBB
Read
Port
Open
Load
Write
L
O
A
D
VOL
Gx Off
Vclamp
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
Input SettingsTiming Chart
Timer is running for
turn-on blank time
Timer is running for
turn-off blank time
INx
IGx
tp(on)
tp(off)
Gate begins
to charge
VGS = VTH
VGSx
Set blank time to expire
after VSx nears VBB
Set blank time to expire
after VSx nears 0 V
VBB
VSx
Fault Logic Table
Circled data cells indicate default settings, X indicates “don’t care”, Z indicates high impedance state
Causes Effects
Channel-Specific
Mode of Operation
Gates actively pulled low
1
0
0
0
0
0
0
X
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
0
0
X
0
0
0
X
X
1
0
1
0
1
0
1
INx
INx
INx
1
1
1
1
1
1
Normal operation
FAULTZ issued but A3942 fully operational
Normal operation, OL and STB masked
1
1
1
X
X
X
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
X
0
0
X
X
X
0
0
0
0
0
0
1
1
1
1
1
1
STG cannot be masked
STB
OL
1
1
0
X
X
X
0
1
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
Z
UV
1
1
1
0
VCP UVLO disables outputs only
VDD UVLO disables outputs only
Sleep mode
0
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
Serial Port Registers Description
There are two 8-bit registers served by the serial port,
the Input register and the Output Fault register. The
structure of the registers is shown in the table at the
bottom of this page. The function of each bit in the
registers is described in this section.
time for the VDS monitor, according to the following
table:
D2
0
D1
0
tON Selected
tON(00)
*
0
1
tON(01)
tON(10)
tON(11)
Input Register
1
0
1
1
D0 Gate On/Off Bit This bit is used to control the gate
drive output. It is logically ORed with the signal on
the discrete input pin, INx, corresponding to each of
the four channels, according to the following table:
*default state at device power-on
D3 Clear Faults Bit This bit is used to clear a latched
fault. After the fault is cleared, the gate output can
again follow the input logic to determine if the fault is
still present. Faults are cleared on a channel specific
basis.
ORed Settings
Result on
Gx Pin
Bit D0
Pin INx
0
0
1
1
0
1
0
1
Off
On
On
On
D4 Mask Off-State Faults Bit [See asterisks (*) in
the table below.] When the application requires that
Short-to-Battery (STB) and Open Load (OL) faults be
checked primarily before output is enabled for the first
time, this bit can be used to allow STB and Open Load
faults to be ignored during normal operation (Short-to-
Ground faults can not be masked). This bit is applied
D1, D2 Short-to-Ground (STG) Turn-On Blank Time
MSB and LSB Bits The blank time, ton(xx), delay
allows switching transients to settle before the A3942
STG function checks for a short. For each individual
channel, the combination of these bits sets the wait
Serial Port Bit Definition All bits active high, except WriteZ
Bits
Register
D7
D6
D5
D4
D3
D2
D1
D0
Input Read
Enable
Mask
Off-State Faults (*)
STG Blank
Time MSB
STG Blank
Time LSB
Gate
On/Off
Input
Address MSB Address LSB
Clear Faults
Charge Pump
UVLO
Thermal
Warning
Open Load
Fault (*)
Output Fault Address MSB Address LSB
WriteZ
STB Fault (*)
STG Fault
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
on a channel-specific basis, according to the following The A3942 enables monitoring for an STG fault after
the MOSFET is turned on and the turn-on blank time,
ON , expires. (The MOSFET is turned on via the Input
table:
t
Handling of
D4 Setting
register D0 bit, ORed with the INx discrete input pin
for the channel of the MOSFET, and tON is set by
Input register D1 and D2 bits). If the MOSFET gate-
to-source voltage exceeds the VDS threshold, then
Off-State Faults
0
1
Registered
Ignored
D5 Read Enable Bit This bit enables or disables read- an STG fault will be registered for that channel, the
MOSFET gate will be discharged, and the FAULTZ
pin will be set low (active).
ing on the serial inputs, according to the following
table:
An STG fault is latched until cleared (using the Input
register D3 bit). In the meantime, the other channels
can continue to operate normally.
Handling of
D5 Setting
Serial Input
0
1
Ignored
Registered
D1 Short to Battery (STB) Fault Bit When a chan-
nel turns off, STB fault detection is blanked for tOFF
.
D6, D7 Address MSB and LSB Bits (Input and Out-
put Fault registers) For channel-specific bits, these
bits are used to specify which channel is indicated.
The channel-specific bits are:
Subsequently, if the Sx pin voltage exceeds the VDS
threshold voltage for that channel, an STB fault is
latched. The output for that channel is disabled until
the fault is either cleared (via the Input register D3 bit)
or the off-state fault diagnostics are masked (via the
Input register D4 bit).
Register
Input
Channel-Specific Bits
D0, D1, D2, D3, D4
D0, D1, D2
Output
Because the output is disabled, there is no active
pull-down during an STB event. Note that, in general,
when the voltage on SX is high enough to trip the STB
comparator, it also trips the OL comparator, and both
the STB and the OL faults are latched.
These bits determine the channel, according to the fol-
lowing table:
D7
0
D6
0
Channel Selected
1
2
3
4
D2 Open Load (OL) Fault Bit When a channel turns
off, the OL fault is blanked for tOFF. A small bias
current, IOL, is sourced to the Sx pin of the channel.
There it divides between RSx and the load. If the load
is open, the Sx voltage will rise above the OL fault
detection threshold. In that case, the output is disabled
until the fault is cleared (via the Input register D3 bit)
or the off-state fault diagnostics are masked (via the
Input register D4 bit).
0
1
1
0
1
1
Output FAULT Register
D0 Short-to-Ground (STG) Fault Bit The voltage
from drain to source for each MOSFET is monitored.
An internal current source sinks IDx from the Dx pins
to set the VDS threshold for each channel, the level at
which an STG fault condition is evaluated.
D3 Thermal Warning Bit A die temperature monitor
is integrated on the A3942 chip. If the die temperature
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quad High-Side Gate Driver
for Automotive Applications
A3942
IN1 through IN4 Discrete Inputs For each output
channel, the gate pin, Gx, sources voltage when the
corresponding INx pin is set high. Gx sinks voltage to
ground when the corresponding INx pin is set low. The
INx setting is logically ORed with the Gate On/Off bit
(Input register bit D0) for the respective output.
approaches the maximum allowable level, a thermal
warning signal will be triggered.
Note that this fault sets the FAULTZ pin low (active),
but does not disable the outputs or operation of the
chip.
D4 Charge Pump UVLO Bit The charge pump must
maintain a voltage guard band above VBB , in order
to charge the gates when commanded to turn on the
MOSFETs. If an undervoltage (UVLO) condition is
detected on the charge pump, the FAULTZ pin will be
set low (active), and all outputs will be disabled.
D1 through D4 Output Drains For each output chan-
nel, the voltage on the corresponding Dx pin is used
to evaluate STB and STG fault conditions. The A3942
compares the Dx voltage level to the VDS threshold of
the MOSFET to determine if a fault condition exists.
The trip voltage level is set by selecting an appropriate
value for the resistor, RDx, connected to the corre-
sponding current sink. Because both the Dx pins and
RDx are high impedance, each RDx must be placed
as close to the corresponding A3942 Dx pin as practi-
cable.
D5 WriteZ (Not Write) Bit In a written byte, D5 = 0.
D6, D7 Address Bits See description, above.
Pin Descriptions
In this section, the functions of the individual termi-
nals of the A3942 are described.
G1 through G4 Output Gates These pins drive the
gates of the high-side external MOSFETs. They source
voltage from VCP and sink to GND. The correspond-
ing external gate resistors, RGx, should be ≥ 2 kΩ
for consistent switching times between A3942s when
applicable (see IG(HI) and IG(LO) in the Electrical Char-
acteristics table).
VBB Supply Voltage (Power) The A3942 is fully
operational over the specified range of VBB. The exter-
nal MOSFETs must be supplied by the same voltage
source as the A3942. A bypass capacitor should be
placed as close as practicable to the A3942.
VDD Supply Voltage (Logic) Logic voltage must be
supplied to the A3942. The wide allowable range of
input voltages allows both 3.3 V and 5 V supplies. A
bypass capacitor should be placed as close as practi-
cable to the A3942.
If negative voltages are applied, Gx is clamped to
GND by internal diodes. Back-to-back Zener diodes
are internally connected between Gx and Sx.
Sx Output Sources These are used to measure the
source terminal of the external MOSFET. The pins
may be tied directly to the MOSFET. Although the Sx
pins can survive large negative transients, it is recom-
mended to connect a clamp diode between the Sx pin
and ground to limit any negative transients at the Sx
pin when a load is switched off. This helps to avoid
false fault detection caused by transient noise coupling
into adjacent channels which may not be switching
and therefore have no fault blanking during the tran-
sient. This is especially recommended when there is
significant wiring between the load and the Sx pin
even if the load incorporates a recirculation diode.
VCP Charge Pump The integrated charge pump is
used to generate a supply above VBB to drive the gates
of the external power MOSFETs. This tripler keeps the
part functional over a wide range of VBB.
CP1 through CP4 Charge Pump Capacitor Con-
nections These are the connections for the two exter-
nal capacitors that level-shift the charge up to VCP.
VREG Internal Linear Voltage Regulator This pro-
vides a connection for an external capacitor that sets
the regulation value for voltage supplied to internal
logic circuits.
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Quad High-Side Gate Driver
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A3942
RESETZ Master Reset and Sleep Mode Pulsing this be charged at typically 240μA until it reaches VREF
.
pin low clears all latched faults in the channel-specific The time taken to charge the capacitor will be approxi-
fault registers. It also clears the serial port registers
(they return to their default values). When RESETZ is
held low long enough (t > tSLEEP) the A3942 goes to
sleep, as described in the Sleep topic in the Functional
Description section.
mately:
tCHARGE = 5 × C
where tCHARGE is in μs and C is the capacitor value
in nF. At least twice this time should be allowed, after
power-on or after coming out of sleep mode, before
the A3942 is used to switch any loads.
ENB Enable Set low to actively pull low all outputs.
FAULTZ Fault Active low open drain output. Signals a
fault. Allows parallel connection with FAULTZ sig-
nals from other devices when required.
GND Ground All GND pins are internally fused to
the metal die pad to which the chip is soldered. This
allows for high thermal conductance through the GND
pins. Connecting to these pins to a PCB ground plane
improves thermal performance.
SCLK SPI Clock See Serial Port Operation topic in
Functional Description section.
CSZ SPI Chip Select input.
Functional Description
Power On When power is applied to either VDD or
VBB, the Output Fault register is initially loaded with
default values, all zeros (0). However, as individual
internal circuits are initially powered on, they may
latch spurious faults in the fault registers for each
channel. Therefore, before operating the A3942 all
fault registers must be cleared by pulsing the RESETZ
pin.
SDO SPI Data Output connection.
SDI SPI Data Input connection.
IREF Current Reference Defines the current used
as a reference to set gate drive currents, diagnostic
currents and internal timers. A resistor, RREF, con-
nected between the IREF pin and the adjacent GND
pin is selected to set the reference current to 20μA.
The IREF pin is a voltage source at a voltage, VREF
,
Sleep Mode This mode disables various internal cir-
cuits including the charge pump, VREG, and the logic
circuits. The serial port also is disabled. All Input and
Output Fault register bits are cleared.
of typically 1.2V. The resistor required is therefore
60.4kOhm, which is the standard resistor value that
provides a typical current closest to the 20μA target.
Any variation in RREF will affect the internal settings
as described in the section below on RREF selection.
Being a high impedance node, the IREF pin is suscep-
tible to external sources of noise and transients and
should be decoupled with a capacitor across RREF
between the IREF pin and the adjacent GND pin. The
capacitor value should be less than 100pF to avoid
any delay when power is first applied to the A3942
or when coming out of sleep mode. When control-
ling large load currents a larger capacitor may be
required to suppress any transient noise. At power-on
or when coming out of sleep mode this capacitor will
To leave sleep mode, pull RESETZ high and then
allow a delay for the charge pump to stabilize. Before
sending commands, clear any spurious faults as
described in the Power On topic.
Faults Faults are categorized either as system faults or
load faults. All faults are ORed to the FAULTZ pin.
System faults are VREG UVLO, CP UVLO, VDD
UVLO, and Thermal Warning. They are not latched in
the channel-specific self-protection circuit fault reg-
isters, however, the flags in the Output Fault register
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Quad High-Side Gate Driver
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A3942
bits D3, D4, and D5, are latched. If the fault condition • Daisy Chain Connection The master shifts n bytes
(eight bits each) during n × 8 clock cycles. Regard-
less of the position of an individual A3942 slave
in the daisy chain, the slaves shift the output byte
during the first eight clock cycles after CSZ goes
low. When CSZ goes high, the eight bits in the Shift
register are latched into the Input register.
is resolved, these flags are latched until they are read,
at which time they are cleared.
Load faults are OL, STB, and STG. They are latched
into the channel-specific self-protection circuit fault
registers, and shifted into Output Fault register bits
D0, D1, and D2 when called. Thus, load faults may be
masked or cleared on a channel-specific basis.
Serial Port Disabling Disable the serial port by set-
ting the CSZ pin high while in sleep mode. This loads
the Input register with default values, all zeroes (0).
Serial Port Operation
The serial port is compatible with the full duplex
Serial Peripheral Interface (SPI) conventions. The
inputs to the SPI port are logically ORed with the
discrete input pins, INx, settings. This allows indepen-
dent operation using only the discrete inputs, only the
serial inputs, or both. Timing is clocked by an on-
board 4 MHz oscillator.
Serial Port Error Handling Input data is discarded if
the number of bits in an input stream are not a mul-
tiple of eight. Furthermore, unless the number of clock
cycles is a multiple of eight while CSZ is active, any
bits shifted in from the SDI pin are discarded.
Input Register Operation After a valid byte is
latched into the Input register from the shift register,
bit D5 is evaluated to determine if the byte is to be
read. An inactive (0) bit value causes all other bits to
be ignored.
When a Chip Select event occurs, the Output Fault
register loads one eight-bit byte into the shift register,
and the byte is then shifted out through the SDO pin.
Simultaneously, bits at the SDI pin are shifted into the
shift register (full duplex). At the end of a Chip Select
event, the shift register contents are latched into the
Input register.
If bit D5 is active (1) the other bits are read and
decoded. Bits D6 and D7 are used to determine which
output channel is updated. Bits D0 through D4 set
the channel-specific operation, including clearing and
masking of faults.
Alternative Configurations Multiple A3942s can be
configured together.
Output Fault Register Operation This register is
loaded with fault data to be shifted out through the
SDO pin. No handshaking is required.
• Standalone Connection In this configuration, the
master simultaneously shifts eight bits in through
the SDI pin and shifts eight bits out of the SDO pin.
First, the CSZ pin is set low. Then, the Output Fault
register is loaded with the relevant fault byte (see
the Output Fault Register topic below). Eight clock
cycles are used to perform the shifts.
The Output Fault register contains data on active
faults. Four internal channel-specific fault registers
contain any latched fault data for each respective
channel. The following describes how the A3942
determines which channel-specific fault register to
transfer into the Output Fault register.
• Parallel Connection Because each slave has a CSZ
pin, operation is identical to the Standalone configu-
ration. When CSZ is inactive, SDI is “don’t care” and
SDO is high impedance.
• No Faults If there are no current faults, the Output
Fault register is loaded with all zeros:
0 0 0 0 0 0 0 0
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A3942
• Single Fault If there is only one fault detected, the
Output Fault register is filled to indicate that fault.
and the second CSZ writes:
1 1 0 0 0 0 0 1
For a load fault, the Address bits are set to indicate
the affected channel; for example, a short-to-battery
on channel 3 would be written:
In summary, all faults are retrieved by issuing con-
secutive CSZ events until the channel number stops
increasing.
1 0 0 0 0 0 1 0
• If there are no faults, this byte will be shifted out
each time:
On the other hand, for system faults, the Address bits
are irrelevant, and a CP UVLO fault would be loaded
as:
0 0 0 0 0 0 0 0
• If there are only system faults, this byte will be
shifted out each time:
0 0 0 1 0 0 0 0
with the Address bits defaulting to 0 0.
0 0 [1|0] [1|0] [1|0] 0 0 0
• Multiple System Faults If there are multiple system
faults, the Output Fault register is loaded with the
setting for each system fault (the Address bits re-
main irrelevant, as in the case of a single fault). For
example, when CP UVLO and Thermal Warning
faults both have occurred, the Output Fault register is
loaded with:
• If there are system faults and only one load fault, one
byte contains all of the fault data.
• If there are load faults on more than one channel,
these bytes would be shifted out in succession, and
any existing system faults will be indicated. For ex-
ample, if there were no system faults and load faults
on channels 2, 3, and 4, the following series of bytes
would be shifted out:
0 0 0 1 1 0 0 0
• Multiple System Faults and Single Channel Load
Fault If one or more system faults and one or more
load faults from a single channel have occurred, all
faults are loaded into the Output Fault register, with
the channel of the load faults indicated in the Address
bits. For example, a CP UVLO system fault and an
STG load fault on Channel 2 would be written as:
0 1 0 0 0 [1|0] [1|0] [1|0]
1 0 0 0 0 [1|0] [1|0] [1|0]
1 1 0 0 0 [1|0] [1|0] [1|0]
0 1 0 0 0 [1|0] [1|0] [1|0]
. . .
Applications
0 1 0 1 0 0 0 1
Unused Outputs When any of the four output chan-
nels are not used, the related pins should be connected
as follows:
• Multiple Channel Load Faults When load faults
occur on more than one channel, the data cannot be
signalled in a single SDO byte. However, the data
can still be retrieved. The A3942 polls each channel-
specific fault register, in ascending order by channel
number.
Unused Channel Pin
Connection
GND
INx
Sx
GND
Dx
Gx
VBB
Each output is delimited by the appropriate CSZ
event. For example, assume an OL on channel 2 and
an STG on Channel 4. The first CSZ event writes:
Floating
RREF Selection The tolerance on RREF can be
0 1 0 0 0 1 0 0
as high as ±4%. Depending on how a specific part
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Quad High-Side Gate Driver
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A3942
changes over temperature changes and lifetime, the
±4% range generally covers nominal 1% resistors.
low VBB levels, the only repercussion is a nuisance
STB fault, and this only occurs when an OL condi-
tion exists. The limit on VDx can be ignored either if
the off-state faults are masked or if it is acceptable to
latch the nuisance fault and clear it when the OL fault
is cleared.
The parameters which are affected by changes in
RREF are listed in the following table:
Change as RREF Tolerance
Parameter
Increases
Decreases
Because VOS << VOL , a fault is registered if
IREF
tRESET
–
+
+
+
–
–
+
+
–
–
–
+
+
–
IOL × RL // RGS > VOL
.
tSLEEP
Hence, the trip level, RL(trip) is:
tWAKE
–1
1
I
⎛
⎛
OL
⎜
⎜
⎜
⎜
–
IG(HI) and IG(LO)
IOL
R (trip)
=
L
VOL RGS
⎝
⎝
tON and tOFF
The OL circuit and its tolerances are designed to
ensure that external loads above 50 kΩ are identified
as open load and that loads below 10 kΩ are identified
as valid. Note that these numbers are valid in steady
state. As a result, blanking times must be set appropri-
ately for a given load.
Setting Fault Circuit Trip Levels The load faults,
Short-to-Battery (STB), Short-to-Ground (STG), and
Open Load (OL), are all latched. The thresholds for
STG and OL faults can be set by the value for the RDx
resistor.
Under normal conditions, when the external MOSFET
is off, and the load is in circuit,
Open Load Fault Level When the gate is commanded
off, a commanded current, IOL, is sourced to Sx to
detect if the load is still in the circuit. VOL is compared
to
IOL × RL < VOL.
Short-to-Battery Fault Level The STB comparator
compares the load voltage
IOL × [RL // RGS]
IOL × RL // RGS]
to evaluate an OL fault.
to the voltage set by RDx,
If the load has been removed, VSx exceeds VOL and
a fault is registered. VSx would drift to VBB when an
open load exists and thereby inadvertantly trip a nui-
sance STB fault. To prevent this, the Sx pin is clamped
V
BB –ID × RD .
The comparator is active only when the gate is com-
manded off.
to VCLAMP
.
During an STB condition, IOL = 0 because the current
source has run out of headroom. A fault is registered
when
The operating limits specified in the Electrical Char-
acteristics table allow the fault circuitry to distinguish
all faults within the operating range of VBB. If, how-
ever, the specified limits on VDx are too restrictive at
VL > VBB –ID × RD ± VOS.
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A3942
Power Limits
That is, the load voltage is within ∆V = ID × RD volts
of VBB.
Power dissipation, PD, is limited by thermal con-
straints. The maximum junction temperature, TJ(max),
and the thermal resistance, RθJA, are given in this
datasheet. The maximum allowed power is then found
for a given ambient, TA, from this equation:
Using VDS = VBB – VL and rearranging, we find that
VDS < ID × RD ± VOS .
Therefore,
RD = (VDS(trip) ±VOS) / ID ,
TJ = PD × RθJA + TA , or
PD = (TJ – TA) / RθJA
.
which is also the case for STG faults, described below.
Note that an STB condition generally latches the OL
flag as well.
The three main contributions to power dissipation are:
• quiescent supply, PBB(Q)
• driver outputs, PDRV , and
Under normal conditions RL << RGS and IOL flows
through the load, given
• logic level supply, PDD
.
IOL × (RD + RL ) < VBB –ID × RD ± VOS .
These three terms appear in the following equation:
Because IOL × (RD + RL ) ≈ 0 when the external
MOSFET is off, no fault is registered.
PD = PBB(Q) + PDRV + PDD
.
The quiescent supply current leads to a baseline power
loss:
Short-to-Ground Fault Level The effect of the STG
comparator is to compare the external MOSFET VDS
(VL) to the set trip voltage VBB –ID × RD .
PBB(Q) = VBB × IBB(Q)
.
The comparator is active only when the gate is com-
manded on. Also, the sourced current IOL is deacti-
vated.
In general, the losses in a driver can be quantified as
follows. Given that the driver current leaves Gx to
charge a gate, and assuming that the external circuit
is approximately lossless, then the same charge is
sunk back into Gx. Therefore, all driver current can be
treated as going to heat the chip.
If VDS is too large, an STG fault is registered when
VL < VBB –ID × RD ± VOS
,
or, because the external MOSFET VDS = VBB – VL,
VDS > ID × RD ± VOS .
Total current into VBB includes the quiescent current,
IBB(Q) , plus additional current, ∆IBB, to energize the
gates. The latter is three times the average gate cur-
rent:
Therefore, the STG trip level in the on state is the
same as the STB level in the off state:
RD = (VDS(trip) ±VOS) / ID .
Converse to the preceding, in normal operation
VL > VBB –ID × RD ± VOS,
or
∆IBB = 3 × IGx(av).
The average load current is calculated using the gate
charge, QG , from the external MOSFET datasheet and
the switching frequency:
VDS < ID × RD ± VOS .
IGx(av) = fsw × QG .
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Quad High-Side Gate Driver
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A3942
If all four outputs are supplying this current,
∆IBB = 4 (3 × IGx) = 12 × fSW × QG,
and
• Use both bulk storage capacitors (for example, elec-
trolytic) and low impedance bypass capacitors (for
example, ceramic) on all supply pins. See the Func-
tional Block Diagram for recommended values.
P
DRV = VBB × ∆IBB = 12 × fSW × QG × VBB
Finally, loss in the logic circuits is
DD = VDD × IDD.
.
• Input and output lines should not be in close proxim-
ity. If they do overlap, it should be at right angles.
• Use ample copper in the ground and power paths.
Use planes or fills where possible.
P
Example:
• The A3942 ground and VBB supply should be star-
connected to the power ground and supply.
Find the junction temperature with one IRFZ44ES
MOSFET at each output, being switched at 5 kHz, and
given VBB = 14 V and VDD = 5.5 V.
• The trace connecting the RDx resistors to the A3942
Dx pins should be as short as possible.
Answer: The IRFZ44ES datasheet gives QG(max)
= 60 nC (note that this parameter depends on circuit
design constraints, such as VDS). The Electrical Char-
acteristics table gives the following maximum values
for the A3942: IBB(Q) = 10 mA, VDD = 5.5 V, and IDD
= 3 mA.
• The trace leaving the other side of the RDx resistors
can be long because it has a low impedance path to
ground; however, it must run independently to the re-
spective external MOSFET in order to make a Kelvin
connection.
• All support capacitors are to be referenced to the
A3942 ground plane or ground fill. Minimize loop
area of traces.
First, calculate total power loss:
PD = VBB IBB(Q) + 12 fswQGVBB+VDD DD
= 14 V × 11 mA
+ 4 × 3 × 5 kHz ×60 nC × 14 V
+ 5.5 V × 3 mA
= 221 mW .
I
• These traces should be as wide as practicable: VBB,
VDD, VREG, VCP, and Gx. Secondarily, it is also
preferred that the traces to the charge pump caps be
as wide as practicable. In both cases, the number of
vias should be minimized.
Then, the junction temperature can be found for a
given ambient temperature; TA = 125°C is assumed
here. Thermal resistance depends significantly on the
board design; RθJA = 100 °C/W is assumed here. Sub-
stituting these values:
• Minimize the distance connecting to ground pins in
order to minimize ground loops.
TJ = PD × RθJA + TA
= 221 mW × 100 °C/W + 125°C
= 147°C .
Finally, a note about thermals. Because the A3942
ground pins are internally fused to the die mounting
pad, they are the main path for heat dissipation. In
applications producing high junction temperatures,
care must be given to designing the thermal path. For
example, multiple thermal vias should be run from
ground pins down to the ground plane. If space allows,
wide traces from ground pins to exposed copper fills
on the top layer efficiently release heat through con-
vection cooling.
LAYOUT AND COMPONENTS
General good practices should be followed. In addi-
tion, the following are recommended:
• Locate bypass capacitors (VBB, VDD, VREG, and
IREF) as close to the A3942 as practicable.
• Traces to bypass capacitors should be as wide as
practicable; minimize the number of vias.
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Quad High-Side Gate Driver
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A3942
Terminal List
No.
Name
Pin Description
1
SDO
Serial Data Out
Serial Data In
Serial Clock
2
SDI
3
SCLK
CSZ
4
Chip Select – NOT
Fault – NOT (Open Drain)
5
FAULTZ
6
RESETZ Reset – NOT (Discrete)
7
ENB
VDD
IREF
GND
IN2
Enable (Discrete)
Logic Supply
8
9
Current Reference Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Discrete Input Channel 2
Discrete Input Channel 1
Channel 2: Drain
IN1
D2
D1
Channel 1: Drain
GND
S1
Channel 1: Source
Channel 1: Gate
Channel 2: Gate
Channel 2: Source
Channel 3: Source
Channel 3: Gate
Channel 4: Gate
Channel 4: Source
G1
G2
S2
S3
G3
G4
S4
GND
D3
Channel 3: Drain
D4
Channel 4: Drain
IN3
Discrete Input Channel 3
Discrete Input Channel 4
Internal Regulator
Power Supply
IN4
VREG
VBB
GND
VCP
CP1
CP3
CP2
CP4
GND
GND
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
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Quad High-Side Gate Driver
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A3942
LG Package, 38-Pin TSSOP
1.60
38
9.70 ±0.10
0.50
4º
0.30
38
+0.06
–0.05
0.15
4.40 ±0.10
6.40 ±0.20
6.00
A
1
2
1
2
0.25
B
PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
38X
C
All dimensions nominal, not for tooling use
(reference JEDEC MO-153 BD-1)
Dimensions in millimeters
SEATING
PLANE
0.10
C
Pins 10, 15, 24, 31, 37, and 38 fused internally
0.22 ±0.05
0.50
1.20 MAX
0.10 ±0.05
A
B
Terminal #1 mark area
Reference pad layout (reference IPC SOP50P640X110-38M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2008-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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相关型号：
A3942KLG-T
Buffer/Inverter Based Peripheral Driver, PDSO38, 1.20 MM HEIGHT, LEAD FREE, MO-153BD-1, TSSOP-38
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