A3959SLBTR-T [ALLEGRO]
Stepper Motor Controller, 6A, NMOS, PDSO24, LEAD FREE, MS-013AD, SOIC-24;
| 型号： | A3959SLBTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Stepper Motor Controller, 6A, NMOS, PDSO24, LEAD FREE, MS-013AD, SOIC-24 电动机控制 光电二极管 |
| 文件： | 总12页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3959
DMOS Full-Bridge PWM Motor Driver
Features and Benefits
▪ ±3 A, 50 V Output Rating
▪ Low rDS(on) Outputs (270 m, Typical)
Description
Designedforpulsewidthmodulated(PWM)currentcontrolof
DCmotors, theA3959iscapableofoutputcurrentsto±3Aand
▪ Mixed, Fast, and Slow Current-Decay Modes
▪ Synchronous Rectification for Low Power Dissipation
▪ Internal UVLO and Thermal-Shutdown Circuitry
▪ Crossover-Current Protection
operatingvoltagesto50V.Internalfixedoff-timePWMcurrent-
control timing circuitry can be adjusted via control inputs to
operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externallyappliedPWM-controlsignals.Internalsynchronous
rectification control circuitry is provided to reduce power
dissipation during PWM operation.
▪ Internal Oscillator for Digital PWM Timing
Packages:
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge
pump, and crossover-current protection. Special power-up
sequencing is not required.
Package B, 24-pin DIP
with exposed tabs
TheA3959providesachoiceofthreepowerpackages,a24-pin
DIP with batwing tabs (package suffix ‘B’), a 24-lead SOIC
with four internally-fused pins (package suffix ‘LB’), and a
thin (<1.2 mm) 28-pin TSSOP with an exposed thermal pad
(suffix ‘LP’). In all cases, the power pins and tabs are at ground
potential and need no electrical isolation. Each package is lead
(Pb) free, with 100% matte tin leadframes.
Package LB, 24-pin SOIC
with internally fused pins
Package LP, 28-pin TSSOP
with exposed thermal pad
Not to scale
Functional Block Diagram
VBB
VDD
+
LOGIC
SUPPLY
LOAD
SUPPLY
CHARGE PUMP
BANDGAP
VREG
CHARGE
PUMP
UNDER-
VOLTAGE &
FAULT DETECT
BANDGAP
REGULATOR
V
DD
REG
TSD
TO VDD
C
SLEEP
OUT
A
B
EXT MODE
PHASE
CONTROL LOGIC
ENABLE
OUT
SENSE
TO VDD
CS
ZERO
CURRENT
DETECT
BLANK
PFD1
PFD2
PWM
TIMER
RS
CURRENT
SENSE
OSC
ROSC
REFERENCE
BUFFER &
REF
w10
VREF
Dwg. FP-048-2A
29319.37L
A3959
DMOS Full-Bridge PWM Motor Driver
Selection Guide
Part Number
A3959SB-T
Package
24-pin DIP with exposed tabs
Packing
15 per tube
A3959SLBTR-T
A3959SLPTR-T
24-pin SOIC with internally fused pins
28-pin TSSOP with exposed thermal pad
1000 per reel
4000 per reel
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
Units
Load Supply Voltage
50
V
V
V
V
V
V
V
Logic Supply Voltage
VDD
7.0
Continuous
tw < 30 ns
Continuous
tw < 3 μs
–0.3 to VDD + 0.3
Input Voltage
VIN
–1.0 to VDD + 1.0
0.5
2.5
Sense Voltage
VS
Reference Voltage
VREF
VDD
Output current rating may be limited by duty cycle, am-
bient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating
or a junction temperature of 150°C.
Repetitive
±3.0
±6.0
A
A
Output Current
IOUT
Peak, < 3 μs
Package Power Dissipation
PD
TA
See Thermal Characteristics
Range S
–
–
Operating Ambient Temperature
–20 to 85
ºC
Fault conditions that produce excessive junction temperature will activate
Maximum Junction Temperature
Storage Temperature
TJ(max) the device’s thermal shutdown circuitry. These conditions can be toler-
ated but should be avoided.
150
ºC
ºC
Tstg
–55 to 150
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
Thermal Characteristics
Characteristic
Symbol
Test Conditions
Value
3.3
2.5
3.1
54
Units
W
B package
LB package
LP package
Package Power Dissipation
PD
W
W
1-layer PCB, minimal exposed copper area
2-layer PCB, 1-in2. 2-oz copper exposed area
4-layer PCB, based on JEDEC standard
1-layer PCB, minimal exposed copper area
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
B Package
36
26
77
Package Thermal Resistance, Junction
to Ambient
RθJA
LB Package 2-layer PCB, 1-in2. 2-oz copper exposed area
4-layer PCB, based on JEDEC standard
51
35
1-layer PCB, minimal exposed copper area
100
40
LP Package 2-layer PCB, 1-in2. 2-oz copper exposed area
4-layer PCB, based on JEDEC standard
28
Package Thermal Resistance, Junction
to Tab
RθJT
RθJP
B and LB packages
LP package
6
2
ºC/W
ºC/W
Package Thermal Resistance, Junction
to Pad
*Additional thermal information available on Allegro website.
5
SUFFIX 'B', RQJA = 26oC/W
SUFFIX 'LP', RQJA = 28oC/W
SUFFIX 'LB', RQJA = 35oC/W
4-LAYER BOARD
4
3
2
1
0
SUFFIX 'B', RQJA = 36oC/W
SUFFIX 'LP', RQJA = 40oC/W
SUFFIX 'LB', RQJA = 51oC/W
2-LAYER BOARD,
1 SQ. IN. COPPER EA. SIDE
25
50
75
100
125
150
o
TEMPERATURE IN C
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise)
Characteristics
Output Drivers
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Operating
9.5
0
–
–
50
50
V
V
Load Supply Voltage Range
Output Leakage Current
VBB
During sleep mode
VOUT = VBB
–
<1.0
<-1.0
270
270
600
–
20
μA
μA
mΩ
mΩ
ns
IDSS
VOUT = 0 V
–
-20
300
300
1000
1.6
1.6
7.0
5.0
20
Source driver, IOUT = -3 A
Sink driver, IOUT = 3 A
–
Output On Resistance
Crossover Delay
rDS(on)
–
300
–
Source diode, IF = -3 A
Sink diode, IF = 3 A
fPWM < 50 kHz
V
Body Diode Forward Voltage
VF
–
–
V
–
4.0
2.0
–
mA
mA
μA
Load Supply Current
IBB
Charge pump on, outputs disabled
Sleep mode
–
–
Control Logic
Logic Supply Voltage Range
VDD
VIN(1)
VIN(0)
IIN(1)
IIN(0)
Operating
4.5
2.0
–
5.0
–
5.5
–
V
V
Logic Input Voltage
–
0.8
20
V
VIN = 2.0 V
–
<1.0
<-2.0
6.0
–
μA
μA
mA
mA
μA
μA
MHz
MHz
V
Logic Input Current
(all inputs except ENABLE)
VIN = 0.8 V
–
-20
10
fPWM < 50 kHz
Sleep mode
VIN = 2.0 V
–
Logic Supply Current
ENABLE Input Current
Internal OSC frequency
IDD
–
2.0
100
40
IIN(1)
IIN(0)
–
40
VIN = 0.8 V
–
16
ROSC shorted to GROUND
ROSC = 51 kΩ
Operating
3.25
3.65
0.0
–
4.25
4.25
–
5.25
4.85
VDD
±1.0
–
fOSC
Reference Input Volt. Range
Reference Input Current
VREF
IREF
VIO
VREF = VDD
–
μA
mV
Comparator Input Offset Voltage
VREF = 0 V
–
±5.0
Continued next page …
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise)
Characteristics
Symbol
Test Conditions
Min.
Typ.
10
–
Max.
–
Units
–
Reference Divider Ratio
–
–
–
–
VREF = VDD
±4.0
±14
%
Gm Error
(Note 3)
EGm
VREF = 0.5 V
–
%
0.5 Ein to 0.9 Eout
:
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
600
50
750
150
750
100
165
15
1200
350
1200
150
–
ns
ns
ns
ns
°C
°C
V
Propagation Delay Times
tpd
600
50
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
TJ
–
∆TJ
–
–
UVLO
∆UVLO
Increasing VDD
3.90
0.05
4.2
4.45
–
0.10
V
NOTES:
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. Gm error = ([VREF/10] – VSENSE)/(VREF/10) where VSENSE = ITRIP•RS.
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high, slow
decay mode, both sink drivers are on with ENABLE low.
VREG. This internally generated voltage is used to operate
the sink-side DMOS outputs. The VREG terminal should
be decoupled with a 0.22 μF capacitor to ground. VREG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than VBB to drive the source-
side DMOS gates. A 0.22 μF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22 μF ceramic capacitor should be connected between
CP and VBB to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
EXT MODE
Decay
0
1
Fast
Slow
Current Regulation. Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (RS) and the
applied analog reference voltage (VREF):
PHASE Logic. The PHASE input terminal determines if
the device is operating in the “forward” or “reverse” state.
ITRIP = VREF/10RS
PHASE
OUTA
OUTB
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fixed off-time period. The current path during recirculation
is determined by the configuration of slow/mixed/fast
current-decay mode via PFD1 and PFD2.
0
1
Low
High
Low
High
ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the ROSC
terminal to VDD. Typical value of 4 MHz is set with a
51 kΩ resistor. The allowable range of the resistor is from
20 kΩ to 100 kΩ.
ENABLE
Outputs
fOSC = 204 x 109/ROSC
.
0
1
Chopped
On
If ROSC is not pulled up to VDD, it must be shorted to
ground.
Fixed Off Time. The A3959 is set for a fixed off time of
96 cycles of the internal oscillator, typically 24 μs with a
4 MHz oscillator.
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
the appropriate pair of DMOS outputs during the current
decay and effectively short out the body diodes with the
low rDS(on) driver. This will reduce power dissipation
significantly and can eliminate the need for external
Schottky diodes.
Internal Current-Control Mode. Inputs PFD1 and
PFD2 determine the current-decay method after an
overcurrent event is detected at the SENSE input. In slow-
decay mode, both sink drivers are turned on for the fixed
off-time period. Mixed-decay mode starts out in fast-decay
mode for a portion (15% or 48%) of the fixed off time, and
then is followed by slow decay for the remainder of the
period.
Synchronous rectification will prevent reversal of load
current by turning off all outputs when a zero-current level
is detected.
PFD2
PFD1
% toff
Decay
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on CP or VREG) the outputs of
the device are disabled until the fault condition is removed.
At power up, and in the event of low VDD, the UVLO
circuit disables the drivers.
0
0
1
1
0
1
0
1
0
Slow
Mixed
Mixed
Fast
15
48
100
Braking. The braking function is implemented by
driving the device in slow-decay mode via EXTMODE
and applying an enable chop command. Because it is
possible to drive current in either direction through the
DMOS drivers, this configuration effectively shorts out
the motor-generated BEMF as long as the ENABLE
chop mode is asserted. It is important to note that the
internal PWM current-control circuit will not limit the
current when braking, because the current does not flow
through the sense resistor. The maximum brake current
can be approximated by VBEMF/RL. Care should be taken
to ensure that the maximum ratings of the device are not
exceeded in worst-case braking situations of high speed
and high inertial loads.
PWM Blank Timer. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents
of the clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable latch,
the sense comparator is blanked. The blank timer runs
after the off-time counter to provide the blanking function.
The blank timer is reset when ENABLE is chopped or
PHASE is changed. For external PWM control, a PHASE
change or ENABLE on will trigger the blanking function.
The duration is determined by the BLANK input and the
oscilator.
BLANK
tblank
SLEEP Logic. The SLEEP input terminal is used to
minimize power consumption when when not in use.
This disables much of the internal circuitry including the
regulator and charge pump. Logic low will put the device
into sleep mode, logic high will allow normal operation.
0
1
6/fosc
12/fosc
Synchronous Rectification. When a PWM off cycle
is triggered, either by an ENABLE chop command or
internal fixed off-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A3959 synchronous rectification feature will turn on
Note: If the sleep mode is not used, connect a 5 kΩ pull-
up resistor between the SLEEP terminal and VDD
.
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
Current Sensing. To minimize inaccuracies in
sensing the ITRIP current level, which may be caused by
ground trace IR drops, the sense resistor should have an
independent ground return to the ground terminal of the
device. For low-value sense resistors the IR drops in the
PCB sense resistor’s traces can be significant and should
be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their
contact resistance.
Layout. A star ground system located close to the driver
is recommended. The printed wiring board should use a
heavy ground plane. For optimum electrical and thermal
performance, the driver should be soldered directly onto
the board. The ground side of RS should have an indi-
vidual path to the ground terminals of the device. This path
should be as short as is possible physically and should not
have any other components connected to it. It is recom-
mended that a 0.1 μF capacitor be placed between SENSE
and ground as close to the device as possible; the load sup-
ply terminal, VBB, should be decoupled with an electrolyt-
ic capacitor (> 47 μF is recommended) placed as close to
the device as is possible. On the 28-lead TSSOP package,
the copper ground plane located under the exposed thermal
pad is typically used as a star ground.
The maximum value of RS is given as RS = 0.5/ITRIP
.
Thermal Protection. Circuitry turns off all drivers
when the junction temperature reaches 165°C typically. It
is intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has
a hysteresis of approximately 15°C.
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
Package B (DIP)
Package LB (SOIC)
Package LP (TSSOP)
CP
2
CP
28
27
26
25
24
23
22
21
1
2
24
23
22
CP
CP
CP
1
2
3
4
GROUND
VREG
CP
24
VREG
1
2
3
4
CHARGE PUMP
2
CP
1
VREG
CP
2
23 SLEEP
SLEEP
1
ı
θ
NO
22
SLEEP
PHASE
ROSC
3
4
CP
1
NC
CONNECTION
NO
NC
BB
NC
PHASE
CONNECTION
Q
21 OUT
B
PHASE
ROSC
21
20
OUTB
Q
OUTB
5
6
LOAD
SUPPLY
V
GROUND
GROUND
5
6
7
8
20
BB
V
5
6
7
8
LOAD SUPPLY
V
BB
LOAD SUPPLY
ROSC
19 GROUND
GROUND
19 GROUND
18 GROUND
NC
7
8
GROUND
18
SENSE
NC
GROUND
GROUND
GROUND
GROUND
GROUND
V
20
19
18
LOGIC SUPPLY
9
DD
17 SENSE
LOGIC SUPPLY
V
SENSE
16 OUT
DD
17
NC
ENABLE 10
LOGIC
SUPPLY
9
V
OUTA
16
15
14
13
DD
ENABLE
A
9
OUTA
NC
11
12
NO
EXT MODE
REF
ENABLE
10
11
NC
PFD2
15
14
13
10
NO
CONNECTION
17
16
PFD2
NC
CONNECTION
÷10
PFD
2
EXT MODE
REF
BLANK 11
PFD 12
EXT MODE
REF
BLANK
PFD1
13
14
÷
10
PWM TIMER
÷10
PFD
1
BLANK 12
15
1
Dwg. PP-069-5A
Dwg. PP-069-4
Terminal List
Terminal Name
Terminal Description
Reservoir capacitor (typically 0.22 μF)
B (DIP)
LB (SOIC)
LP (TSSOP)
CP
24
1
2 & 3
—
1
2 & 3
4
CP1 & CP2
NC
The charge pump capacitor (typically 0.22 μF)
No (internal) connection
1 & 2
—
PHASE
Logic input for direction control
Oscillator resistor
3
4
5
ROSC
4
5
6
GROUND
LOGIC SUPPLY
ENABLE
NC
Grounds
5, 6, 7, 8*
6, 7
8
7, 8*
9
VDD, the low voltage (typically 5 V) supply
Logic input for enable control
No (internal) connection
9
10
–
9
10
11
–
PFD2
Logic-level input for fast decay
Logic-level input for blanking control
Logic-level input for fast decay
VREF, the load current reference input voltage
Logic input for PWM mode control
No (Internal) connection
11
10
11
12
13
14
15
16
–
12
13
14
15
16
17
18
19, 20
21
22
—
BLANK
12
13
14
15
—
PFD1
REF
EXT MODE
NO CONNECT
OUTA
One of two DMOS bridge outputs to the motor
No (internal) connection
16
–
NC
SENSE
Sense resistor
17
–
17
–
NC
No (internal) connection
GROUND
LOAD SUPPLY
OUTB
Grounds
18, 19*
20
21
—
18, 19
20
21
22
23
24
—
VBB, the high-current, 9.5 V to 50 V, motor supply
One of two DMOS bridge outputs to the motor
No (Internal) connection
23
24
25
26
27
28*
NO CONNECT
SLEEP
Logic-level Input for sleep operation
Regulator decoupling capacitor (typically 0.22 μF)
Ground
22
23
—
VREG
GROUND
* For the B (DIP) package only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5
and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. For the LP (TSSOP) package, the grounds at terminals 7, 8, and 28
should be connected together at the exposed pad beneath the device.
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
B package 24-pin DIP
+0.25
30.10
–0.64
24
+0.10
0.38
–0.05
+0.76
–0.25
+0.38
10.92
–0.25
6.35
7.62
A
1
2
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
5.33 MAX
+0.51
3.30
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
–0.38
1.27 MIN
A
2.54
Terminal #1 mark area
+0.25
–0.38
1.52
0.018
0.46 ±0.12
LB package 24-pin SOICW
15.40±0.20
4° ±4
0.27
24
+0.07
–0.06
2.20
10.30±0.33
7.50±0.10
9.60
A
2
+0.44
–0.43
0.84
0.25
1
0.65
1.27
PCB Layout Reference View
B
24X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10
C
0.41 ±0.10
1.27
2.65 MAX
0.20 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
LP package 28-pin TSSOP
0.45
9.70 ±0.10
0.65
28
4° ±4
28
+0.05
–0.06
1.65
0.15
B
4.40 ±0.10 6.40 ±0.20
3.00
6.10
3.00
0.60 ±0.15
(1.00)
A
1
2
5.00
0.25
1
2
5.00
C
28X
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10
C
C
PCB Layout Reference View
+0.05
–0.06
1.20 MAX
0.10 MAX
0.25
0.65
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
C
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3959
DMOS Full-Bridge PWM Motor Driver
Copyright ©2001-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
相关型号：
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Stepper Motor Controller, 6A, NMOS, PDSO28, 1.20 MM HEIGHT, LEAD FREE, MO-153AET, TSSOP-28
ALLEGRO
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