A3959 [ALLEGRO]
DMOS FULL-BRIDGE PWM MOTOR DRIVER; DMOS全桥PWM电机驱动器
| 型号： | A3959 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | DMOS FULL-BRIDGE PWM MOTOR DRIVER |
| 文件： | 总12页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3959
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3959SB, A3959SLB, and A3959SLP are capable of
output currents to ±3 A and operating voltages to 50 V. Internal fixed
off-time PWM current-control timing circuitry can be adjusted via
control inputs to operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.
The A3959SB/SLB/SLP is a choice of three power packages, a
24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), a
24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’),
and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal
pad (suffix ‘LP’). In all cases, the power tab is at ground potential and
needs no electrical isolation. Each package is available in a lead-
free version (100% matte tin leadframe).
A3959SLB (SOIC)
CP
24
VREG
1
2
3
4
CP
2
23 SLEEP
NO
22
CP
1
NC
BB
CONNECTION
θ
PHASE
ROSC
21
OUT
B
V
20
19
18
5
6
7
8
LOAD SUPPLY
GROUND
GROUND
SENSE
GROUND
GROUND
LOGIC SUPPLY
V
DD
17
9
9
ENABLE
16 OUTA
NO
CONNECTION
NC
PFD
2
15
14
13
10
EXT MODE
REF
BLANK 11
PFD 12
÷
10
1
Dwg. PP-069-4
Note that the A3959SLB(SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ......................... 50 V
Output Current, IOUT (Repetitive) ........... ±3.0 A
(Peak, <3 µs)................................... ±6.0 A
Logic Supply Voltage, VDD ....................... 7.0 V
Logic Input Voltage Range, VIN
(Continuous)............ -0.3 V to VDD + 0.3 V
(tw <30 ns) ............... -1.0 V to VDD + 1.0 V
Sense Voltage, VS (Continuous) .............. 0.5 V
(tw <3 µs) ........................................... 2.5 V
Reference Voltage, VREF ............................ VDD
Package Power Dissipation (TA = 25°C), PD
A3959SB ........................................ 3.3 W*
A3959SLB ...................................... 2.5 W*
A3959SLP ...................................... 3.1 W*
Operating Temp. Range, TA .... -20°C to +85°C
Junction Temperature, TJ ..................... +150°C
Storage Temp. Range, TS ..... -55°C to +150°C
FEATURES
■ ±3 A, 50 V Output Rating
■ Low rDS(on) Outputs (270 mΩ, Typical)
■ Mixed, Fast, and Slow Current-Decay Modes
■ Synchronous Rectification for Low Power Dissipation
■ Internal UVLO and Thermal-Shutdown Circuitry
■ Crossover-Current Protection
■ Internal Oscillator for Digital PWM Timing
Always order by complete part number:
Part Number
A3959SB
Package
24-pin batwing DIP
24-pin batwing DIP; Lead-free
24-lead batwing SOIC
24-lead batwing SOIC; Lead-free
28-lead thin shrink SOIC
RθJA
*
RθJT
38°C/W 6°C/W
38°C/W 6°C/W
50°C/W 6°C/W
50°C/W 6°C/W
A3959SB-T
A3959SLB
A3959SLB-T
A3959SLP
A3959SLP-T
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
40°C/W
—
—
28-lead thin shrink SOIC; Lead-free 40°C/W
* Double-sided board, one square inch copper each side. See also, Layout, page 7.
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
VBB
VDD
+
LOGIC
SUPPLY
LOAD
SUPPLY
CHARGE PUMP
BANDGAP
VREG
CHARGE
PUMP
UNDER-
VOLTAGE &
FAULT DETECT
BANDGAP
REGULATOR
V
DD
REG
TSD
C
SLEEP
OUT
A
B
EXT MODE
PHASE
CONTROL LOGIC
ENABLE
OUT
SENSE
TO VDD
CS
ZERO
CURRENT
DETECT
BLANK
PFD1
PFD2
PWM
TIMER
RS
CURRENT
SENSE
OSC
ROSC
REFERENCE
BUFFER &
REF
÷10
VREF
Dwg. FP-048-2A
CP
2
CP
1
2
24
23
22
21
CHARGE PUMP
CP
1
VREG
θ
SLEEP
PHASE
ROSC
3
4
OUT
B
LOAD
SUPPLY
V
GROUND
GROUND
5
6
7
8
20
19
18
A3959SB (DIP)
BB
Note that the A3959SLB (SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
GROUND
GROUND
GROUND
GROUND
17 SENSE
LOGIC
SUPPLY
9
V
OUTA
16
15
14
13
DD
EXT MODE
REF
ENABLE
10
11
÷
10
PFD
2
PWM TIMER
PFD
1
BLANK 12
Dwg. PP-069-5A
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2001, 2003 Allegro MicroSystems, Inc.
2
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise)
Limits
Characteristics
Symbol Test Conditions
Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range
VBB
Operating
9.5
0
–
–
50
50
V
V
During sleep mode
VOUT = VBB
Output Leakage Current
Output On Resistance
IDSS
–
<1.0 20
<-1.0 -20
270 300
270 300
µA
µA
mΩ
mΩ
ns
VOUT = 0 V
–
rDS(on) Source driver, IOUT = -3 A
Sink driver, IOUT = 3 A
–
–
Crossover Delay
300 600 1000
Body Diode Forward Voltage
VF
Source diode, IF = -3 A
Sink diode, IF = 3 A
fPWM < 50 kHz
–
–
–
–
–
–
–
1.6
1.6
7.0
5.0
20
V
V
Load Supply Current
IBB
4.0
2.0
–
mA
mA
µA
Charge pump on, outputs disabled
Sleep Mode
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
VDD
VIN(1)
VIN(0)
IIN(1)
IIN(0)
IIN(1)
IIN(0)
fOSC
Operating
4.5
2.0
–
5.0
–
5.5
–
V
V
–
0.8
V
Logic Input Current
(all inputs except ENABLE)
VIN = 2.0 V
–
<1.0 20
<-2.0 -20
µA
µA
µA
µA
MHz
MHz
V
VIN = 0.8 V
–
ENABLE Input Current
VIN = 2.0 V
–
40
16
100
40
VIN = 0.8 V
–
Internal OSC frequency
ROSC shorted to GROUND
ROSC = 51 kΩ
Operating
3.25 4.25 5.25
3.65 4.25 4.85
Reference Input Volt. Range
Reference Input Current
VREF
IREF
VIO
0.0
–
–
–
VDD
±1.0
–
VREF = VDD
µA
mV
Comparator Input Offset Volt.
VREF = 0 V
–
±5.0
Continued next page …
www.allegromicro.com
3
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise), continued.
Limits
Characteristics
Control Logic
Symbol Test Conditions
Min. Typ. Max. Units
Reference Divider Ratio
Gm Error
–
–
–
–
10
–
–
–
EGm
VREF = VDD
±4.0
±14
%
%
(Note 3)
VREF = 0.5 V
–
Propagation Delay Times
tpd
0.5 Ein to 0.9 Eout:
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
600 750 1200
50 150 350
600 750 1200
ns
ns
ns
ns
50
100 150
Thermal Shutdown Temp.
TJ
–
165
15
–
–
°C
°C
V
Thermal Shutdown Hysteresis
∆TJ
–
UVLO
Enable
ThresholdUVLO Increasing
V
3.90 4.2 4.45
DD
UVLO Hysteresis
∆UVLO
0.05 0.10
–
V
Logic Supply Current
IDD
fPWM < 50 kHz
Sleep Mode
–
–
6.0
–
10
2.0
mA
mA
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. Gm error = ([VREF/10] – VSENSE)/(VREF/10) where VSENSE = ITRIP•RS.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high,
slow decay mode, both sink drivers are on with ENABLE
low.
VREG. This internally generated voltage is used to operate
the sink-side DMOS outputs. The VREG terminal should
be decoupled with a 0.22 µF capacitor to ground. VREG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than VBB to drive the source-
side DMOS gates. A 0.22 µF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22 µF ceramic capacitor should be connected between
CP and VBB to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
EXT MODE
Decay
Fast
0
1
Slow
Current Regulation. Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (RS) and the
applied analog reference voltage (VREF):
PHASE Logic. The PHASE input terminal determines if
the device is operating in the “forward” or “reverse” state.
PHASE
OUTA
Low
OUTB
High
Low
ITRIP = VREF/10RS
0
1
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fixed off-time period. The current path during
recirculation is determined by the configuration of slow/
mixed/fast current-decay mode via PFD1 and PFD2.
High
ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the ROSC
terminal to VDD. Typical value of 4 MHz is set with a
51 kΩ resistor. The allowable range of the resistor is from
20 kΩ to 100 kΩ.
ENABLE
Outputs
Chopped
On
f
OSC = 204 x 109/ROSC
.
0
1
If ROSC is not pulled up to VDD, it must be shorted to
ground.
Fixed Off Time. The A3959 is set for a fixed off time of
96 cycles of the internal oscillator, typically 24 µs with a
4 MHz oscillator.
www.allegromicro.com
5
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Internal Current-Control Mode. Inputs PFD1 and
PFD2 determine the current-decay method after an
overcurrent event is detected at the SENSE input. In
slow-decay mode, both sink drivers are turned on for the
fixed off-time period. Mixed-decay mode starts out in
fast-decay mode for a portion (15% or 48%) of the fixed
off time, and then is followed by slow decay for the
remainder of the period.
Synchronous Rectification. When a PWM off cycle
is triggered, either by an ENABLE chop command or
internal fixed off-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A3959 synchronous rectification feature will turn on
the appropriate pair of DMOS outputs during the current
decay and effectively short out the body diodes with the
low rDS(on) driver. This will reduce power dissipation
significantly and can eliminate the need for external
Schottky diodes.
PFD2
PFD1
% toff
0
Decay
Slow
0
0
1
1
0
1
0
1
Synchronous rectification will prevent reversal of load
current by turning off all outputs when a zero-current level
is detected.
15
Mixed
Mixed
Fast
48
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on CP or VREG) the outputs of
the device are disabled until the fault condition is
removed. At power up, and in the event of low VDD, the
UVLO circuit disables the drivers.
100
PWM Blank Timer. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents
of the clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable latch,
the sense comparator is blanked. The blank timer runs
after the off-time counter to provide the blanking function.
The blank timer is reset when ENABLE is chopped or
PHASE is changed. For external PWM control, a PHASE
change or ENABLE on will trigger the blanking function.
The duration is determined by the BLANK input and the
oscilator.
Braking. The braking function is implemented by
driving the device in slow-decay mode via EXTMODE
and applying an enable chop command. Because it is
possible to drive current in either direction through the
DMOS drivers, this configuration effectively shorts out
the motor-generated BEMF as long as the ENABLE chop
mode is asserted. It is important to note that the internal
PWM current-control circuit will not limit the current
when braking, because the current does not flow through
the sense resistor. The maximum brake current can be
approximated by VBEMF/RL. Care should be taken to
ensure that the maximum ratings of the device are not
exceeded in worst-case braking situations of high speed
and high inertial loads.
BLANK
tblank
6/fosc
0
1
12/fosc
SLEEP Logic. The SLEEP input terminal is used to
minimize power consumption when when not in use. This
disables much of the internal circuitry including the
regulator and charge pump. Logic low will put the device
into sleep mode, logic high will allow normal operation.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Current Sensing. To minimize inaccuracies in sensing
the ITRIP current level, which may be caused by ground
trace IR drops, the sense resistor should have an
independent ground return to the ground terminal of the
device. For low-value sense resistors the IR drops in the
PCB sense resistor’s traces can be significant and should
be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their
contact resistance.
Layout. A star ground system located close to the driver
is recommended. The printed wiring board should use a
heavy ground plane. For optimum electrical and thermal
performance*, the driver should be soldered directly onto
the board. The ground side of RS should have an indi-
vidual path to the ground terminals of the device. This
path should be as short as is possible physically and
should not have any other components connected to it. It
is recommended that a 0.1 µF capacitor be placed between
SENSE and ground as close to the device as possible; the
load supply terminal, VBB, should be decoupled with an
electrolytic capacitor (> 47 µF is recommended) placed as
close to the device as is possible. On the 28-lead TSSOP
package, the copper ground plane located under the
exposed thermal pad is typically used as a star ground.
The maximum value of RS is given as RS ≤ 0.5/ITRIP
where ITRIP ≤ 3.0 A.
Thermal Protection. Circuitry turns off all drivers
when the junction temperature reaches 165°C typically. It
is intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has
a hysteresis of approximately 15°C.
* The thermal resistance, RθJA, and absolute maximum
allowable package power dissipation specified on page 1
is measured on a typical two-sided PCB with one square
inch copper ground area on each side. With minimal
copper on a single-sided PCB (worst-case), the ‘B’
package RθJA is 40°C/W, ‘LB’ is 77°C/W, and ‘LP’ is
80°C/W. See also, Application Note 29501.5, Improving
Batwing Power Dissipation.
5
SUFFIX 'B', RθJA = 26°C/W
SUFFIX 'LP', RθJA = 28°C/W
SUFFIX 'LB', RθJA = 35°C/W
4
3
MULTI-LAYER HIGH-K BOARD
For specification purposes, the multi-layer high-K board
performance graphed here is per JEDEC Standard
JESD51.
2
1
0
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
SUFFIX 'B', RθJA = 38°C/W
SUFFIX 'LP', RθJA = 40°C/W
SUFFIX 'LB', RθJA = 50°C/W
DOUBLE-SIDED BOARD,
1 SQ. IN. COPPER EA. SIDE
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
25
50
75
100
125
150
°
TEMPERATURE IN C
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
Dwg. GP-049-6
www.allegromicro.com
7
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
Terminal List
LBB LP
Terminal Name
CP
Terminal Description
(SOIC) (DIP) (TSSOP)
Reservoir capacitor (typically 0.22 µF)
The charge pump capacitor (typically 0.22 µF)
No (internal) connection
1
24
1
CP1 & CP2
NC
2 & 3 1 & 2
2 & 3
—
4
—
3
4
5
6
PHASE
ROSC
Logic input for direction control
Oscillator resistor
5
4
GROUND
LOGIC SUPPLY
ENABLE
NC
Grounds
6, 7 5, 6, 7, 8* 7, 8*
VDD, the low voltage (typically 5 V) supply
Logic input for enable control
No (internal) connection
8
9
9
9
10
10
–
–
11
PFD2
Logic-level input for fast decay
Logic-level input for blanking control
Logic-level input for fast decay
10
11
12
13
14
15
16
–
11
12
13
14
15
—
16
–
12
BLANK
13
PFD1
14
REF
VREF, the load current reference input voltage
15
EXT MODE
NO CONNECT
OUTA
Logic input for PWM mode control
No (Internal) connection
16
17
One of two DMOS bridge outputs to the motor
No (internal) connection
18
NC
19, 20
21
SENSE
NC
Sense resistor
17
–
17
–
No (internal) connection
22
GROUND
LOAD SUPPLY
OUTB
Grounds
18, 19 18, 19*
—
VBB, the high-current, 9.5 V to 50 V, motor supply
One of two DMOS bridge outputs to the motor
No (Internal) connection
20
21
22
23
24
20
21
—
22
23
23
24
NO CONNECT
SLEEP
25
Logic-level Input for sleep operation
Regulator decoupling capacitor (typically 0.22 µF)
26
VREG
27
GROUND
Ground—
—
28*
* For the A3959SB (DIP) only, there is an indeterminate resistance between the substrate grounds (pins 6, 7,
18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together
externally. For the A3959SLP (TSSOP) the grounds at terminals 7, 8, and 28 should be connected together at
the exposed pad beneath the device.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
A3959SB
Dimensions in Inches
(controlling dimensions)
0.014
0.008
NOTE 1
24
13
0.430
MAX
0.300
BSC
0.280
0.240
1
6
7
12
0.100
BSC
0.070
0.045
0.005
MIN
1.280
1.230
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-25A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
NOTE 1
24
13
10.92
MAX
7.11
6.10
7.62
BSC
1
6
7
12
2.54
BSC
1.77
1.15
0.13
MIN
32.51
31.24
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-25A mm
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Exact body and lead configuration at vendor’s option within limits shown.
3. Lead spacing tolerance is non-cumulative.
4. Lead thickness is measured at seating plane or below.
5. Supplied in standard sticks/tubes of 15 devices.
www.allegromicro.com
9
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
A3959SLB
24
13
0.0125
0.0091
0.419
0.394
Dimensions in Inches
(for reference only)
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
3
0.050
0.6141
0.5985
0° TO 8°
BSC
NOTE 1
NOTE 3
0.0926
0.1043
Dwg. MA-008-25A in
0.0040 MIN.
24
0.32
0.23
10.65
10.00
7.60
7.40
Dimensions in Millimeters
(controlling dimensions)
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
15.60
15.20
0° TO 8°
NOTE 1
NOTE 3
2.65
2.35
Dwg. MA-008-25A mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
4. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
A3959SLP
28-pin TSSOP
9.8 .386
9.6 .378
8”
0”
28
0.20 .008
0.09 .004
A
4.5 .177
4.3 .169
3
.118
BSC
6.6 .260
6.2 .244
1
.039
REF
5
.200
1
2
BSC
0.75 .030
0.45 .018
0.25 .010
BSC
Seating Plane
Gauge Plane
0.30 .012
0.19 .007
0.65 .026
BSC
1.20 .047
MAX
0.15 .006
0.00 .000
0.65 .026
BSC
0.30 .012
BSC
6.6 .260
BSC
2.7 .106
BSC
4.5 .138
BSC
0.75 .030
BSC
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
A
Exposed thermal pad (bottom surface)
www.allegromicro.com
11
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
MOTOR DRIVERS
Function
Output Ratings*
Part Number†
INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS
3-Phase Power MOSFET Controller
3-Phase Power MOSFET Controller
3-Phase Power MOSFET Controller
3-Phase Back-EMF Controller/Driver
3-Phase PWM Current-Controlled DMOS Driver
—
—
—
28 V
40 V
50 V
14 V
50 V
3933
3935
3932 & 3938
8904
3936
±900 mA
±3.0 A
INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORS
PWM Current-Controlled Dual Full Bridge
Dual Full Bridge with Protection & Diagnostics
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
Microstepping Translator/Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual DMOS Full Bridge
PWM Current-Controlled Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled DMOS Full Bridge
PWM Current-Controlled Microstepping Full Bridge
PWM Current-Controlled Microstepping Full Bridge
PWM Current-Controlled Dual DMOS Full Bridge
PWM Current-Controlled Dual DMOS Full Bridge
PWM Current-Controlled Full Bridge
±500 mA
±500 mA
±650 mA
±650 mA
±750 mA
±750 mA
±750 mA
±750 mA
±800 mA
±1.0 A
±1.3 A
±1.5 A
±1.5 A
±1.5 A
±1.5 A
±1.5 A
±1.5 A
±2.0 A
18 V
30 V
30 V
30 V
30 V
45 V
45 V
45 V
33 V
35 V
50 V
45 V
50 V
50 V
50 V
50 V
50 V
50 V
50 V
35 V
50 V
3965
3976
3966
3968
3967
2916
2919
6219
3964
3973
3953
2917
3948
3955
3957
3972
3974
3952
3958
3977
3959
PWM Current-Controlled DMOS Full Bridge
Microstepping Translator/Dual DMOS Full Bridge
PWM Current-Controlled DMOS Full Bridge
±2.0 A
±2.5 A
±3.0 A
UNIPOLAR STEPPER MOTOR & OTHER DRIVERS
Unipolar Stepper-Motor Translator/Driver
Unipolar Stepper-Motor Translator/Driver
Unipolar Stepper-Motor Quad Drivers
Unipolar Microstepper-Motor Quad Driver
Unipolar Stepper-Motor Quad Driver
Unipolar Stepper-Motor Translator/Driver
Unipolar Stepper-Motor Quad Driver
Unipolar Microstepper-Motor Quad Driver
Unipolar Stepper-Motor Translator/Driver
1.0 A
1.25 A
1.5 A
1.5 A
1.8 A
2.0 A
3.0 A
3.0 A
3.0 A
46 V
50 V
46 V
46 V
50 V
46 V
46 V
46 V
46 V
7050
5804
7024 & 7029
7042
2540
7051
7026
7044
7052
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits
or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output.
† Complete part number includes additional characters to indicate operating temperature range and package style.
Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
相关型号：
A3959SLPTR-T
Stepper Motor Controller, 6A, NMOS, PDSO28, 1.20 MM HEIGHT, LEAD FREE, MO-153AET, TSSOP-28
ALLEGRO
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