A4450_技术文档

A4450

Buck-Boost Controller with Integrated Buck MOSFET

FEATURES AND BENEFITS

DESCRIPTION

• Automotive AEC-Q100 qualified

The A4450 is a power management IC that can implement

either a buck or buck-boost regulator to efficiently convert

automotive battery voltages into a tightly regulated voltage. It

includes control, diagnostics, and protection functions.

• Wide operating range of 3 to 36 V_IN, 40 V_INmaximum,

covers automotive stop/start, cold crank, double battery,

and load dump

• Regulated output can range from 3 to 8 V at up to 1 A DC

• Adjustable PWM switching frequency:

250 kHz to 2.2 MHz

An enable input to the A4450 is compatible to a high-voltage

battery level, (EN).

• PWM frequency can be synchronized to external clock:

250 kHz to 2.4 MHz

Adiagnostic output from theA4450 includes a power-on reset

output (NPOR) signal.

• Frequency dithering helps reduce EMI/EMC

• Undervoltage protection

• Pin-to-pin and pin-to-ground tolerant at every pin

• Thermal shutdown protection

Protectionfeaturesincludepulse-by-pulsecurrentlimit,hiccup

mode short-circuit protection, LX short-circuit protection,

missing freewheeling diode (buck diode at LX node inA4450)

protection, and thermal shutdown.

• Operating junction temperature range −40°C to 150°C

The A4450 is most suitable for applications where the input

voltage can vary from less than or greater than the regulated

output voltage.

PACKAGES:

20-pin 4 × 4 mm QFN (ES) with wettable flank

The A4450 is supplied in 4 × 4 mm QFN (suffix “ES”) with

exposed power pad.

APPLICATIONS

• Infotainment

• Instrument Clusters

• Control Modules

Not to scale

VBAT

BOOT

VIN

D2 Boost

Diode

V_OUT

LX

D1

Buck

Diode

AVIN

A4450

COMP

LG

FB

RNG

FSET /SYNC

SS

NPOR

GND

EN

PGND

Typical Application Diagram

A4450-DS

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

SELECTION GUIDE

Part Number

Temperature Range

Packing¹

Package

Lead Frame

A4450KESTR-J

–40°C to 150°C

1500 pieces per 7-inch reel

20-pin QFN with thermal pad and wettable flank

100% matte tin

¹Contact Allegro for additional packing options.

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS²

Characteristic

Symbol

V_IN

Notes

Rating

Unit

V

VIN

AVIN

EN

–0.3 to 40

–0.3 to V_IN

V_AVIN

V_EN

V

continuous

t < 250 ns

t < 50 ns

−0.3 to V_IN+ 0.3

V

LX

V_LX

–1.5

V

V_IN+ 3

V

LG

V_LG

–0.3 to 8.5

V_LX– 0.3 to V_LX+ 6

–0.3 to 7.5

V

BOOT

V_BOOT

V

All other pins

V

Junction Temperature Range

Storage Temperature Range

T_J

–40 to 150

°C

T_stg

–55 to 150

²Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of

the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability

THERMAL CHARACTERISTICS

Characteristic

Symbol

Test Conditions³

Value

Unit

Junction to Ambient Thermal Resistance

R_θJA

QFN-20 (ES) package, 4-layer PCB based on JEDEC standard

37

°C/W

³Additional thermal information available on the Allegro website.

Allegro MicroSystems, LLC

115 Northeast Cutoff

2

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

PINOUT DIAGRAM AND TERMINAL LIST TABLE

VIN

GND

EN

1

2

3

4

5

15 FB

14 COMP

13 NC

12 GND

11 SS

NC

Package ES, 20-Pin QFN Pinout Diagram

Terminal List Table

Symbol

Number

Function

VIN

1, 2

Input voltage; ensure decoupling capacitors are connected directly to this pin.

GND

3, 7, 12

Ground pin for decoupling and ground connection.

Enable pin; 40 V rated and logic level compatible; can be connected to VIN or switching battery.

Used to turn the regulator on or off: set pin high to turn the regulator on or set pin low to turn the regulator off. Can be

used to set UVLO threshold with external resistor divider.

EN

4

NC

5, 13

6

No connection.

Input to internal voltage regulator and boost duty generator; must connect to VIN through a resistor (5 Ω typ) and a

capacitor is suggested to be added between AVIN pin and GND to form a RC filter.

AVIN

Frequency setting and synchronization input. Switching frequency is programmed by connecting a resistor from

this pin to ground. This pin can also accept a square wave switching signal that synchronizes the converter through

internal PLL.

FSET/SYNC

8

RNG

NPOR

SS

9

Output range select pin. A resistor connected between RNG pin and GND is selected base on the target V_OUT

Active-low power-on reset output signal. This pin is an open-drain regulator fault detection output that transitions from

low to high impedance after the output has maintained regulator for t_dNPOR

.

10

11

14

.

A capacitor from this pin to GND sets the soft-start time. This capacitor also determines the hiccup period.

Error amplifier compensation network pin. Connect series RC network from this pin to ground for loop compensation to

stabilize the converter.

COMP

FB

LG

15

16

17

Feedback pin for output. Connect a voltage divider from the output to this pin to program the output voltage.

Gate drive output for the external boost switch. Connect a 10 kΩ resistor from this pin to PGND.

Power ground. Provide power ground return for drivers.

PGND

Bootstrap capacitor connection. Connect a capacitor from this pin to LX pin. This pin provides supply voltage for the

high-side and low-side gate drivers.

BOOT

LX

18

Switching node of the regulator; the output inductor and cathode of the buck diode should be connected to this pin

with relatively wide traces. The inductor and buck diode should be placed as close as possible to this pin.

19, 20

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

FUNCTIONAL BLOCK DIAGRAM

VIN

BG_UV

BG

BOOT

VCC

BG1

LDO

EN

Boot Circuit

AVIN

0.1 µA

COMP

BUCK-BOOST

BG

Control

LX

(w/ Hiccup Mode)

OSC2

CLK_1MHz

BOOT

CLK @ f_osc

100 nA

OSC1

PLL

LG

FSET/SYNC

VOUT_OV

FB

RANGE

FB

SS

Soft Start

t_SS

RNG

SS OK

TSD

VOUT_OV

BG_UV

VIN_UV

*D1_MISSING

*I_LIM(LX)

MASTER

IC POR

NPOR Timing

* indicates a

latched fault

CLK_1MHz

FB

NPOR

*D1_MISSING

*I_LIM(LX)

MPOR

ON

GND

EN

DE-

GLITCH

t_dEN(FILT)

ON

1.9 V_TYP

1.24 V_TYP

↑

PGND

↓

A4450

Allegro MicroSystems, LLC

115 Northeast Cutoff

4

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

ELECTRICAL CHARACTERISTICS: Valid at 3 V ≤ V_IN≤ 36 V and V_INhaving ﬁrst reached V_INSTART

,

‒40°C ≤ T_J≤ 150°C, unless noted otherwise

Characteristics

GENERAL SPECIFICATIONS

Operating Input Voltage

VIN UVLO Start

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_IN

After V_IN> V_INSTART, V_EN≥ 4 V

3.0

–

13.5

–

36

4.8

2.9

–

V

V_INSTART

V_INSTOP

I_Q

V_INrising

VIN UVLO Stop

V_INfalling, when in Buck-Boost mode

V_IN= 13.5 V, V_EN≥ 4 V, no load

V_IN= 13.5 V, V_EN≤ 1 V, no load

–

V

–

4.5

–

mA

µA

Supply Quiescent Current¹

I_Q(SLEEP)

–

10

PWM SWITCHING FREQUENCY AND DITHERING

R_FSET= 7.87 kΩ

1.8

343

–

2.0

400

±12

7.0*

16.6

7.0*

18

2.2

457

–

MHz

kHz

%

Switching Frequency

f_OSC

Δf_OSC

R

_FSET= 41.2 kΩ

Frequency Dithering

As a percent of f_OSC

V_INrising, R_NG= 15 kΩ, target V_OUT= 5 V

V

VIN Dithering START Threshold

V_{IN(DITHER,ON)}

V

_INfalling

V_INfalling, R_NG= 15 kΩ, target V_OUT= 5 V

_INrising

–

V

VIN Dithering STOP Threshold

V_{IN(DITHER,OFF)}

V_{IN(DITHER,HYS)}

V

–

V

VIN Dithering Hysteresis

1.5

V

THERMAL PROTECTION

Thermal Shutdown Threshold²

Thermal Shutdown Hysteresis²

OUTPUT VOLTAGE SPECIFICATIONS

Feedback Voltage Tolerance

PULSE-WIDTH MODULATION (PWM)

PWM Ramp Offset

T_TSD

T_HYS

T_Jrising

160

–

170

20

180

–

°C

V_FB

V_IN= 13.5 V, EN = high

0.788

0.800

0.812

V

V_PWMOFFS

LX_RISE

V_COMPfor 0% duty cycle

–

400

1.5

–

mV

V/ns

ns

LX Rising Slew Rate²

V_IN= 13.5 V, 10% to 90%, I_LX= 1 A

LX Falling Slew Rate²

LX_FALL

–

1.8

–

Buck Minimum On-Time

t_ON(MIN,BUCK)

t_{OFF(MIN,BUCK)}

–

85

120

–

Buck Minimum Off-Time

–

85

ns

V_IN= 3.5 V, V_OUT= 8 V target, R_NG= 25.5 kΩ, 2 MHz

–

0.75

0.57

0.31

4.7

–

Boost Maximum Duty Cycle

D_MAX(BST)

V

_IN= 3.5 V, V_OUT= 5 V target, R_NG= 15 kΩ, 2 MHz

_IN= 3.5 V, V_OUT= 3 V target, R_NG= 9.31 kΩ, 2 MHz

–

COMP to LX Current Gain

Slope Compensation²

INTERNAL MOSFET

gm_POWER

S_E

3.5

1.76

0.35

5.9

2.64

0.53

A/V

A/µs

f_OSC= 2 MHz

2.2

f_OSC= 400 kHz

0.44

V_IN= 13.5 V, T_J= –40°C ⁽²⁾, I_DS= 0.1 A

–

60

80

90

mΩ

MOSFET On Resistance

R_DSon

V

_IN= 13.5 V, T_J= 25°C ⁽²⁾, I_DS= 0.1 A

_IN= 13.5 V, T_J= 150°C, I_DS= 0.1 A

110

170

140

V_EN≤ 1 V, V_LX= 0 V, V_IN= 13.5 V,

−40°C ≤ T_J≤ 85°C⁽²⁾

MOSFET Leakage

I_FET(LKG)

–

10

µA

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

5

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

ELECTRICAL CHARACTERISTICS (continued): Valid at 3 V ≤ V_IN≤ 36 V and V_INhaving ﬁrst reached V_INSTART

,

‒40°C ≤ T_J≤ 150°C, unless noted otherwise

Characteristics

ERROR AMPLIFIER

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Open-Loop Voltage Gain

Transconductance

Output Current

AVOL

gm_EA

I_EA

–

550

–

65

–

950

–

dB

µA/V

µA

750

±75

Maximum Output Voltage,

Buck-Boost Mode

V_{EAVO(max)BuckBoost}

–

1.5

–

V

Maximum Output Voltage,

Buck Mode

V_{EAVO(max)Buck}

V_EAVO(min)

–

1.2

–

V

Minimum Output Voltage

150

220

290

mV

BOOST MOSFET (LG) GATE DRIVER

LG High Output Voltage

LG Low Output Voltage

LG Source Current¹

V_LG(ON)

V_LG(OFF)

I_LG(ON)

V_IN= 7 V

5.0

–

8.0

0.4

–

V

V_IN= 13.5 V

V_LG= 1 V

V

–

−265

500

mA

LG Sink Current¹

I_LG(OFF)

–

SOFT-START

0.12 ×

f_OSC

V_FB= 0 V

–

0.43 ×

f_OSC

V

_FB= 0.2 V

SS PWM Frequency Foldback

(Linear)

f_SW(SS)

0.93 ×

f_OSC

V

_FB= 0.6 V

_FB= 0.8 V

–

f_OSC

–

0 V < V_FB< 0.2 V

f_SYNC/4

f_SYNC/2

f_SYNC

Switching Frequency in SYNC Mode

with Applied Frequency f_SYNC

f_SW(SYNC)

0.2 V < V_FB< 0.4 V

0.4 V < V_FB

HICCUP MODE

PWM

cycles

V_FB< 0.4 V (typical), V_COMP= V_EAVO(max)

–

30

120

–

Hiccup OCP PWM Counts

t_HIC(OCP)

PWM

cycles

V

_FB> 0.4 V (typical), V_COMP= V_EAVO(max)

LX switching stops to LX switching starts, during

overcurrent

Hiccup Mode Recovery Time

t_HIC(RECOVER)

3.0

5.6

ms

A

CURRENT PROTECTIONS

Pulse-by-Pulse Current Limit,

Buck-Boost Mode

I_{LIM(BuckBoost)}

Buck-Boost mode

Buck mode

3.9

4.5

5.1

Pulse-by-Pulse Current Limit,

Buck Mode

I_LIM(Buck)

I_LIM(LX)

2.4

6.3

2.8

7.4

3.4

8.5

A

LX Short-Circuit Current Limit

MISSING BUCK DIODE (D1) PROTECTION

Detection Level²

Time Filtering ²

V_D(OPEN)

t_D(OPEN)

−1.6

−1.4

−1.1

V

50

–

250

ns

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

6

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

ELECTRICAL CHARACTERISTICS (continued): Valid at 3 V ≤ V_IN≤ 36 V and V_INhaving ﬁrst reached V_INSTART

,

‒40°C ≤ T_J≤ 150°C, unless noted otherwise

Characteristics

ENABLE (EN) INPUT

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_EN(H)

V_EN(L)

V_ENrising

–

1.0

–

1.9

1.2

700

28

2.25

–

V

EN Thresholds

EN Hysteresis

EN Bias Current¹

V_ENfalling

V_EN(HYS)

V_EN(H)– V_EN(L)

–

mV

µA

kΩ

V_EN= 3.5 V, T_J= 25°C ⁽²⁾

_EN= 3.5 V, T_J= 150°C

–

45

55

–

I_EN(BIAS)

R_EN

V

–

35

EN Pulldown Resistance

EN DEGLITCH

–

650

Enable Filter/Deglitch Time

EN SHUTDOWN DELAY

t_dEN(FILT)

10

28

20

32

30

36

µs

Measured from the falling edge of EN to the time

when LX stops switching

Shutdown Delay

t_dOFF

FSET/SYNC INPUT

FSET/SYNC Pin Voltage

V_FSET/SYNC

No external SYNC signal

–

640

3

–

mV

µs

FSET/SYNC Open Circuit

(Undercurrent) Detection Time²

PWM switching frequency becomes 1 MHz upon

detection

V_{FSET/SYNC(UC)}

FSET/SYNC Short Circuit

(Overcurrent) Detection Time²

V_{FSET/SYNC(OC)}

PWM switching frequency can rise up to 3.2 MHz_TYP

–

3

–

µs

Sync High Threshold²

V_SYNCVIH

V_SYNCVIL

DC_SYNC

t_wSYNC

V_SYNCrising

V_SYNCfalling

–

0.5

–

2.0

–

V

Sync Low Threshold²

Sync Input Duty Cycle

–

80

–

%

ns

Sync Input Pulse Width

200

–

Sync Input Transition Times²

VFB THRESHOLDS

t_tSYNC

10

15

NPOR VFB Overvoltage Threshold

NPOR VFB Overvoltage Hysteresis

VFB Overvoltage Threshold

V_FBNPOROV(H)

V_{FBNPOROV(HYS)}

V_FBOV

V_FBrising, PWM disabled, NPOR pulled low

840

–

890

10

930

–

mV

High-side FET off, LG turns high, NPOR remains high

–

840

750

740

10

–

V_FBNPORUV(H)

V_FBNPORUV(L)

V_FBrising

V_FBfalling

–

NPOR VFB Undervoltage Thresholds

720

–

760

–

NPOR VFB Undervoltage Hysteresis V_{FBNPORUV(HYS)}V_FBNPORUV(H)– V_FBNPORUV(L)

UNDERVOLTAGE/OVERVOLTAGE FILTERING/DEGLITCH

Undervoltage Filter/Deglitch Times

Overvoltage Filter/Deglitch Times

NPOR OUTPUT

t_dUV(FILT)

t_dOV(FILT)

20

30

40

µs

NPOR Rising Delay

t_dNPOR

V_NPOR(L)

I_NPOR(LKG)

Time from output in regulation to NPOR rising edge

EN High, V_IN≥ 3 V, I_NPOR= 4 mA

V_NPOR= 5 V

–

2.1

150

–

400

2

ms

mV

µA

NPOR Low Output Voltage

NPOR Leakage Current

¹For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin

(sinking).

²Ensured by design and characterization, not production tested.

* Threshold is adjustable following the equation R_NG(kΩ) / 1.844 (V).

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

TYPICAL PERFORMANCE CHARACTERISTICS

0.812

0.808

0.804

0.8

2.2

2

1.8

1.6

1.4

1.2

1

R_FSET= 7.87 kΩ

R_FSET= 41.2 kΩ

0.8

0.6

0.4

0.2

0

0.796

0.792

0.788

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Reference Voltage versus Temperature

Switching Frequency f_OSCversus Temperature

4.75

4.5

4.25

4

925

900

875

850

825

800

775

750

725

700

OV Rising

OV Falling

UV Rising

UV Falling

3.75

3.5

3.25

3

V_INUVLO Start

V_INUVLO Stop

2.75

2.5

2.25

2

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

VIN UVLO START and STOP Thresholds versus

Temperature

NPOR V_FBOvervoltage and Undervoltage versus

Temperature

4.5

4

2.2

2.1

2

3.5

3

1.9

1.8

1.7

2.5

2

Rising

1.6

Falling

1.5

1

1.4

1.3

1.2

1.1

1

0.5

0

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

EN Rising and Falling Threshold versus Temperature

Quiescent Current I_Qversus Temperature

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

100 mV/div

V

_OUT= 5.0 V

V_OUT= 5.0 V

V_IN= 4 to 18 V

V_IN= 18 to 4 V

(100 µs/div)

V_INTransient Response: 4 to 18 V at 0.5 A Load for

5 V_OUT, 2 MHz design example

V_INTransient Response: 18 to 4 V at 0.5 A Load for

5 V_OUT, 2 MHz design example

100 mV/div

V_OUT= 5.0 V

500 mA/div

I_OUT

500 mA/div

I_OUT

50 mA/µs

(100 µs/div)

Transient Response 0 to 0.5 A Load Step at V_IN= 5 V for Transient Response 0.5 to 1 A Load Step at V_IN= 5 V for

5 V_OUT, 2 MHz design example

100 mV/div

V_OUT= 5.0 V

500 mA/div

I_OUT

500 mA/div

I_OUT

50 mA/µs

(100 µs/div)

Transient Response 0 to 0.5 A Load Step at V_IN= 12 V

for 5 V_OUT, 2 MHz design example

Transient Response 0.5 to 1 A Load Step at V_IN= 12 V

for 5 V_OUT, 2 MHz design example

Allegro MicroSystems, LLC

115 Northeast Cutoff

9

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

FUNCTIONAL DESCRIPTION

Overview

Operation Modes

The A4450 features all the necessary functions to implement an

efficient buck or buck-boost regulation to convert automobile

battery voltage into a tightly regulated voltage. The regulator can

smoothly switch between Buck mode operation and Buck-Boost

A buck-boost regulator can regulate the output voltage with input

voltage greater than or less than the output voltage. However, the

buck-boost regulator is not as efficient as the buck regulator. The

A4450 is designed as a dual mode controller to resolve this chal-

mode operation, allowing the operation with input voltage greater lenge so that the regulator can operate efficiently under the Buck

than or less than the output voltage. The A4450 integrates low

R_DSONhigh-side N-MOSFET as a controlled buck switch. The

mode when the input voltage is greater than the output voltage.

Figure 1 shows the basic buck-boost regulator configuration with

A4450 provides a gate driver output for the external boost switch. dual mode controller A4450.

As shown in Figure 1, the configuration of typical buck-boost

BUCK MODE

regulator consists of an external freewheeling Schottky diode

dictated as buck diode, another Schottky diode dictated as boost

diode, an external MOSFET as boost switch, inductor, and output

capacitor. The A4450 can provide regulated output voltage rang-

ing from 3 to 8 V with up to 1 A DC load. The A4450 employs

peak current-mode control to provide superior line and load

regulation, pulse-by-pulse current limit, fast transient response,

and simple compensation.

In case the input voltage is high compared to the output voltage,

the regulator will enter Buck mode: buck switch Q1 turns on and

off with duty cycle, D_Buck, to maintain regulation while boost

switch Q2 is off, according to the following equation:

V_OUT= D_Buck× V_IN

(1)

where D_Buckis the duty cycle of buck switch.

The A4450 features include a transconductance error amplifier

for external compensation network, an enable input (EN), exter-

nally set soft-start time, a SYNC/FSET input to set PWM switch-

ing frequency or synchronize to external clock, an output voltage

range set pin (RNG), a Power-On Reset output (NPOR) pin, and

frequency dithering. Protection features of the A4450 include V_IN

undervoltage lockout, pulse-by-pulse overcurrent protections in

Buck-Boost and Buck modes, BOOT capacitor protection, two

levels output overvoltage protection, hiccup mode short-circuit

protection, LX short-circuit protection, missing buck diode pro-

tection, and thermal shutdown. In addition, the A4450 provides

open-circuit, adjacent pin short-circuit, and pin-to-ground short-

circuit protection at every pin.

BUCK-BOOST MODE

When the input voltage decreases toward to the output voltage,

the duty cycle of the buck switch Q1 will increase to maintain

regulation. At the same time, once the programmed boost switch

duty cycle, D_Boost(shown in the equation below), is greater

than 0, the boost switch starts to turn on and off with duty cycle

D_Boost. The regulator then enters Buck-Boost mode.

The boost switch duty cycle is determined by the equation below:

V_IN× 1.844

D_Boost= max 0,1 –

(

(2)

)

R_NG

The A4450 is available in industry-standard QFN-20 package.

where V_INis in Volts (V) and R_NG(kΩ) is the resistor connected

between RNG pin and GND.

VIN

Boost

Diode

Buck

VOUT

LX

The Range resistor RNG (kΩ) programs the targeted output volt-

Switch

age, V_OUT, following the equation below:

Buck

Diode

Q1

V_OUT(V) × 1.844

R_NG

=

(3)

D_BUCK0

Q2

Boost

Switch

LG

A4450

where D_BUCK0is the preferred buck duty cycle at the instant that

the boost switch starts to switch, typically set between 0.60 and

0.65.

Figure 1: Basic Buck-Boost Regulator Conﬁguration

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Buck-Boost Controller

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A4450

Under the Buck-Boost mode operation, the buck switch duty

cycle, D_Buck, is controlled through the feedback network to regu-

late V_OUT, as shown in the equation below:

Reference Voltage

The A4450 incorporates an internal precision reference at 0.8 V

(V_REF) as the reference of the output voltage feedback divider.

The output voltage of the regulator is then programmed with a

resistor divider between V_OUTand the FB pin of the A4450. After

V_OUTis set, R_NGresistor can be selected based on equation 3.

The accuracy of the internal reference is ±1.5% across a –40°C to

150°C temperature range.

V_OUT= D_Buck/ (1 – D_Boost) × V_IN

(4)

This dual mode controller of A4450 enables smooth transition

between Buck and Buck-Boost mode over a wide range of input

voltages to maintain the regulation of output voltages.

Take as an example, V_OUT= 5 V buck-boost regulator, setting

D_BUCK0= 0.61 results in R_NG= 15 kΩ from equation 4. As

shown in Figure 2, when V_INis greater than ~8.5 V, the regulator

is in Buck mode and the duty cycle of Boost switch is 0; when

V_INis less than ~8.5 V, the regulator enters is in Buck-Boost

mode with both switches turning on and off. It is recommended

that the duty cycle of the buck switch should be larger than that

of the boost switch for efficient operation.

Oscillator/Switching Frequency and Synchronization

The PWM switching frequency of the A4450 is adjustable from

250 kHz to 2.2 MHz and has an accuracy of about ±10% over the

operating temperature range. A resistor, R_FSET, connected from

the FSET/SYNC pin to GND, sets the switching frequency. An

FSET/SYNC resistor with ±1% tolerance is recommended. A

graph of switching frequency versus FSET/SYNC resistor value

is shown in the Component Selection section of this datasheet.

0.80

The FSET/SYNC pin can also be used as a synchronization input

that accepts an external clock to switch the A4450 from 250 kHz

to 2.4 MHz; the slope compensation will be scaled according to

the applied synchronization frequency. When used as a synchro-

nization input, the applied clock pulses must satisfy the pulse-

width duty-cycle requirements shown in the Electrical Character-

istics table of this datasheet.

0.60

0.40

Duty_Boost

Duty_Buck

0.20

0.00

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

V_IN(V)

Figure 2: Duty Cycles of Boost and Buck Switches vs

V_INfor example above with V_OUT= 5 V, R_NG= 15 kΩ

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Buck-Boost Controller

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A4450

Frequency Dithering

The A4450 adopts a frequency dithering technique to help reduce

EMI/EMC for demanding automotive applications. The A4450

implements the linear triangular dithering of the PWM frequency,

spreading the energy above and below the base frequency set

by R_FSET. A typical fixed-frequency PWM regulator will cre-

ate distinct “spikes” of energy at f_OSC, and at higher frequency

multiples of f_OSC. Conversely, the A4450 spreads the spectrum

around f_OSC, thus creating a lower magnitude at any comparative

frequency. Frequency dithering is disabled if FSET/SYNC pin is

used for external synchronization.

Dithering

Buck

Mode

No Dithering

Rising

18 V

*

V_{IN(DITHER,ON)}

Figure 3: V_INRising Dithering Threshold

Frequency dithering of A4450 only applies in Buck mode—there

is no frequency dithering in Buck-Boost mode. Therefore, when

V_INrises from low level to be above the V_INDithering Start

Threshold (see EC table), frequency dithering will be activated

where the A4450 enters into Buck mode from Buck-Boost mode.

This V_INDithering Start Threshold is approximately equal to

R_NG(kΩ) / 1.844 V.

Dithering

Buck

Mode

If V_INcontinues to rise and exceeds the V_INDithering Stop

Threshold at 18 V (typical), frequency dithering will be disabled.

Then if V_INstarts to fall, frequency dithering will resume again

when V_INgoes below 16.6 V (typical). When V_INcontinues to

drop below the V_INDithering Stop Threshold (V_INfalling) to

trigger the Buck-Boost mode operation, then frequency dithering

is disabled. The V_INDithering Stop Threshold is approximately

equal to R_NG(kΩ) / 1.844 V.

No Dithering

Falling

V_{IN(DITHER,OFF)}

16.6 V

V_IN

*

Figure 4: V_INFalling Dithering Threshold,

where threshold is adjustable following the equation

R_NG(kΩ) / 1.844 (V)

Refer to Figure 3 and Figure 4 and the PWM Switching Fre-

quency and Dithering specifications in Electrical Characteristics

table.

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A4450

Transconductance Error Amplifier and

Compensation Network

Slope Compensation

The A4450 incorporates internal slope compensation to allow

PWM duty cycles above 50% for a wide range of input/output

voltages, switching frequencies, and inductor values. The slope

compensation signal of the A4450 is actually subtracted from

COMP signal, equivalently being added into the current sense

signal. The amount of slope compensation is scaled with the

switching frequency when programming the frequency with a

resistor or with an external clock.

The transconductance error amplifier primary function is to

control the regulator output voltage. It has three-terminal inputs

with two positive inputs and one negative input (as shown in

Figure 5). The negative input is connected to the FB pin to sense

the feedback output voltage for regulation. The two positive

inputs are used for soft-start and steady-state regulation. The

error amplifier regulates to the lower value of those two positive

inputs. The error amplifier regulates the FB voltage according to

the soft-start voltage minus Soft-Start Offset during startup; when

the soft-start voltage minus Soft-Start Offset exceeds the internal

0.8 V reference, the error amplifier then “switches over” and

regulates the FB voltage to the 0.8 V reference voltage.

The value of the output inductor should be chosen such that slope

compensation rate, S_E, is theoretically at least greater than half

the falling slope of the inductor current (S_F). Because the A4450

will work in the Buck-Boost mode, a larger compensation slope

is preferred; refer to Output Inductor section for details.

Soft-Start Offset

400 mV

Enable Input (EN)

-

SS

Error Amp

An enable pin is available on the A4450. When this pin is low,

the A4450 is shut down and enters a “sleep mode”, where the

internal control circuits will be shut off and draw less current

from VIN. If EN goes high, the A4450 will turn on, and provided

there are no fault conditions, soft-start will be initiated and V_OUT

will ramp to its final voltage in a time set by the soft-start capaci-

tor (C_SS). To automatically enable the A4450, the EN pin may be

connected to VIN through a current-limiting resistor (1 ~10 kΩ).

For transient suppression, it is recommended that a 0.1 to 0.22 µF

capacitor is placed after the series resistor to form a low-pass

filter before the EN pin. Larger external resistance is needed if

EN signal rings below GND significantly.

+

COMP

800 mV

VREF

+

-

FB

Figure 5: Error Ampliﬁer

To stabilize the regulator, a series RC compensation network

(R_Zand C_Z) must be connected from the error amplifier output

(the COMP pin) to GND, as shown in the Typical Application

Diagram. In most instances, an additional relatively low-value

capacitor (C_P) should be connected in parallel with the R_Z-C_Z

components to reduce the loop gain at very high frequencies.

However, if the C_Pcapacitor is too large, the phase margin of the

converter can be reduced. A general guideline about how to select

R_Z, C_Z, and C_Pis provided in the Component Selection section of

this datasheet.

Integrated Buck MOSFET

The A4450 integrates an 80 mΩ_TYPhigh-side N-channel MOS-

FET as the buck switch.

Current Sense Amplifier

If a fault occurs or the regulator is disabled, the COMP pin is

pulled to GND via approximately 4.5 kΩ and the switching is

inhibited.

The A4450 incorporates a high-bandwidth current sense amplifier

to monitor the current through the high-side MOSFET. This cur-

rent signal is used to regulate the peak current when the high-side

MOSFET is turned on. The current signal is also used by the pro-

tection circuitry for the pulse-by-pulse current limit and hiccup

mode short-circuit protection.

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

When V_INrises above 18 V, the A4450 starts to linearly fold-

back the PWM switching frequency, f_SW, based on V_IN, from the

original frequency, f_SWO, before foldback, up to about half f_SWO

at 36 V. In this way, the on-time of the buck switch is relatively

extended to ensure the duty cycle regulation is within control.

Pulse-Width Modulation (PWM) Mode

The A4450 employs peak current-mode control to provide excel-

lent load and line regulation, fast transient response, and simple

compensation.

A high-speed comparator and control logic is included in the

A4450. The inverting input of the PWM comparator is the sub-

traction of the slope compensation signal from the output of the

error amplifier. The noninverting input is connected to the sum

of the current sense signal, and a DC PWM Ramp offset voltage

(V_PWMOFFS).

The test results illustrate the foldback behavior of switching fre-

quency f_SWversus V_IN, in Figure 7 (where switching frequency

f_SWis normalized to the original switching frequency f_SWObefore

foldback).

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

At the beginning of each PWM cycle, the CLK signal sets the

PWM flip-flop and the high-side buck switch is turned on. When

the voltage at the noninverting of the PWM comparator rises

above the error amplifier output, COMP, the PWM flip-flop is

reset and the high-side buck switch is turned off.

In the A4450, the duty cycle of the buck switch is controlled to

regulate the output voltage, regardless of Buck-Boost or Buck

mode. This makes control loop analysis easy, and facilitates the

compensation to design a stable system without the right-half-

plane zero introduced.

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36

As illustrated in Figure 6, in Buck-Boost mode, both Q1 and Q2

are turned on at the beginning of each PWM cycle; Q2 operates

V_IN(V)

with the programmed duty cycle, D_Boost

:

Figure 7: Normalized Switching Frequency

f_SW/f_SWOFoldback vs. V_IN

V_IN(V)× 1.844

D_Boost= 1 –

(5)

R_NG(kΩ)

and the buck switch Q1 is controlled by the PWM comparator to

regulate the output voltage with the duty cycle, D_Buck

:

BOOT Regulator

The A4450 includes an internal regulator to charge its boot

capacitor. The voltage across the boot capacitor is typically

5 V, which provides voltage for the gate drivers of the buck

switch and the boost switch. A 7 Ω bottom MOSFET is also also

integrated, which is turned on during minimum off-time to help

ensure the boot capacitor is always charged. When V_INis below

5 V, to ensure sufficient gate voltage, it is recommended to add an

external boot diode, which is connected to a 5 V supply, as shown

in Figure 8.

D_Buck= (V_OUT/ V_IN) × (1 – D_Boost

)

(6)

In Buck mode, the boost switch (Q2) is off and the buck switch

(Q1) is active.

Boost

Diode

Buck

Switch

VOUT

VIN

Buck

Q1

Diode

Boost

Switch

Q2

Figure 6: Buck-Boost Regulator

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A4450

shorted or soft-starting a relatively high capacitance or very

heavy load. However, during Overcurrent Protection or Hiccup

mode, the soft-start PWM switching frequencies will become half

of the corresponding linear foldback frequencies during normal

startup.

Extra Boot Diode

recommended for V_IN< 5 V

BOOT

5 V

C_BOOT

A4450

L_O

0.22 µF

V_OUT

LX

If the A4450 is disabled or a fault occurs, the internal fault latch

is set and the capacitor at the SS pin is discharged to ground very

quickly through a 2 kΩ pull-down resistor. The A4450 will clear

the internal fault latch when the voltage at the SS pin decays to

approximately 200 mV. However, if the A4450 enters Hiccup

mode, the capacitor at the SS pin is slowly discharged through

10 µA sink current. Therefore, the soft-start capacitor C_SSnot

only controls the startup time but also the time between soft-start

attempts in Hiccup mode.

Buck Diode

D₁

Figure 8: Extra Boot Diode Suggested for V_IN< 5 V

If the boot capacitor is missing or shorted, the A4450 will detect

such a fault and enter hiccup mode. Also, the boot regulator has a

current limit to protect itself during a short-circuit condition.

Pre-Biased Startup

Soft-Start (Startup) and Inrush Current Control

If the output of the regulator is pre-biased at a certain output

voltage level, the A4450 will modify the normal startup routine

to prevent discharging the output capacitors. As described in the

Soft-Start (Startup) and Inrush Current Control section, the error

amplifier usually becomes active when the voltage at the soft-

start pin exceeds the Soft-Start Offset. If the output is pre-biased,

the voltage at the FB pin will be non-zero, the Boost diode blocks

reverse current from the output, and the A4450 will not start

switching until the voltage at SS pin minus the Soft-Start Offset

rises to approximately V_FB. From then on, the error amplifier

becomes active, the voltage at the COMP pin rises, PWM switch-

ing starts, and the output voltage will ramp upward from the

pre-bias level.

The soft-start function controls the inrush current at startup. The

soft-start pin, SS, is connected to GND via a capacitor. When

the A4450 is enabled and all faults are cleared, the soft-start pin

will source the charging current and the voltage on the soft-start

capacitor C_SSwill ramp upward from 0 V. When the voltage at

the soft-start pin exceeds the Soft-Start Offset (typical 0.4 V), the

error amplifier will ramp up its output voltage above the PWM

Ramp Offset. At that instant, PWM switching begins.

Once the A4450 begins PWM switching, the error amplifier

will regulate the voltage at the FB pin to the soft-start pin volt-

age minus the Soft-Start Offset. During the active portion of

soft-start, the regulator output voltage will rise from 0 V to the

targeted output voltage.

Not Power-On Reset (NPOR) Output

When the voltage of the soft-start pin minus the Soft-Start Offset

is greater than 0.8 V, the error amplifier will start to regulate the

voltage at the FB pin to the A4450 reference voltage, 800 mV.

The voltage at the soft-start pin will continue to rise to the inter-

nal LDO regulator output voltage.

The A4450 has an inverted Power-On Reset Output (NPOR) with

a fixed delay of its rising edge (t_dNPOR). The NPOR output is an

open-drain output, so an external pull-up resistor must be used, as

shown in the Typical Application Diagram. NPOR transitions high

when the output voltage, sensed at the FB pin, is within regulation.

During normal startup, the PWM switching frequency is linearly

scaled from 0.12 × f_OSCto f_OSC(depending on the FB voltage

level) as the voltage at the FB pin ramps from 0 to 800 mV (see

the details in the Electrical Characteristics table). Note if the

theoretically scaled switching frequencies are less than 100 kHz,

then 100 kHz frequency will take over. The scaled scheme is

implemented to prevent the output inductor current from climb-

ing to a level that may damage the A4450 regulator when the

input voltage is high and the output of the regulator is either

The NPOR output is immediately pulled low if either a NPOR

V_FBOvervoltage or Undervoltage condition occurs, or the A4450

junction temperature exceeds the thermal shutdown threshold

(TSD). For other faults, NPOR depends on the output voltage.

At power-up, NPOR must be initialized (set to a logic low) when

V_INis relatively low. At power-down, NPOR must be held in the

logic-low state as long as possible.

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Buck-Boost Controller

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A4450

An OCP (Overcurrent Pulses) counter and hiccup mode circuit

are incorporated to protect the A4450 regulator when the output

of the regulator is shorted to ground or when the load current is

too high.

Protection Features

The A4450 was designed to satisfy the most demanding automo-

tive and nonautomotive applications. In this section, a description

of protection features is provided.

If V_FBis less than 400 mV_TYP, the number of overcurrent pulses

is limited to 30; If V_FBis greater than 400 mV_TYP, the number of

overcurrent pulses is increased to 120 to accommodate the pos-

sibility of starting into a relatively high output capacitance.

UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)

An Undervoltage Lockout (UVLO) comparator in the A4450

monitors V_INat the VIN pin and keeps the regulator disabled

either if the voltage is below the start threshold, V_INSTART, while

If the OCP counter reaches the preset counts, a hiccup latch is

set and the COMP pin is quickly pulled down by a relatively low

resistance.

V_INis rising, or if V_INis below the stop threshold, V_INSTOP

,

while V_INis falling in Buck-Boost mode. The UVLO comparator

incorporates some hysteresis to help reduce on/off cycling of the

regulator due to the resistive or inductive drops in the VIN path

during heavy loading or during startup.

The hiccup latch also enables a small current sink connected to

the SS pin. This causes the voltage at the soft-start pin to slowly

ramp downward. When the voltage at the soft-start pin decays

to a preset low level, the hiccup latch is cleared and the small

current sink is turned off. At that instant, the SS pin will begin to

source current and the voltage at the SS pin will ramp upward.

This marks the beginning of a new, normal soft-start cycle. When

the voltage at the soft-start pin exceeds the Soft-Start Offset, the

error amplifier will force the voltage at the COMP pin to quickly

slew upward and PWM switching will resume. But the PWM

switching frequencies during the Hiccup SS upward period are

half of the SS PWM Foldback Frequency listed in Electrical

Characteristics table. Figure 9 below shows the Overcurrent Hic-

cup operation.

OVERCURRENT PROTECTION (OCP)

The A4450 monitors the current through the high-side MOSFET. If

this current exceeds the LX Short-Circuit Current Limit, I_LIM(LX)

for example when LX is hard short to ground (note: high V_IN

,

triggers a hard short condition more easily than low V_INcase), the

high-side MOSFET will be turned off and the regulator stays in the

latched-off status unless the regulator is reset. If this current is less

than I_LIM(LX)but above the pulse-by-pulse current limit I_LIM(Buck)

while in Buck mode or I_{LIM(BuckBoost)}while in Buck-Boost mode,

the A4450 will enter into Hiccup mode. The A4450 includes

leading-edge blanking to prevent false triggering the overcurrent

protection when the high-side MOSFET is turned on.

V_OUT

SS

1.8 V

0.2 V

V_EAVO(MAX)

COMP

120×

OCP

# OCP pending

on FB level

# OCP pending

on FB level

OCP*

LX

t_HIC,RECOVER

f_SWwill be half of SS

frequencies in EC table

Figure 9: Output Short Circuit to Ground Hiccup Operation

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A4450

If the short circuit at the regulator output remains, another hic-

cup cycle will occur. Hiccups will repeat until the short circuit

is removed or the converter is disabled. If the short circuit is

removed, the A4450 will soft-start normally and the output volt-

age will automatically recover to the desired level.

of LX to ground, as described in Overcurrent Protection section,

the high-side MOSFET will be turned off and the regulator will

stay in latched-off status unless the regulator is reset.

OVERVOLTAGE PROTECTION (OVP)

The A4450 includes two levels of overvoltage comparators

that monitor the FB pin voltage, V_FB. When rising V_FBfirst

exceeds 840 mV (typical, i.e. V_FBOV, 105% of 800 mV V_REF),

the high-side buck switch turns off and the boost gate driver LG

turns high, but NPOR still remains high. In this way, the further

buildup of output current is inhibited so that it cannot charge the

output capacitors further. If V_FBkeeps rising and exceeds the

second overvoltage threshold (V_FBNPOROV(H), 110% of V_REF),

NPOR will be pulled low, the high-side buck switch remains off,

and the boost gate driver LG remains high. If the duration of the

overvoltage condition is less than OV Deglitch Times, t_dOV(FILT)

(30 µs_TYP), no OV protection event is triggered. When V_FBdrops

below NPOR V_FBUV Thresholds specified in Electrical Char-

acteristics table, an NPOR Undervoltage fault is triggered and

NPOR will be pulled low.

Thus Hiccup mode is very effective protection for the overload

condition. It can avoid false trigger for a short term overload. For

the extended overload, the average power dissipation during Hic-

cup operation is very low to keep the controller cool and enhance

reliability.

BOOT CAPACITOR PROTECTION

The A4450 monitors the voltage across the boot capacitor to

detect if the capacitor is missing or short-circuited. If the boot

capacitor is missing, the regulator will enter hiccup mode after

approximate 14 PWM cycles. If the boot capacitor is shorted to

GND, Boot Undervoltage protection will be triggered and the

regulator will enter Hiccup mode after about 32 PWM cycles.

For a boot fault, hiccup mode will operate virtually the same as

described previously for an output short-circuit fault (OCP), with

SS ramping up and down as a timer to initiate repeated soft-start

attempts. Boot faults are nonlatched conditions, so the A4450

will automatically recover when the fault is corrected.

The error amplifier and its regulation voltage clamp are not

effective when the FB pin is disconnected. When the FB pin is

disconnected from the feedback resistor divider, a tiny internal

current source will force the voltage at the FB pin to rise above

the OV threshold and disables the regulator, preventing the load

from being significantly over voltage. If the conditions causing

the overvoltage are corrected, the regulator will automatically

recover.

PROTECTION OF BUCK DIODE AT LX NODE

If the buck diode at LX node is missing or damaged (open), the

LX node will be subject to unusually high negative voltages. These

negative voltages may cause the A4450 to malfunction and could

lead to damage. When the buck diode is missing, the internal ESD

diode will carry most of the freewheeling current and will cause

thermal shutdown. Also if this diode is shorted, which is hard short

Figure 10 below shows a timing diagram of UV/OV conditions

with respect to NPOR (refer to Electrical Characteristics table).

V_FBNPOROV(H)

V_FBNPOROV(L)

FB

V_FBNPORUV(H)

V_FBNPORUV(L)

t_dOV(FILT)

t_dUV(FILT)

NPOR

t_dNPOR

Figure 10: UV/OV Delay Timing Diagram (not scaled)

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A4450

THERMAL SHUTDOWN (TSD)

The A4450 protects itself from overheating by monitoring its

junction temperature. If the junction temperature exceeds the

Thermal Shutdown Threshold (T_TSD, 170°C_TYP), the A4450 will

stop PWM switching and pull NPOR low. TSD is a non-latched

fault, so the A4450 will automatically recover if the junction

temperature decreases by approximately 20°C from T_TSD

.

PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS

The A4450 was designed to satisfy the most demanding automo-

tive and nonautomotive applications. For example, the A4450

was carefully designed “up front” to withstand a short circuit to

ground at each pin without suffering damage.

In addition, care was taken when defining the A4450’s pinout

to optimize protection against pin-to-pin adjacent short circuits.

For example, logic pins and high-voltage pins were separated as

much as possible. Inevitably, some low-voltage pins were located

adjacent to high-voltage pins. In these instances, the low-voltage

pins were designed to withstand increased voltages, with clamps

and/or series input resistance, to prevent damage to the A4450.

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DESIGN AND COMPONENT SELECTION

PWM Switching Frequency (f_SW, R_FSET

Setting the Output Voltage

)

The output voltage of the regulator is determined by a resistor

divider from the output node (V_OUT) to the FB pin as shown in

Figure 11. There are tradeoffs when choosing the value of the

feedback resistors. If the series combination (R_FB1+ R_FB2) is

too low, then the light load efficiency of the regulator will be

reduced. To maximize efficiency, it’s best to choose higher values

of resistors. If the parallel combination (R_FB1//R_FB2) is too high,

then the regulator may be susceptible to noise coupling onto the

FB pin. 1% resistors are recommended to maintain the output

voltage accuracy.

The desired switching frequency (f_SW) can be set with a resistor

R_FSETconnected at pin FSET/SYNC to the ground. The recom-

mended R_FSETvalue for various switching frequencies f_SWcan be

obtained from either Table 1 or Figure 12:

3000

2500

2000

1500

1000

500

R_FB1

V_OUT

FB

R_FB2

< <

Figure 11: Connecting a Feedback Divider to

Set the Output Voltage

0

The feedback resistors must satisfy the ratio shown in equation

0

10

20

30

40

50

60

70

80

90

below to produce a desired output voltage, V_OUT

.

R_FSET(kΩ)

V_OUT

0.8 V

R_FB1

R_FB2

– 1

Figure 12: PWM Switching Frequency f_SWversus R_FSET

Table 1: f_SWversus R_FSET

=

(7)

After the output voltage is set, the range resistor R_NG(kΩ) at

RNG pin can be calculated from equation 3 found under Opera-

tion Modes in the Functional Description section, repeated

below:

f_SW(kHz)

2500

2300

2000

1500

1250

1000

800

R_FSET(kΩ)

6.04

6.81

7.87

V_OUT(V) × 1.844

10.0

R_NG

=

D_BUCK0

12.7

15.8

where D_BUCK0is the preferred buck duty cycle at the instant

when the boost switch starts to switch, typically set at around 0.6

to 0.65.

20.0

600

26.7

400

41.2

300

53.6

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

In Buck mode, the peak inductor current is:

Output Inductor (L_O)

For the peak current-mode control, the priority to consider when

selecting the inductor is to prevent the subharmonic oscillations

when the duty cycle is near or above 50%. To prevent the subhar-

monic oscillations, the theorectical slope compensation ramp S_E

should be at least 50% of the down slope of the inductor current.

In the A4450, the inductor value L_Ois suggested to start with the

equation below, because A4450 will also operate in Buck-Boost

mode:

ΔI_L

I_PEAK= I_OUT

+

(10)

2

where

V_OUT× (V_IN(MAX)– V_OUT

V_IN(MAX)× f_SW× L_O

)

ΔI_L=

After an inductor is chosen, it should be tested during output

0.5 × V_OUT

S_E

V

_OUT– V_IN(MIN)

L_O≥ 1.5 × max

,

(8)

(

)

short-circuit conditions. The inductor current should be moni-

tored using a current probe. A good design should ensure neither

the inductor nor the regulator are damaged when the output is

shorted to ground at the highest expected ambient temperature.

S_E

where V_OUTis the output voltage, V_IN(MIN)is the minimum input

voltage, S_Eis in A/µs, which scales with the switching frequency

and can be estimated by interpolating from Electrical Characteris-

tics table, and L_Ois in µH.

Buck Diode (D₁) and Boost Diode (D₂)

Schottky diodes with proper ratings should be chosen for the

buck diode (D₁) and boost diode (D₂), because of their low

forward voltage drop and fast reverse recovery time. The key

parameters in D₁and D₂selection are the average forward current

I_f(AVG)and the DC reverse voltage.

Ideally, the inductor should not saturate at the highest pulse-by-

pulse current limit. This may be too costly. At the very least, the

inductor should not saturate at the peak operating current.

In Buck-Boost mode, the peak inductor current is calculated as:

The boost diode D₂should be greater than V_OUTwith some

margin. The average forward current rating of the boost diode

should be above the full load current, and the peak current should

be above the peak inductor current which is calculated in previous

Output Inductor section.

ΔI_L

I_OUT

+

× (1 – D_Buck)

2

(9)

I_PEAK

=

1 – D_BOOST(MAX)

where

The buck diode D₁must be able to withstand the input voltage

when the high-side buck switch is on. Therefore, the reverse

voltage rating should be greater than the maximum expected V_IN

with some margin.

V_IN(MIN)× D_Boost(MAX)V_IN(MIN)× D_Boost(MAX)

,

ΔI_L= max

{

f_SW× L_O

When the buck switch is off, the buck diode D₁must conduct the

output current. The average forward current rating of the buck

diode should be above the full load current.

V_IN(MIN)– V_OUT

+

× (D_Buck– D_Boost(MAX))

}

f_SW× L_O

V

_IN(MIN)× 1.844

D_Boost(MAX)= 1 –

R_NG

V_OUT

V_IN(MIN)

D_Buck(MAX)= (1 – D_Boost(MAX)) ×

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

choices for output capacitors. It should be noted that the effective

capacitance of the ceramic capacitors decrease due to the DC

bias effect.

External Boost Switch

The A4450 requires a N-channel MOSFET as the external boost

switch to form the buck-boost configuration. A suitable boost

switch should have low gate charge, small on-resistance, break-

down voltage greater than V_OUT, and maximum gate driver

voltage greater than 8 V. The maximum current I_DS(MAX)should

be larger than the peak inductor current calculated in Output

Inductor section. STL10N3LLH5 from STMicroelectronics and

NVTFS4823N from ON Semiconductor are good examples.

A 10 kΩ_TYPresistor must be added at LG pin to ground to avoid

false turn-on from coupling noise.

For larger bulk values of capacitance, a high quality low ESR

electrolytic output capacitor can be used; however, electrolytic

capacitors have poor tolerance, especially over temperature. The

ESR of electrolytic capacitors usually increases significantly at

cold ambients, as much as 10×, which increases the output volt-

age ripple and, in most cases, reduces the stability of the system.

The transient response of the regulator depends on the number

and type of output capacitors. In general, minimizing the ESR of

the output capacitance will result in a better transient response. At

the instant of a fast load transient (di/dt), the output voltage will

change by the amount:

Output Capacitors

In Buck-Boost mode, the output capacitors must supply the entire

output current when the boost switch is on. The output capacitors

are chosen based on the Buck-Boost mode instead of the Buck

mode where the demand is much less when the application runs

through both operation modes.

ꢀ

ΔV_OUTꢀ=ꢀΔI_LOAD× ESR_CO+ di/dt × ESL_CO

(13)

After the load transient occurs, the output voltage will deviate

from its nominal value for a short time. This time will depend on

the system bandwidth, the output inductor value, and the output

capacitance. Eventually, the error amplifier will bring the output

voltage back to its nominal value.

The output capacitance in Buck-Boost mode is selected to limit

the output voltage ripple to meet the specification requirement,

and is calculated according to the equation below for the given

A higher bandwidth usually results in a shorter time to return to

the nominal voltage. However, with a higher bandwidth system

it may be more difficult to obtain acceptable gain and phase

margins.

output ripple voltage ΔV_OUT

:

I

_OUT× D_Boost(MAX)

(11)

C_OUT(MIN)

=

f_SW× ΔV_OUT

Input Capacitors

where

Selection of input capacitors should meet these three require-

ments: first, they must support the maximum expected input

surge voltage with adequate design margin; second, the capaci-

tor’s RMS current rating must be higher than the expected RMS

input current to the regulator; third, they must have enough

capacitance and a low enough ESR to limit the input voltage

deviation to something much less than the VIN UVLO hysteresis

at maximum loading and minimum input voltage.

V

_IN(MIN)(V) × 1.844

D_Boost(MAX)= 1 –

R_NG(kΩ)

The voltage rating of the output capacitors must support the out-

put voltage with sufficient design margin.

In Buck-Boost mode, the output voltage ripple (ΔV_OUT) is

mainly due to the voltage drop across the ESR of output capaci-

tors, ESR_CO, and the ESR requirements can be obtained from:

The RMS current of the input capacitors depends on the opera-

tion mode. During the Buck mode, the input capacitors must

deliver the RMS current according to:

ΔV_OUT

(12)

ESR_CO

=

I_OUT

(14)

I_{RMS =}I_OUT

×

D_Buck× (1 – D_Buck)

The ESR requirement can usually be met by simply using mul-

tiple capacitors in parallel or by using higher quality capacitors.

Ceramic capacitors have good ESR characteristics and are good

where D_Buckis the duty cycle of Buck switch.

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

The D_Buck× (1 – D_Buck) term in equation 14 above has an abso-

lute maximum value of 0.25 at 50% duty cycle.

Bootstrap Capacitor

A bootstrap capacitor must be connected between the BOOT

and LX pins to provide the gate drives for the buck and boost

switches. A 220 nF, 50 V, X7R ceramic capacitor is recommended

in A4450 applications.

During Buck-Boost mode, the RMS current of input capacitors is:

I_OUT

(15)

I_{RMS =}

D_Buck× (1 – D_Buck)

×

1 – D_Boost

Soft-Start and Hiccup Mode Timing (C_SS)

Thus the RMS currents of both operation modes should be

checked to ensure the input capacitors are able to handle the

larger ripple current of the two.

The soft-start time of the A4450 is determined by the value of the

capacitance at the soft-start pin, C_SS.

When the A4450 is enabled, the voltage at the soft-start pin will

The input capacitor(s) must limit the voltage deviations at the

start from 0 V and will be charged by the soft start current, I_SSSU

However, PWM switching will not begin instantly because the

voltage at the soft-start pin must rise above 400 mV (Soft-Start

Offset). The soft-start delay (t_SS(DELAY)) can be calculated using

equation 18:

.

VIN pin to a value significantly less than UVLO hysteresis dur-

ing maximum load and minimum input voltage. For Buck opera-

tion mode, the minimum input capacitance can be calculated as

follows:

I_OUT× D_Buck× (1 – D_Buck

0.85 × f_SW× ΔV_IN(MIN)

)

(16)

C_IN≥

400 mV

(18)

t_SS(DELAY)= C_SS×

( _I)

SS(SU)

For Buck-Boost mode, the required minimum input capacitance

becomes:

If the A4450 is starting with a very heavy load, a very fast

soft-start time may cause the regulator to exceed the pulse-by-

pulse overcurrent threshold. This occurs because the sum of the

full load current, the inductor ripple current, and the additional

I_OUT× D_Buck× (1 – D_Buck

(1 – D_Boost) × 0.85 × f_SW× ΔV_IN(MIN)

)

(17)

C_IN≥

current required to charge the output capacitors (I_CO= C_OUT

×

where ΔV_IN(MIN)is chosen to be much less than the hysteresis

of the VIN UVLO comparator (ΔV_IN(MIN) ≤ 150 mV is recom-

mended), and f_SWis the nominal PWM frequency.

V_OUT/t_SS) is higher than the pulse-by-pulse current threshold.

To avoid prematurely triggering the pulse-by-pulse current limit, a

larger soft-start capacitance can be used. The soft-start capacitor,

C_SS, should be calculated according to equation 19:

A good design should consider the DC bias effect on a ceramic

capacitor: as the applied voltage approaches the rated value, the

capacitance value decreases. This effect is very pronounced with

the Y5V and Z5U temperature characteristic devices (as much as

90% reduction) so these types should be avoided. The X7R type

capacitors should be the primary choices due to their stability

versus both DC bias and temperature.

I_SS(SU)×V_OUT× C_OUT

(19)

C_SS≥

0.8 V × I_CO

where V_OUTis the output voltage, C_OUTis the output capacitance,

I_COis the amount of current allowed to charge the output capaci-

tance during soft-start (recommend 0.1 A < I_CO< 1 A). Higher

values of I_COresult in faster soft-start times. Howewer, lower

values of I_COensure that hiccup mode is not falsely triggered. It

is recommended to start the design with an I_COof 0.1 A and to

increase I_COonly if the soft-start time is too slow.

For all ceramic capacitors, the DC bias effect is even more

pronounced on smaller case sizes, so a good design will use the

largest affordable case size (i.e. 1206 or 1210). Also, it is advis-

able to select input capacitors with plenty of design margin in

voltage rating to accommodate the worst-case transient input

voltage (such as a load dump as high as 40 V for automotive

applications).

The output voltage ramp time, t_SS, can be calculated by using

either of the following methods:

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

C_OUT

I_CO

C_SS

I_SS(SU)

A4450

LX

t_SS= V_OUT

×

or 0.8 V ×

(20)

v_O

(1-D_Boost)gm_POWER

When the A4450 is in hiccup mode, the soft-start capacitor is

ESR

used as a timing capacitor and sets the hiccup period. The soft-

start pin charges the soft-start capacitor with I_SS(SU)during a

startup attempt and discharges the same capacitor with smaller

current than I_SS(SU)between startup attempts. Therefore, the

effective duty cycle will be very low and the junction temperature

will be kept low.

v_c

R_L

C_OUT

Figure 14: Simpliﬁed Small Signal Model of

A4450 Power Stage

Compensation Components (R_Z, C_Z, C_P)

where gm_POWERis COMP to LX Current Gain (see Electrical

Characteristics table), i.e. the transconductance of power stage;

D_Boostis the duty cycle of boost switch,

To compensate the system, it is important to understand the over-

all control loop response in frequency domain. The A4450 simpli-

fied control loop, consisting of power stage and transconductance

error amplifier, is shown in Figure 13 for compensation analysis.

The error amplifier uses a Type II compensation network to

ensure system stability and to optimize transient response with

desirable phase margin and gain margin.

0,

_IN(MIN)(V) × 1.844

in Buck mode

D_Boost

=

V

, in Buck-Boost mode

1 –

{

R_NG(kΩ)

Boost

Diode

A4450

LX

The control-to-output transfer function of the power stage is

shown in equation 21 and consists of a DC gain, one dominant

pole, and one ESR zero.

V_OUT

ESR

Boost

Buck

gm_POWER

Switch

Diode

R_L

s

C_OUT

1 +

Q2

v_o

v_c

2π × f_ESR(z)

(21)

power = G_DC(power)

×

0.8 V

EA

+

COMP

v_c

s

FB

1 +

-

C_P

2π × f_power(p)

R_FB1

gm_EA

R_FB2

R_Z

C_Z

R_O(EA)

where

G_DC(power) is the DC gain of the power stage,

G_DC(power)= (1 – D_Boost) × gm_POWER× R_L,

Figure 13: Simpliﬁed Overall Current-Mode Control Loop

f_ESR(z)is the ESR zero of the power stage,

Figure 14 is a simplified small signal model of the A4450 power

stage. The power stage is approximated as a voltage-controlled

current source to provide current to the load and output capacitor.

Because the duty cycle of boost switch Q2 is programmed with

R_NGresistor at pin RNG and the inductor provides current to the

output only during off-time of Q2, the transconductance of the

voltage-controlled current source is expressed as (1 – D_Boost) ×

1

f_ESR(z)

=

2π × ESR × C_OUT

f_power(p)is the dominant pole of the power stage,

1

f_power(p)

=

2π × R_L× C_OUT

R_Lis the load resistance,

gm_POWER

.

ESR is the equivalent series resistance of the output capacitor,

_OUTis the output capacitance.

C

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

For a design with very low-ESR-type output capacitors (i.e.

ceramic or OSCON output capacitors), the ESR zero is usually

at a very high frequency, so it can be ignored. If the ESR zero

falls below or near the 0 dB crossover frequency of the system

(as is the case with electrolytic output capacitors), then it should

be cancelled by the pole formed by the C_Pcapacitor and the R_Z

resistor (identified and discussed later as f_EA(p2)).

1

f_EA(p2)

=

2π × R_Z× C_P

Placing f_EA(z)just above f_power(p)will result in excellent phase

margin, but relatively slow transient recovery time.

The sum of power stage control-to-output response equation 21

and the feedback loop response equation 22, including error

amplifier, is the overall loop frequency response of the entire

system. The goal of compensation design is to shape the transfer

function of the overall loop to get a stable converter with the

desired loop gain and phase margin.

The feedback loop includes a feedback output voltage divider

(R_FB1and R_FB2), the error amplifier (gm_EA), and the compensa-

tion network (R_Z, C_Z, and C_P). The transfer function of the feed-

back can be derived and simplified if R_O(EA)≫ R_Z, and C_Z≫ C_P.

In most cases, R_O(EA)> 2 MΩ, 1 kΩ < R_Z< 100 kΩ, 220 pF <

C_Z< 47 nF, and C_P< 50 pF, so the following equations are very

accurate:

A Generalized Tuning Procedure

1. Choose the system bandwidth, f_C, the frequency at which the

magnitude of the gain will cross 0 dB. Recommended values

for f_Care f_SW/20 < f_C< f_SW/7.5. A higher value of f_Cwill gen-

erally provide a better transient response, while a lower value

of f_Cwill be easier to obtain higher gain and phase margins.

s

1 +

v_c

v_o

2π × f_EA(z)

feedback = G_DC(EA)

×

s

1 +

)(

(

)

2π × f_EA(p1)

2π × f_EA(p2)

(22)

2. Calculate the R_Zresistor value to set the desired system

bandwidth (f_C),

where

R_FB1+ R_FB2

R_FB2

2 × π × C_OUT

gm_POWER× gm_EA

G_DC(EA)is the DC gain of the feedback loop,

R_Z= f_C×

×

R_FB2

G_DC(EA)

=

× gm_EA× R_O(EA)

3. Calculate the dominant pole frequency of power stage

(f_power(p)) formed by C_OUTand R_L.

R_FB1+ R_FB2

gm_EAis the error amplifier transconductance (see EC table),

1

f_power(p)

=

R_O(EA)is the output resistance of the error amplifier (the small

output capacitance of the error amplifer is neglected), and

2π × R_L× C_OUT

4. Calculate a range of values for the C_Zcapacitor and set the

compensation zero below the one fourth of the crossover

frequency f_C,

RO_(EA)= AVOL / gm_EA

AVOL is the error amplifier open-loop voltage gain (see EC

table),

4

1

< C_Z<

2 × π × R_Z× 1.5 × f_power(p)

2 × π × R_Z× f_C

f_EA(z)is the low-frequency zero of the error amplifier compensa-

tion network,

To maximize system stability (i.e. have the most gain mar-

gin), use a higher value of C_Z. To optimize transient recovery

time at the expense of some phase margin, use a lower value

of C_Z.

1

f_EA(z)

=

2π × R_Z× C_OUT

f_EA(p1)is the low-frequency pole of the error amplifier compen-

sation network,

5. Calculate the frequency of the ESR zero (f_ESR(z)) formed by

the output capacitor(s).

1

f_EA(p1)

=

f_ESR(z)

=

2π × R_O(EA)× C_Z

2π × ESR × C_OUT

f_EA(p2)is the high-frequency pole of the error amplifier compen-

sation network,

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

A. If f_ESR(z)is at least 1 decade higher than the target

B. If f_ESR(z)is near or below the target crossover frequency

(f_C) then use equation above to calculate the value of C_Pby

setting f_EA(p2)equal to f_ESR(z). This is usually the case for a

design using high ESR electrolytic output capacitors.

crossover frequency (f_C), then f_ESR(z)can be ignored.

This is usually the case for a design using ceramic output

capacitors. Use equation below to calculate the value of

C_Pby setting f_EA(p2)to either 5 × f_Cor f_SW/2, whichever

is higher.

Typical design examples are provided for V_OUT= 5 V and V_OUT

= 8 V with f_SW= 400 kHz and 2 MHz respectively.

1

f_EA(p2)

=

2π × R_Z× C_P

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

VBAT

Boot diode

VIN

BOOT

VIN

D_BAT

C_boot

Boost Diode

L_O

0.22 µF

D₂

V_OUT= 5 V

+

PDS1040L

R_IN

LX

C_B

C_IN

Buck Diode

D₁

5.11 Ω

C_O1

C_O2

AVIN

1.0 µF

C_n

COMP

A4450

Q₂

C_P

LG

24.9 kΩ

4.75 kΩ

R_Z

C_Z

R_FB1

10 kΩ

R_LG

FB

R_FB2

RNG

FSET/SYNC

SS

<< V_OUT

R_NG

R_FSET

R_PU

10 kΩ

22 nF

NPOR

GND

C_SS

3.3 kΩ

EN

PGND

0.1 µF

Figure 15: Schematic of 5 V_OUTDesign Example at 400 kHz and 2 MHz

Table 2: Recommended Key Components of 5 V_OUTat 400 kHz and 2 MHz Designs

Reference

Description

Manufacturer/Part Number

ST, STL10N3LLH5

Q2 – Boost Switch

NFET, 20 V/30 V, 25 mΩ and 14 nC_MAX@ 4.5 V_GS

OnSemi, NVTFS4823N

Vishay, SS3P4-M3/84A

Panasonic, EEE-FK1H470XP

TDK, Murata, Taiyo Yuden

D₁, D₂

C_B

Schottky 3 A, 40 V

47 µF, electrolytic capacitor, 50 V

Total ~10 µF, ceramic capacitors, X7R, ≥50 V

2 MHz 5 V_OUT(R_FSET= 7.87 kΩ, R_NG= 15 kΩ)

(7.32 kΩ + 2.2 nF)//33 pF

C_IN

(R_Z+C_Z)//C_P

L_O

–

10 µH, I_R= 5.2 A, I_SAT= 12.5 A, 27 mΩ

Total ~20 µF, ceramic, X7R, ≥16 V

BAS16

Wurth, 74437368100

TDK, Murata, Taiyo Yuden

NXP, Vishay

C_O

Boot Diode

400 kHz 5 V_OUT(R_FSET= 41.2 kΩ, R_NG= 15 kΩ)

(9.31 kΩ + 5.6 nF)//10 pF

(R_Z+C_Z)//C_P

L_O

–

33 µH, I_R= 4.2 A, I_SAT= 5.5 A, 45 mΩ

Total ~30 µF, ceramic, X7R, ≥16 V

BAS16

Wurth, 7447709330

TDK, Murata, Taiyo Yuden

NXP, Vishay

C_O

Boot Diode

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

VBAT

Boot diode

3 V Zener diode

VIN

BOOT

VIN

D_BAT

C_boot

Boost Diode

D₂

L_O

0.22 µF

V_OUT= 8 V

+

PDS1040L

R_IN

LX

C_B

C_IN

Buck Diode

D₁

5.11Ω

C_O1

C_O2

AVIN

1.0 µF

C_n

COMP

Q₂

C_P

LG

A4450

R_Z

C_Z

R_FB1

46.4 kΩ

5.11 kΩ

10 kΩ

R_LG

FB

R_FB2

RNG

FSET/SYNC

SS

<<V_AUX≤ 5 V

R_NG

R_FSET

R_PU

10 kΩ

22 nF

NPOR

GND

C_SS

3.3 kΩ

EN

PGND

0.1 µF

Figure 16: Schematic of 8 V_OUTDesign Example at 400 kHz

Table 3: Recommended Key Components of 8 V_OUTat 400 kHz Design

Reference

Description

Manufacturer/Part Number

400 kHz 8 V_OUT(R_FSET= 41.2 kΩ, R_NG= 23.2 kΩ)

(20.5 kΩ + 3.3 nF)//10 pF

(R_Z+C_Z)//C_P

L_O

–

47 µH, I_R= 3.8 A, I_SAT= 4.5 A, 60 mΩ

Total ~55 µF, ceramic, X7R, ≥16 V

BAS16

Wurth, 7447709470

TDK, Murata, Taiyo Yuden

NXP, Vishay

C_O

Boot Diode

Zener Diode

3 V Zener Diode BZT52C3V0T-7

Diodes Inc.

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

VBAT

VIN

BOOT

VIN

D_BAT

C_boot

Boost Diode

L_O

0.22 µF

D₂

V_OUT= 8 V

+

PDS1040L

R_IN

LX

C_B

C_IN

Buck Diode

D₁

5.11 Ω

C_O1

C_O2

AVIN

1.0 µF

C_n

A4450

COMP

Q₂

C_P

LG

46.4 kΩ

5.11 kΩ

R_Z

C_Z

R_FB1

10 kΩ

R_LG

FB

R_FB2

RNG

FSET/SYNC

SS

V

_AUX≤ 5 V

<<

R_NG

R_FSET

R_PU

10 kΩ

22 nF

NPOR

GND

C_SS

3.3 kΩ

EN

PGND

0.1 µF

Figure 17: Schematics of 8 V_OUTDesign Example at 2 MHz

Table 4: Recommended Key Components of 8 V_OUTat 2 MHz Design

Reference

Description

Manufacturer/Part Number

2 MHz 8 V_OUT(R_FSET= 7.87 kΩ, R_NG= 23.2 kΩ)

(20 kΩ + 2.2 nF)//10 pF

(R_Z+C_Z)//C_P

–

L_O

10 µH, I_R= 5.2 A, I_SAT= 12.5 A, 27 mΩ

Total ~20 µF, ceramic, X7R, ≥16 V

Wurth, 74437368100

TDK, Murata, Taiyo Yuden

C_O

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

The recommended operation ranges of design examples are

shown below for reference:

R_FSET= 41.2 kΩ

R_FSET= 7.87 kΩ

9

8

7

6

5

4

3

0

5

10

15

20

25

30

35

40

Input Voltage (V)

Figure 18: Recommended Operating Range, I_OUT= 1 A

R_FSET= 41.2 kΩ

R_FSET= 7.87 kΩ

9

8

7

6

5

4

3

0

5

10

15

20

25

30

35

40

Input Voltage (V)

Figure 19: Recommended Operating Range, I_OUT= 0.5 A

Note: The input voltage of 8 V_OUT, 2 MHz configuration with boot diode and 3 V Zener diode added (the same as in 8 V_OUT

400 kHz) can go as low as ~4 V at 1 A load (versus 5.5 V without the help circuit) and as low as ~3.5 V at 0.5 A load (versus 5 V

without the help circuit).

,

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1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

POWER DISSIPATION AND THERMAL CALCULATIONS

The power dissipated in the A4450 is the sum of the power dis-

sipated from the V_INsupply current (P_IN), the switching power

dissipation of the integrated buck switch (P_SW1), the conduction

power dissipation of the integrated Buck switch (P_COND1), and

the power dissipated by both gate drivers (P_DRIVER).

The power dissipated by the high-side Buck switch while it is

conducting can be calculated using equation 25,

P_COND1= I²_RMS(FET)× R_DS(ON)HS

=

(25)

D_Buck

ΔI_L²

12

× I²

+

× R_DS(ON)HS

OUT

2

(_{(1 – D}) ( )

The power dissipated from the V_INsupply current can be calcu-

lated using equation 23,

)

Boost

where

I_OUTis the regulator output current,

ΔI_Lis the peak-to-peak inductor ripple current,

_Boostis the duty cycle of the boost switch,

D_Buckis the duty cycle of the buck switch, and

P_IN= V_IN× I_Q+ (V_IN– V_GS1) × Q_G1× f_SW+ P_IN2

where

(23)

(V_IN– V_GS2) × Q_G2× f_SW, in Buck-Boost mode

D

P_IN2

=

{

0,

in Buck mode

R_DS(ON)HSis the on-resistance of the high-side buck switch

MOSFET.

V_INis the input voltage,

I_Qis the input quiesent current drawn by the A4450 (see

Electrical Characteristics table),

The R_DS(ON)HSof the high-side buck switch has some initial

tolerance plus an increase from self-heating and elevated ambi-

ent temperatures. A conservative design should accomodate

an R_DS(ON)with at least a 15% initial tolerance plus 0.39%/°C

increase due to temperature.

V_GS1is the MOSFET gate drive voltage of high-side buck

switch (typically 5 V),

Q_G1is the internal high-side buck switch gate charges

(approximately 5.7 nC),

The sum of the power dissipated by both gate drivers of the inte-

grated buck switch and the external boost switch is,

Q_G2is the external boost switch gate charges, and

f_SWis the PWM switching frequency.

P_DRIVER= P_G1+ P_G2

(26)

where

P_G1= Q_G1× V_GS1× f_SW

The switching power dissipation of the high-side buck switch can

be calculated using equation 24,

I_OUT

1 – D_Boost

1

2

Q_G2× V_GS2× f_SW, in Buck-Boost mode

P_SW1

=

× V_IN

×

× (t_r+ t_f) × f_SW

(24)

P_G2

=

{

where

V_INis the input voltage,

I_OUTis the regulator output current,

0, in Buck mode

Finally, the total power dissipated by the A4450 (P_TOTAL) is the

sum of the previous equations,

D_Boostis the duty cycle of the boost switch,

f_SWis the PWM switching frequency, and

P_TOTAL= P_IN+ P_SW1+ P_COND1+ P_DRIVER

(27)

The average junction temperature can be calculated with the

equation 28,

t_rand t_fare the rise and fall times measured at the SW node.

T_J= P_TOTAL× R_θJA+ T_A

(28)

The exact rise and fall times at the LX node will depend on the

external components and PCB layout, so each design should be

measured at full load. Approximate values for both t_rand t_frange

from 5 to 20 ns.

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

where

It is critical that the thermal pad on the bottom of the IC should be

connected to at least one ground plane using multiple vias.

P_TOTALis the total power dissipated from equation 27,

As with any regulator, there are limits to the amount of heat that

can be dissipated before risking thermal shutdown. There are trade-

offs between ambient operating temperature, input voltage, output

voltage, output current, switching frequency, PCB thermal resis-

tance, airflow, and other nearby heat sources. Even a small amount

of airflow will reduce the junction temperature considerably.

R_θJAis the junction-to-ambient thermal resistance of QFN-20

package (37°C/W on a 4-layer PCB), and

T_Ais the ambient temperature.

The maximum junction temperature will be dependent on how

efficiently heat can be transferred from the PCB to the ambient air.

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115 Northeast Cutoff

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1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

PCB COMPONENT PLACEMENT AND ROUTING

A good PCB layout is critical for the A4450 to provide clean,

stable output voltages. Follow these guidelines to ensure a good

PCB layout. Figure 20 shows a typical buck-boost converter

schematic with the critical power paths/loops.

away from the LX and LXb polygons.

6. Place the feedback resistor divider (R_FB1and R_FB2) very

close to the FB pin. Make the ground side of R_FB2as close as

possible to the A4450.

1. Place the ceramic input capacitors C_INas close as possible to

the VIN pin and GND pins to minimize the area of the criti-

cal Loop 1 (shown in Figure 20); and the traces of the input

capacitors to VIN pin should be short and wide to minimize

the inductance. The larger input capacitor can be located

further away from VIN pin. The input capacitors and A4450

IC should be on the same side of the board with traces on the

same layer.

7. Place the compensation components (R_Z, C_Z, and C_P) as

close as possible to the COMP pin. R_Zshould be in COMP

pin side and C_Zin GND side. Also make the ground side of

C_Zand C_Pas close as possible to the IC.

8. Place the FSET resistor as close as possible to the SYNC/

FSET pin; place the soft-start capacitor C_SSas close as pos-

sible to the SS pin.

9. The output voltage sense trace (from V_OUTto R_FB1) should

be connected as close as possible to the load to obtain the

best load regulation.

2. The critical Loop 2 consisting of boost diode, output capaci-

tor C_OUT, and the external boost switch Q2 should be mini-

mized with relatively wide traces.

10. Place the bootstrap capacitor (C_boot) near the BOOT pin and

keep the routing from this capacitor to the LX polygon as

short as possible.

3. The Loop 3 shows the external boost switch gate driver cur-

rent loop. It is supplied from the bootstrap capacitor, C_boot

Ensure that the gate driver Loop 3 is small and place the

traces parallel with small gap.

.

11. When connecting the input and output ceramic capacitors,

use multiple vias to GND and place the vias as close as possi-

ble to the pads of the components. Do not use thermal reliefs

around the pads for the input and output ceramic capacitors.

4. Ideally, the output capacitors, output inductor, buck diode,

boost diode, boost switch, and the controller IC should be on

the same layer. Connect these components with fairly wide

traces. A solid ground plane should be used as a very low-

inductance connection to the GND.

12. To minimize PCB losses and improve system efﬁciency, the

input and output traces should be as wide as possible and be

duplicated on multiple layers, if possible.

5. Place the output inductor (L_O) as close as possible to the

LX pin with short and wide traces. The LX and LXb nodes

have high dv/dt rate, which are the root cause of many noise

issues. It is suggested to minimize the copper area to mini-

mize the coupling capacitance between these nodes and other

noise-sensitive nodes; However the nodes’ area cannot be too

small in order to conduct high current. A ground copper area

can be placed beneath the node to provide additional shield-

ing. Also, keep low-level analog signals (like FB, COMP)

13. The thermal pad under the IC should be connected to the

GND plane (preferably on the top and bottom layer) with

as many vias as possible. Allegro recommends vias with an

approximately 0.25 to 0.30 mm hole and a 0.13 and 0.18 mm

ring.

14. EMI/EMC issues are always a concern. Allegro recommends

having locations for an RC snubber from LX to ground. The

resistor should be 0805 or 1206 size.

BOOT

C_boot

Boost

Diode

VOUT

A4450

LXb

Lo

LX

VIN

Q1

Buck

Diode

Q2

2

C_IN

1

LG

C_OUT

3

GND

Figure 20: Typical Buck-Boost Regulator

A single-point ground is recommended, which could be the exposed thermal pad under the IC.

Allegro MicroSystems, LLC

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Buck-Boost Controller

with Integrated Buck MOSFET

A4450

PACKAGE OUTLINE DRAWING

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-220WGGD)

Dimensions in millimeters

NOT TO SCALE

Exact case and lead conﬁguration at supplier discretion within limits shown

0.30

0.50

4.00 0.10

0.08 REF

20

0.95

1

2

A

1

2

4.00 0.10

4.10

2.60

DETAIL A

2.60

4.10

D

C

21X

0.75 0.05

0.08

C

SEATING

PLANE

C

PCB Layout Reference View

0.22 0.05

0.50 BSC

0.40 0.10

0.203 REF

0.08 REF

0.20

0.40 0.10

0.05 REF

B

Detail A

2.45 0.10

2

1

A

B

Terminal #1 mark area

Exposed thermal pad (reference only, terminal #1 identiﬁer appearance at supplier

discretion)

20

0.25

2.45 0.10

0.10

C

Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM);

all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to

meet application process requirements and PCB layout tolerances; when mounting

on a multilayer PCB, thermal vias at the exposed thermal pad land can improve

thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

Coplanarity includes exposed thermal pad and terminals

D

Figure 21: Package ES, 20-Pin QFN with Exposed Thermal Pad and Wettable Flank

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Buck-Boost Controller

with Integrated Buck MOSFET

A4450

Revision Table

Number

Date

Description

–

June 29, 2016

Initial release

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com


型号：	A4450
厂家：	ALLEGRO MICROSYSTEMS
描述：	Buck-Boost Controller with Integrated Buck MOSFET
文件：	总34页 (文件大小：680K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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