A6271KLPTR-T [ALLEGRO]
Automotive, High-Current LED Controller;
| 型号： | A6271KLPTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Automotive, High-Current LED Controller |
| 文件： | 总36页 (文件大小：654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A6271
Automotive, High-Current LED Controller
FEATURES AND BENEFITS
• Automotive AEC-Q100 qualified
• Constant-current LED drive
DESCRIPTION
The A6271 is a DC-DC converter controller, providing a
programmable constant-current output for drivinghigh-power
LEDs in series. The controller is based on a programmable
fixed-frequency, peak current-mode control architecture. The
DC-DC converter can be configured in a myriad of different
switching configurations including boost, buck-boost, and
buck (ground-referenced switch).
• 4.2 to 50 V supply
• 53.3 V maximum LED string voltage
• Boost, buck-boost, and buck switching converters
• Programmable switching frequency 70 to 700 kHz
• PWM-controlled PMOS driver allows accurate LED
current control at low duty cycles
TheA6271 provides a cost-effective solution using an external
logic-level MOSFET and minimum additional external
components. The maximum LED current is set with a single
external sense resistor and can be accurately modulated using
a current reference input (analog control). External PWM
dimmingispossibleviathePWMINinput,whichalsoprovides
ashutdownmode.Asanalternative,aninternalPWMdimming
circuit can be used by programming the PWMIN and DR pins.
Either PWM scheme controls the PWMOUT output which
drives an external p-channel MOSFET connected in series
with the LED string. This MOSFET is also used to isolate the
load during certain fault conditions, including output shorts
to ground.
• Dimming via external PWM, internal PWM and/or
analog dimming
• Frequency dither scheme for effective spread spectrum to
reduce EMI
• Comprehensive fault protection and fault flag
PACKAGES:
16-Pin eTSSOP (LP)
with Exposed Thermal Pad
Continued on next page...
APPLICATIONS
• Automotive high-power LED lighting systems
• Fog lights, reversing lights, daytime running lights,
position lights, headlights
Not to scale
56 µH
L1
D2
VBAT
C1
C2
4.7 µF
4.7 µF
R6
C7
R5
150 Ω
1.35 Ω
47 nF
VIN
LP
LN
PWMOUT
OVUV
VREG
GND
C3
1 µF
M2
R1
2.7 kΩ
FAULTn
DR
R7
LED1
4.3 k
Ω
A6271
C8
4.4 µF
R8
12 Ω
M1
PWMIN
IREF
PWM Control
R11
SG
SP
LED14
240 kΩ
R9
OSC
DITH
R3
COMP
1.3 kΩ
R4
R2
39 Ω
C6
22 pF
R10
75 mΩ
110 kΩ
73.2 kΩ
C4
C5
22 nF
680 nF
GND
Boost Switcher Driving 14 LEDs at 150 mA
A6271-DS, Rev. 5
December 2, 2016
A6271
Automotive, High-Current LED Controller
Description (continued)
TheA6271hasbeencarefullydesignedtominimizeelectromagnetic faults. Fixed-output overvoltage protection ensures no maximum
emissions through distributed decoupling and an externally voltage rating violations, even under a single point failure of the
programmable frequency dither circuit configured for the EMI programmable-outputovervoltageprotectioncircuit.Otherprotection
specificationCISPR25.Itisalsopossibletoprogramthefundamental features include: LED overload (boost), output undervoltage (buck
switchingfrequencybelow150kHzwheremostEMIstandardsbegin. or buck-boost), input supply (VIN) undervoltage, 5 V regulator
(VREG) output undervoltage, high-side supply (PWM PMOS)
undervoltage, and thermal protection.
TheA6271hasacomprehensivesetofintegratedprotectionfeatures
to protect the IC, the LED driver system, and the LED string against
SPECIFICATIONS
SELECTION GUIDE
Part Number
Packing1
Package
A6271KLPTR-T
4000 pieces per 13-in. reel
16-pin TSSOP with exposed thermal pad
1 Contact Allegro™ for additional packing options.
ABSOLUTE MAXIMUM RATINGS2
Characteristic
Symbol
Notes
Rating
Unit
V
VIN
VIN
–0.3 to 55
–0.3 to 58
PWMOUT, LP, LN, OVUV
V
OSC, DITH, COMP, FAULTn, SG, SP,
IREF, PWMIN, DR, VREG
–0.3 to 6.5
–0.5 to 0.5
150
V
V
LP
VLP
TJ(max)
Tstg
With respect to LN
Maximum Continuous Junction
Temperature
ºC
ºC
Storage Temperature Range
2 With respect to GND.
–55 to 150
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions3
Value
Unit
4-layer PCB based on JEDEC standard
34
ºC/W
RθJA
eTSSOP Package
2-layer PCB with 3.8in2 of copper area each side
Junction to thermal pad
43
2
ºC/W
ºC/W
RθJC
3 Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
PINOUT DIAGRAM AND TERMINAL LIST TABLE
16 VIN
COMP
IREF
1
2
3
4
5
6
7
8
15 LP
14 LN
FAULTn
OSC
13 PWMOUT
12 OVUV
11 GND
10 SP
PAD
DITH
DR
PWMIN
VREG
9
SG
Package LP, 16-Pin eTSSOP Pinout Diagram
Terminal List Table
Symbol
Number
Function
COMP
1
Compensation pin for output of GM error amplifier.
Analog dimming input. With a capacitor connected to this pin, provides a soft-start period when coming out of
sleep mode.
IREF
2
3
Open drain. Logic low indicates detection of a fault.
Faults include: LED overload (boost), output undervoltage (buck or buck-boost), output overvoltage,
programmable overvoltage, input supply (VIN) undervoltage, 5 V Regulator (VREG) output undervoltage.
FAULTn
OSC
DITH
DR
4
5
6
Oscillator input for setting switching frequency and for external synchronization.
Dither frequency range set. Connect resistor from this pin to GND. Connect to VREG if not used.
A voltage applied to this pin programs the duty cycle of PWM internal mode.
Used for either putting the device into sleep mode or analog dimming control. Can also be used for external or
internal PWM control.
PWMIN
7
VREG
SG
8
5 V regulator output. Connect filter capacitor from VREG to GND.
Switch gate drive output.
9
SP
10
11
12
13
14
15
16
Switch current sense and slope compensation.
Ground.
GND
OVUV
PWMOUT
LN
Programmable-output overvoltage and undervoltage protection input.
PWM gate drive for external p-channel MOSFET (active low).
LED current sense -ve.
LP
LED current sense +ve.
VIN
Main supply.
Exposed pad of both packages provides both electrical contact to the ground and good thermal contact to the
PCB. This pad must be soldered to the ground plane preferably by multiple through-hole vias.
PAD
–
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
RSL
VBAT
PWMOUT
OVUV
VIN
LN
LP
–
+
–8 V
wrt LP
Output OV
–
CB
CD
CA
+
AA
VREG
Prog
Output OV
5 V
Linear
Reg
VREG
FAULTn
Internal
Linear
Reg
PWM
Output UV
VIN UVLO
VREG UVLO
Fault
Block
Prog Output OV
Output OV
Thermal
+
CE
–
–
+
Overload
–
+
Analog
DIM/
Soft
–
AB
SG
IREF
CF
R
S
+
Q
Start
SP
+
PWM
AC–
RSLOPE
PWMIN
DR
–
RSS
CG
+
GND
Osc
Dither
Internal PWM
Generator
COMP
OSC
DITH
PWM
On/Off
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VIN = 5 to 45 V, unless noted otherwise.
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY and REFERENCE
VIN undervoltage turn off plus VIN undervoltage
hysteresis cleared; PWMOUT undervoltage turn-
on cleared
V
IN Functional Operating Range2
IN Quiescent Current
VIN
4.2
–
50
V
IINQ
IINS
SG Open Circuit
–
3.5
6
5
20
5.15
–
mA
µA
V
V
PWMIN = GND > disable time
IREG = 0 to 2 mA, VIN ≥ 5.3 V
–
4.85
4.65
5.04
–
VREG Output Voltage
VREG Output Voltage3
VREG
I
REG = 2 mA, VIN = 5 V
V
IREG = 2 mA, VIN = 9 to 45 V,
TJ = –40°C to 125°C
VREG
4.95
25
5.05
–
5.15
–
V
VREG Current Limit
GATE OUTPUT DRIVE
Turn-On Time
IREGCL
mA
tr
tf
CLOAD = 1 nF, 20% to 80%
CLOAD = 1 nF, 80% to 20%
–
–
–
–
–
–
–
30
30
–
–
ns
ns
ns
Ω
Turn-Off Time
Minimum Off-Time
toff(MIN)
135
1.7
–
165
–
TJ = 25°C, IGHx = –100 mA
TJ = 150°C, IGHx = –100 mA
TJ = 25°C, IGLx = 100 mA
TJ = 150°C, IGLx = 100 mA
Pull-Up On-Resistance
RDS(on)UP
3.6
–
Ω
0.75
–
Ω
Pull-Down On-Resistance
Output High Voltage
RDS(on)DN
2
Ω
VREG
0.1
–
VSGH
VSGL
ISG = –100 µA
ISG = 100 µA
–
–
VREG
0.1
V
V
Output Low Voltage
–
LOGIC INPUTS AND OUTPUTS
FAULTn Output (Open Drain)
FAULTn Output Leakage Current1
PWMIN Low Voltage
VOL
IOH
IOL = 1 mA, fault asserted
–
–1
–
–
–
0.4
1
V
µA
V
VO = 5.5 V, fault not asserted
VPWMINL
VPWMINH
VIhys
–
0.3
–
PWMIN High Voltage
2
–
V
Input Hysteresis
150
–
180
–1.5
–
mV
µA
PWMIN Sleep Pull-Up Current1
OSCILLATOR
IPWMSLEEP
–
ROSC = 51 kΩ
–
315
70
–
500
350
–
–
385
700
0.8
–
kHz
kHz
kHz
V
Oscillator Frequency
fOSC
R
OSC = 73.4 kΩ
Oscillator Frequency Range3
OSC Input Low Voltage
OSC Input High Voltage
OSC Watchdog Period
fOSC
VOIL
VOIH
tOSWD
–
2
–
V
Between successive rising edges
17
–
–
µs
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VIN = 5 to 45 V, unless noted otherwise.
Characteristics
LED CURRENT SENSE
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Input Bias Current LN
Input Bias Current LP
Differential Sense Voltage
Input Common-Mode Range
ANALOG DIMMING
Disable Time
ILN
ILP
VIDL
VCMLH
VLP = VLN = 12 V
–
–
5
–
–
µA
µA
mV
V
VLP = VLN = 12 V
200
204
–
PWMIN = high, VIDL = VLP – VLN, IREF > 1.2 V
VLP = VLN
200
5
208
53.3
tDISAN
VIDL
PWMIN = low
VIREF = 0.5 V
24.8
–
29
102
51
1
35
–
ms
mV
mV
V
Differential Sense Voltage
V
IREF = 0.25 V
47
–
55
–
IREF Maximum Voltage
VIREFMAX
VIREFMIN
Corresponds to sense voltage = 200 mV
Corresponds to sense voltage = 0 mV
IREF Minimum Voltage
–
0
–
V
PWM DIMMING: INTERNAL AND EXTERNAL
PWMIN to LED Turn-On Time
PWMIN to LED Turn-Off Time
PWMOUT Low Voltage
tDIMON
tDIMOFF
VPWMLO
IPULLUP
CL = 2 nF between PWMOUT and LN
CL = 2 nF between PWMOUT and LN
LED on, PWMOUT wrt LP, VIN = 10 V
PWMIN = low, PWMOUT wrt LP = 0 V
–
–
270
210
–
–
–
ns
ns
–9
–
–6.5
–
V
Peak Pull-Up Current1
–25
50
mA
mA
Peak Pull-Down Current
IPULLDOWN PWMIN = high, PWMOUT wrt LP = –8 V
–
–
PWM DIMMING: EXTERNAL
Disable Time
tDISEPWM
PWMIN = low
24.8
29
35
ms
PWM DIMMING: INTERNAL
Maximum PWM Dimming Frequency
Minimum PWM Dimming Frequency
PWM Dimming Frequency
fPWM
fPWM
fPWM
–
–
1000
200
200
90
–
–
Hz
Hz
Hz
%
70 kΩ between PWMIN and GND
180
87
–
220
93
–
TJ = 25°C
TJ = 150°C
TJ = 25°C
TJ = 150°C
TJ = 25°C
DPWM90
VDR = 3.24 V, fPWM = 200 Hz
90
%
4.5
–
5
5.5
–
%
PWM Duty Cycle
DPWM5
DPWM0
VDR = 180 mV, fPWM = 200 Hz
VDR = 0 V, fPWM = 200 Hz
5
%
–
0.3
3.6
14.5
–
%
VDRDCMAX Minimum voltage on DR for 100% duty cycle
–
–
V
Disable Time
tDISIPWM
PWMIN = low
12.4
17.5
ms
SOFT-START
Startup Ramp Up Source Current1
Ramp Up Threshold
ISOURCE
VRAMPUP
Coming out of sleep mode
–
–
–
–1
1
–
–
–
µA
V
Ramp Down Threshold
VRAMPDOWN
100
mV
SWITCH CURRENT SENSE AND AMPLIFIER
Input Bias Current1
IBIASS
VIDS
ACS
VSP = 300 mV, RSLOPE = 1.5 kΩ
–20
375
–
–
–
435
–
µA
mV
V/V
Switch Current Overload Threshold Voltage3
Voltage Gain
400
2.25
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VIN = 5 to 45 V, unless noted otherwise.
Characteristics
SLOPE COMPENSATION
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Sawtooth current waveform added to current-
sense input (SP)
Peak Current1
ISLOPE
–116
–
–93
µA
GM AMPLIFIER
Open Loop DC Gain
AVEA
gmCOMP
ICOMP
–
550
–
62
750
±50
±200
–
950
–
dB
µA/V
µA
Transconductance
COMP Source/Sink Current1
COMP Leakage Current1
ILCOMP
–
–
nA
DITHER GENERATOR
Dither Modulation Frequency
Maximum Switching Frequency
Minimum Switching Frequency
PROTECTION FEATURES
Fault Blank Timer4
fDITH
7.9
348
261
9.6
400
300
11.2
452
339
kHz
kHz
kHz
fOSCMAX
fOSCMIN
ROSC = 72 kΩ, RDITH = 110 kΩ
ROSC = 72 kΩ, RDITH = 110 kΩ
tFB
Startup
–
3
–
–
4.2
380
3.5
–
ms
V
VIN Undervoltage Turn-Off
VIN Undervoltage Hysteresis
VREG Undervoltage Turn-Off
VREG Undervoltage Hysteresis
LED Overcurrent Threshold
Fixed-Output Overvoltage Threshold
Programmable-Output Overvoltage Threshold
Output Undervoltage Threshold
VINUV
Decreasing VIN , IREG = 2 mA
3.9
DVINUV
VREGUV
DVREGUV
VOCLED
VFOOV
VPOOV
VOUV
250
3.25
–
–
mV
V
Decreasing VREG
–
300
320
55.5
–1.1
–
mV
mV
V
LP wrt LN
260
53.3
–1.24
–300
380
57
–1
–
Monitored at LP pin with respect to GND
OVUV wrt LN
V
OVUV wrt LN
mV
clock
cycles
Switch Current Overload Period
LED Overcurrent Period
tSCOP
tOPI
tOPV
tHIC
Inner loop switch current
–
–
64
2
–
–
clock
cycles
clock
cycles
LED Output Undervoltage Period
Hiccup Shutdown Period
–
30
–
LED overcurrent, or output undervoltage, or
overvoltage, or switch overload
22
26.5
31.75
ms
PWMOUT Undervoltage Turn-On
PWMOUT Undervoltage Turn-Off
Overtemperature Shutdown Threshold
Overtemperature Hysteresis
VPWMUVON Measured at LP wrt GND
VPWMUVOFF Measured at LP wrt GND
–
3.7
155
–
–
–
6
5.8
–
V
V
TJF
Temperature increasing
170
20
ºC
ºC
DTJ
Recovery = TJF – DTJ
–
1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2 Function is correct, but some parameters may not meet specification.
3 Parameters guaranteed by design and characterization.
4 Fault blank timer only enabled for either output undervoltage or switch current overload.
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
FUNCTIONAL DESCRIPTION
The A6271 is a DC-DC converter controller designed to drive
series-connected high-power LEDs in automotive applications.
The A6271 can be configured in a variety of switching topolo-
gies, including: boost, buck-boost, and buck (ground-referenced
switch). For each switching configuration, the appropriate loop
compensation (COMP) and slope compensation (SLOPE) passive
components are selected for optimal performance.
increases, causing the current demand signal to decrease. This
reduces the amount of energy transferred to the LED load by ter-
minating the switch current sooner and reducing the LED current.
EXTERNAL PULSE-WIDTH MODULATION DIMMING
The DR pin should be pulled to VREG.
During PWM operation, when PWMIN is pulled low, the LED
stack PWMOUT is pulled high with respect to LP, turning off
the external p-channel MOSFET, isolating the LED string. In
addition, the GM output (amplifier AB) is ‘parked’ (COMP com-
ponents disconnected) at the new level and the gate drive (SG)
is disabled. As the output capacitance is isolated from the LED
string, there is no loss of charge.
The A6271 integrates all the necessary control elements to
provide a cost-effective solution using an external logic-level,
n-channel MOSFET (switching device), p-channel MOSFET
(PWM device), and minimum additional external passive com-
ponents. The maximum LED current is set with a single external
sense resistor and can be accurately modulated using a current
reference input (analog control). Direct PWM control is possible
via the PWMIN input, which also provides a shutdown mode.
When PWMIN goes high impedance, or is pulled high, the
COMP components are reconnected (with the previous ‘parked’
value’), the gate drive (SG) is enabled, PWMOUT is pulled to
around –8 V with respect to LP turning on the external MOSFET
and allowing current to flow through the LED string.
Circuit Operation
CONVERTER
The controller is based on a fixed-frequency, peak current-mode
control architecture. There are two loops within the controller.
The inner loop, formed by the amplifier AC (refer to Functional
Block Diagram), the slope generator, the comparator, CF, and the
RS bistable, controls the inductor current as measured through
the switching MOSFET by the sense resistor RSS. The outer loop,
formed by the amplifier AA and the integrating GM amplifier
AB, controls the average LED current by providing the current
demand signal for the inner loop.
INTERNAL PULSE-WIDTH MODULATION DIMMING
Where an external PWM signal is not available, the internal
PWM generator can be used for controlling the LED brightness.
A resistor connected between the PWMIN pin and GND sets the
PWM frequency according to the following formula:
14,000
fPWM
RFREQ
=
where RFREQ is in kΩ and fPWM is in Hz.
The LED current is measured by the sense resistor, RSL, and is
averaged and amplified to a level where it is compared to the
internal reference current to produce an error signal at the output
of the GM amplifier, AB. This error signal is effectively the cur-
rent demand signal and determines the amount of energy trans-
ferred to the LEDs on a cycle-by-cycle basis via the inner loop.
The duty cycle is controlled by applying a voltage to the DR pin.
The VREG can be used for the supply voltage and a potential
divider can be used to set the DR voltage. An additional resistor
can be added in parallel via a MOSFET switch between DR and
GND to change the duty cycle between two levels.
The control loops work together as follows: at the beginning
of each oscillator cycle, the bistable is set and the switching
MOSFET is on. The switch current builds up due to the volt-
age developed across the inductor, and when the corresponding
signal produced at the output of amplifier AC reaches the current
demand level on the output of amplifier AB, the bistable is reset
and the switching MOSFET is turned off. The cycle is repeated
on the next oscillator cycle.
The relationship between the DR voltage and the duty cycle is as
follows:
PWM Duty cycle (%) = 27.81 × DR voltage
So, for example, with a DR voltage = 1.8 V, the programmed duty
cycle = 50%.
In terms of the control of the external MOSFET via the PWM-
OUT pin, the control is identical as the external PWM scheme.
If the current through the LEDs increases, the output of AA
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
tsoft × 1 × 10-6
When using the internal PWM scheme, an n-channel MOSFET
is required to open the ground connection of the resistor con-
nected between PWMIN and GND to ensure that startup occurs.
The gate of the MOSFET is connected to VREG as shown in
Figures 13 and 14, or to an external control signal as shown in
Figures 9 and 11.
Csoft
=
where tsoft is the desired soft-start period.
If analog dimming is applied, the equivalent current source from
this circuit will add to the internal 1 µA source current on the
IREF node. Generally speaking, when using analog dimming via
VREG and a potential divider, no soft-start or negligible soft-start
is provided as shown in the example below. References are taken
from Figure 9 on page 23:
As the PWMIN input has a pull-up of only 1.1 µA in sleep mode,
it is essential that the zero gate voltage, drain current (leakage) of
the MOSFET does not exceed this number at maximum ambient
temperatures.
ANALOG DIMMING
1 µA
R5
20 kΩ
The IREF pin can then be used for full analog control. The LED
current can be linearly adjusted from zero to full (100%) LED
current (ILED) by changing the IREF pin from 0 to ≥ 1 V.
IREF
Pin
VREG
(5 V)
R7
10 kΩ
C6
22 nF
This feature is useful in applications where PWM control is either
not required or not available and the LEDs require some dynamic
correction for brightness adjustment.
Figure 1
Analog dimming can be used along with either pulse-width-
modulation technique, internal or external. This is useful for
applications where some color correction is required along with
brightness control.
From the above diagram, VREG, R5, and R7 can be simplified
using Norton’s Theorem.
The equivalent resistance can be found:
Soft-start can be provided via the analog dim signal when either
coming out of sleep or hiccup mode. The internal 1 µA internal
source current on the IREF node can be overridden by applying
a ramp signal to IREF. The soft-start duration is controlled by the
signal on IREF as it is ramped from 0 to 1 V.
20 × 10
20 + 10
RT =
= 6.67 kΩ
The current source can be found:
5
RT
Isource=
= 750 µA
If no soft-start is required, the IREF pin should be connected to
VREG. If no internal PWM is required, the DR pin should be
connected to VREG.
1 µA
SOFT-START
When the A6271 comes out of sleep mode, soft-start is required
to bring the output voltage up in a controlled open-loop fashion.
This minimizes the possibility of the control loop saturating dur-
ing the startup phase and subsequent output voltage overshoot,
which can induce high transient peak currents in the LED string
prior to the loop being brought back into linear control.
IREF
Pin
RT
6.67 kΩ
C6
22 nF
750 µA
Figure 2
The soft-start period can be programmed by the selection of the
appropriate capacitor between IREF pin and GND pin according
to the following formula:
From the above schematic, it is clear that the 750 µA current
source will dominate and almost no soft-start will be provided. In
this particular case, the only option is to resize C6, or increase the
values of R5 and R7, or both.
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LED CURRENT-SENSE RESISTOR
5 V REGULATOR, VREG
The LED current is programmed by the LED sense resistor, RSL
according to:
,
To provide a filtered output and to ensure the regulator is stable,
a 1 µF ceramic capacitor is required to be connected between
VREG and GND. The ceramic type should be a quality type such
as X5R, X7R, or X8R.
VIDL
ILED
=
RSL
The 5 V regulator is sized for driving the external switching
MOSFET. However, it can be used for functions that require
minimal current, e.g. pulling up the FAULTn output and provid-
ing a reference for the DR, the IREF pin, or both.
where the loop typically regulates VIDL to 200 mV when in either
internal or external PWM modes.
The power loss of the resistor should be taken into account to
ensure the correct package size is selected.
To check the load that the MOSFET provides, it is necessary to
check the total gate charge required for a 5 V drive. This can be
The power loss of the LED current-sense resistor, RSL is:
derived from the gate charge, QG, versus gate drive voltage, VGS
from the MOSFET datasheet. Once the gate charge is found, the
regulator load current can be determined:
,
P = ILED2 × RSL
It is advisable to insert a 150 Ω resistor in series with the LN pin,
as shown below, to protect the internal ESD structures between
LN and LP under certain fault conditions. The 150 Ω value is
selected as a balance between limiting the fault current and mini-
mizing the LED current error caused by the bias current flowing
into the LN pin.
ILOAD = (QG × fSW )+ Iexternal
where Iexternal is the additional circuitry added to the VREG
output.
The ILOAD should not exceed the VREG external current limit
(IREGCL).
LP
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
A6271
LN
RSL
150 Ω
Figure 3
SLEEP MODE
If PWMIN is held low for longer than the disable time, tDIS1 or
tDIS2, then the A6271 will shut down and put the majority of the
circuitry into a low-power sleep mode.
When internal PWM dimming is used, the disable time, tDIS1, is
14.5 ms.
When either external PWM dimming or analog dimming is used,
the disable time, tDIS2 is 29 ms.
0
50
100
150
200
250
300
350
400
Oscillator Resistor Value, ROSC (kΩ)
Figure 4: ROSC Required for a Particular Oscillator
Frequency
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OSCILLATOR
25,690
fOSC
ROSC
25,690
=
The main oscillator may be configured as a clock source or
it may be driven by an external clock signal. The oscillator is
designed to run between 70 and 700 kHz.
ROSC
=
= 73.4 kΩ, say 72 kΩ
350
When the oscillator is configured as a clock source, the frequency
is programmed via an external resistor between OSC pin and
GND pin. The appropriate resistor can be found:
Δf as a percentage of the delta with respect to the oscillator fre-
quency is (50 / 350) × 100% = 14.3%.
Therefore, RDITH can be found from:
25,690
fOSC
ROSC
=
ROSC
f = 22 ꢀ
RDITH
where ROSC is in kΩ and fOSC is in kHz.
72
14.3
RDITH = 22 ꢀ
= 110 k
Figure 4 shows the resulting ROSC for various frequencies.
When the OSC pin is driven by an external clock source, a num-
ber of A6271s can be synchronized together. If the clock period
is greater than or equal to 17 µs, a watchdog circuit causes the
running frequency to default to the internal oscillator, which runs
at 350 kHz.
The switching frequency is modulated at a rate of 10 kHz via a
triangular waveform. This means in one modulation cycle, the
switching frequency varies linearly from a minimum to a maxi-
mum to a minimum again.
If the dither feature is not required, the DITH pin should be tied
to VREG.
If the oscillator pin goes either open circuit or short circuits to
GND, the running frequency defaults to 350 kHz.
PROTECTION
FREQUENCY DITHERING
The A6271 includes a number of safety features to ensure the
controller, the external power components, and the LED string
are protected.
To assist in minimizing EMI emissions, the main oscillator can
be dithered so that the energy is spread over a defined frequency
band. The defined frequency band is effectively the minimum
and maximum switching frequency selected. This frequency is
varied above and below the selected oscillator frequency and is
set via a resistor connected between Dither pin and GND pin. The
frequency band can be selected as follows:
The Fault Flag becomes active for any fault.
When the device recovers from a fault, a soft-start is performed
unless analog dimming is selected and the DR pin is tied to
VREG.
ROSC
RDITH
At initial startup, when coming out of sleep mode, or when the
hiccup period terminates, a fault blank period, tFB, of 3 ms is
applied for two fault conditions including low-side switch cur-
rent limit (inner loop) protection and LED overload protection
(caused by an undervoltage), before the fault circuitry becomes
active. This period allows steady-state conditions to occur before
fault monitoring takes place.
Δ f =±±± ꢀ
where Δf is a plus/minus percentage change with respect to the
oscillator frequency.
For example, if an oscillator frequency of 350 kHz and a dith-
ered frequency band of ±50 kHz was selected, given a minimum
switching frequency of 300 kHz and a maximum switching
frequency of 400 kHz, the ROSC and RDITHER can be found:
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Output Overvoltage Protection
Two overvoltage protection circuits exist: an internal fixed
circuit and an externally programmable circuit. In the majority
of applications, the externally programmable circuit will provide
the protection. The internal circuit is present in the event that the
external feedback resistor chain of the programmable circuit goes
open circuit. This feature is particularly desirable in systems that
require high levels of reliability and the ability to withstand fail-
ure modes. Another advantage is the possibility, in lower voltage
applications, to select reduced operating voltages for the switch-
ing MOSFET, PWM MOSFET, recirculation diode, and output
filter capacitors with confidence.
Switcher Output
R1
VOVUV = 1 V
LED1
OVUV
VLEDOV
LEDn
R2
If an overvoltage occurs in either of the two circuits, the high-
side MOSFET drive (PWMOUT) and the low-side MOSFET
drive (SG) are immediately disabled and FAULTn is active. After
one fault mask switching cycle, the hiccup timer, tHIC, is initiated
for a period of 26.5 ms. At the beginning of the hiccup period, the
IREF node (soft-start) capacitor is discharged immediately. After
the hiccup period, an auto-restart is performed under control of
the soft-start capacitor.
Cathode: LED Stack
Figure 5
R2 can be found:
R1× (VLEDOV – VOVUV
)
R2 =
VOVUV
A potential divider is set up between the LP node (output of the
converter) and the cathode end of the LED stack. The output of
the potential divider is monitored by a comparator referenced to
the LN node. Once this voltage decreases below –1 V(max), an
overvoltage condition is reported.
Assume resistor R1 is selected to be 4.3 kΩ.
VLEDOV is 1.15 × 45 = 52 V.
VOVUV is a minimum of 1 V.
From the above formula:
It is recommended that the impedance of the potential divider is
kept relatively high, especially in high-voltage LED strings, to
minimize the current draw. It should be noted that there is negli-
gible bias current drawn by the comparator monitor circuit.
4.3 × ( 52 – 1 )
R2 =
=219 kΩ, select 220 kΩ
1
As an example, consider an LED string which has a maximum
LED string voltage of 45 V and an output overvoltage
(VLEDOV) is to be reported at a minimum of 15% above this
value.
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Overload Protection
Input Undervoltage or VREG Undervoltage Protection
There are two circuits:
If either condition occurs, the low-side MOSFET drive (SG)
is disabled and FAULTn is active (assuming VREG is high
enough, if FAULTn is pulled to VREG). In the case of the input
undervoltage, the high-side MOSFET drive (PWMOUT) is also
1. LED overcurrent threshold
2. Output undervoltage threshold
In the case of a LED overcurrent fault, the high-side MOSFET
drive (PWMOUT) and the low-side MOSFET drive (SG) are
disabled after two fault mask switching cycles, FAULTn is active,
the IREF node (soft-start) capacitor is discharged, then the hiccup
timer, tHIC, is initiated for a period of 26.5 ms. After the hiccup
period, an auto-restart is performed under control of the soft-start
capacitor.
disabled.
Both the input voltage and the VREG voltage must rise above
their respective turn-on thresholds before a restart is possible. In
the case of startup through the input voltage turn-on threshold,
the system is brought up under control of the soft-start. In the
case of startup through the VREG turn-on threshold, no soft-start
is provided.
In the case of an output undervoltage fault, the high-side MOS-
FET drive (PWMOUT) is immediately disabled and FAULTn
is active. After thirty fault mask switching cycles, the low-side
MOSFET drive (SG) is disabled, IREF node (soft-start) capacitor
is discharged, and the hiccup timer, tHIC, is initiated for a period
of 26.5 ms. After the hiccup period, an auto-restart is performed
under control of the soft-start capacitor.
PWM Output Undervoltage
During startup, the output (LP node) must increase above 6 V
to ensure the high-side MOSFET turns on. This is generally not
a problem with switching topologies that can boost the output
voltage with respect to the input voltage. In the case of the buck
topology, the LN/LP node is referenced to VIN; therefore, the
input voltage has to be equal to or greater than 6 V to guarantee a
successful startup.
Low-Side Switch Current Limit (inner loop)
At startup, a 3 ms blank period is applied before the circuitry
becomes active. Cycle-by-cycle current protection is provided
through the low-side MOSFET. If an overcurrent occurs for
longer than 64 switching clock cycles, the high-side MOSFET
drive (PWMOUT) and the low-side MOSFET drive (SG) are
disabled, FAULTn is active, and the hiccup timer, tHIC, is initiated
for a period of 26.5 ms. During the hiccup period, the IREF node
(soft-start) capacitor is discharged immediately. After the hiccup
period, an auto-restart is performed under control of the soft-start
capacitor.
Overtemperature Shutdown
If the chip exceeds the overtemperature shutdown threshold, the
low-side MOSFET drive (SG) is immediately disabled, FAULTn
is active, and the IREF node (soft-start) capacitor is discharged
immediately. An auto-restart is performed under control of the
soft-start capacitor once the temperature drops below the over-
temperature minus the hysteresis level.
The table on the following page summarizes the above faults
along with other pin specific faults.
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Table 1: Fault Table
Fault
Action
Low-Side Switch Current Limit
When fault occurs, cycle-by-cycle current limit operates.
If fault >64 counts: low-side MOSFET (SG) and PWM MOSFET (PWMOUT) off and FAULTn active, hiccup
period, then auto-restart with soft-start.
Note: fault blanked for 3 ms during startup.
LED Overcurrent
Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately off and FAULTn active, hiccup period
after 2 counts, then auto-restart with soft-start.
Output Undervoltage
Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately off. If fault > 30 counts: FAULTn active,
hiccup period, then auto-restart with soft-start.
Note: fault blanked for 3 ms during startup.
Fixed-Output Overvoltage
Programmable-Output Overvoltage
Input Undervoltage
Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active, hiccup
period after 1 count, then auto-restart with soft-start.
Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active, hiccup
period after 1 count, then auto-restart with soft-start.
Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active assuming
there is sufficient drive to the flag. Once input voltage is above the VIN undervoltage threshold, plus hysteresis,
auto-restart with soft-start occurs.
VREG Undervoltage
Thermal Shutdown
Low-side MOSFET (SG) immediately turns off and FAULTn active assuming there is sufficient drive to the flag.
Once VREG voltage is above the VREG undervoltage threshold, plus hysteresis, then auto-restart.
Low-side MOSFET (SG) immediately turns off and FAULTn active. Auto-restart with soft start occurs after the
temperature drops below the overtemperature minus hysteresis level.
PWMOUT Undervoltage
Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) off immediately and FAULTn active. Auto-restart
with soft-start occurs.
OSC Pin Fault
The oscillator will switch to default frequency of 350 kHz.
Force regulator to minimum duty cycle.
COMP Short to GND
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COMPONENT SELECTION
The ripple current, ΔI = 0.15 × IAVE
.
Inductor
The minimum inductance can now be found:
The main factor in selecting the inductor value is to target a cer-
tain ripple current to ensure the peak current-mode control works
correctly. A reasonable figure is a peak-to-peak ripple current
of around 15% of the average inductor current. The maximum
inductor current occurs at minimum input voltage and maximum
duty cycle.
VIN(MIN)× DMAX
L =
ΔI × fSW
where fSW is the switching frequency.
The peak current in the inductor is:
BOOST INDUCTOR SELECTION
ΔI
2
ILPK = IAVE
+
The maximum duty cycle can be found:
VLED+ (Vf – VIN(MIN)
VLED+ Vf
)
When selecting an inductor from manufacturers’ datasheets, there
are often two current ratings given:
DMAX
=
1. Saturation current. This is the current level that causes the
inductance to drop by between 10 and 40% depending on the
manufacturer.
where VLED is the LED output voltage, Vf is the forward volt-
age drop of the recirculation diode, and VIN(MIN) is the minimum
input voltage.
The saturation current should be greater than the peak cur-
rent, ILPK, with some margin to allow for overload condi-
tions.
The maximum average inductor current can be determined:
ILED
IAVE
=
2. RMS or average current. This is the current level that deter-
mines a certain temperature rise in the inductor with a given
ambient temperature. This is normally presented as a single
figure: operating temperature.
(1 – DMAX
The ripple current, ΔI = 0.15 × IAVE
)
.
The minimum inductance can now be found:
The RMS or average inductor current rating should be greater
(VLED+ V – VIN(MIN))× (1 – DMAX
)
f
than the estimated maximum average current, IAVE
.
L =
ΔI × fSW
Recommended inductor manufacturers:
where fSW is the switching frequency.
• Coilcraft: MSS1278T or MSS1078T Range
• TDK: SLF12575 type H
The peak current in the inductor is:
ΔI
SWITCH CURRENT SENSE
ILPK = IAVE
+
The switch current sense of the ‘inner loop’ is measured by the
external sense resistor, RSS, and the switch sense amplifier, AC.
As well as providing the peak current information to determine
the duty cycle, it also provides pulse-by-pulse current limiting
through the switching MOSFET and slope compensation to pre-
vent subharmonic oscillations at duty cycles greater than 50%.
BUCK-BOOST INDUCTOR SELECTION
The maximum duty cycle can be found:
VLED+ Vf
DMAX
=
VLED+ Vf + V
IN(MIN)
The current limit of the inner loop is set by the input limit of the
sense amplifier, VIDS, the maximum switch current that has been
determined, and the effects of the slope compensation have to be
taken into account. The operating duty cycle has to be calculated
at maximum load and minimum operating input voltage. The
amount of slope compensation can be calculated for this operat-
ing point and can then be added to the actual current-sense signal
to determine the maximum signal amplitude before cycle-by-
where VLED is the LED output voltage, Vf is the forward volt-
age drop of the recirculation diode, and VIN(MIN) is the minimum
input voltage.
The maximum average inductor current can be determined:
ILED
1 – DMAX
IAVE
=
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cycle current limiting takes effect. Refer to Slope Compensation
Section to find diL /dt then diSLOPE / dt.
Buck-Boost Slope Resistor
The inductor down slope is:
0.32
RSS =
diL
=
VLED+ Vf
DMAX
FSW
diSLOPE
dt
1.2×
ILP
+
×
)
(
The optimum down slope as illustrated by Ridley can be found
from:
Note that the minimum value of VIDS is used with an additional
20% to allow for margin.
diSLOPE diL
=
0.18
DMAX
× 1 –
( )
ILP is the peak current in the inductor.
dt
dt
The power loss of the switch current-sense resistor, RSS, can be
found:
The slope compensation resistor can be found:
di
SLOPE × RSS
Boost RSS Power Loss
dt
RSLOPE=
100 × 10–6 × 1 × 10–6 × fSW
Using the DMAX and IAVE from the boost part of the inductor sec-
tion, the power loss of RSS can be found:
where RSLOPE is in ohms (Ω).
Ploss = IAVE2 × DMAX × RSS
CONTROL LOOP COMPENSATION
Buck-Boost RSS Power Loss
The recommended way of closing the control loop is to remove
the influence of the right-hand plane zero (RHPZ) in both boost
and buck-boost topologies. The reason for this is that the RHPZ
increases the gain by 20 dB/decade and at the same time intro-
duces a 90-degree phase lag.
Using the DMAX and IAVE from the buck-boost part of the induc-
tor section, the power loss of RSS can be found:
Ploss = IAVE2 × DMAX × RSS
Resistor manufacturers typically derate the devices from an
ambient temperature of around 70°C. The power rating including
derating of the sense resistor should exceed the maximum power
loss at maximum ambient temperature.
The minimum frequency that the RHPZ occurs at is:
For boost mode:
2
VLED× (1 – DMAX
)
fRHPZ
For buck-boost mode:
fRHPZ
=
SLOPE COMPENSATION
2 × π × L × ILED
Slope compensation can be added to the MOSFET current-sense
signal on pin SP to prevent subharmonic oscillations where the
peak-to-average control error becomes increasingly larger at duty
cycles in excess of 50%. A current source is provided at the SP
2
VLED× (1 – DMAX
)
=
2 × π × L × ILED× DMAX
pin as a sawtooth from 0 to 100 µA. An external resistor, RSLOPE
connected between the SP pin and the source connection of the
MOSFET, is used to program the appropriate voltage level to
,
It is recommended that the 0 dB crossover point is approxi-
mately:
scale the slope compensation for correct use with the appropriate
topology and set up conditions that have been adopted.
fRHPZ
5
fCROSS
=
Boost Slope Resistor
With effective peak current-mode control, it can be assumed that
the second power pole is pushed high enough in the frequency
domain to have no influence on the overall loop response. It is
reasonable to assume the overall loop response is effectively a
single pole set by the GM amplifier (COMP node). The error
The inductor down slope is:
diL
dt
VLED+ Vf – VIN(MIN)
L
=
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amp zero is set at the same frequency as the output power pole to
ensure the loop is closed at a rate of 20 dB/decade.
The frequency position of the power stage pole and the GM
amplifier zero is:
The open-loop DC gain of the system can be found:
Boost:
VLED+ ILED× ((n × Rdyn) + RSL )
fp2 and fz1 =
Boost:
2 × π × VLED× COUT× ((n × Rdyn) + RSL )
VLED
5 × 1,259 × RSL × (1 – DMAX )×
( I )
Buck-Boost:
LED
DC Gain =
VLED+ DMAX× ILED× ((n × Rdyn) + RSL )
fp2 and fz1 =
VLED
R ×
SS
+ (n × R )+ R )
(( I )
)
dyn
SL
2 × π × VLED× COUT× ((n × Rdyn) + RSL )
LED
The resistor (Rcomp) in series with the compensation capacitor
(Ccomp) on the COMP node can be found:
Buck-Boost:
VLED
1
5 × 1,259 × RSL × (1 – DMAX) ×
VLED
( )
ILED
Rcomp =
2 × π × fp2 × Ccomp
DC Gain =
R ×
SS
+ DMAX × ((n × Rdyn) + R )
(( I )
)
SL
LED
LOW-SIDE SWITCHING MOSFET
A logic-level n-channel MOSFET is used as the switch for the
DC-DC converter.
where n = number of LEDs and Rdyn = LED dynamic resistance.
Note that the LED dynamic resistance may be given in the LED
datasheet. If it is not, it can be derived by a simple measurement.
Set up a power supply with a current limit at the operating point
(ILED1). Apply the current to an individual LED and measure
the voltage drop (VLED1). Change the current limit by a small
amount, say 5% (ILED2), and measure the voltage drop (VLED2).
The dynamic resistance can be estimated:
In the boost configuration, the maximum voltage across the
drain-source connection is:
VDS = VLED + Vf
In the buck-boost configuration, the maximum voltage across the
drain-source connection is:
VDS = VLED + Vf + VINMAX
VLED1 – VLED2
Rdyn
=
The actual rating of the MOSFET selected should be greater than
the maximum voltage plus some margin. It is recommended that
the minimum margin should be no less than 20% of the maxi-
mum voltage.
ILED1 – ILED2
The RC constant required to achieve 0 dB with a slope of 20 dB/
decade at the crossover frequency, fCROSS
:
1
In the case of buck-boost mode, the maximum rating should fac-
tor in load-dump conditions.
RC =
2 × π × fCROSS
In terms of the current rating, the MOSFET is generally selected
for a low RDS rating to minimize the power dissipation. This
means the current rating is well in excess of the actual maximum
current used in the application.
The frequency of the first GM amplifier pole can be found:
1
fp1 =
2 × π × RC × DC Gain
The power loss in the MOSFET is determined by the static loss
and the switching losses.
Capacitor on the output of the GM amplifier (COMP node)
required to achieve the above pole position:
750 × 10–6
2 × π × fp1 × 1,258
Static Loss
Ccomp
=
Using the DMAX and IAVE from the boost or buck-boost part of
the inductor section, the power loss of RDS can be found:
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Ploss = IAVE2 × DMAX × RDS
In the boost configuration, the maximum reverse voltage across
the diode is:
Note that the RDS figures are generally presented at 25°C room
ambients. The actual RDS can be determined by considering the
normalized RDS versus temperature graph.
V
RRM = VLED + Vf
In the buck-boost configuration, the maximum reverse voltage
across the diode is:
Another consideration of the static loss is cold-crank situations.
It is important to ensure the gate-drive amplitude (derived from
VREG) at the minimum input voltage provides sufficient drive
that the RDS does not increase by much, therefore minimizing any
increase in losses. A good quality logic-level MOSFET should
have good RDS performance at drive voltages of less than 4 V.
VRRM = VLED + Vf + VIN(MAX)
The actual rating of the diode selected should be greater than the
maximum voltage plus some margin. It is recommended that the
minimum margin should be no less than 20% of the maximum
voltage. In the case of buck-boost mode, the maximum rating
should factor in load-dump conditions.
The VREG load can be determined by estimating the gate losses.
From the MOSFET datasheet, the total gate charge can estimated
with a gate drive of 5 V using the appropriate graph. In addition,
any other circuitry that VREG is powering should also be fac-
tored. The current drawn from VREG due to the MOSFET drive
can be determined:
HIGH-SIDE PWM MOSFET
A p-channel MOSFET is used as the PWM switch for the LED
stack.
In both boost and buck-boost modes, the maximum voltage
across the drain-source connection is VLED. The actual rating
of the MOSFET selected should be greater than the maximum
voltage plus some margin. It is recommended that the minimum
margin should be no less than 20% of the maximum voltage.
VREGMOSFETload = QTOTALGate × fSW
Switching Losses
The switching losses in the MOSFET are determined by the
length of time of the Miller region. To minimize conducted and
radiated EMI emissions, this region is deliberately extended by
adding series resistance between the gate drive (SG) and the gate
of the device. It is assumed that the turn-off loss is similar to the
turn-on loss.
The power loss of this MOSFET is dominated by the static loss.
The switching losses can largely be ignored as the PWM frequen-
cies are relatively low.
The power loss of the MOSFET RDS can be found:
In the case of the boost converter, the switching loss:
Pswitch = (VLED + Vf ) × IAVE × tmiller × fSW
Ploss = ILED2 × RDS
The gate drive for the PWM MOSFET is derived from the LED
output rail (LP pin). In boost and buck-boost modes, this node is
boosted with respect to the input voltage (VIN), so there should be
sufficient negative gate drive.
In the case of the buck boost converter, the switching loss:
Pswitch = (VLED + Vf + VIN(MIN) ) × IAVE × tmiller × fSW
RECIRCULATION DIODE
In other operating modes such as buck, where the output volt-
age is less than the input voltage, it may be necessary to use low
threshold p-channel MOSFETs to ensure adequate overdrive dur-
ing cold-crank situations.
The diode should have a low forward voltage to reduce conduc-
tion losses and a low capacitance to reduce switching losses
and minimize EMI. Schottky diodes can provide both features
if carefully selected. The forward voltage drop is a natural
advantage for Schottky diodes and reduces as the current rating
increases. However, as the current rating increases, the diode
capacitance also increases, so the optimum selection is usually
the lowest current rating above the required maximum, in this
case ILPK
.
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115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
OUTPUT CAPACITOR
Layout
There are several points to consider when selecting the output
capacitor.
The following layout guidelines should be followed to ensure
satisfactory electrical and EMI performance.
Due to the switching topology used, the ripple current for this
circuit is high since the output capacitor provides the LED cur-
rent when the DC-DC converter switch is active in both boost
and buck-boost modes. The capacitor is then recharged each time
the inductor passes energy to the output. The ripple current on the
output capacitor will be equal to the peak inductor current. The
corresponding output ripple can be derived from the amount of
charge transferred to the output during the switch on time.
Ground planes should be used on as many layers as possible. This
is essential in minimizing ‘ground bounce’ (differential voltage
across the ground connection). ‘Ground bounce’ can lead to radi-
ated noise which can then be picked up on both input and output
connections and manifest as common-mode noise. Any ground
planes on different layers should be connected using multiple vias
in an attempt to minimize ground impedances. The ground tab
under the A6271 should also have multiple vias connecting to the
ground plane or planes.
To minimize heating effects and voltage ripple, the equivalent
series resistance (ESR) and the equivalent series inductance (ESL)
should be kept as low as possible. This can be achieved by mul-
tilayer ceramic chip (MLCC) capacitors. To reduce performance
variation over temperature, low drift types such as X7R and X5R
should be used.
The drain connection of the switching MOSFET, PWM MOS-
FET, and cathode terminal of the recirculation diode are used for
thermal heatsinking. It is advised to use sufficient copper around
these connections on the component layer of the PCB only. The
areas directly under these connections on the PCB should form
part of the ground plane. The reason for restricting the copper
area on these nodes is because they can radiate noise due to the
nature of the dv/dt and di/dt power signals that appear.
The value of the output capacitor will typically be in the range
of 3.3 to 10 µF, and it should be rated above the maximum LED
stack voltage, VLED. There is an E-field effect with ceramic
capacitors that causes the capacitance to fall at elevated voltages.
It is therefore recommended that a good margin is selected to
minimize this effect.
The area of the switching power loops should be minimized as
much as possible. In addition, the trace connections should be as
wide as possible to minimize parasitic leakage inductances, but at
the same time not compromising the power loop area. There are
two power loops:
One potential issue of ceramic capacitors is audible noise during
pulse-width modulation (PWM). This is caused by the piezo-
electric effect of the ceramic substrate. To minimize the effects
of this, it is recommended to use multiple physically smaller
capacitors. If this is still an issue, it is recommended that either
low-impedance electrolytic or polymer capacitors be used.
Loop 1: formed by the input filter, main switching MOSFET,
power inductor, and inner loop sense resistor.
Loop 2: formed by the power inductor, recirculation diode,
LED sense resistor, PWM MOSFET, and the output capacitor or
capacitors.
INPUT CAPACITOR
The function of the input filter capacitor is to provide a low-
impedance shunt path for the current drawn by the A6271 when
the switching MOSFET turns on. The objective is to minimize
the ripple current reflected back into the source supply. This
approach helps to minimize conducted emissions into the power
source. Additional line impedance in the form of chokes can be
added to improve the emissions further.
Where practical, keep input or output filter magnetics as far away
from the power-switching inductor (L1) as possible. This is to
avoid or at least minimize the effects of magnetic crosstalk.
One of the major noise contributors is the switching MOSFET
(M1). Slowing down the gate drive without compromising the
thermal solution will help to minimize noise.
To comply with CISPR 25, a common-mode choke is typically
required as part of the input filter.
In a correctly designed system, with a quality capacitor or capaci-
tors positioned adjacent to the power train circuitry, these capaci-
tors should supply the ripple current.
The amount of capacitance required at the input is dictated by the
EMI performance. This is usually distributed with series ferrite
beads and either differential-mode chokes, or common-mode
chokes, or both.
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A6271
Automotive, High-Current LED Controller
INPUT FILTER
Reducing EMI
The selection of the components that form the input filter
It is essential that good layout practice as defined in the Layout
Section should be adopted. The following techniques are also
recommended.
depends on the noise that is present in the system in terms of the
frequency and whether it is common mode or differential mode.
In addition, the common automotive standards that exist define
onerous specification limit lines for the emissions in the AM band
(approximately 530 kHz to 1.7 MHz) and the FM band (approxi-
mately 70 to 108 MHz). Some consideration must be given to
these frequency bands to understand how to filter these regions.
SNUBBER
Adding a low-loss R-C snubber network between the drain of
the main switching MOSFET and ground helps to suppress the
resonant ringing on the switching node. The process for selecting
these components involves some ‘trial and error’ on the actual
printed circuit board.
At the lower frequencies, below a few 10s of MHz, the noise is
generally dominated by differential noise with some common
mode noise. At frequencies above a few 10s of MHz, the noise is
dominated by common mode noise with some differential noise.
Step 1: Measure the voltage resonance frequency on the LX
node.
To address the differential noise, a differntial inductor can be
used along with differential capacitance to form an L-C filter.
One problem in using standard differential inductors is that the
self-resonance frequency (SRF) is typically in the region of a few
10s of MHz, even with a modest few microhenries (µH) (note:
the higher the inductance, the lower the SRF). This means that
above the self-resonant frequency points, these components actu-
ally amplify the noise and make matters worse.
Step 2: Add an additional capacitance between LX and ground
until the resonant frequency is halved. Note that this capacitance
should be around 1 nF.
Step 3: Two equations with two unknowns are now obtained:
1
FRES
=
=
2 × π × Lleak× Cleak
FRES
2
1
Some differential-mode inductive filtering is always necessary.
Ferrite beads can be used for this function. Although ferrite beads
are designed to act as a lossy resistor at particular frequency
bands, they do have an inherent inductive element which can be
in the region of several µH. The inductance of a ferrite bead can
be extracted from the reactance information graph (refer to Fig-
ure 7). At a particular frequency, the reactance can be found and
then the inductance can be derived.
2 × π × Lleak× Cnew
where Cnew = Cleak + Cadd
.
Cadd = additional capacitance added.
Cleak = parasitic capacitance.
Lleak = parasitic inductance.
Now to halve the frequency, Cleak + Cadd = 4 x Cleak
As a single ferrite bead may not be effective enough, a two-stage
ferrite bead filter approach can be taken. These components,
along with input differential-mode capacitors, can form L-C filter
stages. For the best result, the first L-C filter should be placed as
close to the power stage as possible.
Cadd
3
Therefore,
Cleak=
With Cleak solved, Lleak can also be solved.
At higher frequencies, the majority of the noise problems is
associated with common-mode noise. This noise is induced by
ground-referenced differential noise radiating through the ground
plane. This noise can be picked up on the input stage forming
common-mode noise on the positive and negative power supply
connections to the battery. Even with excellent layout, this noise
is always present.
The characteristic impedance of the parasitic components can be
found:
Lleak
RO =
Cleak
RO can be selected as the damping resistor. Typically, either an
0805 or 0603 resistor case size is adequate.
To address this problem, a common-mode inductor is required.
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A6271
Automotive, High-Current LED Controller
This inductor is selected to present a high impedance around the
FM region. An example of a common-mode (CM) choke with a
high impedance around the FM region is shown below in Figure 6.
FREQUENCY DITHERING
Further improvements to the differential-mode performance can
be made by the use of frequency dithering techniques.
10000
1000
100
10
The A6271 contains a dither circuit which changes the switching
oscillator frequency on a cycle-by-cycle basis across a defined
frequency band.
As the noise in a switcher is typically narrow-band noise, both
the peak and average signals are similar in amplitude. When a
frequency dither scheme is introduced, it ‘spreads’ the noise,
converting it from narrow band into broad band. While the peak
noise reduces across the majority of the spectrum, the reduction
in the average measurement is a lot more effective. This effect
is particularly helpful in the conducted emissions for the average
measurement between 76 and 108 MHz. This region is unusual,
as typically the peak and average limit lines track one another,
but in this area, while the peak limit line increases, the average
limit line reduces (refer to Figure 7 below). Note the red limit
lines are peak and the pink limit lines are average.
90
80
Limits
1
55025 P5
1
10
100
1000
70
60
50
40
30
20
10
55025 A5
Frequency (MHz)
Z (comm)
Z (diff)
Figure 6: Common-Mode (CM) Choke Impedance
Transducer
UniRFPro
Traces
PK+
AV
Another important consideration is the relative positioning of
the common-mode choke with respect to the switching inductor.
Magnetic crosstalk can occur between these components which
can degrade the effectiveness of the CM choke. Even the use of
a magnetically-screened switching inductor is not sufficient to
avoid this problem. It is important to physically separate these
two components as far as possible. Another advantage of a good
physical separation is that any ‘ground bounce’ induced CM
noise will couple onto the input power traces. The strength of the
coupling will reduce with distance. The further the CM choke is
away from the switching circuit, the more likely it will be to filter
this noise.
0
-10
150 kHz
1 MHz
10 MHz
108 MHz
Figure 7: CISPR 25 Class 5 Limit Lines
The reason that the average limit line is relatively low (making
it challenging to pass) is that average weighted signals have an
adverse effect on FM radio signals.
All filter capacitors should be a quality ceramic: X7R or X8R.
Minimizing the noise at the high end of the conducted emis-
sion frequency spectrum also benefits the radiated noise at this
frequency band and above.
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A6271
Automotive, High-Current LED Controller
Note that a modulation frequency of 10 kHz was chosen, since
this aligns with the resolution bandwidth of the measurement
receiver as defined in CISPR 25. The resolution bandwidth is
effectively the ‘measurement window’ at each measurement step.
the dithering is. However, there is a trade-off with switching
losses and sizing of the power inductor in terms of inductance
value and the corresponding physical size.
Another consideration when optimizing the frequency dithering
is the depth of frequency. This is the maximum and minimum
switching frequency that the converter operates, effectively the
‘spread range’. The wider the spread range is, the more effective
Allegro MicroSystems, LLC
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A6271
Automotive, High-Current LED Controller
APPLICATION CIRCUITS
12 µH
L1
D2
VBAT
C2
C1
C3
D1
4.7 µF
4.7 µF
100 nF
R13
R14
C9
R11
150 Ω
C4
470 mΩ
2.7 Ω
47 nF
100 nF
R12 10 kΩ
VIN
LP
LN
PWMOUT
VREG
GND
C5
M4
R1
1 µF
2.7 kΩ
R2
FAULTn
DR
R15
270 kΩ
LED1
4.3 kΩ
R3
A6271
10 kΩ
OVUV
R16
C10
C11
C12
M1
R4
0 Ω
M3
4.7 µF 4.7 µF 4.7 µF
68 kΩ
SG
SP
High = internal
PWM ON (5%)
PWMIN
IREF
LED12
R21
R5
R17
220 kΩ
OSC
DITH
20 kΩ
M2
COMP
1.2 kΩ
Analog
Control
R18
R19
R20
R10
R9
R8
100 kΩ
10 kΩ 68 mΩ 68 mΩ
39 Ω
C8
R7
110 kΩ
C6
22 pF
R6
10 kΩ
C7
10 kΩ
22 nF
470 nF
GND
Figure 8: Boost Driving 12 LEDs at 500 mA, Switching Frequency 250 kHz
Internal PWM (5%) and/or analog dimming, no soft-start, and frequency dither on. The minimum startup voltage is determined by the voltage
on the output (LP) node. 6 V is required at this node, so the input voltage, VIN = 6 V + Vf (of recirculation diode, D2). If for example, Vf = 0.4 V,
then VIN = 6.4 V. Once operating, the A6271 will function down to an input voltage of 4.5 V. The maximum operating voltage on the input is the
maximum LED string voltage, plus the diode drop of D2.
Table 2: Application Circuit 1 Bill of Materials
Reference
Description
Manufacturer/Part Number
C1,C2,C10,C11,C12
4.7 µF, ceramic capacitor, X7R, 50 V
100 nF, ceramic capacitor, X7R, 50 V
1 µF, ceramic capacitor, X7R, 16 V
22 nF, ceramic capacitor, X7R, 50 V
470 nF, ceramic capacitor, X7R, 50 V
22 pF, ceramic capacitor, X7R, 50 V
47 nF, ceramic capacitor, X7R, 16 V
200 mA, 30 V Schottky diode
TDK, MuRata
C3,C4
C5
C6
C7
C8
C9
D1
NXP, ON Semiconductor, Fairchild / BAT54
Vishay / SS10P6
D2
10 A, 60 V Schottky diode
22 µH, high current shielded
construction
L1
Vishay / IHLP-5050FDER220M-5A
M1,M2
M3
N-channel signal MOSFET
ON Semiconductor, IR / NTR4003N
Vishay / SQD50N10
N-channel 50 A, 100 V MOSFET
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
Table 2: Application Circuit 1 Bill of Materials (continued)
Reference
Description
Manufacturer/Part Number
Infineon / SPD15P10PL G
M4
P-channel 15 A, 100 V MOSFET
Heatsink for M3 (TO-252)
2.7 kΩ, 1%, 0603 or 0805
270 kΩ, 1%, 0603 or 0805
10 kΩ, 1%, 0603 or 0805
68 kΩ, 1%, 0603 or 0805
20 kΩ, 1%, 0603 or 0805
10 kΩ, potentiometer
AAVID Thermalloy / 573100D00010G
R1
R2
R3,R6,R12,R18
R4
R5
R7
R8
100 kΩ, 1%, 0603 or 0805
110 kΩ, 1%, 0603 or 0805
39 Ω, 1%, 0603 or 0805
150 Ω, 1%, 0603 or 0805
470 mΩ, 1%, 0805 or 1206
2.7 Ω, 1%, 0603 or 0805
4.3 kΩ, 1%, 0603 or 0805
0 Ω, 0603 or 0805
R9
R10
R11
R13
R14
R15
R16
R17
R19,R20
R21
1.2 kΩ, 1%, 0603 or 0805
68 mΩ, 1%, 2010
220 kΩ, 1%, 0603 or 0805
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A6271
Automotive, High-Current LED Controller
56 µH
L1
D2
VBAT
C1
C2
C3
D1
4.7 µF
4.7 µF
100 nF
R7
R8
C9
R5
150 Ω
C4
2.7 Ω
2.7 Ω
47 nF
100 nF
R6 10 kΩ
VIN
LP
LN
PWMOUT
VREG
GND
C5
M2
R1
2.7 kΩ
1 µF
FAULTn
DR
R9
LED1
4.3 kΩ
A6271
OVUV
R10
C10
C11
C12
12 Ω
M1
2.2 µF 2.2 µF 2.2 µF
External PWM
Drive Signal
SG
SP
PWMIN
IREF
LED14
R15
240 kΩ
R11
OSC
DITH
COMP
1.3 kΩ
R12
R13
R14
150 mΩ
R4
R3
R2
73.2 kΩ
10 kΩ 150 mΩ
C8
39 Ω
C7
110 kΩ
C6
22 pF
22 nF
680 nF
GND
Figure 9: Boost Driving 14 LEDs at 150 mA, Switching Frequency 350 kHz
External PWM, no analog dimming, soft-start, and frequency dither on. The minimum startup voltage is determined by the voltage on the output
(LP) node. 6 V is required at this node, so the input voltage, VIN = 6 V + Vf (of recirculation diode, D2). If for example, Vf = 0.4 V, then VIN = 6.4 V.
Once operating, the A6271 will function down to an input voltage of 4.5 V. The maximum operating voltage on the input is the maximum LED
string voltage, plus the diode drop of D2.
Table 3: Application Circuit 2 Bill of Materials
Reference
Description
Manufacturer/Part Number
C1,C2
4.7 µF, ceramic capacitor, X7R, 50 V
100 nF, ceramic capacitor, X7R, 50 V
1 µF, ceramic capacitor, X7R, 16 V
22 nF, ceramic capacitor, X7R, 50 V
680 nF, ceramic capacitor, X7R, 50 V
22 pF, ceramic capacitor, X7R, 50 V
47 nF, ceramic capacitor, X7R, 16 V
2.2 µF, ceramic capacitor, X7R, 100 V
200 mA, 30 V Schottky diode
TDK, MuRata
C3,C4
C5
C6
C7
C8
C9
C10,C11,C12
TDK, MuRata
NXP, ON Semiconductor, Fairchild / BAT54
Vishay, ST / SS2H10
D1
D2
L1
2 A, 100 V Schottky diode
56 µH, power inductor shielded
construction
Coilcraft / MSS1048T-563ML
M1
N-channel, 30 A, 100 V MOSFET
NXP / PSMN038-100YLX
Continued on next page...
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115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
Table 3: Application Circuit 2 Bill of Materials (continued)
Reference
M2
Description
Manufacturer/Part Number
P-channel 15 A, 100 V MOSFET
2.7 kΩ, 1%, 0603 or 0805
73.2 kΩ, 1%, 0603 or 0805
110 kΩ, 1%, 0603 or 0805
39 Ω, 1%, 0603 or 0805
150 Ω, 1%, 0603 or 0805
10 kΩ, 1%, 0603 or 0805
2.7 Ω, 1%, 0805 or 1206
4.3 kΩ, 1%, 0603 or 0805
12 Ω, 1%, 0603 or 0805
1.3 kΩ, 1%, 0603 or 0805
150 mΩ, 1%, 1206
Infineon / SPD15P10PL G
R1
R2
R3
R4
R5
R6,R12
R7,R8
R9
R10
R11
R13,R14
R15
240 kΩ, 1%, 0603 or 0805
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115 Northeast Cutoff
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A6271
Automotive, High-Current LED Controller
12 µH
L1
D2
VBAT
C1
C2
4.7 µF
C3
D1
4.7 µF
100 nF
C9
R12
R11
R9
150 Ω
C4
47 nF
270 mΩ
270 mΩ
100 nF
R10 10 kΩ
VIN
LP
LN
PWMOUT
VREG
GND
C5
M4
R1
1 µF
2.7 kΩ
R2
FAULTn
DR
270 kΩ
LED1
R13
R3
A6271
4.3 kΩ
10 kΩ
OVUV
R14
C10
C11
C12
M1
R4
0 Ω
M3
4.7 µF 4.7 µF 4.7 µF
68 kΩ
SG
SP
High = internal
PWM ON (5%)
PWMIN
IREF
LED5
R19
84.5 kΩ
R15
OSC
DITH
M2
COMP
1 kΩ
R16
R17
R18
R8
R6
100 kΩ
R7
10 kΩ 62 mΩ 62 mΩ
C8
22 pF
39 Ω
C7
110 kΩ
C6
R5
10 kΩ
22 nF
220 nF
GND
Figure 10: Buck-Boost Driving 5 LEDs at 1.5 A, Switching Frequency 250 kHz
Internal PWM (5%), no analog dimming, soft-start, and frequency dither on.
The minimum start up voltage is determined by the voltage on the output (LP) node. 6 V is required at this node, so the input voltage, VIN = 6 V + Vf
(of recirculation diode, D2). If for example, Vf = 0.4 V, then VIN = 6.4 V. Once operating, the A6271 will function down to an input voltage of 5.5 V. The
maximum operating voltage on the input is 36 V, plus the diode drop of D2.
Table 4: Application Circuit 3 Bill of Materials
Reference
Description
Manufacturer/Part Number
C1,C2,C10,C11,C12
4.7 µF, ceramic capacitor, X7R, 50 V
100 nF, ceramic capacitor, X7R, 50 V
1 µF, ceramic capacitor, X7R, 16 V
22 nF, ceramic capacitor, X7R, 50 V
220 nF, ceramic capacitor, X7R, 50 V
22 pF, ceramic capacitor, X7R, 50 V
47 nF, ceramic capacitor, X7R, 16 V
200 mA, 30 V Schottky diode
TDK, MuRata
C3,C4
C5
C6
C7
C8
C9
D1
NXP, ON Semiconductor, Fairchild / BAT54
Vishay / SS10P6
D2
10 A, 60 V Schottky diode
L1
12 µH, high current shielded
construction
Vishay / IHLP-5050FDER120M-5A
M1,M2
M3
N-channel signal MOSFET
ON Semiconductor, IR / NTR4003N
Vishay / SQD50N10
N-channel 50 A, 100 V MOSFET
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
Table 4: Application Circuit 3 Bill of Materials (continued)
Reference
Description
Manufacturer/Part Number
Infineon / SPD15P10PL G
M4
P-channel 15 A, 100 V MOSFET
Heatsink for M3 (TO-252)
2.7 kΩ, 1%, 0603 or 0805
270 kΩ, 1%, 0603 or 0805
10 kΩ, 1%, 0603 or 0805
68 kΩ, 1%, 0603 or 0805
100 kΩ, 1%, 0603 or 0805
110 kΩ, 1%, 0603 or 0805
39 Ω, 1%, 0603 or 0805
150 Ω, 1%, 0603 or 0805
270 mΩ, 1%, 0805 or 1206
4.3 kΩ, 1%, 0603 or 0805
0 Ω, 0603 or 0805
AAVID Thermalloy / 573100D00010G
R1
R2
R3,R5,R10,R16
R4
R6
R7
R8
R9
R11,R12
R13
R14
R15
1 kΩ, 1%, 0603 or 0805
62 mΩ, 1%, 2010
R17,R18
R19
84.5 kΩ, 1%, 0603 or 0805
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115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
47 µH
L1
D2
VBAT
C1
C2
4.7 µF
C3
D1
4.7 µF
100 nF
R8
R9
C4
R6
150 Ω
C4
1 Ω
1 Ω
47 nF
100 nF
R7 10 kΩ
VIN
LP
LN
PWMOUT
VREG
GND
C5
M2
R1
2.7 kΩ
1 µF
FAULTn
DR
LED1
LED4
R10
A6271
4.3 kΩ
OVUV
R11
C10
C11
C12
24 Ω
M1
4.7 µF 4.7 µF 4.7 µF
External PWM
Drive Signal
SG
SP
PWMIN
IREF
R16
R2
R12
68 kΩ
20 kΩ
OSC
DITH
COMP
1 kΩ
R3
R13
R14
R15
180 mΩ
R5
10 kΩ
R4
100 kΩ
10 kΩ 180 mΩ
Analog
Control
C8
27 Ω
C7
C6
22 pF
22 nF
470 nF
GND
Figure 11: Buck-Boost Driving 4 LEDs at 400 mA, Switching Frequency 250 kHz
External PWM and/or analog dimming, no soft-start, and frequency dither off.
The minimum startup voltage is determined by the voltage on the output (LP) node. 6 V is required at this node, so the input voltage is VIN = 6 V + Vf
(of recirculation diode, D2). If for example, Vf = 0.4 V, then VIN = 6.4 V. Once operating, the A6271 will function down to an input voltage of 4.5 V. The
maximum operating voltage on the input is 40 V, plus the diode drop of D2.
Table 5: Application Circuit 4 Bill of Materials
Reference
Description
Manufacturer/Part Number
C1,C2,C10,C11,C12
4.7 µF, ceramic capacitor, X7R, 50 V
100 nF, ceramic capacitor, X7R, 50 V
1 µF, ceramic capacitor, X7R, 16 V
22 nF, ceramic capacitor, X7R, 50 V
470 nF, ceramic capacitor, X7R, 50 V
22 pF, ceramic capacitor, X7R, 50 V
47 nF, ceramic capacitor, X7R, 16 V
200 mA, 30 V Schottky diode
TDK, MuRata
C3,C4
C5
C6
C7
C8
C9
D1
NXP, ON Semiconductor, Fairchild / BAT54
ON Semiconductor / MBRS260T3
Coilcraft / MSS1048T-473ML
D2
2 A, 60 V Schottky diode
L1
47 µH, power inductor shielded
construction
M1
M2
N-channel, 30 A, 100 V MOSFET
P-channel 15 A, 100 V MOSFET
NXP / PSMN038-100YLX
Infineon / SPD15P10PL G
Continued on next page...
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A6271
Automotive, High-Current LED Controller
Table 5: Application Circuit 4 Bill of Materials (continued)
Reference
R1
Description
Manufacturer/Part Number
2.7 kΩ, 1%, 0603 or 0805
20 kΩ, 1%, 0603 or 0805
10 kΩ, potentiometer
R2
R3
R4
100 kΩ, 1%, 0603 or 0805
27 Ω, 1%, 0603 or 0805
150 Ω, 1%, 0603 or 0805
10 kΩ, 1%, 0603 or 0805
1 Ω, 1%, 0805 or 1206
4.3 kΩ, 1%, 0603 or 0805
24 Ω, 1%, 0603 or 0805
1 kΩ, 1%, 0603 or 0805
180 mΩ, 1%, 1206
R5
R6
R7,R13
R8,R9
R10
R11
R12
R14,R15
R16
68 kΩ, 1%, 0603 or 0805
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A6271
Automotive, High-Current LED Controller
D1
DRL
Park
22 µH
R11
L1
D3
D2
C1
C2
C3
4.7 µF
4.7 µF
100 nF
R13
R14
C9
C4
470 mΩ
2.7 Ω
47 nF
150 Ω
100 nF
R12
VIN
LP
LN
PWMOUT
VREG
10 kΩ
C5
M4
R1
2.7 kΩ
1 µF
GND
FAULTn
DR
R2
270 kΩ
LED1
R15
A6271
4.3 kΩ
R3
OVUV
10 kΩ
R16
C10
C11
C12
0 Ω
M3
4.7 µF 4.7 µF 4.7 µF
R4
68 kΩ
SG
SP
R22
PWMIN
IREF
LED12
10 kΩ
R21
M1
R5
M2
R17
220 kΩ
OSC
DITH
COMP
20 kΩ
R7
1.2 kΩ
R18
R19
R20
68 mΩ
R10
R8
100 kΩ
R9
110 kΩ
10 kΩ 68 mΩ
Analog
Control
C8
10 kΩ
39 Ω
C7
R6
10 kΩ
D4
5.1 V
C6
22 pF
22 nF
470 nF
GND
Figure 12: Boost Driving 12 LEDs at 500 mA, Switching Frequency 250 kHz
Park Mode: internal PWM (5%) and analog dimming, no soft start, and frequency dither on.
Daylight Running Mode (DRL): 100% LED current and analog dimming, no soft start, and frequency dither on.
Battery voltage applied either at daylight running (DRL) terminal or park terminal. Note that Park Mode is dominant.
The minimum startup voltage is determined by the voltage on the output (LP) node. 6 V is required at this node, so the input voltage, VIN = 6 V + Vf
(of recirculation diode, D2). If for example, Vf = 0.4 V, then VIN = 6.4 V. Once operating, the A6271 will function down to an input voltage of 4.5 V. The
maximum operating voltage on the input is the maximum LED string voltage, plus the diode drop of D2.
Table 6: Application Circuit 5 Bill of Materials
Reference
Description
Manufacturer/Part Number
C1,C2,C10,C11,C12
4.7 µF, ceramic capacitor, X7R, 50 V
100 nF, ceramic capacitor, X7R, 50 V
1 µF, ceramic capacitor, X7R, 16 V
22 nF, ceramic capacitor, X7R, 50 V
470 nF, ceramic capacitor, X7R, 50 V
22 pF, ceramic capacitor, X7R, 50 V
47 nF, ceramic capacitor, X7R, 16 V
3 A, 100 V Schottky diode
TDK, MuRata
C3,C4
C5
C6
C7
C8
C9
D1, D3
D2
ON Semiconductor / NRVBS3100T3G
Vishay / SS10P6
10 A, 60 V Schottky diode
D4
5.1 V, zener diode
ON Semiconductor / SZBZX84C5V1
Vishay / IHLP-5050FDER220M-5A
L1
22 µH, high current shielded
construction
M1, M2
N-channel signal MOSFET
ON Semiconductor, IR / NTR4003N
Continued on next page...
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Worcester, Massachusetts 01615-0036 U.S.A.
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A6271
Automotive, High-Current LED Controller
Table 6: Application Circuit 5 Bill of Materials (continued)
Reference
M3
Description
Manufacturer/Part Number
Vishay / SQD50N10
N-channel, 50 A, 100 V MOSFET
P-channel, 15 A, 100 V MOSFET
Heatsink for M3 (TO-252)
2.7 kΩ, 1%, 0603 or 0805
270 kΩ, 1%, 0603 or 0805
10 kΩ, 1%, 0603 or 0805
68 kΩ, 1%, 0603 or 0805
20 kΩ, 1%, 0603 or 0805
10 kΩ, potentiometer
M4
Infineon / SPD15P10PL G
AAVID Thermalloy / 573100D00010G
R1
R2
R3,R6,R12,R18,R22
R4
R5
R7
R8
100 kΩ, 1%, 0603 or 0805
110 kΩ, 1%, 0805 or 1206
39 Ω, 1%, 0603 or 0805
150 Ω, 1%, 0603 or 0805
470 mΩ, 1%, 0805 or 1206
2.7 Ω, 1%, 0603 or 0805
4.3 kΩ, 1%, 0603 or 0805
0 Ω, 0603 or 0805
R9
R10
R11
R13
R14
R15
R16
R17
R19, R20
R21
1.2 Ω, 1%, 0603 or 0805
68 mΩ, 1%, 2010
220 kΩ, 1%, 0603 or 0805
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A6271
Automotive, High-Current LED Controller
D1
Park
22 µH
R11
L1
D3
D2
DRL
C1
C2
C3
4.7 µF
4.7 µF
100 nF
R13
R14
C9
C4
470 mΩ
2.7 Ω
47 nF
150 Ω
100 nF
R22
R12
10 kΩ
VIN
LP
LN
PWMOUT
VREG
10 kΩ
R5
C5
M4
D5
R1
2.7 kΩ
100 kΩ
1 µF
GND
IREF
FAULTn
DR
R7
10 kΩ
R2
5.1 kΩ
LED1
R15
A6271
4.3 kΩ
OVUV
R23
100 kΩ
R16
C10
C11
C12
M5
0 Ω
M3
4.7 µF 4.7 µF 4.7 µF
R4
SG
SP
RT
100 kΩ
PWMIN
IREF
LED12
68 kΩ
R21
M1
M2
R17
220 kΩ
OSC
DITH
COMP
1.2 kΩ
R3
390 Ω
R18
R19
R20
68 mΩ
R10
R8
100 kΩ
R9
110 kΩ
10 kΩ 68 mΩ
C8
39 Ω
C7
D4
5.1 V
R6
10 kΩ
C6
22 pF
22 nF
470 nF
GND
Figure 13: Boost Driving 12 LEDs at 500 mA, Switching Frequency 250 kHz
Park Mode: internal PWM (10%) and analog dimming at 45% of target level, no soft start, and frequency dither on.
Daylight Running Mode (DRL): 100% LED current, no analog dimming, no soft start, and frequency dither on.
Battery voltage applied either at daylight running (DRL) terminal or park terminal. Note that DRL Mode is dominant.
The minimum startup voltage is determined by the voltage on the output (LP) node. 6 V is required at this node, so the input voltage, VIN = 6 V + Vf
(of recirculation diode, D2). If for example, Vf = 0.4 V, then VIN = 6.4 V. Once operating, the A6271 will function down to an input voltage of 4.5 V. The
maximum operating voltage on the input is the maximum LED string voltage, plus the diode drop of D2.
Table 7: Application Circuit 6 Bill of Materials
Reference
Description
Manufacturer/Part Number
C1,C2,C10,C11,C12
4.7 µF, ceramic capacitor, X7R, 50 V
100 nF, ceramic capacitor, X7R, 50 V
1 µF, ceramic capacitor, X7R, 16 V
22 nF, ceramic capacitor, X7R, 50 V
470 nF, ceramic capacitor, X7R, 50 V
22 pF, ceramic capacitor, X7R, 50 V
47 nF, ceramic capacitor, X7R, 16 V
3 A, 100 V Schottky diode
TDK, MuRata
C3,C4
C5
C6
C7
C8
C9
D1, D3
D2
ON Semiconductor / NRVBS3100T3G
Vishay / SS10P6
10 A, 60 V Schottky diode
D4
5.1 V, zener diode
ON Semiconductor / SZBZX84C5V1
1N4148WS
D5
Signal diode
L1
22 µH, high current shielded
construction
Vishay / IHLP-5050FDER220M-5A
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6271
Automotive, High-Current LED Controller
Table 7: Application Circuit 6 Bill of Materials (continued)
Reference
M1, M2, M5
M3
Description
Manufacturer/Part Number
ON Semiconductor, IR / NTR4003N
Vishay / SQD50N10
N-channel signal MOSFET
N-channel, 50 A, 100 V MOSFET
P-channel, 15 A, 100 V MOSFET
Heatsink for M3 (TO-252)
2.7 kΩ, 1%, 0603 or 0805
5.1 kΩ, 1%, 0603 or 0805
390 Ω, 1%, 0603 or 0805
68 kΩ, 1%, 0603 or 0805
100 kΩ, 1%, 0603 or 0805
10 kΩ, 1%, 0603 or 0805
110 kΩ, 1%, 0805 or 1206
39 Ω, 1%, 0603 or 0805
150 Ω, 1%, 0603 or 0805
470 mΩ, 1%, 0805 or 1206
2.7 Ω, 1%, 0603 or 0805
4.3 kΩ, 1%, 0603 or 0805
0 Ω, 0603 or 0805
M4
Infineon / SPD15P10PL G
AAVID Thermalloy / 573100D00010G
R1
R2
R3
R4
R5, R8, R23
R6,R7,R12,R18,R22
R9
R10
R11
R13
R14
R15
R16
R17
1.2 Ω, 1%, 0603 or 0805
68 mΩ, 1%, 2010
R19, R20
R21
220 kΩ, 1%, 0603 or 0805
100 kΩ, NTC, Thermistor
RT
Vishay / NTCS0603E3104FXT
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A6271
Automotive, High-Current LED Controller
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.65
0.45
8º
0º
16
5.00 0.10
16
0.20
0.09
1.70
B
4.40 0.10
3 NOM
6.40 0.20
3.00
6.10
A
0.60 0.15
1.00 REF
1
2
3 NOM
1
2
0.25 BSC
Branded Face
SEATING PLANE
GAUGE PLANE
3.00
C
16X
PCB Layout Reference View
C
0.10
C
SEATING
PLANE
0.30
0.19
1.20 MAX
0.65 BSC
NNNNNNN
YYWW
LLLL
0.15
0.00
A
B
C
Terminal #1 mark area
Exposed thermal pad (bottom surface); dimensions may vary with device
1
D
Standard Branding Reference View
N = Device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W= Week of manufacture
L = Characters 5-8 of lot number
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D
Branding scale and appearance at supplier discretion
Figure 14: Package LP, 16-Pin eTSSOP with Exposed Thermal Pad
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A6271
Automotive, High-Current LED Controller
Revision Table
Revision Number
–
Revision Date
Description
February 3, 2015
Initial Release
Corrected formula on top of page 15. Updated electrical characteristics (VREG Output Voltage, LED
Current Sense and Analog Dimming Differential Sense Voltage). Updated internal PWM and analog
dimming (page 9), LED current-sense resistor (page 10), output overvoltage protection (page 12).
Application circuits 5 and 6 added (pages 31-34). Figures renumbered.
1
August 28, 2015
Corrected Functional Block Diagram (page 4); updated electrical characteristics (disable times, voltage
gain, dither modulation frequency, programmable output overvoltage threshold, hiccup shutdown period,
2
3
December 15, 2015 and output overvoltage threshold test condition); added PWM output undervoltage section (page 13);
updated formula to calculate potential divider for programmable overvoltage protection (page 12 and 13);
added comments to application schematics (page 31 and 33).
Corrected electrical characteristics (PWMOUT Low Voltage, Peak Pull-Up Current, Peak Pull-Down
January 19, 2016
Current) test conditions.
Updated Features and Benefits (page 1), VIN Functional Operating Range test condition (page 5), PWM
Dimming: External Disable Time limits (page 6), PWM Dimming Internal Disable Time limits and Duty
4
5
April 25, 2016
Cycle (page 6), Dither Modulation Frequency limits (page 7), Electrical Characteristics footnote 2 (page
7), Input Undervoltage or VREG Undervoltage Protection section (page 13), VREG Undervoltage action
statement (page 14).
December 2, 2016 Removed extraneous NC row from Terminal List table (page 3).
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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