A6595KA [ALLEGRO]
8-BIT SERIAL-INPUT, DMOS POWER DRIVER; 8位串行输入， DMOS功率驱动器
| 型号： | A6595KA |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 8-BIT SERIAL-INPUT, DMOS POWER DRIVER |
| 文件： | 总10页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6595
ADVANCE INFORMATION
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
(Subject to change without notice)
January 24, 2000
The A6595KA and A6595KLW combine an 8-bit CMOS shift
register and accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power
loads.
POWER
POWER
20
1
2
3
4
GROUND
GROUND
LOGIC
GROUND
LOGIC
SUPPLY
19
V
DD
SERIAL
DATA OUT
SERIAL
DATA IN
18
OUT
0
17
OUT
7
The serial-data input, CMOS shift register and latches allow direct
interfacing with microprocessor-based systems. Serial-data input rates
are over 5 MHz. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
OUT
6
OUT
1
16
15
5
6
OUT
2
OUT
5
14
OUT
3
OUT
4
7
8
A CMOS serial-data output enables cascade connections in appli-
cations requiring additional drive lines. Similar devices with reduced
REGISTER
CLEAR
CLK 13
CLOCK
CLR
OE
OUTPUT
ENABLE
9
12
11
STROBE
ST
r
DS(on) are available as the A6A595.
POWER
GROUND
POWER
GROUND
10
The A6595 DMOS open-drain outputs are capable of sinking up to
750 mA. All of the output drivers are disabled (the DMOS sink drivers
turned off) by the OUTPUT ENABLE input high.
Dwg. PP-029-13
Note that the A6595KA (DIP) and the A6595KLW (SOIC)
are electrically identical and share a common terminal
number assignment.
The A6595KA is furnished in a 20-pin dual in-line plastic package.
The A6595KLW is furnished in a wide-body, small-outline plastic
package (SOIC) with gull-wing leads. Copper lead frames, reduced
supply current requirements, and low on-state resistance allow both
devices to sink 150 mA from all outputs continuously, to ambient
temperatures over 85°C.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................... 50 V
Output Drain Current,
Continuous, IO .......................... 250 mA*
Peak, IOM ................................. 750 mA*†
Peak, IOM ....................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ................................................. 75 mJ
Logic Supply Voltage, VDD .................. 7.0 V
Input Voltage Range,
FEATURES
I 50 V Minimum Output Clamp Voltage
I 250 mA Output Current (all outputs simultaneously)
I 1.3 Ω Typical rDS(on)
VI ................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ........................................... See Graph
Operating Temperature Range,
I Low Power Consumption
I Replacements for TPIC6595N and TPIC6595DW
TA ................................. -40°C to +125°C
Storage Temperature Range,
TS ................................. -55°C to +150°C
* Each output, all outputs on.
Always order by complete part number:
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Part Number
A6595KA
Package
20-pin DIP
RθJA
RθJC
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
55°C/W
70°C/W
25°C/W
17°C/W
A6595KLW
20-lead SOIC
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
LOGIC SYMBOL
2.5
2.0
1.5
1.0
0.5
0
9
G3
C2
12
SRG8
R
8
13
C1
3
1D
2
4
5
6
7
14
15
16
17
18
2
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GS-004A
Dwg. FP-043
FUNCTIONAL BLOCK DIAGRAM
REGISTER
CLEAR
(ACTIVE LOW)
LOGIC
SUPPLY
V
DD
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
STROBE
OUTPUT
ENABLE
(ACTIVE LOW)
LOGIC
GROUND
POWER
GROUND
POWER
GROUND
OUT
OUT
N
0
Dwg. FP-013-5
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
V
OUT
DD
IN
Dwg. EP-063-3
Dwg. EP-010-15
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
V
DD
RECOMMENDED OPERATING CONDITIONS
OUT
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
Dwg. EP-063-2
SERIAL DATA OUT
TRUTH TABLE
Shift Register Contents
Data ClockData
Serial
Latch Contents
Output Contents
Output
Input Input
I
I
I
...
…
…
…
…
…
I
I
Output Strobe
I
I
I
...
I
I
Enable
I
I
I
…
I
I
7
0
1
2
6
7
0
1
2
6
7
0
1
2
6
H
L
H
L
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
1
1
1
2
5
5
6
6
6
7
6
6
7
X
R
0
X
X
X
X
X
X
—
R
R
R
…
R
R
0
1
2
6
7
P
P
P
P
P
P
P
P
P
…
…
P
P
L
P
P
P
…
P
P
0
1
2
6
7
7
0
1
2
6
7
0
1
2
6 7
X
X
X
X
X
H
H
H
H
…
H
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Limits
Characteristic
Symbol Test Conditions
Min.
Typ.
Max.
Units
Output Breakdown
Voltage
V(BR)DSX
IO = 1 mA
50
—
—
V
Off-State Output
Current
IDSX
VO = 40 V
—
—
—
—
—
—
0.05
0.15
1.3
1.0
5.0
2.0
3.2
2.0
—
µA
µA
Ω
VO = 40 V, TA = 125°C
Static Drain-Source
On-State Resistance
rDS(on)
IO = 250 mA, VDD = 4.5 V
IO = 250 mA, VDD = 4.5 V, TA = 125°C
IO = 500 mA, VDD = 4.5 V (see note)
VDS(on) = 0.5 V, TA = 85°C
2.0
Ω
1.3
Ω
Nominal Output
Current
ION
250
mA
Logic Input Current
IIH
IIL
VI = VDD = 5.5 V
—
—
—
4.4
4.1
—
—
—
—
—
—
—
—
—
—
—
1.0
-1.0
—
µA
µA
V
VI = 0, VDD = 5.5 V
Logic Input Hysteresis VI(hys)
1.3
SERIAL-DATA
Output Voltage
VOH
IOH = -20 µA, VDD = 4.5 V
IOH = -4 mA, VDD = 4.5 V
IOL = 20 µA, VDD = 4.5 V
IOL = 4 mA, VDD = 4.5 V
IO = 250 mA, CL = 30 pF
IO = 250 mA, CL = 30 pF
IO = 250 mA, CL = 30 pF
IO = 250 mA, CL = 30 pF
All inputs low
4.49
4.3
—
V
—
V
VOL
0.002
0.2
0.1
0.4
—
V
V
Prop. Delay Time
tPLH
tPHL
650
150
7500
425
15
ns
ns
ns
ns
µA
µA
mA
—
Output Rise Time
Output Fall Time
Supply Current
tr
—
tf
—
IDD(OFF)
IDD(ON)
IDD(fclk)
100
300
5.0
VDD = 5.5 V, Outputs on
fclk = 5 MHz, CL = 30 pF, Outputs off
150
0.6
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
B
SERIAL
DATA IN
DATA
50%
t
p
SERIAL
DATA OUT
50%
DATA
D
E
50%
STROBE
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
t
p
HIGH = OUTPUT OFF
50%
DATA
LOW = OUTPUT ON
Dwg. WP-029-2
OUT
N
HIGH = ALL OUTPUTS DISABLED
50%
OUTPUT
ENABLE
t
PLH
t
t
t
r
PHL
f
90%
OUT
N
DATA
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 10 ns
C. Clock Pulse Width, tw(CLK) ............................................. 20 ns
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) .............................................. 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
www.allegromicro.com
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TEST CIRCUITS
+15 V
INPUT
t
av
IAS = 1.0 A
IO
DUT
OUT
V
(BR)DSX
O(ON)
V
O
V
Dwg. EP-066-1
EAS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
Terminal No.
Terminal Name
POWER GROUND
LOGIC SUPPLY
SERIAL DATA IN
OUT0-3
Function
1
2
Reference terminal for output voltage measurements (OUT0-3).
(VDD) The logic supply voltage (typically 5 V).
Serial-data input to the shift-register.
3
4-7
8
Current-sinking, open-drain DMOS output terminals.
When (active) low, the registers are cleared (set low).
CLEAR
9
OUTPUT ENABLE
When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
10
11
POWER GROUND
POWER GROUND
STROBE
Reference terminal for output voltage measurements (OUT0-3).
Reference terminal for output voltage measurements (OUT0-7).
Data strobe input terminal; shift register data is latched on rising edge.
Clock input terminal for data shift on rising edge.
12
13
CLOCK
14-17
18
OUT4-7
Current-sinking, open-drain DMOS output terminals.
SERIAL DATA OUT
LOGIC GROUND
POWER GROUND
CMOS serial-data output to the following shift register.
Reference terminal for input voltage measurements.
19
20
Reference terminal for output voltage measurements (OUT4-7).
NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
www.allegromicro.com
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
A6595KA
Dimensions in Inches
(controlling dimensions)
0.014
0.008
20
11
0.430
MAX
0.280
0.240
0.300
BSC
1
10
0.100
0.070
0.045
0.005
BSC
MIN
1.060
0.980
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
0.204
20
11
10.92
MAX
7.11
6.10
7.62
BSC
1
10
2.54
1.77
1.15
0.13
BSC
MIN
26.92
24.89
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-20 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
A6595KLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.5118
0.4961
0.0926
0.1043
Dwg. MA-008-20 in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
13.00
12.60
2.65
2.35
Dwg. MA-008-20 mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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