A6810SLWTR-T [ALLEGRO]
10-Bit Serial Input Latched Source Driver; 10位串行输入锁存源极驱动器
| 型号： | A6810SLWTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 10-Bit Serial Input Latched Source Driver |
| 文件： | 总9页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A6810
10-Bit Serial Input Latched Source Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6810
10-Bit Serial Input Latched Source Driver
Features and Benefits
Description
▪ Controlled output slew rate
▪ High-speed data storage
The A6810 combines 10-bit CMOS shift registers,
accompanying data latches, and control circuitry with bipolar
sourcing outputs and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent (VF) displays, the 60 V
and –40 mAoutput ratings also allow this device to be used in
many other peripheral power driver applications. The A6810
features an increased data input rate (compared with the older
UCN/UCQ5810-F) and a controlled output slew rate.
▪ 60 V minimum output breakdown
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL4810x, UCN5810x, and
UCQ5810x
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, serial data-input rates of at least 10 MHz can be
attained
Packages:
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6812 (20-bit) and A6818 (32-bit).
TheA6810outputsourcedriversareNPNDarlingtons,capable
ofsourcingupto40mA.Thecontrolledoutputslewratereduces
electromagnetic noise, which is an important consideration in
systemsthatincludetelecommunicationsandmicroprocessors,
and to meet government emissions regulations. For inter-digit
18-pin DIP
(A package)
20-pin SOICW
(LW package)
Not to scale
Continued on the next page…
Functional Block Diagram
26182.124I
A6810
10-Bit Serial Input Latched Source Driver
Description (continued)
DIP (package A) and surface-mount SOIC (package LW). Copper
leadframes,lowlogic-powerdissipation,andlowoutput-saturation
voltages allow all devices to source 25 mA from all outputs
continuously over the full operating temperature range.
blanking, all output drivers can be disabled and all sink drivers
turned on with a BLANKING input high. The PNP active pull-
downs can sink at least 2.5 mA.
The A6810 is available in three temperature ranges for optimum
performance in commercial (S), industrial (E), and automotive (K)
applications. It is provided in two package styles, through-hole
The lead (Pb) free versions have 100% matte tin leadframe
plating.
Selection Guide
Part Number
Pb-free
Yes
Packing
Ambient Temperature, TA (°C)
–40 to 85
Package
A6810EA-T
21 pieces/tube
18-pin DIP
A6810SA-T
Yes
21 pieces/tube
–20 to 85
A6810ELWTR-T
A6810KLWTR-T
A6810SLWTR-T
Yes
1000 pieces/13-in. reel
1000 pieces/13-in. reel
1000 pieces/13-in. reel
–40 to 85
Yes
–40 to 125
20-pin SOIC-W
Yes
–20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and
notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased
for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change May 3,
2010. Deadline for receipt of LAST TIME BUY orders is October 29, 2010.
Absolute Maximum Ratings*
Characteristic
Symbol
VDD
Notes
Rating
7.0
Units
V
Logic Supply Voltage
Driver Supply Voltage
VBB
60
V
Input Voltage Range
VIN
–0.3 to VDD + 0.3
–40 to 15
–40 to 85
–40 to 125
–20 to 85
150
V
Continuous Output Current Range
IOUT
mA
ºC
ºC
ºC
ºC
ºC
Range E
Range K
Range S
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
TJ(max)
T
stg
–55 to 125
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6810
10-Bit Serial Input Latched Source Driver
Pin-out Diagrams
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
Value Units
Package A, 1-layer PCB with copper limited to solder pads
65
90
ºC/W
ºC/W
Package Thermal Resistance
RθJA
Package LW, 1-layer PCB with copper limited to solder pads
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6810
10-Bit Serial Input Latched Source Driver
ELECTRICAL CHARACTERISTICS at T = +25°C (A6810S-) or over operating temperature range (A6810E-),
A
V
= 60 V, logic supply operating voltage VDD = 3.0 to 5.5 V; unless otherwise noted
BB
Limits @ V
= 3.3 V Limits @ V
= 5 V
DD
DD
Characteristic
Symbol
Test Conditions
= 0 V
Mln.
—
Typ.
Max.
-15
—
Min. Typ. Max.
<-0.1 -15
Units
μA
V
Output Leakage Current
Output Voltage
I
V
<-0.1
58.3
1.0
—
CEX
OUT
V
V
I
I
= -25 mA
= 1 mA
57.5
—
57.5 58.3
—
1.5
—
OUT(1)
OUT(0)
OUT(0)
OUT
OUT
1.5
—
—
2.5
3.3
—
1.0
5.0
—
V
Output Pull-Down Current
Input Voltage
I
V
= 5 V to V
2.5
2.2
—
5.0
mA
V
OUT
BB
V
V
—
—
—
IN(1)
IN(0)
IN(1)
IN(0)
—
1.1
1.0
—
1.7
V
Input Current
I
I
V
V
= V
—
<0.01
—
<0.01 1.0
<-0.01 -1.0
μA
μA
V
IN
DD
= 0 V
—
<-0.01 -1.0
—
IN
Input Clamp Voltage
V
I
I
I
= -200 μA
—
-0.8
3.05
0.15
—
-1.5
—
—
-0.8
4.75
0.15
—
-1.5
—
IK
IN
Serial Data Output Voltage
V
V
= -200 μA
= 200 μA
2.8
—
4.5
—
V
OUT(1)
OUT(0)
OUT
OUT
0.3
—
0.3
—
V
Maximum Clock Frequency
Logic Supply Current
f
10*
—
10*
—
MHz
mA
mA
mA
μA
μs
μs
μs
μs
μs
μs
c
I
All Outputs High
All Outputs Low
0.25
0.25
1.5
0.2
0.7
1.8
0.7
1.8
—
0.75
0.75
3.0
20
0.3
0.3
1.5
0.2
0.7
1.8
0.7
1.8
—
1.0
1.0
3.0
20
DD(1)
DD(0)
I
—
—
Load Supply Current
I
All Outputs High, No Load
All Outputs Low
—
—
BB(1)
BB(0)
I
—
—
Blanking-to-Output Delay
Strobe-to-Output Delay
t
C = 30 pF, 50% to 50%
—
2.0
3.0
2.0
3.0
12
—
2.0
3.0
2.0
3.0
12
dis(BQ)
L
t
C = 30 pF, 50% to 50%
—
—
en(BQ)
L
t
R = 2.3 kΩ, C ≤ 30 pF
—
—
p(STH-QL)
L
L
t
R = 2.3 kΩ, C ≤ 30 pF
—
—
p(STH-QH)
L
L
Output Fall Time
Output Rise Time
t
R = 2.3 kΩ, C ≤ 30 pF
2.4
2.4
2.4
2.4
f
L
L
t
R = 2.3 kΩ, C ≤ 30 pF
—
12
—
12
r
L
L
Output Slew Rate
dV/dt
R = 2.3 kΩ, C ≤ 30 pF
4.0
—
—
20
—
4.0
—
—
20
—
V/μs
L
L
Clock-to-Serial Data Out Delay t
I
= ±200 μA
50
50
ns
p(CH-SQX)
OUT
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
*Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6810
10-Bit Serial Input Latched Source Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
B
SERIAL
DATA IN
DATA
50%
t
p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
E
50%
STROBE
BLANKING
LOW = ALL OUTPUTS ENABLED
t
p(STH-QH)
t
p(STH-QL)
90%
DATA
OUT
N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
BLANKING
OUT
t
dis(BQ)
t
t
f
r
t
90%
50%
en(BQ)
DATA
N
10%
Dwg. WP-030A
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................... 25 ns
B. Data Active Time After Clock Pulse
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
(Data Hold Time), th(D) ................................................ 25 ns
C. Clock Pulse Width, tw(CH) ................................................. 50 ns
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns
E. Strobe Pulse Width, tw(STH) .............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specified maximum clock frequency.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the PNP active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6810
10-Bit Serial Input Latched Source Driver
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data Clock
Input Input I
Data Strobe
Output Input
I
I
...
I
I
I
I
I
...
I
I
Blanklng
I
I
I
... I
I
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
N-1 N
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2
N-2
N-1
N-1
N-1
N
N-1
N-1
N
X
R
1
X
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P
P
N-1 N
1
2
3
N-1
N
N
1
2
3
N-1
N
1
2
3
X
H
... L
L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6810
10-Bit Serial Input Latched Source Driver
Package A 18-Pin DIP
22.86 ±0.51
18
+0.10
–0.05
0.25
+0.38
–0.25
+0.76
–0.25
10.92
7.62
6.35
A
1
2
C
5.33 MAX
+0.51
SEATING
PLANE
3.30
–0.38
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
2.54
+0.25
–0.38
1.52
0.46 ±0.12
A
Terminal #1 mark area
Package LW 20-Pin SOICW
12.80±0.20
4° ±4
20
20
+0.07
–0.06
2.25
0.27
10.30±0.33
7.50±0.10
9.50
A
+0.44
–0.43
0.84
0.25
1
2
1
2
0.65
1.27
PCB Layout Reference View
B
20X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10
C
1.27
0.41 ±0.10
2.65 MAX
0.20 ±0.10
Terminal #1 mark area
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
B
Reference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6810
10-Bit Serial Input Latched Source Driver
Copyright ©1998-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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