A80603KESJSR [ALLEGRO]
LED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple;
| 型号： | A80603KESJSR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | LED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple |
| 文件： | 总30页 (文件大小：4525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A80603 and A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
FEATURES AND BENEFITS
DESCRIPTION
The A80603 and A80603-1 are multi-output LED drivers that
integrateacurrent-modeboostconverterwithaninternalpower
switch and four current sinks. The boost converter can drive
four strings of LEDs at up to 120 mA, or LED sinks can be
paralleledtogethertoachievehighercurrentsupto480mAtotal.
• Automotive AEC-Q100 qualified
• Enhanced fault handling for ASIL B system compliance
• Wide input voltage range of 4.5 to 40 V for start/stop,
cold crank, and load dump requirements
• Fully integrated LED current sinks and boost converter
with internal power MOSFET
• Operate in Boost or SEPIC mode for flexible output
• Drives up to 11 series white LED in 4 parallel strings, at
up to 120 mA per string (VF = 3.3 V max).
• Boost switching frequency synced externally or
programmed from 200 kHz to 2.3 MHz
• Clock-Out feature for internal switching frequency
• Adjustable boost frequency dithering to reduce EMI
• Advanced control allows minimum PWM on-time down
to 0.3 µs, and avoids MLCC audible noises
• LED contrast ratio: 15,000:1 at 200 Hz using PWM
dimming alone, 150,000:1 when combining PWM and
analog dimming
The devices operate from single power supply from 4.5 to
40 V; once started, they can continue to operate down to 3.9 V.
This allows the parts to withstand stop/start, cold crank, and
load dump conditions encountered in automotive systems. By
using patented Pre-Emptive Boost control, an LED brightness
contrast ratio of 15,000:1 can be achieved using PWM-only
dimming at 200 Hz. Higher ratios are possible when using a
combination of PWM and analog dimming.
Switching frequency can be either above or below the AM
band, set by either a resistor or the synchronization pin to
between 200 kHz and 2.3 MHz. A programmable dithering
feature further reduces EMI. The Clock-Out pin allows other
converterstobefedtheclockfrequency,includingprogrammed
dithering—even when the LED output is turned off.
Continued on next page...
PACKAGE:
The A80603 provides protection against application faults
and external component open/short. Current sense/gate drive
functionsallowoptionaluseofaninputsupplydisconnectFET
incaseofoutputtogroundshortfaultinboostconfiguration.The
A80603-1 is identical to theA80603 except for soft start timer
and FAULT pin behavior (see Fault Table section for details).
24-Pin 4 mm × 4 mm QFN
with Wettable Flank
Not to scale
VIN
VOUT
ꢀoptional
L1
D1
RSC
Q1
Cin
RADJ
ROVP
COUT1
COUT2
SW
GATE
OVP
PGND
LED1
Vsense
Vin
V
c
CVDD
VDD
RPU
FAULT
A80603
LED2
LED3
Up to 11 WLEDs in series
Up to 120 mA/channel
EN
Enable
PWM
APWM
PWM tON ≥ 0.3 µs
LED4
CLKOUT
AGND
COMP
PEB
FSET
ISET
DITH
APWM 100 kHz 0-90%
RZ
CP
RDITH
CDITH
RISET
RFSET
RPEB
CZ
Figure 1: Typical application diagram showing A80603 in Boost mode
A80603-DS
March 4, 2019
MCO-0000619
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
FEATURES AND BENEFITS (continued)
APPLICATIONS
• Excellent input voltage transient response even at lowest
PWM duty cycle
• Automotive infotainment backlighting
• Automotive cluster
• Gate driver for optional PMOS input disconnect switch
• Extensive protection against:
• Automotive center stack
• Automotive exterior lighting
□ Shorted boost switch, inductor or output capacitor
□ Shorted FSET or ISET resistor
□ Open or shorted LED pins and LED strings
□ Open boost Schottky diode
□ Overtemperature
SELECTION GUIDE [1]
Part Number
Soft Start Timer
Package
Packing
Leadframe Plating
A80603KESJSR
8 ms
24-pin 4 × 4 mm wettable flank QFN
with exposed thermal pad and sidewall plating
6000 pieces per reel
100% matte tin
A80603KESJSR-1 [2]
16 ms
[1] Contact Allegro for additional packing options.
[2] Contact Allegro factory for availability of A80603KESJSR-1.
ABSOLUTE MAXIMUM RATINGS [3]
Characteristic
Symbol
VLEDx
VOVP
VIN
Notes
Rating
Unit
V
LEDx Pin
OVP pin
VIN
x = 1..4
–0.3 to 40
–0.3 to 40
–0.3 to 40
V
V
Higher of –0.3
and (VIN – 7.4) to
VIN +0.4
VSENSE
VGATE
,
VSENSE, GATE
V
Continuous
–0.6 to 50
–1.0 to 54
–1.5 to 60
–0.3 to 40
V
V
V
V
SW
VSW
t < 50 ns (repetitious, <2.5 MHz)
Single-event in case of Fault [4]
FAULT
VFAULT
APWM, EN, PWM, CLKOUT, COMP,
DITH, FSET, ISET, VDD, PEB
–0.3 to 5.5
V
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
TJ(max)
Tstg
Range K
–40 to 125
150
°C
°C
°C
–55 to 150
[3] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[4] SW DMOS is self-protecting and will conduct when VSW exceeds 60 V.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions [5]
Value
Unit
Package Thermal Resistance
RθJA
ES package measured on 4-layer PCB based on JEDEC standard
37
°C/W
[5] Additional thermal information available on the Allegro website.
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Table of Contents
Clock Out Function.......................................................... 15
LED Current Setting ........................................................ 16
PWM Dimming ............................................................... 16
Pre-Emptive Boost (PEB)................................................. 17
Analog Dimming with APWM Pin....................................... 18
Extending LED Dimming Ratio.......................................... 19
Analog Dimming with External Voltage............................... 20
VDD.............................................................................. 21
Shutdown....................................................................... 21
Fault Detection and Protection............................................. 22
LED String Partial-Short Detect ........................................ 22
Overvoltage Protection .................................................... 22
Boost Switch Overcurrent Protection ................................. 23
Input Overcurrent Protection and Disconnect Switch ........... 24
Setting the Current Sense Resistor ................................... 24
Input UVLO.................................................................... 25
Fault Protection During Operation ..................................... 25
Fault Recovery Mechanism.............................................. 28
Package Outline Drawing.................................................... 29
Features and Benefits........................................................... 1
Description.......................................................................... 1
Applications......................................................................... 1
Package ............................................................................. 1
Selection Guide ................................................................... 2
Absolute Maximum Ratings................................................... 2
Thermal Characteristics ........................................................ 2
Typical Application – SEPIC .................................................. 3
Functional Block Diagram ..................................................... 4
Pinout Diagram and Terminal List........................................... 5
Electrical Characteristics....................................................... 6
Functional Description .......................................................... 9
Enabling the IC................................................................. 9
Powering Up: LED Detection Phase.................................. 10
Powering Up: Boost Output Undervoltage.......................... 12
Soft Start Function .......................................................... 12
Frequency Selection........................................................ 13
Synchronization.............................................................. 14
Loss of External Sync Signal............................................ 14
Switching Frequency Dithering ......................................... 15
Lꢄ
ꢀSꢆ ꢑ ꢀꢁN ꢒ ꢀꢂUꢃ ≤ 50 ꢀ
ꢅ1 ꢓreaꢔdown ꢕoltageꢖ ꢗ0 ꢀ
ꢀꢁN
ꢅ1
L1
CC
L1 ꢝ Lꢄ may ꢞe either
seꢋarate or integrated
CꢁN
RꢂꢀP
CꢂUꢃ1
CꢂUꢃꢄ
Sꢆ
ꢙAꢃꢈ
ꢂꢀP
ꢀsense
ꢀin
ꢀc
Cꢀꢅꢅ
ꢀꢅꢅ
RPU
Lꢈꢅ1
ꢊAULꢃ
Aꢘ0ꢗ03
Uꢋ to ꢌ ꢆLꢈꢅs in series
ꢍꢀꢂUꢃ ꢎ 15 ꢀꢏ
Uꢋ to 1ꢄ0 mAꢐch
Lꢈꢅꢄ
Lꢈꢅ3
Lꢈꢅꢌ
ꢈN
PꢆM
APꢆM
PꢆM tꢂN ≥ 0.3 ꢇs
CꢂMP
Pꢈꢓ
CLꢚꢂUꢃ
AꢙNꢅ
ꢊSꢈꢃ
ꢁSꢈꢃ
APꢆM 100 ꢔHꢛ 0-90ꢜ
ꢅꢁꢃH
Rꢉ
CP
RꢅꢁꢃH
CꢅꢁꢃH
RꢁSꢈꢃ
RꢊSꢈꢃ
RPꢈꢓ
Cꢉ
Figure 2: Typical application showing SEPIC configuration for flexible input/output voltage ratio
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
ꢋꢄUꢈ
ꢋ
SꢇNSꢇ
ꢇꢚternal
SꢖNC
L1
CꢅꢌꢈH
RꢀSꢇꢈ
RꢅꢌꢈH
ꢍAꢈꢇ
Sꢓ
ꢀSꢇꢈꢊSꢖNC
ꢅꢌꢈH
CLꢙꢄUꢈ actiꢆe as
long as ꢇNꢛH
ꢄscillator
ꢀreꢗꢁency
dithering
CLꢙꢄUꢈ
ꢋꢅꢅ
Clocꢃ ꢄꢁt
ꢂꢁꢏꢏer
NMꢄS
ꢀꢇꢈ
ꢏSꢓ
NMꢄS
ꢍate
CꢄMP
ꢅriꢆe
ꢂoost
ꢇnaꢘle
Comꢉarator
Rsense
CꢄMP
PꢍNꢅ
Soꢏt Start
Ramꢉ
ꢐꢝꢊ1ꢞ msꢒ
Cꢁrrent
sense
PꢍNꢅ
CCꢄMP
ꢋ
Lꢇꢅ
reꢏ
1 MHꢜ
ꢟꢑ
ꢑ MHꢜ
Lꢇꢅ1
.
.
Mꢁlti-inꢉꢁt
ꢇrror Amꢉ
ꢄCPꢎ
ꢈSꢅ
System
ꢄscillator
Lꢇꢅꢑ
ꢋꢄUꢈ
ꢀSꢇꢈ or ꢌSꢇꢈ
ꢉin ꢄꢉenꢊShort
ꢋꢅꢅ
ꢌnternal ꢋꢅꢅ
ꢐꢑ.ꢎ5ꢋꢒ
Cꢋꢅꢅ
Roꢆꢉ
ꢋꢌN
ꢄꢋP
sense
Regꢁlator
UꢋLꢄ ꢂlocꢃ
1.ꢎ35 ꢋ
Rꢇꢀ
ꢄꢋP
ꢋreꢏ
ꢀaꢁlt ꢂlocꢃ
AꢍNꢅ
RSC
ꢇnaꢘle
ꢄꢉenꢊShort
Lꢇꢅ ꢅetect
ꢔ
ꢌnꢉꢁt cꢁrrent
sense amꢉ
ꢋ
SꢇNSꢇ
Choꢉꢉing
ꢀreꢗꢁency
ꢑ MHꢜ
iAꢅꢕ
Lꢇꢅ1
Lꢇꢅꢎ
Lꢇꢅ3
Lꢇꢅꢑ
Lꢇꢅ
ꢅriꢆer
ꢂlocꢃ
ꢋꢌN
ꢄnꢊꢄꢏꢏ
ꢍAꢈꢇ
ꢄꢀꢀ
ꢂoost
ꢇnaꢘle
ꢍAꢈꢇ
ꢇN
Cꢁrrent
leꢆel
PMꢄS
ꢅriꢆer
AꢍNꢅ
ꢇnaꢘle
APꢓM
ꢌnt ꢋꢅꢅ
ꢌSꢇꢈ
ꢌSꢇꢈ
ꢂlocꢃ
ꢋreꢏ
ꢙeeꢉ-Aliꢆe
ꢈimer
RꢌSꢇꢈ
1 MHꢜ
100kΩ
ꢇꢚternal PꢓM
ꢋꢅꢅ
PꢓM
RPU
Lꢇꢅ ꢇnaꢘle
start
Pre-ꢇmꢉtiꢆe
ꢂoost
100kΩ
ꢀAULꢈ
Pꢇꢂ
ꢌnternal ꢀAULꢈ
delay
RPꢇꢂ
AꢍNꢅ
A80603
Figure 3: Functional Block Diagram
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
PINOUT DIAGRAM AND TERMINAL LIST
FAULT
CLKOUT
VDD
1
2
3
4
5
6
18 PGND
17 PGND
16 LED4
15 LED3
14 LED2
13 LED1
PAD
AGND
COMP
ISET
Package ES, 24-Pin QFN Pinouts
Terminal List Table
Number
Name
Function
The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 10 kΩ resistor between this pin and desired
logic level voltage.
1
FAULT
Logic output representing the switching frequency of internal boost oscillator. This allows other converters to be synchronized to the same fSW
with the same dithering modulation, if applicable. Output is active as long as EN = H.
2
CLKOUT
3
4
5
6
7
VDD
AGND
COMP
ISET
Output of internal LDO (bias regulator). Connect a 1 µF decoupling capacitor between this pin and GND.
LED current ground. Also serves as ‘quiet’ ground for analog signals.
Output of the error amplifier and compensation node. Connect a series RZ-CZ network from this pin to GND for control loop compensation.
Connect RISET resistor between this pin and GND to set the 100% LED current.
PEB
Connect resistor to GND to adjust delay time (~2 to 9 µs) for Pre-Emptive Boost. Leave pin open for minimum PEB delay of 1 µs.
Dithering control: connect a capacitor to GND to set the dithering modulation frequency (typically 1 to 3 kHz). Connect a resistor between
DITH and FSET pins to set the dithering range (such as ±5% of fSW).
8
9
DITH
FSET/SYNC
APWM
Frequency/synchronization pin. A resistor RFSET from this pin to GND sets the switching frequency fSW (with dithering super-imposed)
between 200 kHz and 2.3 MHz. It can also be used to synchronize fSW to an external frequency between 260 kHz and 2.3 MHz (dithering is
disabled in this case).
Analog dimming. Apply APWM clock (40 kHz to 1 MHz) to this pin and the duty cycle of this clock determines the LED current. Leave open or
connect to GND for 100%.
10
Controls the on/off state of LED current sinks to reduce the light intensity by using pulse-width modulation. Typical PWM dimming frequency
is in the range of 200 Hz to 2 kHz. EN and PWM pins may be tied together to allow single-wire dimming control.
11
12
PWM
EN
Enables the IC when this pin is pulled high. If EN goes low, the IC remains in standby mode for up to 16 ms, then shuts down completely.
LED current sinks #1 to 4. Connect the cathode of each LED string to pin. Unused LED pin must be terminated to GND through a 6.19 kΩ
resistor.
13-16
LED1-4
17-18
19
PGND
OVP
SW
Power ground for internal NMOS switching device.
Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the over voltage protection level.
The drain of the internal NMOS switching device of the boost converter.
Output gate driver pin for external P-channel FET control.
20-21
22
GATE
Connect this pin to the negative sense side of the current sense resistor RSC. The threshold voltage is measured as VIN – VSENSE. There is
also a fixed ~20 µA current sink to allow for trip threshold adjustment.
23
24
–
VSENSE
VIN
Input power to the IC as well as the positive input used for current sense resistor.
Exposed pad of the package providing enhanced thermal dissipation. Must be connected to the ground plane(s) of the PCB with at least
8 vias, directly in the pad.
PAD
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
ELECTRICAL CHARACTERISTICS [1]: Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indicates specifica-
tions guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C
Characteristics
INPUT VOLTAGE SPECIFICATIONS
Operating Input Voltage Range [3]
VIN UVLO Start Threshold
VIN UVLO Stop Threshold
UVLO Hysteresis [2]
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VIN
●
●
●
4.5
−
−
–
40
V
V
VUVLO(rise)
VUVLO(fall)
VUVLO_HYS
VIN rising
VIN falling
4.35
3.95
600
−
–
V
300
450
mV
INPUT CURRENTS
VIN Pin Operating Current
VIN Pin Quiescent Current
VIN Pin Sleep Current
IOP
IQ
EN and PWM = H, fSW = 2 MHz
EN = H and PWM = L, fCLKOUT = 2 MHz
VIN = 16 V, VEN = 0 V
●
●
●
−
−
−
13
10
2
18
−
mA
mA
µA
IQSLEEP
10
INPUT LOGIC LEVELS (EN, PWM, APWM)
Input Logic Level-Low
Input Logic Level-High
VIL
●
●
−
−
−
0.4
V
V
VIH
1.5
−
R
EN, RPWM,
RAPWM
Input Pull-Down Resistor
Input = 5 V
60
100
140
kΩ
OUTPUT LOGIC LEVELS (CLKOUT)
Output Logic Level-Low
Output Logic Level-High
CLKOUT Duty Cycle
VOL
VOH
5 V < VIN < 40 V
●
●
●
−
1.8
33
−
−
−
0.3
−
V
V
5 V < VIN < 40 V
DCLKOUT
tCLKNPW
fSW = 2 MHz, no external sync
External sync = 260 kHz to 2.3 MHz
50
200
67
−
%
ns
CLKOUT Negative Pulse Width [2]
APWM PIN
APWM Frequency Range [2]
APWM Duty Cycle Range [2]
VDD REGULATOR
fAPWM
Clock signal applied to pin
Clock signal applied to pin
●
●
40
0
−
−
1000
90
kHz
%
DAPWM
Regulator Output Voltage
VDD UVLO Start Threshold
VDD UVLO Stop Threshold
ERROR AMPLIFIER
VDD
VIN > 4.5 V, iLOAD < 1 mA
4.05
−
4.25
3.2
4.45
−
V
V
V
VDDUVLOrise VDD rising, no external load
VDDUVLOfall VDD falling, no external load
−
2.65
−
Amplifier Gain [2]
gm
VCOMP = 1.5 V
−
−
−
−
1000
–500
+500
1.4
−
−
−
−
μA/V
μA
Source Current
IEA(SRC)
IEA(SINK)
RCOMP
VCOMP = 1.5 V
Sink Current
VCOMP = 1.5 V
μA
COMP Pin Pull Down Resistance
FAULT = 0, VCOMP = 1.5 V
kΩ
Continued on the next page…
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
ELECTRICAL CHARACTERISTICS [1] (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indi-
cates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C
Characteristics
DITHERING CONTROL
DITH Pin Source Current
DITH Pin Sink Current
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
iDITH(src)
iDITH(sink)
Output current when VDITH < 0.8 V
Output current when VDITH > 1.2 V
−
−
20
−
−
μA
μA
−20
OVERVOLTAGE PROTECTION
OVP Pin Voltage Threshold
VOVP(th)
iOVP(th)
OVP pin connected to VOUT
Current into OVP pin at 125ºC
Measured over temperature
●
●
2.2
140
140
2.5
146.5
150
2.8
153
160
V
µA
µA
OVP Pin Sense Current Threshold
OVP Sense Current Temperature
Coefficient [2]
∆iOVP
Current into OVP pin
−
−36
−
nA/ºC
OVP Pin Leakage Current
OVP Variation at Output
IOVPLKG
VOUT = 16 V, EN = L
●
−
−
−
−
0.1
−
1
5
µA
%
V
ΔOVP
Measured at VOUT when ROVP = 249 kΩ
Measured at VOUT when ROVP = 249 kΩ [2]
Measured at VOUT when ROVP = 0 Ω
3.3
0.2
4.2
0.25
Undervoltage Detection Threshold
Secondary Overvoltage Protection
VUVP(th)
V
Measured at SW pin; part latches when OVP2
is detected
VOVP2
●
●
51
55
59
V
BOOST SWITCH
Switch On Resistance
RSW
ISW = 0.75 A, VIN = 16 V
−
−
−
250
0.1
−
500
1
mΩ
µA
µA
ISWLKG25
VSW = 13.5 V, VPWM = VIL, TJ = 25°C
VSW = 13.5 V, VPWM = VIL, TJ = 85°C
Switch Pin Leakage Current
[2]
ISWLKG85
10
IC truncates present switching cycle when
primary limit is reached
Switch Pin Current Limit
ISW(LIM)
●
3.0
3.75
4.5
A
Secondary Switch Current Limit [2]
Minimum Switch On-Time
ISW(LIM2)
tSW(ON)
tSW(OFF)
IC latches off when secondary limit is reached
−
45
−
5.1
65
50
−
A
●
●
85
66
ns
ns
Minimum Switch Off-Time
OSCILLATOR FREQUENCY
RFSET = 10 kΩ
●
1.95
−
2.15
200
2.35
−
MHz
kHz
V
Oscillator Frequency
fSW
R
FSET = 110 kΩ
FSET Pin Voltage
VFSET
RFSET = 10 kΩ
−
1.00
−
SYNCHRONIZATION
VSYNCL
VSYNCH
FSET/SYNC pin logic Low
FSET/SYNC pin logic High
●
●
●
●
●
−
−
−
−
−
−
0.4
−
V
V
Sync Input Logic Level
1.5
260
150
150
Synchronized PWM Frequency
Synchronization Input Min Off-Time
Synchronization Input Min On-Time
fSWSYNC
2300
−
KHz
ns
tPWSYNCOFF
tPWSYNCON
−
ns
Continued on the next page…
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
ELECTRICAL CHARACTERISTICS [1] (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indi-
cates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
LED CURRENT SINKS
iISET = 120 µA (RISET = 8.33 kΩ),
LEDx Accuracy [4]
LEDx Matching
ErrLED
ΔLEDx
VLED
●
●
●
●
−
−
0.7
0.8
700
3
2
%
%
R
FSET = 10 kΩ, VAPWM = 0 V
iISET = 120 µA, RFSET = 10 kΩ, VAPWM = 0 V
Measured individually with all other LED pins
tied to ≥1 V, iISET = 120 µA, VAPWM = 0 V
LEDx Regulation Voltage
600
800
mV
I
ISET to ILEDx Current Gain
AISET
VISET
iISET
iISET = 120 µA, VAPWM = 0 V
812
0.97
20
832
1
852
1.03
144
A/A
V
ISET Pin Voltage
Allowable ISET Current
●
●
−
µA
LED String Partial-Short-Detect
Voltage
Sensed from each LED pin to GND while its current
sink is in regulation; all other LED pins tied to 1 V
VLEDSC
tLEDSC
4.5
−
5.2
−
6
6.6
−
V
LED String Partial-Short-Detect
Duration
Time required to confirm LED string partial-
short and pull FAULT = L
µs
ms
LED Pin Shorted-to-GND Check
Duration
Wait time before proceeding with Soft-Start (if
no LED pin is shorted to GND)
tLEDSTG
−
1.5
A80603
6.5
13
8
9.5
19
ms
ms
Soft-Start Ramp Up Time
tSSRU
A80603-1
16
EN goes from High to Low; exceeding tEN(OFF)
results in IC shutdown
Enable Pin Shut Down Delay
tEN(OFF)
tPWMH
●
●
10
16
22
ms
µs
Minimum PWM Dimming On-Time
GATE PIN
First and subsequent PWM pulses
−
0.3
0.4
Gate Pin Sink Current
Gate Pin Source Current
IGSINK
VGS = VIN, no input OCP fault
−
−
−113
−
−
µA
IGSOURCE
VGS = VIN – 6 V, input OCP fault tripped
6
mA
Gate Shutdown Delay When Over-
Current Fault Is Tripped [2]
tFAULTT
VGS
VIN – VSENSE = 200 mV; monitored at FAULT pin
−
−
−
3
µs
V
Measured between GATE and VIN when gate
is fully on
Gate Voltage
−6.7
−
VSENSE PIN
VSENSE Pin Sink Current
VSENSE Trip Point
iADJ
●
●
16
88
20
24
µA
VSENSETRIP Measured between VIN and VSENSE, RADJ = 0 Ω
100
110
mV
PEB PIN
PEB Delay Time
tPEB
iPEB = 60 µA
2.4
3.2
4.0
µs
FAULT PIN
FAULT Pull Down Voltage
FAULT Pin Leakage Current
THERMAL PROTECTION (TSD)
Thermal Shutdown Threshold [2]
Thermal Shutdown Hysteresis [2]
VFAULT
IFAULT = 1 mA
VFAULT = 5 V
−
−
−
−
0.5
1
V
iFAULT-LKG
µA
TSD
Temperature rising
155
170
20
−
−
°C
°C
TSDHYS
−
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing);
positive current is defined as going into the node or pin (sinking).
[2] Ensured by design and characterization; not production tested.
[3] Minimum VIN = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to VIN = 4 V.
[4] LED current is trimmed to cancel variations in both Gain and ISET voltage.
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
FUNCTIONAL DESCRIPTION
The A80603 is a multistring LED regulator with an integrated
boost switch and four precision current sinks. It incorporates a
patented Pre-Emptive Boost (PEB) control algorithm to achieve
PWM dimming ratio over 15,000:1 at 200 Hz. PEB control
also minimizes output ripple to avoid audible noise from output
ceramic capacitors.
Only if no faults were detected, then the IC can proceed to start
switching.
As long as EN = H, the PWM pin can be toggled to control the
brightness of LED channels by using PWM dimming. Alterna-
tively, EN and PWM can be tied together to allow single-wire
control for both power on/off and PWM dimming. If EN is pulled
low for longer than 16 ms, the IC shuts off.
The switching frequency can be either synchronized to an
external clock or generated internally. Spread-spectrum tech-
nique (with user-programmable dithering range and modulation
frequency) is provided to reduce EMI. A clock-out signal (CLK-
OUT) allows other converters to be synchronized to the switching
frequency of A80603.
Enabling the IC
The A80603 wakes up when EN pin is pulled above logic high
level, provided that VIN pin voltage is over the VIN_UVLO
threshold. The boost stage and LED channels are enabled sepa-
rately by PWM = H signal after the IC powers up.
The IC performs a series of safety checks at power up, to deter-
mine if there are possible fault conditions that might prevent the
system from functioning correctly. Power-up checks include:
• VOUT shorted to GND
Figure 4: Startup showing EN, VDD, CLKOUT, and ISET (PWM = L).
Note that CLKOUT is available as soon as VDD ramps up, even though
Boost stage and LED drivers are not yet enabled.
• LED pin shorted to GND
• FSET pin open/shorted
• ISET pin open/shorted to GND, etc.
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
ꢄꢅUꢆ
Powering Up: LED Detection Phase
ꢄꢅUꢆ
The VIN pin has an undervoltage lockout (UVLO) function that
prevents the A80603 from powering up until the UVLO threshold is
reached. Once the VIN pin goes above UVLO and a high signal is
present on the EN pin, the IC proceeds to power up. At this point, the
A80603 is going to enable the disconnect switch and will try to check
if any LED pins are shorted to GND and/or are not used. The LED
detection phase starts when PWM = H and the GATE voltage of the
input disconnect PMOS switch is pulled down to 3.3 V below VIN.
Using all Lꢀꢁ
Channels
Using Lꢀꢁ
Channels 1-3
Lꢀꢁ1
Lꢀꢁꢈ
Lꢀꢁ3
Lꢀꢁ1
Lꢀꢁꢈ
Lꢀꢁ3
Lꢀꢁꢂ
ꢃNꢁ
Lꢀꢁꢂ
ꢃNꢁ
ꢇ.19 kΩ
Figure 6: How to signal an unused LED channel
during startup LED detection phase
Table 1: LED Detection phase voltage threshold levels
LED Pin
Voltage Measured
Interpretation
Outcome
Cannot proceed with
soft-start unless fault
is removed
LED pin shorted to
GND fault
< 120 mV
LED channel is
removed from
operation
LED channel not in
use
~ 230 mV
> 340 mV
LED channel in use
Proceed with soft-start
Figure 5: Startup showing EN+PWM, GATE, LED1, and ISET.
Switching frequency = 2.15 MHz. Note that LED Detection Phase
starts as soon as GATE pin is pulled down to 3.3 V below VIN
(provided that PWM = H).
Once the voltage threshold on VLED pins exceeds ~120 mV, a
delay of approximately 1.5 ms is used to determine the status of
the pins.
Unused LED pin should be terminated with a 6.19 kΩ resistor to
GND. At the end of LED detection phase, any channel with pull
down resistor is then disabled and will not contribute to the boost
regulation loop.
Figure 7: A80603 normal startup showing all channels passed LED
Detection phase. Total LED current = 100 mA × 4 (only LED1 and
LED2 pin voltages are shown).
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Figure 10: A80603; LED1 is shorted-to-GND initially, then released.
After the fault is removed, the IC auto-recovers and proceeds with
Figure 8: A80603-1 normal startup showing all channels passed
LED Detection phase. Note longer soft start timer.
soft-start. FAULT is released at the end of LED detection phase.
Figure 9: A80603 normal startup showing LED1 channel is disabled
with a 6.19 kΩ resistor to GND. Total LED current = 100 mA × 3.
Figure 11: A80603-1, LED1 is shorted-to-GND initially, then released.
After the fault is removed, the IC auto-recovers and proceeds with
soft-start. FAULT is released at the beginning of LED detection phase.
If an LED pin is shorted to ground, the A80603 will not proceed
with soft start until the short is removed from the LED pin. This
prevents the A80603 from ramping up the output voltage and put-
ting an uncontrolled amount of current through the LEDs.
The FAULT pin is pulled low in case of LED pin shorted-to-GND
fault (A80603 only), but the IC continues to retry. Once the fault
is removed, the soft-start process will continue. The same applies
in case of FSET or ISET pin is shorted to GND.
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
This is illustrated by the following startup timing diagram (not to
scale):
Power Up: Boost Output Undervoltage
During startup, after the input disconnect switch has been
enabled, the output voltage is checked through the OVP (over-
voltage protection) pin. If the sensed voltage does not rise above
VUVP(th), the output is assumed to be at fault and the IC will not
proceed with soft start. Output UVP level is linked to the OVP
level programmed according to the equation:
ꢀꢁ
ꢂꢃꢄ
ꢀꢁN
3.3 ꢀ
ꢂ.ꢃ ꢀ
ꢅAꢆꢀ
0
VUVP = VOVP / 12
1ꢀ
ꢊꢀꢋꢌ
0
Undervoltage protection may be caused by one of the following
faults:
Lꢆꢇ detection
ꢈhase
ꢄꢀP
93ꢅ ꢄꢀP
1.5 ms
• Output capacitor shorted to GND
• Boost inductor or diode open
• OVP sense resistor open
ꢇꢈꢉꢆ
ꢀꢁN
0
After an UVP (undervoltage protection) fault, the A80603 is
immediately shutdown and latched off. To enable the IC again,
the latched fault must be cleared. This can be achieved by
powering-cycling the IC, which means either:
tSSRU
ꢍ
ꢊꢀꢋ
0
Soꢉt-Start
Regꢊlation
A
ꢎ
ꢏ
ꢋ
ꢀ
• VIN falls below falling UVLO threshold, or
• EN = L for >16 ms.
Figure 12: Complete startup process of A80603
Explanation of Events:
Alternatively, latched fault can be cleared by keeping EN = H but
pulling PWM = L for >16 ms. This method has the advantage that
it does not interrupt the CLKOUT signal.
A: EN = H wakes up the IC. VDD ramps up and CLKOUT
becomes available. IC starts to pull down GATE slowly.
Soft Start Function
B: When GATE is pulled down to 3.3 V below VIN, ISET becomes
enabled. IC is now waiting for PWM = H to startup.
During startup, the A80603 ramps up its boost output voltage
following a fixed slope, as determined by OVP set point and Soft-
Start Timer. This technique limits the input inrush current, and
ensures consistent startup time regardless of the PWM dimming
duty cycle.
C: Once PWM = H, the IC checks each LEDx pins to determine
if it is in use, disabled, or shorted to GND.
D: Soft-Start begins at the completion of LED pin short-detect
phase of 1.5 ms. VOUT ramps up following a fixed slope set by
OVP and soft-start timer of ~8 ms (16 ms for the A80603-1).
The soft-start process is completed when any one of the follow-
ing conditions is met:
E: Soft-start terminates when all LED currents reached regula-
• All enabled LED channels have reached their regulation
current,
tion, VOUT reached 93% OVP, or soft-start timer expired.
• Output voltage has reached 93% of its OVP threshold, or
• Soft-start ramp time (tSSRU) has expired.
To summarize, the complete startup process of A80603 consists
of:
• Power-up error checking
• Enabling input disconnect switch
• LED pin open/short detection
• Soft-start ramp
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Frequency Selection
ꢃC ꢄꢅꢅ
The switching frequency of the boost regulator is programmed
by a resistor connected to FSET pin. The switching frequency
can be selected anywhere from 200 kHz to 2.3 MHz. The chart
below shows the typical switching frequency verses FSET resis-
tor value.
ꢎNꢑH ꢕ
ꢈꢃNꢖUꢈLꢄ
Power ꢁꢆ
ꢇꢈꢉꢉ, ꢊꢋ readyꢌ ꢋAꢍꢎ
ꢆꢁlled Lꢌ ꢀaꢁlt checꢏingꢐ
ꢎNꢑL
ꢀAULꢍ State
ꢇꢀAULꢍ ꢑ Lꢐ
Any ꢀaꢁlt
detectedꢂ
ꢒes
No
ꢎNꢑH ꢕ
PꢗMꢑL
ꢃC Ready
ꢇCLꢓꢄUꢍ actiꢔe,
ꢎNꢑL
ꢀAULꢍꢑ Lꢐ
ꢎNꢑH ꢕ PꢗMꢑH
Pin shorted
to ꢋNꢉ ꢅaꢁlt
Lꢎꢉ Pin Checꢏ
ꢇꢃn Use, ꢉisaꢘled, or
Shorted to ꢋNꢉꢐ
→ FAULT = L
ꢍime-oꢁt withoꢁt ꢅaꢁlts
→ FAULT = H
Soꢅt Start
ꢇꢘoost Sꢗ actiꢔeꢌ
Lꢎꢉ sinꢏs ꢑ on
when PꢗM ꢑ Hꢐ
Soꢅt start ꢅinished
Figure 14: Switching Frequency
as a function of FSET Resistance
Any ꢀaꢁlt
detectedꢂ
ꢒes
No
Alternatively, the following empirical formula can be used:
PꢗM ꢉimming
Equation 1:
fSW = 21.5 / (RFSET + 0.2)
Lꢎꢉꢑon
Clear 1ꢙ ms timer
where fSW is in MHz and RFSET is in kΩ.
ꢎN ꢕꢕ PꢗM ꢑ L
ꢎN ꢕꢕ PꢗM ꢑ H
If a fault occurs during operation that will increase the switch-
ing frequency, the internal oscillator frequency is clamped to a
maximum of 3.5 MHz. If the FSET pin is shorted to GND, the
part will shut down. For more details, refer to the Fault Mode
Table section.
Lꢎꢉꢑoꢅꢅ
Start 1ꢙ ms timer
ꢍimer eꢚꢆired
Figure 13: A80603 Startup Flow Chart
13
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Synchronization
ꢃꢒ
The A80603 can also be synchronized using an external clock.
At power up, if the FSET pin is held low, the IC will not start.
Only when the FSET pin is tristated to allow for the pin to rise to
about 1 V, or when a sync clock is detected, the A80603 will then
try to power up.
ꢀꢁꢂ
500 ns
ꢃꢄꢅꢆꢇꢈnꢉ
ꢊ ꢋꢇꢃꢌ
1 ꢀ
ꢍꢎꢏꢐꢑꢌ
The basic requirement of the external sync signal is 150 ns
minimum on-time and 150 ns minimum off time. The diagram
below shows the timing restrictions for a synchronization clock at
2.2 MHz.
ꢁnternal oscillator
ꢂꢃternal Sync
Figure 16: Avoid switching over between Internal
Oscillator and External Sync in highlighted region
t PꢂSꢃNCꢄN
15ꢁ ns
Loss of External Sync Signal
150 ns
Suppose the A80603 started up with a valid external SYNC sig-
nal, but the SYNC signal is lost during normal operation. In that
case, one of the following happens:
150 ns
tPꢂSꢃNCꢄꢅꢅ
• If the external SYNC signal is high impedance (open), the
IC continues normal operation after approximately 5 μs, at
the switching frequency set by RFSET. No FAULT flag is
generated.
t ꢀ ꢁ5ꢁ ns
Figure 15: Pulse width requirements
for an External Sync clock at 2.2 MHz
• If the external SYNC signal is stuck low (shorted to ground),
the IC will detect an FSET-shorted-to-GND fault. FAULT
pin is pulled low after approximately 10 μs, and switching is
disabled. Once the FSET pin is released or SYNC signal is
detected again, the IC will proceed to soft-start.
Based on the above, any clock with a duty cycle between 33%
and 66% at 2.2 MHz can be used. The table below summarizes
the allowable duty cycle range at various synchronization fre-
quencies.
To prevent generating a fault when the external SYNC signal
is stuck at low, the circuit shown below can be used. When the
external SYNC signal goes low, the IC will continue to operate
normally at the switching frequency set by the RFSET. No FAULT
flag is generated.
Table 2: Acceptable Duty Cycle range for External Sync
clock at various frequencies
Sync. Pulse Frequency
2.2 MHz
Duty Cycle Range
33% to 66%
ꢁꢅternal
2 MHz
30% to 70%
Sychroniꢆation
ꢊꢊ0ꢋꢀ
Signal
1 MHz
15% to 85%
ꢀSꢁꢂꢃSꢄNC
600 kHz
9% to 91%
300 kHz
4.5% to 95.5%
RꢀSꢁꢂ
10kΩ
Schottꢇy
ꢈarrier
ꢉiode
If it is necessary to switch over between internal oscillator and
external sync during operation, ensure the transition takes place
at least 500 ns after the previous PWM = H rising edge. Alterna-
tively, execute the switchover during PWM = L only. This restric-
tion does not apply if PWM dimming is not being used.
Figure 17: Countermeasure for
External Sync Stuck-at-Low Fault
It is important to use a small capacitance for the AC-coupling
capacitor (220 pF in the above example). If the capacitance is too
large, the IC may incorrectly declare a FSET-shorted-to-GND
fault and restart.
14
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
There are no hard limits on dithering range and modulation
Switching Frequency Dithering
frequency. As a general guideline, pick a dithering range between
±5% and 10%, with the modulation frequency between 1 kHz and
3 kHz. In practice, using a larger dithering range and/or higher
modulation frequency do not generate any noticeable benefits.
To minimize the peak EMI spikes at switching frequency har-
monics, the A80603 offers the option of frequency dithering, or
spread-spectrum clocking. This feature simplifies the input filters
needed to meet the automotive CISPR 25 conducted and radiated
emission limits.
If dithering function is not desired, it can be disabled by discon-
necting the RDITH between DITH and FSET pins. Connect DITH
pin to VDD if CDITH is not populated. Dithering is always dis-
abled when fSW is controlled by external sync. RDITH and CDITH
have no effects in this case even if they were populated.
For maximum flexibility, the A80603 allows both dithering range
and modulation frequency to be independently programmable
using two external components.
The Dithering Modulation Frequency is given by the approximate
equation:
Clock Out Function
The A80603 allows other ICs to be synchronized to its internal
switching frequency through the CLKOUT pin.
Equation 2:
fDM (kHz) = 25 / CDITH (nF)
where CDITH is the value of capacitor connected from DITH
pin to GND.
The CLKOUT signal is available as soon as the IC is enabled
(EN = H), even when the boost stage is not active (PWM = L).
Its frequency is the same as that of the internal oscillator. Its
duty cycle, however, depends on how the switching frequency is
generated:
The dithering Range is given by the approximate equation:
Equation 3:
Range (±%) = 20 × RFSET / RDITH
where RFSET is the resistor from FSET pin to GND, RDITH is
the resistor between DITH and FSET pins.
• If fSW is programmed by FSET resistor, the CLKOUT duty
cycles is approximately 50%.
As an example, by using RFSET = 10 kΩ, RDITH = 40.1 kΩ,
and CDITH = 22 nF, the resulted switching frequency is fSW
2.15 MHz ±5% modulated at 1.1 kHz. This is illustrated by the
following diagram.
• If fSW is controlled by external sync, the output signal has a
fixed 150 ns negative pulse width (CLKOUT = L), regardless
of the external sync frequency.
=
This is illustrated by the following waveforms:
ꢈꢄꢅꢃꢆ
ꢇ
ꢀꢁꢂꢃ ꢈ 100 ꢊA
ꢉ5 ꢊA
ꢀꢁꢂꢃ
ꢄꢅꢃꢆ
1.ꢅ ꢌ
1.0 ꢌ
0.ꢋ ꢌ
ꢇꢄꢅꢃꢆ ꢈ ꢉꢅ0 ꢊA
ꢈꢆSꢇꢂ
RꢀꢁꢂH
ꢃ0.1 ꢄΩ
RꢆSꢇꢂ
10 ꢄΩ
CꢀꢁꢂH
ꢅꢅ nꢆ
ꢇꢄꢅꢃꢆ
ꢅ0 ꢊA
0
ꢀithering Range ꢈ
ꢉ5ꢖ
ꢍꢅ0 ꢊA
Modꢒlation
ꢓreꢔꢒency
ꢈ 1.1 ꢄHꢕ
Period ꢈ 0.ꢋ ꢎ C ꢏ i
ꢐ0.ꢋꢋ ms when C ꢈ ꢅꢅ nꢆꢑ
ꢉꢁꢊ ꢋꢌꢆꢍꢎ
ꢅ.ꢅ5
ꢅ.15
ꢅ.05
ꢂime ꢐmsꢑ
0
0.ꢋꢋ
Figure 18: How to Program Switching Frequency
Dithering Range and Modulation Frequency
Figure 19: Without external sync, the CLKOUT signal has a fixed
duty cycle of 50%. Delay from CLKOUT falling edge to SW falling
edge is approximately 50 ns.
15
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
PWM Dimming
When both EN and PWM pins are pulled high, the A80603 turns
on all enabled LED current sinks. When either EN or PWM is
pulled low, all LED current sinks are turned off. The compensa-
tion (COMP) pin is floated, and critical internal circuits are kept
active.
Figure 20: With external sync, the CLKOUT signal has a fixed
negative pulse width of 200 ns. Delay from SYNC rising edge to
CLKOUT falling edge is approximately 60 ns.
LED Current Setting
The maximum LED current can be up to 120 mA per channel,
and is set through the ISET pin. Connect a resistor RISET between
this pin and GND. The relation between ILED and RISET is given
below:
Figure 21: PWM dimming operation at 20% 1 kHz. CH1 = PWM (5 V/
div), CH2 = SW (20 V/div), CH3 = VOUT, CH4 = iLED (200 mA/div).
Equation 4:
By using the patented Pre-Emptive Boost (PEB) control algo-
rithm, the A80603 is able to achieve minimum PWM dimming
on-time down to 300 ns. This translates to PWM dimming ratio
up to 15,000:1 at the PWM dimming frequency of 200 Hz. Tech-
nical details on PEB will be explained in the next section.
ILED = ISET × AISET
ISET = VISET / RISET
Therefore RISET = (VISET × AISET ) / ILED
= 832 / ILED
where ILED current is in mA and RISET is in kΩ.
This sets the maximum current through the LEDs, referred to
as the ‘100% current’. The average LED current can be reduced
from the 100% current level by using either PWM dimming or
analog dimming.
Table 3: ISET resistor values vs. LED current. Resistances
are rounded to the nearest E-96 (1%) resistor value.
Standard Closest RISET
LED current per channel
Resistor Value
6.98 kΩ
8.25 kΩ
10.5 kΩ
13.7 kΩ
21.0 kΩ
120 mA
100 mA
80 mA
60 mA
40 mA
Figure 22: Zoom in view for PWM on-time = 10 µs. Notice that the
LED current is shifted with respect to PWM signal. Ripple at VOUT
is ~0.2 V when using 2 × 4.7 µF MLCC as output capacitors.
16
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
CH1 (Yellow) = PWM (5 V/div); CH2 (Red) = Inductor current
(500 mA/div); CH3 (Blue) = VOUT (1 V/div); CH4 (Green) =
LED current (200 mA/div); time scale = 2 µs/div.
Figure 23: Zoom-in view showing A80603 is able to regulate LED
current at PWM on-time down to 300 ns.
The typical PWM dimming frequencies fall between 200 Hz and
1 kHz. There is no hard limit on the highest PWM dimming fre-
quency that can be used. However at higher PWM frequency, the
maximum PWM dimming ratio will be reduced. This is shown in
the following table:
Figure 24: Traditional PWM Dimming operation where boost switch
and LED current are enabled at the same time. Note that VOUT
shows overall ripple of ~0.5 V
When PWM signal goes high, a conventional LED driver turns
on its boost switching at the time with LED current sinks. The
problem is that the inductor current takes several switching cycles
to ramp up to its steady-state value before it can deliver full
power to the output load. During the first few cycles, energy to
the LED load is mainly supplied by the output capacitor, which
results in noticeable dip in output voltage.
Table 4: Maximum PWM Dimming Ratio that can be achieved
when operating at different PWM Dimming Frequency
Maximum PWM
PWM Frequency
PWM Period
Dimming Ratio
15,000:1
3,000:1
200 Hz
1 kHz
5 ms
1 ms
3.3 kHz
20 kHz
300 µs
50 µs
1,000:1
150:1
Pre-Emptive Boost
The basic principle of pre-emptive boost (PEB) can be best
explained by the following two waveforms. The first one shows
how a conventional LED driver operates during PWM dimming
operation. The second one shows that of the A80603.
Common test conditions for both cases:
PWM = 1% at 1 kHz (on-time=10 µs), fSW = 2.15 MHz,
L = 10 µH, VIN = 12 V, LED load = 8 series (VOUT = ~25 V)
at 100 mA × 4. COUT = 2 × 4.7 µF 50 V 1210 MLCC.
COMP: RZ = 280 Ω, CZ = 68 nF.
Figure 25: A80603 PWM dimming operation with PEB delay set to
3 µs. Note that VOUT ripple is reduced to ~0.2 V.
Common scope settings:
17
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
In the A80603, the boost switch is also enabled when PWM goes
high. However, the LED current is not turned on until after a
short delay of tPEB. This allows the inductor current to build up
before it starts to deliver the full power to LED load. During the
pre-boost period, VOUT actually bumps up very slightly, while
the following dip is essentially eliminated. When PWM goes low,
both boost switching and LED remains active for the same delay
of tPEB. Therefore the PWM on-time is preserved in LED current.
Analog Dimming with APWM Pin
APꢀM
ꢁSꢂꢃ
Cꢄrrent
Mirror
APꢀM ꢁSꢂꢃ
ꢁSꢂꢃ
Cꢄrrent
Adꢅꢄst ꢆlocꢇ
RꢁSꢂꢃ
PEB delay can be programmed using an external resistor, RPEB
from PEB pin to GND. Their relationship is shown in the follow-
ing chart:
,
PꢀM
Lꢂꢈ ꢈriꢉer
PEB Delay (µs) vs. PEB Resistor value (kΩ)
10
Figure 27: Simplified block diagram of APWM function
9
8
7
6
5
4
3
2
1
0
The APWM pin is used in conjunction with the ISET pin to
achieve analog dimming. This is a digital signal pin that inter-
nally adjusts the ISET current. The typical input signal frequency
is between 40 kHz and 1 MHz. The duty cycle of this signal is
inversely proportional to the percentage of current delivered to
the LED. The relationship is shown below:
Normalized LED Current vs. APWM Duty Cycle
100%
80%
Measured
6
8
10
12
14
16
18
20
22
24
60%
RPEB (kΩ)
Theore�cal
Figure 26: How PEB delay time varies with value of PEB pin resis-
40%
20%
0%
tor to GND.
Ideally, tPEB is equal to the inductor current ramp up time. But the
latter is affected by many external parameters, such as switching
frequency, inductance, VIN and VOUT ratio, etc. Therefore, some
experimentation is required to optimize the PEB delay time. In
general for switching frequency at 2 MHz, tPEB = 2.5 to 4 µs is a
good starting point.
0%
20%
40%
60%
80%
100%
APWM Duty Cycle
The advantage of PEB is that even a non-optimized delay time
can significantly reduce the output ripple voltage compared to a
conventional LED driver.
Figure 28: Showing LED current is inversely proportional to the
APWM duty cycle. Test conditions: VIN =12 V, VOUT = 25 V (8 ×
WLED), total LED current = 100 mA × 4, APWM frequency = 100 kHz
As an example, a system that delivers a full LED current of
100 mA per channel would deliver 75 mA when an APWM signal
with a duty-cycle of 25% is applied (because analog dimming
level is 100% – 25% = 75%). This is demonstrated by the fol-
lowing waveforms.
18
Allegro MicroSystems, LLC
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
As an example, assume that:
• LED from lowest bin has an efficacy of 80 lm/W
• LED highest bin has an efficacy of 120 lm/W
Suppose the maximum LED current was set at 100 mA based
LEDs from lowest bin. When using LEDs from highest bin, the
current should then be reduces to 67% (80/120). This can be
achieved by sending APWM clock with 33% duty cycle.
When analog dimming is not used, APWM pin should be either
tied to GND or left floating (there is an internal pull-down resis-
tor to GND).
Extending LED Dimming Ratio
The dynamic range of LED brightness can be further extended,
by using a combination of PWM duty cycle, APWM duty cycle,
and analog dimming method.
Figure 29: PWM = H. Total LED current drops from 400 mA (4 ×
100 mA/ch) to 300 mA when APWM of 25% duty cycle is applied.
Note that LED current takes ~0.5 ms to settle after change in APWM.
For example, the following approach can be used to achieve a
100,000:1 dimming ratio at 200 Hz:
• Vary PWM duty cycle from 100% down to 0.01% to give
10,000:1 dimming. This requires PWM dimming on-time be
reduced down to 0.5 µs.
• With PWM dimming on-time fixed at 0.5µs, vary APWM
duty from 0% to 90% to reduce peak LED current from 100%
down to 10%. This gives a net effect of 100,000:1 dimming.
Average LED Current vs. PWM Dimming Duty Cycle
100
10
1
Figure 30: PWM = 25% at 1 kHz. Peak LED current drops from
400 mA (4 × 100 mA/ch) to 300 mA when APWM of 25% duty cycle
is applied
0.1
One popular application of analog dimming is for LED brightness
calibration, commonly known as ‘LED Binning’. LEDs from
the same manufacturer and series are often grouped into differ-
ent ‘bins’ according to their light efficacy (lumens per watt). It is
therefore necessary to calibrate the ‘100% current’ for each LED
bin, in order to achieve uniform luminosity.
PWM Dimming
0.01
APWM + PWM
Ideal
0.001
0.001
0.01
0.1
1
10
100
PWM Dimming Duty Cycle (%)
To use APWM pin as a trim function, the user should first set
the 100% current based on efficacy of LED from the lowest bin.
When using LED with higher efficacy, the required current is then
trimmed down to the appropriate level using APWM duty cycle.
Figure 31: How to achieve 100,000:1 dimming ratio by using both
PWM and APWM. Test conditions: VIN = 12 V, VOUT = 25 V (8 ×
WLED), total LED current = 400 mA, PWM frequency = 200 Hz,
APWM frequency = 100 kHz.
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Note that the A80603 is capable of providing analog dimming
range greater than 10:1. By applying APWM with 96% duty
cycle, for example, an analog dimming range of 25:1 can be
achieved. However, this requires the external APWM signal
source to have very fine pulse-width resolution. At 200 kHz
APWM frequency, a resolution of 50 ns is required to adjust its
duty cycle by 1%.
When VDAC is lower than 1.00 V, the LED current is increased.
Some common applications for the above scheme include:
• LED binning
• Thermal fold-back using external NTC (negative temperature
coefficient) thermistor
In the following application example, the thermistor used is NTC-
S0805E3684JXT (680 kΩ @ 25°C). R1 = 336 kΩ, R2 = 20 kΩ,
and R3 = 8.45 kΩ. The LED current per channel is reduced from
97 mA at 25°C to 34 mA at 125°C.
Analog Dimming with External Voltage
Besides using APWM signal, the LED current can also be
reduced by using an external voltage source applied through a
resistor to the ISET pin. The dynamic range of this type of dim-
ming is dependent on the ISET pin current. The recommended
ꢀꢁꢁ
ꢂꢃ.ꢄ5 ꢀꢅ
iSET range is from 20 µA to 144 µA for the A80603. Note that
the IC will continue to work at iSET below 20 µA, but the relative
error in LED current becomes larger at lower dimming level.
Aꢉ0ꢊ03
NTC
Rꢄ
ꢆSꢇꢈ
Below is a typical application circuit using a DAC (digital-analog
converter) to control the LED current. The ISET current (which
ꢂ1.0 ꢀꢅ
R1
ꢋNꢁ
R3
directly controls the LED current) is normally set as VISET/RISET
.
The DAC voltage can be higher or lower than VISET, thus adjust-
ing the LED current to a lower or higher value.
Figure 33: Thermal foldback of
LED current using NTC thermistor
Aꢃ0ꢄ03
Rꢅ
ꢈꢇAC
ꢀSꢁꢂ
RꢀSꢁꢂ
ꢆNꢇ
Figure 32: Adjusting LED current
with an external voltage source
Equation 5:
VISET
RISET
VDAC −V
R2
ISET
iISET
=
−
where VISET is the ISET pin voltage (typically 1.0 V), and
VDAC is the DAC output voltage.
Figure 34: LED current varies with temperature
when using thermistor NTCS0805E3684JXT
for thermal foldback
When VDAC is higher than 1.00 V, the LED current is reduced.
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
There is an alternative way to reset the internal fault status reg-
isters. By keeping EN = H and PWM = L for longer than 16 ms,
the A80603 clears all internal fault registers but does not go into
sleep mode. The next time PWM pin goes high, the IC will still
go through soft start process. The difference is that VDD voltage
and CLKOUT signal are always available as long as EN = H.
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect a CVDD capacitor with a value of 1 μF or greater to this
pin. The internal LDO can deliver up to 2 mA of current with a
typical VDD voltage of about 4.25 V. This allows it to serve as
the pull up voltage for FAULT pin.
Shutdown
If EN pin is pulled low for longer than tEN(OFF) (~16 ms), the
A80603 enters shutdown (sleep mode). The next time EN pin
goes high, all internal fault registers are cleared. The IC needs to
go through a complete soft start process after PWM goes high.
Figure 36: As long as EN = H, the IC does not shut down VDD and
CLKOUT. But internal latched faults are cleared by PWM = L for
~16 ms.
Figure 35: After EN = L for ~16 ms, the IC completely shuts down
so VDD (Blue) decays.
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A80603 and
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LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
FAULT DETECTION AND PROTECTION
For the A80603 only, the FAULT pin is pulled low in case any
LED String Partial-Short Detect
LED string is directly or partially shorted. However, the rest of
the LED strings continue to operate. The FAULT pin is latched at
low until it is reset by either EN = L or PWM = L for >16 ms.
All LED current sink pins (LED1 to LED4) are designed to with-
stand the maximum output voltage, as specified in the Absolute
Maximum Ratings table. This prevents the IC from being dam-
aged if VOUT is directly applied to an LED pin due to an output
connector short.
In case of direct-short or partial-shorted fault in any LED string dur-
ing operation, the LED pin with voltage exceeding VLEDSC will be
removed from regulation. This prevents the IC from dissipating too
much power due to large voltage drop across the LED current sink.
Figure 39: A80603-1 startup sequence when LED string#2 has a
partial-short fault (6 × WLED instead of 8). As soon as LED2 pin rises
above VLEDSC (~5 V), the channel is disabled but FAULT remains High.
At least one LED pin must be at regulation voltage (below
~1.2 V) for the LED string partial-short detection to activate.
In case all of the LED pins are above regulation voltage (this
could happen when the input voltage rises too high for the LED
strings), they will continue to operate normally.
Figure 37: A80603 Normal startup sequence showing voltage at LED1 and
LED2 pins. VIN = 6 V, output = 8 × WLED in series, current = 4 × 100 mA
Overvoltage Protection
The A80603 offers a programmable output overvoltage protection
(OVP), plus a fixed secondary overvoltage protection (OVP2).
The OVP pin has a threshold level of 2.5 V typical. Overvoltage
protection is tripped when current into this pin exceeds ~150 µA.
A resistor can be used to set the OVP threshold up to 40 V approxi-
mately. This is sufficient for driving 11 white LEDs in series.
The formula for calculating the OVP resistor is shown below:
Equation 6:
ROVP = (VOVP – VOVP(th)) / iOVP(th)
where VOVP is the desired OVP threshold, VOVP(th) = 2.5 V
typical, iOVP(th) = 150 µA typical.
To determine the desired OVP threshold, take the maximum LED
string voltage at cold and add ~10% margin on top of it.
Figure 38: A80603 startup sequence when LED string#2 has a partial-
short fault (6 × WLED instead of 8). As soon as LED2 pin rises above
VLEDSC (~5 V), the channel is disabled and FAULT = Low.
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
The OVP event is not a latched fault and, by itself, does not pull
the FAULT pin to low. If the OVP condition occurs during a load
dump, for example, the IC will stop switching but not shut down.
There are several possibilities of why an OVP condition is
encountered during operation. The two most common being an
open LED string and a disconnected output connector.
The waveform below shows a typical OVP condition. When one
LED string becomes open, current through its LED driver drops
to zero. The A80603 responses by boosting the output voltage
higher. When output reaches OVP threshold, the LED string with-
out current is removed from regulation. The rest of LED strings
continue to draw current and drain down VOUT. Once VOUT falls
below ~97% OVP, boost will resume switching to power the
remaining LED strings.
Figure 41: An open-diode fault is introduced during normal opera-
tion. SW voltage jumps to ~70 V, causing the MOSFET to self-con-
duct and dissipate energy in the inductor.
It should be noted that the SW MOSFET in A80603 is designed
to avalanche and dissipate the excess energy safely in case of
open-diode fault. Therefore the IC is not damaged even though
SW node rises above AbsMax rating momentarily.
Boost Switch Overcurrent Protection
The boost switch is protected with cycle-by-cycle current limit-
ing set at typical 3.75 A, minimum 3.0 A. The waveform below
shows normal switching at VIN = 6 V, VOUT = 25 V, and total
LED current 400 mA.
Figure 40: An open-LED string faults causes VOUT to ramp up and
trip OVP. The A80603 then disables the open LED string and con-
tinues with remaining strings.
The A80603 also has a fixed secondary overvoltage protection to
protect its internal switch. If the boost Schottky diode suddenly
becomes open during normal operation, the energy stored in the
inductor will force SW node voltage to increase rapidly. Once
voltage on the SW pin exceeds OVP2, switching and all LED
drivers are disabled. The IC remains latched off until it is reset.
Figure 42: Normal switching waveform at VIN = 6 V showing the SW
node voltage (Red) and inductor current (Green).
23
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
When the input voltage is reduced further, input current increases If the input current level goes above the preset current limit thresh-
and peak switch current reaches 3.2 A. SW_OCP is tripped and
the IC skips a switching cycle to reduce the current
old, the part will be shut down in less than 3 µs. This is a latched
condition. The fault flag is also set to indicate a fault. This feature
protects the input from drawing too much current during heavy
load. It also prevents catastrophic failure in the system due to a
short of the inductor or output capacitors shorted to GND.
The waveform below illustrates the typical input overcurrent
fault condition. As soon as input OCP limit is reached, the part
disables the gate of the disconnect switch Q1 and latches off.
Figure 43: When peak current in SW pin reaches ~3.2 A, overcur-
rent protection kicks in and the IC skips a switching cycle.
There is also a secondary current limit (ISW(LIM2)) that is sensed
on the boost switch. This current limit once detected immediately
shuts down the A80603. This current limit is set at about 33%
higher than the pulse-by-pulse current limit. It is to protect the
switch from destructive current spikes in case the boost inductor
is shorted. Once this limit is tripped, the A80603 will immedi-
ately shut down and latch off.
Figure 45: Startup into an output shorted-to-GND fault. Input OCP
is tripped when current (Green trace) exceeds 4 A. PMOS Gate
(Red) is turned off immediately and IC latches off.
During startup when Q1 first turns on, an inrush current flows
through Q1 into the output capacitance. If Q1 turns on too fast
(due to its low gate capacitance), the inrush current may trip
input OCP limit. In this case, an external gate capacitance CG is
added to slow down the turn-on transition. Typical value for CG is
around 4.7 to 22 nF. Do not make CG too large, since it also slows
down the turn-off transient during a real input OCP fault.
Input Overcurrent Protection and
Disconnect Switch
iSꢆNSꢆ
ꢇꢈN
ꢅo L1
RSC
ꢀ1
ꢁPMꢂSꢃ
RAꢉꢊ
Cꢄ
Setting the Current Sense Resistor
iAꢉꢊ
ꢄAꢅꢆ
ꢇSꢆNSꢆ
ꢇꢈN
The typical threshold for the current sense is 100 mV when RADJ
is 0 Ω. The A80603 can have this voltage trimmed using the RADJ
resistor. The typical trip point should be set to at least 3.75 A,
which coincides with the cycle-by-cycle peak current limit typi-
cal threshold. A sample calculation is done below for 4.2 A of
input current.
A80603
ꢇꢈN ꢋ ꢇSꢆNSꢆ ꢌ RSC ꢍ iSꢆNSꢆ ꢎ RAꢉꢊ ꢍ iAꢉꢊ
Figure 44: Optional input disconnect switch using a PMOSFET
When RADJ is not used:
The primary function of the input disconnect switch is to protect
the system and the device from catastrophic input currents during
a fault condition.
Equation 7:
VSENSETRIP = RSC × iSENSE = 100 mV
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A80603 and
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LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
The desired sense resistor is RSC = 100 mV / 4.2 A = 23.8 mΩ.
But this is not a standard E-24 resistor value. Pick the closest
lower value which is 22 mΩ.
The possible fault conditions that the part can detect include:
• Open LED Pin or open LED string
• Shorted or partially shorted LED string
• LED pin shorted to GND
When RADJ is used:
• Open or shorted boost diode
• Open or shorted boost inductor
• VOUT short to GND
Equation 8: VSENSETRIP = RSC × iSENSE + RADJ × iADJ
Therefore
• SW shorted to GND
• ISET shorted to GND
RADJ = [VSENSETRIP – (RSC × iSENSE)] / iADJ
ꢀ
=ꢀ[100ꢀmVꢀ–ꢀ92.4ꢀmV]ꢀ/ꢀ20ꢀµAꢀ=ꢀ380ꢀΩ
• FSET shorted to GND
• Input disconnect switch drain shorted to GND
Input UVLO
Note that some of these faults will not be protected if the input
disconnect switch is not being used. An example of this is VOUT
short to GND fault.
When VIN and VSENSE rise above VUVLOrise threshold, the
A80603 is enabled. The IC is disabled when VIN falls below VUV-
LOfall threshold for more than 50 μs. This small delay is used to
avoid shutting down because of momentary glitches in the input
power supply.
Fault Protection During Operation
The A80603 constantly monitor the state of the system to deter-
mine if any fault conditions occur during normal operation. The
response to a triggered fault condition is summarized in the table
below. It is important to note that there are several points at which
the A80603 monitors for faults during operation. The locations are
input current, switch current, output voltage, switch voltage, and
LED pins. Some of the protection features might not be active dur-
ing startup to prevent false triggering of fault conditions.
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Table 5: A80603 Fault Mode Table
Fault Flag
Set
Disconnect
Switch
Fault Name
Type
Active
Description
Boost Switch
LED Sink drivers
This fault condition is triggered when the SW current exceeds the
cycle-by-cycle current limit, ISW(LIM).The present SW on-time is
truncated immediately to limit the current. Next switching cycle starts
normally.
Primary Switch Overcurrent
Protection (Cycle-By-Cycle Auto-restart
Current Limit)
Off for a single
cycle
Always
NO
YES
YES
ON
OFF
OFF
ON
When current through boost switch exceeds secondary SW current
limit (iSW(LIM2)) the device immediately shuts down the disconnect
switch, LED drivers and boost. The Fault flag is set. To reset the fault
the EN or PWM pin needs to be pulled low for 16 ms.
Secondary Switch Current
Limit
Latched
Off
Always
Always
OFF
OFF
OFF
OFF
The device is immediately shut off if the voltage
across the input sense resistor is above the
VSENSEtrip threshold. To reset the fault the EN or PWM pin must be
pulled low for 16 ms.
Input Disconnect Current
Limit
Latched
Off
Secondary overvoltage protection is used for open diode detection.
When diode D1 opens, the SW pin voltage will increase until
VOVP(SEC) is reached . This fault latches the IC. The input disconnect
switch and LED drivers are disabled. To reset the fault the EN or
PWM pin needs to be pulled low for 16 ms.
Latched
Off
Secondary OVP
LEDx Pin Shorted to GND
LEDx Pin Open
Always
Startup
YES
YES
YES
OFF
OFF
ON
OFF
ON
OFF
OFF
If any of the LED pins is determined to be shorted to GND when PWM
first goes high, soft-start process is halted. Only when the short is
removed, then soft-start is allowed to proceed.
Auto-restart
Auto-restart
If an LED string is not getting enough current, the device will first
respond by increasing the output voltage until OVP is reached. Any
LED string that is still not in regulation will be disabled. The device will
then go back to normal operation by reducing the output voltage to
the appropriate voltage level.
OFF for open
pins.
ON for all others.
Normal
operation
ON
Fault occurs when the ISET current goes above 150% of max current.
The boost will stop switching and the IC will disable the LED sinks
until the fault is removed. When the fault is removed, the IC will try to
regulate to the preset LED current.
ISET Short Protection
Auto-restart
Auto-restart
Always
Always
YES
YES
OFF
OFF
ON
OFF
OFF
Fault occurs when the FSET current goes above 150% of max
current. The boost will stop switching, Disconnect switch will turn off
and the IC will disable the LED sinks until the fault is removed. When
the fault is removed, the IC will try to restart with soft-start.
FSET/SYNC Short
Protection
OFF
Fault occurs when current into OVP pin exceeds iOVP(th) (typically
150 µA). The IC will immediately stop switching but keep the LED
drivers active, to drain down the output voltage. Once the output
voltage decreases to ~97% OVP level, the IC will restart switching to
regulate the output current.
STOP during
OVP event.
Overvoltage Protection
Undervoltage Protection
Auto-restart
Auto-restart
Always
Always
NO
ON
ON
ON
Device immediately shuts off boost and current sinks if the voltage at
VOUT is below VUVP(th). This may happen if VOUT is shorted to GND,
or boost diode is open before startup. It will auto-restart once the fault
is removed.
YES
OFF
ON
OFF
Fault occurs if an LED pin voltage exceeds VLEDSC with its current
sink in regulation, while at least one other LED pin is below ~1.2 V.
This may happen when two or more LEDs are shorted within a string.
The LED string exceeding the threshold will then be disabled and
removed from operation. This fault cannot be detected if PWM on-
time is < tLEDSD (5.5 µs max)
Latched
and
Continue
OFF for shorted
string. ON for all
others.
LED String Partial Short
Detection
Always
YES
ON
Fault occurs when the die temperature exceeds the over-temperature
threshold, typically 170°C. IC will restart after temperatures drops
lower by TSDHYS
Overtemperature Protection Auto-restart
Always
Always
YES
NO
OFF
OFF
OFF
OFF
OFF
OFF
Fault occurs when VIN drops below VUVLO(fall), which is 3.9 V max.
This fault resets all latched faults.
VIN UVLO
Auto-restart
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A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Table 6: A80603-1 Fault Mode Table
Fault Flag
Set
Disconnect
Switch
Fault Name
Type
Active
Description
Boost Switch
LED Sink drivers
This fault condition is triggered when the SW current exceeds the
cycle-by-cycle current limit, ISW(LIM).The present SW on-time is
truncated immediately to limit the current. Next switching cycle starts
normally.
Primary Switch Overcurrent
Protection (Cycle-By-Cycle Auto-restart
Current Limit)
Off for a single
cycle
Always
NO
YES
YES
ON
OFF
OFF
ON
When current through boost switch exceeds secondary SW current
limit (iSW(LIM2)) the device immediately shuts down the disconnect
switch, LED drivers and boost. The Fault flag is set. To reset the fault
the EN or PWM pin needs to be pulled low for 16 ms.
Secondary Switch Current
Limit
Latched
Off
Always
Always
OFF
OFF
OFF
OFF
The device is immediately shut off if the voltage
across the input sense resistor is above the
VSENSEtrip threshold. To reset the fault the EN or PWM pin must be
pulled low for 16 ms.
Input Disconnect Current
Limit
Latched
Off
Secondary overvoltage protection is used for open diode detection.
When diode D1 opens, the SW pin voltage will increase until
VOVP(SEC) is reached . This fault latches the IC. The input disconnect
switch and LED drivers are disabled. To reset the fault the EN or
PWM pin needs to be pulled low for 16 ms.
Latched
Off
Secondary OVP
LEDx Pin Shorted to GND
LEDx Pin Open
Always
Startup
YES
NO *
NO *
OFF
OFF
ON
OFF
ON
OFF
OFF
If any of the LED pins is determined to be shorted to GND when PWM
first goes high, soft-start process is halted. Only when the short is
removed, then soft-start is allowed to proceed.
Auto-restart
Auto-restart
If an LED string is not getting enough current, the device will first
respond by increasing the output voltage until OVP is reached. Any
LED string that is still not in regulation will be disabled. The device will
then go back to normal operation by reducing the output voltage to
the appropriate voltage level.
OFF for open
pins.
ON for all others.
Normal
operation
ON
Fault occurs when the ISET current goes above 150% of max current.
The boost will stop switching and the IC will disable the LED sinks
until the fault is removed. When the fault is removed, the IC will try to
regulate to the preset LED current.
ISET Short Protection
Auto-restart
Auto-restart
Always
Always
YES
YES
OFF
OFF
ON
OFF
OFF
Fault occurs when the FSET current goes above 150% of max
current. The boost will stop switching, Disconnect switch will turn off
and the IC will disable the LED sinks until the fault is removed. When
the fault is removed, the IC will try to restart with soft-start.
FSET/SYNC Short
Protection
OFF
Fault occurs when current into OVP pin exceeds iOVP(th) (typically
150 µA). The IC will immediately stop switching but keep the LED
drivers active, to drain down the output voltage. Once the output
voltage decreases to ~97% OVP level, the IC will restart switching to
regulate the output current.
STOP during
OVP event.
Overvoltage Protection
Undervoltage Protection
Auto-restart
Auto-restart
Always
Always
NO
ON
ON
ON
Device immediately shuts off boost and current sinks if the voltage at
VOUT is below VUVP(th). This may happen if VOUT is shorted to GND,
or boost diode is open before startup. It will auto-restart once the fault
is removed.
YES
OFF
ON
OFF
Fault occurs if an LED pin voltage exceeds VLEDSC with its current
sink in regulation, while at least one other LED pin is below ~1.2 V.
This may happen when two or more LEDs are shorted within a string.
The LED string exceeding the threshold will then be disabled and
removed from operation. This fault cannot be detected if PWM on-
time is < tLEDSD (5.5 µs max)
OFF for shorted
string. ON for all
others.
LED String Partial Short
Detection
Auto-restart
Always
NO *
ON
Fault occurs when the die temperature exceeds the over-temperature
threshold, typically 170°C. IC will restart after temperatures drops
lower by TSDHYS
Overtemperature Protection Auto-restart
Always
Always
YES
NO
OFF
OFF
OFF
OFF
OFF
OFF
Fault occurs when VIN drops below VUVLO(fall), which is 3.9 V max.
This fault resets all latched faults.
VIN UVLO
Auto-restart
* Indicates different behavior between A80603 and A80603-1.
27
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
A80603 Fault Recovery Mechanism
ꢀꢁ ꢂꢃꢃ
ꢉNꢐH ꢑ
ꢃꢒNꢓUꢃLꢎ
Power ꢀꢁ
ꢂꢃꢄꢄ, ꢅꢆ readyꢇ ꢆAꢈꢉ
ꢁꢀlled Lꢇ ꢊaꢀlt checꢋingꢌ
ꢔꢑꢕꢑnꢒ ꢖꢑaꢒꢗaꢕ ꢇꢅ ꢘꢉꢅꢙ ꢉꢅꢙ ꢇꢅ ꢈꢍꢊaꢗ ꢆaꢇꢈꢉꢊd ꢋaꢌꢍꢇ ꢙꢑꢇꢉ ꢚꢛꢜ
ꢝ
ꢆ
ꢉNꢐH ꢑ
PꢔMꢐL
ꢀꢁ ꢏꢊadꢐ
ꢂCLꢍꢎUꢈ actiꢏe,
ꢊAULꢈꢐLꢌ
ꢉNꢐL
Normal
ꢃꢎUꢈ-ꢆNꢄ Shorted ꢊaꢀlt
ꢊaꢀlt Remoꢏed
ꢎCP
ꢉNꢐH ꢑ PꢔMꢐH
ꢑꢟꢀꢄ
Pin shorted
to ꢆNꢄ ꢕaꢀlt
ꢊAULꢈꢐL
Lꢉꢄ Pin Checꢋ
ꢂꢒn-Use, ꢄisaꢖled, or
Shorted-to-ꢆNꢄꢌ
0
ꢈime-oꢀt withoꢀt ꢕaꢀlts
ꢋAꢞꢆꢔ
ꢚꢛꢜ
ꢊAULꢈꢐH
Soꢕt Start
ꢂꢖoost Sꢔ actiꢏeꢇ Lꢉꢄ
sinꢋsꢐon when PꢔMꢐHꢌ
ꢚ
1ꢗ ms
1ꢗ ms
Soꢕt start ꢕinished
ꢁ
ꢠ
ꢋ
ꢉNꢐH ꢑ
PꢔMꢐL ꢕor
ꢓ1ꢗ ms
A
ꢖ
ꢡ
ꢡꢢꢣꢍanaꢇꢑꢅn ꢅꢃ ꢊꢤꢊnꢇꢘ ꢘ
ꢏꢌnnꢑnꢒ
ꢂꢖoost and Lꢉꢄ sinꢋs
controlled ꢖy PꢔMꢌ
Aꢘ ꢃꢎUꢈ-to-ꢆNꢄ Short ꢕaꢀlt introdꢀced. ꢒC triꢁs inꢁꢀt ꢎCP which is a latched ꢕaꢀlt.
ꢊAULꢈ is then ꢁꢀlled Low and ꢒC stays in Latched mode ꢂCLꢍꢎUꢈ remains aꢏailaꢖleꢌ.
ꢠꢘ Aꢕter PꢔMꢐL ꢕor 1ꢗ ms, ꢒC clears the latched ꢕaꢀlt internally ꢖꢀt ꢊAULꢈ stays Low.
ꢁꢘ ꢒnꢁꢀt ꢎCP is triꢁꢁed again since ꢃꢎUꢈ is still shorted to ꢆNꢄ. So ꢒC retꢀrns to
Latched mode again and ꢊAULꢈ remains Low.
ꢖꢘ PꢔMꢐH and ꢃꢎUꢈ-to-ꢆNꢄ Short ꢕaꢀlt is remoꢏed, ꢖꢀt ꢒC cannot restart since it is
still in Latched mode.
ꢡꢘ Aꢕter PꢔMꢐL ꢕor 1ꢗ ms, ꢒC clears the latched ꢕaꢀlt internally again
ꢋꢘ At the neꢙt PꢔM ꢐH, ꢒC restarts and detected no ꢕaꢀlts, so ꢊAULꢈ ꢕinally goes High
ꢉNꢐL ꢕor
ꢓ1ꢗ ms
ꢕaꢀlt cleared
ꢉNꢐH ꢑ PꢔMꢐL
ꢕor ꢓ1ꢗ ms
ꢄꢅn-ꢍaꢇꢈꢉꢑnꢒ
ꢃaꢌꢍꢇ dꢊꢇꢊꢈꢇꢊd ꢓ
ꢆaꢇꢈꢉꢑnꢒ ꢃaꢌꢍꢇ
dꢊꢇꢊꢈꢇꢊd ꢓ
ꢉNꢐL ꢕor
ꢓ1ꢗ ms
ꢆaꢇꢈꢉꢊd ꢂꢃꢃ
ꢂꢆAꢈꢉ ꢁꢀlled H, ꢖoost
Sꢔ and Lꢉꢄ sinꢋs
disaꢖled, ꢊAULꢈꢐLꢌ
ꢄꢅn-ꢆaꢇꢈꢉꢊd
ꢋaꢌꢍꢇ ꢎꢇaꢇꢊ
* Note: Fault conditions may be detected in any state or during any state transition. Most faults are non-latching, meaning the
IC will auto-restart as soon as the fault is removed. Only the following faults are latching: Input Disconnect Overcurrent, SW
Secondary OCP, and SW Secondary OVP.
Latching faults can only be cleared by:
1. Reset the IC by bring VIN below UVLO,
2. Reset the IC by bring EN=L for >16 ms, or
3. EN=H and PWM=L for >16 ms.
The last method has the advantage that it does not interrupt the CLKOUT signal. In case the fault condition (e.g. VOUT
shorted to GND) is still present when the latching fault is cleared by PWM=L for >16 ms, the IC will trip fault once again and
stay latched off.
28
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
PACKAGE OUTLINE DRAWING
For ꢀeꢁerence ꢂnly ꢃ Not ꢁor Tooling ꢄse
ꢀeference Allegro DWG-2871 (ꢀev. A) or ꢁEDEC MO-220WGGD.
Dimensions in millimeters ꢂ NOT TO SCALE.
Exact case and lead configuration at supplier discretion within limits shown.
0.50
0.30
ꢃ.00 ꢅ0.10
2ꢃ
2ꢃ
0.95
1
2
1
2
A
ꢃ.00 ꢅ0.10
ꢃ.10
2.80
DETAIL A
2.80
ꢃ.10
D
C
2ꢃꢄ
0.75 ꢅ0.05
0.0-0.05
0.08
C
SEATING
PLANE
C PCB Layout Reference View
ꢇ0.05
ꢂ0.07
0.25
0.50 BSC
0.ꢃ0 ꢅ0.10
0.14 REF
0.10 REF
0.20 REF
0.203 REF
0.05 REF
0.05 REF
0.ꢃ0 ꢅ0.10
B
Detail A
ꢇ0.10
ꢂ0.15
2.70
2
1
A
B
Terminal ꢆ1 mark area
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
2ꢃ
C
Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm
from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances;
when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation
(reference EIA/ꢁEDEC Standard ꢁESD51-5)
0.20 REF
ꢇ0.10
ꢂ0.15
2.70
0.10 REF
D
Coplanarity includes exposed thermal pad and terminals
Figure 46: Package ES, 24-Pin 4 mm × 4 mm QFN with Exposed Thermal Pad and Wettable Flank
29
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A80603 and
A80603-1
LED Driver with Pre-Emptive Boost
for Ultra-High Dimming Ratio and Low Output Ripple
Revision History
Number
Date
Description
–
March 4, 2019
Initial release
Copyright 2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
30
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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