ACS37800KMACTR-0305B-SPI [ALLEGRO]
Isolated, Digital Output, Power Monitoring IC;
| 型号： | ACS37800KMACTR-0305B-SPI |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Isolated, Digital Output, Power Monitoring IC 监控 |
| 文件： | 总41页 (文件大小：3451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
DESCRIPTION
FEATURES AND BENEFITS
• Accurate power monitoring for AC and DC applications
• UL 60950-1 (ed. 2) and UL 62368-1 (ed. 1) certified for
reinforced isolation up to 517 VRMS in a single package
• Accurate measurements of active, reactive, and apparent
power, as well as power factor
• Separate RMS and instantaneous measurements for both
voltage and current channels
• Two programmable averaging blocks
TheAllegroACS37800powermonitoringICgreatlysimplifies
the addition of power monitoring to manyAC or DC powered
systems. The sensor may be powered from the same supply
as the system’s MCU, eliminating the need for multiple
power supplies. The device’s construction includes a copper
conduction path that generates a magnetic field proportional
to applied current. The magnetic field is sensed differentially
to reject errors introduced by common mode fields.
• 0.85 mΩ primary conductor resistance for low power loss
and high inrush current withstand capability
• Compatible with floating and non-floating GND
• Dedicated voltage or current zero crossing pin
• Fast, user-programmable overcurrent fault pin (5 µs typ.)
• User-programmable undervoltage and overvoltage RMS
thresholds
• 1 kHz bandwidth
• Current sensing range up to 90 A
• Options for I2C or SPI digital interface protocols
Allegro’s Hall-effect-based, galvanically isolated current
sensing technology achieves reinforced isolation ratings
(4800 VRMS) in a small PCB footprint. These features enable
isolated current sensing without expensive Rogowski coils,
oversizedcurrenttransformers,isolatedoperationalamplifiers,
or the power loss of shunt resistors.
The ACS37800 power monitoring IC offers key power
measurement parameters that can easily be accessed through
its SPI or I2C digital protocol interfaces. Dedicated and
configurable I/O pins for voltage/current zero crossing,
undervoltage and overvoltage reporting, and fast overcurrent
fault detection are available in I2C mode. User configuration
of the IC is available through on-chip EEPROM.
PACKAGE
16-pin SOICW (suffix MA)
The ACS37800 is provided in a small low-profile surface
mountSOIC16wide-bodypackage,islead(Pb)free,andisfully
calibrated prior to shipment from theAllegro factory. Customer
calibration can further increase accuracy in application.
Not to scale
REINFORCED
ISOLATION
N (L)
L (N)
1 MΩ 1 MΩ
MCU
RSENSE
1 MΩ 1 MΩ
GND
1
16
VCC
VINP
VINN
IP+ ACS37800
I2C
Only
2
3
15
14
13
12
11
10
9
IP+
IP+
IP+
IP-
IP-
IP-
IP-
RPULLUP
GND
To User
4
5
6
7
8
VCC
IP
RPULLUP
SDA / MISO
SCL / SCLK
DIO_0 / MOSI
DIO_1 / CS
CB Certificate Number:
US-32210-M1-UL
US-36315-UL
Linear
Regulator
Single Output
Isolated Power
Supply
(Flyꢀack, etc.)
Figure 1: Typical Application
ACS37800-DS
MCO-0001004
November 30, 2020
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
SELECTION GUIDE
Communication
Part Number
VCC(typ) (V)
IPR (A)
TA (°C)
Packing [1]
Protocol
ACS37800KMACTR-015B5-SPI
ACS37800KMACTR-030B3-SPI
ACS37800KMACTR-030B3-I2C
ACS37800KMACTR-090B3-I2C
5
±15
±30
±30
±90
SPI
Tape and reel,
1000 pieces per reel,
3000 pieces per box
3.3
3.3
3.3
–40 to 125
I2C
[1] Contact Allegro for additional packing options.
ACS 37800 K MAC TR
-
015
B
5 - SPI
Communication Protocol
Supply Voltage:
5 – VCC = 5 V
3 – VCC = 3.3 V
Output Directionality:
B – Bidirectional (positive and negative current)
Current Sensing Range (A)
Packing Designator
Package Designator
Operating Temperature Range
5 Digit Part Number
Allegro Current Sensor
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VCC
Notes
Rating
6.5
Units
V
Supply Voltage
Reverse Supply Voltage
Input Voltage
VRCC
–0.5
V
VINP, VINN
VRNP, VRNN
VDIO
VCC + 0.5
–0.5
V
Reverse Input Voltage
Digital I/O Voltage
V
6
V
SPI, I2C, and general purpose I/O
Reverse Digital I/O Voltage
Maximum Continuous Current
Operating Ambient Temperature
Junction Temperature
VRDIO
–0.5
V
ICMAX
TA = 25°C
Range K
60
A
TA
–40 to 125
165
°C
°C
TJ(max)
Storage Temperature
Tstg
–65 to 170
°C
ISOLATION CHARACTERISTICS
Characteristic
Symbol
Notes
Rating
Unit
Agency type-tested for 60 seconds per UL 60950-1
(edition 2) and UL 62368-1 (edition 1); Production tested
at 3000 VRMS for 1 second, in accordance with UL 60950-1
(edition 2) and UL 62368-1 (edition 1)
Dielectric Strength Test Voltage
VISO
4800
VRMS
1480
1047
730
VPK or VDC
VRMS
Maximum approved working voltage for basic (single) isolation
according to UL 60950-1 (edition 2) and UL 62368-1 (edition 1)
Working Voltage for Basic Isolation
VWVBI
VPK or VDC
Maximum approved working voltage for reinforced isolation
according to UL 60950-1 (edition 2) and UL 62368-1 (edition 1)
Working Voltage for Reinforced Isolation
VWVRI
517
7.5
VRMS
mm
Clearance
Creepage
Dcl
Dcr
Minimum distance through air from IP leads to signal leads
Minimum distance along package body from IP leads to signal
leads
7.9
mm
Distance Through Insulation
Comparative Tracking Index
DTI
CTI
Minimum internal distance through insulation
Material Group II
90
μm
400 to 599
V
ESD RATINGS
Characteristic
Symbol
VHBM
Notes
Per JEDEC JS-001
Value
±5
Unit
kV
Human Body Model
Charged Device Model
VCDM
Per JEDEC JS-002
±1
kV
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions [1]
Value Units
Mounted on the Allegro ASEK37800 evaluation board with 750 mm2 of 4
oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4,
with thermal vias connecting the layers. Performance values include the
power consumed by the PCB.
Package Thermal Resistance
(Junction to Ambient)
RθJA
23
5
°C/W
°C/W
Package Thermal Resistance
(Junction to Lead)
RθJL
Mounted on the Allegro ACS37800 evaluation board.
[1] Refer to the Thermal Performance section below.
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
FUNCTIONAL BLOCK DIAGRAM
VCC
DIGITAL SYSTEM
Bandgap
Reference
SDA / MISO
SCL / SCLK
DIO_0 / MOSI
Temperature
Compensation
Logic
2
I C/SPI
Temperature
Sensor
To All
Communication
Subcircuits
EEPROM +
VINP
VINN
Charge Pump
V
ADC
ADC
DIO_1 / CS
I
Metrology
Engine
IP+
Fault Logic
Hall Sensor Array
GND
IP–
PINOUT DIAGRAM AND TERMINAL LIST
Terminal List Table
16 VINP
15 VINN
14 GND
13 VCC
IP+
IP+
IP+
IP+
IP-
1
2
3
4
5
6
7
8
Description
Number
Name
I2C
SPI
1, 2, 3, 4
IP+
IP-
Terminals for current being sensed; fused internally
Terminals for current being sensed; fused internally
5, 6, 7, 8
12 SDA / MISO
9
DIO_1/CS
DIO_0/MOSI
SCL /SCLK
SDA /MISO
VCC
Digital I/O 1
Digital I/O 0
SCL
Chip Select (CS)
MOSI
IP-
11 SCL / SCLK
10
11
12
13
14
15
16
IP-
10 DIO_0 / MOSI
SCLK
IP-
9
DIO_1 / CS
SDA
MISO
Device power supply terminal
Pinout Diagram
GND
Device ground terminal
Negative input voltage (always connect to GND)
Positive input voltage
VINN
VINP
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Table of Contents
Device EEPROM Settings................................................ 19
Voltage Measurement...................................................... 19
Current Measurement...................................................... 20
Configuring the Device for DC Applications ........................... 21
Device EEPROM Settings................................................ 21
Voltage Measurement...................................................... 21
Current Measurement...................................................... 21
RMS and Power Accuracy vs. Operation Point....................... 21
RMS and Power Output Error vs. Applied Input................... 21
15B5 IRMS and Power Error ........................................... 22
30B3 IRMS and Power Error ........................................... 22
90B3 IRMS and Power Error ........................................... 22
Digital Communication........................................................ 23
Communication Interfaces................................................ 23
SPI................................................................................ 23
Registers and EEPROM .................................................. 23
EEPROM Error Checking and Correction (ECC)................. 25
I2C Slave Adressing ........................................................ 25
EEPROM/Shadow Memory Map.......................................... 26
Register Details – EEPROM............................................. 27
Volatile Memory Map....................................................... 32
Register Details – Volatile ................................................ 33
Application Information ....................................................... 38
Thermal Rise vs. Primary Current ..................................... 38
ASEK37800 Evaluation Board Layout................................ 38
Recommended PCB Layout ................................................ 39
Package Outline Drawing.................................................... 40
Features and Benefits........................................................... 1
Description.......................................................................... 1
Package ............................................................................. 1
Typical Application................................................................ 1
Selection Guide ................................................................... 2
Absolute Maximum Ratings................................................... 3
Isolation Characteristics........................................................ 3
ESD Ratings........................................................................ 3
Thermal Characteristics ........................................................ 3
Functional Block Diagram ..................................................... 4
Pinout Diagram and Terminal List........................................... 4
Electrical Characteristics....................................................... 6
15B5 Performance Characteristics ......................................... 8
30B3 Performance Characteristics ......................................... 9
90B3 Performance Characteristics ....................................... 10
I2C Operating Characteristics ...............................................11
SPI Operating Characteristics.............................................. 12
Theory of Operation ........................................................... 13
Introduction.................................................................... 13
Voltage and Current Measurements .................................. 13
Overcurrent Measurement Path........................................ 13
Trim Methods ................................................................. 13
Power Calculations ......................................................... 14
Operational Block Diagram.................................................. 15
Configurable Settings ...................................................... 16
Configuring the DIO Pins (I2C Devices) ............................ 16
Configuring the Device for AC Applications............................ 19
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
COMMON ELECTRICAL CHARACTERISTICS [1]: Valid through the full range of TA and VCC = VCC(typ), unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
ELECTRICAL CHARACTERISTICS
5 V variant
4.5
5
5.5
V
V
Supply Voltage
Supply Current
VCC
3.3 V variant
2.97
3.3
3.63
VCC(min) ≤ VCC ≤ VCC(max), no load on
output pins
ICC
–
12
15
mA
Supply Bypass Capacitor
Power-On Time
CBYPASS VCC to GND recommended
tPO
0.1
–
–
–
–
mA
µs
90
VOLTAGE INPUT BUFFER
Differential Input Range
Dynamic Input Frequency
VOLTAGE CHANNEL ADC
Sample Frequency
ΔVINR
ΔVIN = VINP – VINN(GND)
bypass_n_en = 0
–250
35
–
–
250
300
mV
Hz
fdyn_in
fS_V
–
–
32
16
–
–
–
kHz
bits
Number of Bits
ADCV_B
ADC Fullscale
ADCV_FS ΔVIN = ±250 mV, VINN= GND
–27500
27500
codes
Sensitivity
Sens(V)
ΔVINR(min) < ΔVIN < ΔVINR(max)
–
110
–
LSB / mV
Ratio of change on VCC to change in
offset at DC, 100% ±10% VCC(typ)
codes /
%VCC
PSEV_O
PSEV_S
–7
–0.1
60
–
–
7
0.1
–
Voltage Channel Power Supply Error
Ratio of change on VCC to change in
sensitivity at DC, 100% ±10% VCC(typ)
% / %VCC
Ratio of change on VCC to change in
offset, 10 Hz to 10 kHz, 10% VCC(pk-pk)
PSRRV_O
PSRRV_S
70
75
dB
dB
Voltage Channel Power Supply Rejection
Ratio
Ratio of change on VCC to change in
sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk)
60
–
VOLTAGE CHANNEL
Internal Bandwidth
RMS Noise
BW
NV
–
–
–
1
–
–
–
kHz
mV
%
Input referred
±0.3
±0.2
Linearity Error
ELIN_V
CURRENT CHANNEL
Sample Frequency
Number of Bits
fS_C
–
–
32
16
–
–
–
kHz
bits
ADCI_B
ADC Fullscale
ADCI_FS IP = IPR(min) or IPR(max)
–27500
27500
codes
Ratio of change on VCC to change in
offset at DC, 100% ±10% VCC(nom)
codes /
%VCC
PSEI_O
PSEI_S
–60
–0.3
60
–
–
60
0.3
–
Current Channel Power Supply Error
Ratio of change on VCC to change in
sensitivity at DC, 100% ±10% VCC(nom)
% / %VCC
Ratio of change on VCC to change in
offset, 10 Hz to 10 kHz, 10% VCC(pk-pk)
PSRRI_O
PSRRI_S
65
40
dB
dB
Current Channel Power Supply Rejection
Ratio
Ratio of change on VCC to change in
sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk)
20
–
Internal Bandwidth
BW
RIP
–
–
1
–
–
kHz
Primary Conductor Resistance
TA = 25°C
0.85
mΩ
Continued on next page...
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
COMMON ELECTRICAL CHARACTERISTICS [1] (continued): Valid through the full range of TA and VCC = VCC(typ)
,
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
CURRENT CHANNEL (continued)
RMS Noise
NI
Input referred
–
–
±0.1
±1.5
–
–
A
Linearity Error
ELIN_I
%
OVERCURRENT FAULT CHARACTERISTICS
Time from IP rising above IFAULT until
VFAULT < VFAULT(max) for a current
step from 0 to 1.2 × IFAULT; 10 kΩ and
100 pF from DIO_1 to ground;
fltdly = 0
Fault Response Time
tRF
–
5
–
μs
Internal Bandwidth
BW
–
–
200
0.06 × FS
–
–
–
kHz
A
Fault Hysteresis [2]
IHYST
IFAULT
Fault Range
Set using fault field in EEPROM
0.65 × FS
2.00 × FS
A
VOLTAGE ZERO CROSSING
Voltage Zero-Crossing Delay
DIO PINS
td
–
250
–
µs
DIO Output High Level
VOH(DIO) VCC = 3.3 V
VOL(DIO) VCC = 3.3 V
3
–
–
–
–
–
–
–
–
0.3
–
V
V
V
V
V
V
DIO Output Low Level
DIO Input Voltage for Address Selection 0
DIO Input Voltage for Address Selection 1
DIO Input Voltage for Address Selection 2
DIO Input Voltage for Address Selection 3
VADD0
VADD1
VADD2
VADD3
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
0
1.1
2.2
3.3
–
–
–
[1] Device may be operated at higher primary current levels (IP), ambient temperatures (TA), and internal leadframe temperatures, provided that the maximum junction
temperature (TJ(max)) is not exceeded.
[2] After IP goes above IFAULT, tripping the internal fault comparator, IP must go below IFAULT – IHYST before the internal fault comparator will reset.
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
ACS37800KMAC-015B5 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range,
TA = –40°C to 125°C, CBYPASS = 0.1 µF, and VCC = 5 V, unless otherwise specified
Characteristic
GENERAL CHARACTERISTICS
Nominal Supply Voltage
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
VCC(typ)
–
5
–
V
NOMINAL PERFORMANCE – FACTORY CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
–15
–
–
15
–
A
Sens(I)
IPR(min) < IP < IPR(max)
1833.3
LSB/A
NOMINAL PERFORMANCE – INPUT REFERRED FACTORY POWER (POWER SEEN BY THE DEVICE) [2]
Active Power Sensitivity
Imaginary Power Sensitivity
Apparent Power Sensitivity
SensPd_act
SensPd_img
SensPd_app
–
–
–
6.15
12.31
12.31
–
–
–
LSB/mW
LSB/mVAR
LSB/mVA
TOTAL OUTPUT ERROR COMPONENTS [3] – CURRENT CHANNEL
Measured at IP = IPR(max), TA = 25°C to 125°C
Measured at IP = IPR(max), TA = –40°C to 25°C
IP = 0 A, TA = 25°C to 125°C
–
–
–
–
–
–
±1.1
±1.5
±720
±780
±2.1
±2.7
–
–
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(I)
LSB
LSB
%
EO(I)
IP = 0 A, TA = –40°C to 25°C
Measured at IP = IPR(max), TA = 25°C to 125°C
Measured at IP = IPR(max), TA = –40°C to 25°C
Total Output Error
ETOT(I)
%
TOTAL OUTPUT ERROR COMPONENTS [3] – VOLTAGE CHANNEL
Measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
,
–
–
±1.2
±1.2
–
–
%
%
Sensitivity Error
Offset Error
ESENS(V)
Measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
ΔVIN = 0 mV, TA = 25°C to 125°C
ΔVIN = 0 mV, TA = –40°C to 25°C
–
–
±55
±55
–
–
LSB
LSB
EO(V)
Measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
–
–
±1.4
±1.4
–
–
%
%
Total Output Error
ETOT(V)
Measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
,
ACCURACY PERFORMANCE – ACTIVE POWER
IP = IPR(max), measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
,
–
–
±2.1
±3
–
–
%
%
Total Output Error
ETOT(P)
IP = IPR(max), measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
[1] Typical values are mean ±3 sigma.
[2] These sensitivity characteristics are referred to the inputs seen by the device, i.e. the voltage channel resistor divider must be accounted to determine the system sensi-
tivies.
[3] E
= E
+ 100 x V /(Sens x I )
TOT
SENS
OE P
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
ACS37800KMAC-030B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range,
TA = –40°C to 125°C, CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specified
Characteristic
GENERAL CHARACTERISTICS
Nominal Supply Voltage
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
VCC(typ)
–
3.3
–
V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
–30
–
–
30
–
A
Sens(I)
IPR(min) < IP < IPR(max)
916.7
LSB/A
NOMINAL PERFORMANCE – INPUT REFERRED FACTORY POWER (POWER SEEN BY THE DEVICE) [2]
Active Power Sensitivity
Imaginary Power Sensitivity
Apparent Power Sensitivity
SensPd_act
SensPd_img
SensPd_app
–
–
–
3.08
6.15
6.15
–
–
–
LSB/mW
LSB/mVAR
LSB/mVA
TOTAL OUTPUT ERROR COMPONENTS [3] – CURRENT CHANNEL
Measured at IP = IPR(max), TA = 25°C to 125°C
Measured at IP = IPR(max), TA = –40°C to 25°C
IP = 0 A, TA = 25°C to 125°C
–
–
–
–
–
–
±1
–
–
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(I)
±1.5
±510
±570
±2
LSB
LSB
%
EO(I)
IP = 0 A, TA = –40°C to 25°C
Measured at IP = IPR(max), TA = 25°C to 125°C
Measured at IP = IPR(max), TA = –40°C to 25°C
Total Output Error
ETOT(I)
±2.7
%
TOTAL OUTPUT ERROR COMPONENTS [3] – VOLTAGE CHANNEL
Measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
,
–
–
±0.75
±0.75
–
–
%
%
Sensitivity Error
Offset Error
ESENS(V)
Measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
ΔVIN = 0 mV, TA = 25°C to 125°C
ΔVIN = 0 mV, TA = –40°C to 25°C
–
–
±55
±55
–
–
LSB
LSB
EO(V)
Measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
–
–
±1
±1
–
–
%
%
Total Output Error
ETOT(V)
Measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
,
ACCURACY PERFORMANCE – ACTIVE POWER
IP = IPR(max), measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
,
–
–
±2.1
±3
–
–
%
%
Total Output Error
ETOT(P)
IP = IPR(max), measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
[1] Typical values are mean ±3 sigma.
[2] These sensitivity characteristics are referred to the inputs seen by the device, i.e. the voltage channel resistor divider must be accounted to determine the system sensi-
tivies.
[3] E
= E
+ 100 x V /(Sens x I )
TOT
SENS
OE P
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
ACS37800KMAC-090B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range,
TA = –40°C to 125°C, CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specified
Characteristic
GENERAL CHARACTERISTICS
Nominal Supply Voltage
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
VCC(typ)
–
3.3
–
V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
–90
–
–
90
–
A
Sens(I)
IPR(min) < IP < IPR(max)
305.6
LSB/A
NOMINAL PERFORMANCE – INPUT REFERRED FACTORY POWER (POWER SEEN BY THE DEVICE) [2]
Active Power Sensitivity
Imaginary Power Sensitivity
Apparent Power Sensitivity
SensPd_act
SensPd_img
SensPd_app
–
–
–
1.03
2.05
2.05
–
–
–
LSB/mW
LSB/mVAR
LSB/mVA
TOTAL OUTPUT ERROR COMPONENTS [3] – CURRENT CHANNEL
Measured at IP = IPR(max), TA = 25°C to 125°C
Measured at IP = IPR(max), TA = –40°C to 25°C
IP = 0 A, TA = 25°C to 125°C
–
–
–
–
–
–
±1
–
–
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(I)
±1.5
±180
±210
±2
LSB
LSB
%
EO(I)
IP = 0 A, TA = –40°C to 25°C
Measured at IP = 45 A, TA = 25°C to 125°C
Measured at IP = 45 A, TA = –40°C to 25°C
Total Output Error
ETOT(I)
±2.6
%
TOTAL OUTPUT ERROR COMPONENTS [3] – VOLTAGE CHANNEL
Measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
,
–
–
±0.75
±0.75
–
–
%
%
Sensitivity Error
Offset Error
ESENS(V)
Measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
ΔVIN = 0 mV, TA = 25°C to 125°C
ΔVIN = 0 mV, TA = –40°C to 25°C
–
–
±55
±55
–
–
LSB
LSB
EO(V)
Measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
–
–
±1
±1
–
–
%
%
Total Output Error
ETOT(V)
Measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
,
ACCURACY PERFORMANCE – ACTIVE POWER
IP = 45 A, measured at ΔVIN = ΔVINR(max)
TA = 25°C to 125°C
,
,
–
–
±1.3
±2.1
–
–
%
%
Total Output Error
ETOT(P)
IP = 45 A, measured at ΔVIN = ΔVINR(max)
TA = –40°C to 25°C
[1] Typical values are mean ±3 sigma.
[2] These sensitivity characteristics are referred to the inputs seen by the device, i.e. the voltage channel resistor divider must be accounted to determine the system sensi-
tivies.
[3] E
= E
+ 100 x V /(Sens x I )
TOT
SENS
OE P
10
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
xKMACTR-I2C OPERATING CHARACTERISTICS [1]: Valid through the full range of TA, VCC = VCC(typ), REXT = 10 kΩ,
unless otherwise specified
Characteristic
I2C INTERFACE CHARACTERISTICS [2]
Bus Free Time Between Stop and Start
Hold Time Start Condition
Setup Time for Repeated Start Condition
SCL Low Time
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
tBUF
thdSTA
tsuSTA
tLOW
tHIGH
tsuDAT
thdDAT
tsuSTO
VIL
1.3
0.6
0.6
1.3
0.6
100
0
–
–
–
–
–
–
–
–
–
–
–
µs
µs
–
µs
–
µs
SCL High Time
–
µs
Data Setup Time
–
µs
Data Hold Time
900
–
µs
Setup Time for Stop Condition
Logic Input Low Level (SDA, SCL pins)
Logic Input High Level (SDA, SCL pins)
Logic Input Current
0.6
–
µs
30
–
%VCC
%VCC
µA
VIH
70
–1
–
–
–
–
–
IIN
Input voltage on SDA or SCL = 0 V to VCC
SDA sinking = 1.5 mA
1
Output Low Voltage (SDA)
Clock Frequency (SCL pin)
Output Fall Time (SDA pin)
I2C Pull-Up Resistance
VOL
0.36
400
250
–
V
fCLK
–
kHz
ns
tf
REXT = 2.4 kΩ, CB = 100 pF
–
–
REXT
2.4
10
kΩ
Total Capacitive Load for Each of SDA and
SCL Buses
CB
–
–
20
pF
[1] Validated by characterization and design.
[2] These values are ratiometric to the supply voltage. I2C Interface Characteristics are ensured by design and not factory tested.
tsuDAT
tsuSTA thdSTA
tBUF
thdDAT
tsuSTO
SDA
SCL
tLOW
tHIGH
Figure 2: I2C Interface Timing
11
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
xKMATR-SPI OPERATING CHARACTERISTICS [1]: Valid through the full range of TA, VCC = VCC(typ), unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SPI INTERFACE CHARACTERISTICS
MOSI, SCLK, CS pins, VCC = 3.3 V
MOSI, SCLK, CS pins, VCC = 5 V
MOSI, SCLK, CS pins
2.8
4
–
–
–
3.63
5.5
V
V
V
Digital Input High Voltage
Digital Input Low Voltage
VIH
VIL
–
0.5
MISO pin, CL = 20 pF, TA = 25°C,
VCC(typ) = 3.3 V
2.8
4
3.3
5
3.8
5.5
V
V
SPI Output High Voltage
VOH
MISO pin, CL = 20 pF, TA = 25°C,
VCC(typ) = 5 V
SPI Output Low Voltage
SPI Clock Frequency
SPI Frame Rate
VOL
fSCLK
tSPI
MISO pin, CL = 20 pF, TA = 25°C
MISO pin, CL = 20 pF
–
0.3
–
0.5
10
V
0.1
5.8
MHz
kHz
–
588
Time from CS going low to SCLK falling
edge
Chip Select to First SCLK Edge
tCS
50
–
–
ns
Data Output Valid Time
MOSI Setup Time
MOSI Hold Time
tDAV
tSU
Data output valid after SCLK falling edge
Input setup time before SCLK rising edge
Input hold time after SCLK rising edge
–
40
–
–
–
–
ns
ns
ns
25
50
tHD
–
Hold SCLK high time before CS rising
edge
SCLK to CS Hold Time
tCHD
CL
5
–
–
–
–
ns
Load Capacitance
Loading on digital output (MISO) pin
20
pF
[1] Validated by characterization and design.
Figure 3: SPI Timing
12
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
THEORY OF OPERATION
current and voltage measurements are stored in the icodes and
vcodes fields. The instantaneous apparent power, which is the
product of icodes and vcodes, is stored in the field pinstant.
Introduction
The ACS37800 provides a simple solution for voltage, current,
and power monitoring in 60 Hz AC and DC applications and is
particularly well suited for high isolation. The voltage is mea-
sured by resistor dividing it down to fit the input range of the
on-board voltage sense amplifier, as well as to add isolation.
The current is measured using the integrated current loop and
galvanically isolated Hall sensor. Both analog signals are then
sampled using high accuracy ADCs before entering the digital
system. Here, the metrology engine is used to determine fre-
quency, calculate RMS values of current, voltage, and power, as
well as provide a range of averaging and configuration options.
One can choose to read out all the different information provided
using SPI or I2C. When using I2C, there are also options for
using some of the digital I/O pins for overcurrent or zero cross-
ing detection. Overall, with a high degree of configurability and
integrated features, the ACS37800 can fit most power monitoring
applications. The following sections will help explain in more
detail these features and configuration options, as well as how to
best use the ACS37800 for particular applications.
Overcurrent Measurement Path
A separate filter on the current ADC is used to create a lower
resolution but higher bandwidth sample rate measurement of the
current to be used for overcurrent detection. This filter outputs a
12-bit word at a 1 MHz update rate and 200 kHz bandwidth. The
overcurrent fault logic compares this auxiliary current value to the
user-defined overcurrent fault threshold, defined by the field fault.
It is important to note that the trim for the main 16-bit current path
is also applied to the overcurrent path, such that the overcurrent
fault has the same level of accuracy as the main signal path.
Trim Methods
The trim logic for the voltage and current channels is depicted in
Figure 4 and Figure 5. Refer to the Register Details section for
more information regarding trim fields. In general, each chan-
nel, voltage and current, is trimmed for gain and offset both at
room and over temperature. This trim is done before the icodes
and vcodes registers. The user has the ability to trim the nominal
room temperature value.
Voltage and Current Measurements
The main signal paths for the current and voltage measurement,
through the ADCs and internal filtering, have a bandwidth of
1 kHz and an update rate of 32 kHz. These “instantaneous”
Gain Trim
Delay
Offset Trim
Satura�on
adc_out_v
Z-x
+
+
vcodes
VchanGainSel
ichan_del_en
vchan_offset_code
+
+
Factory
Trim
chan_del_sel
vqvo_tc
Figure 4: Voltage Channel Trim Flow
Delay
Offset Trim
Gain Trim
Satura�on
adc_out_i
Z-x
+
+
icodes
ichan_del_en
qvo_fine
+
+
sns_fine
qvo_tc
chan_del_sel
Factory
Trim
sns_tc
Figure 5: Current Channel Trim Flow
13
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
POWER FACTOR
Power Calculations
The magnitude of the ratio of the real power to apparent power,
calculated at the end of each cycle is:
VOLTAGE ZERO CROSSING
The RMS and power calculations of the ACS37800 are calcu-
lated over a window of N samples. By default, this window is
calculated dynamically based on the zero crossings of the voltage
signal. A rising voltage zero crossing triggers the start of a new
window. N then increases with each 32 kHz sample until the next
rising voltage zero crossing, recording the current and voltage
readings at each sample. This ends the calculation window, and
all RMS and power calculations are performed on the saved data.
During this time, the next calculation window is started.
PACTIVE
|PF| =
|S|
LEADING OR LAGGING POWER FACTOR
The current leading or lagging the voltage is communicated as a
single bit, posangle. This bit represents the sign of the reactive
power. The sign of the reactive power is determined by compar-
ing the timing of the zero crossings of the current and voltage. As
such, it is only meaningful in the case of a linear load.
Voltage zero crossings are detected with time-based hysteresis
that removes the possibility of noise causing multiple zero cross-
ings to be reported at each true zero crossing.
The sign of the reactive power, posangle, along with the sign of
the power factor, pospf, can be used to determine whether the
load is inductive or capacitive, as well as whether power is being
generated or consumed. This is shown in the four-quadrant figure
below (refer to Figure 6).
IRMS AND VRMS
The cycle-by-cycle calculation of the root mean square of both
the current and voltage channels is:
n = N – 1 In
∑
n = N – 1Vn
2
2
∑
n = 0
n = 0
POSPF = 0
POSANG = 0
POSPF = 1
POSANG = 1
IRMS
=
VRMS =
N
N
Capacitive and
Generating
Inductive and
Consuming
where In (icodes) and Vn (vcodes) are the instantaneous measure-
ments of current and voltage, respectively.
Lagging
Leading
Real
APPARENT POWER
The magnitude of the complex power being measured; calculated
at the end of each cycle is:
POSPF = 0
POSANG = 1
POSPF = 1
POSANG = 0
|S| = IRMS × VRMS
Inductive and
Generating
Capacitive and
Consuming
ACTIVE POWER
The real component of power being measured, calculated cycle
by cycle is:
Figure 6: Four Quadrant, Power Factor
∑
n = N – 1 Pn
n = 0
PACTIVE
=
Pn = In × Vn
N
REACTIVE POWER
The imaginary component of power being measured, calculated
at the end of each cycle is:
ꢀ ꢄ ꢂ 2 ꢅ ꢃ 2
2
ꢀ ꢁ ꢂ2 ꢃ ꢄꢅCꢆIꢇꢈ
Ф
Actiꢁe Power, ꢂ = ꢁI cosФ
Figure 7: Power Triangle
14
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
OPERATIONAL BLOCK DIAGRAM
Voltage and
Current
Measurement
Factory Trimmed
RSENSE
Voltage
VLINE
ADC
ΣRISO + RSENSE
vcodes
Channel
Delay
Control
Digital
Filter
Temperature
Compensation
icodes
IP+
Overcurrent
Fault
Comparator
fault out
IP–
Current
ADC
fault
RMS, and Power
Calculation
Voltage Zero
Crossing
Zero
Crossing
Flag
vrms
irms
vcodes
RMS
and
Power
pospf
X
pinstant
icodes
posangle
Calculations
papparent
pactive
pimag
Averaging and
VRMS Flagging
ovrms
uvrms
O/UVRMS
Flag
vrms
0
vrmsavgonesec
vrmsavgonemin
pactiveavgonesec
pactiveavgonemin
irmsavgonesec
irmsavgonemin
1
irms
iavgselen
Averaging
0
1
pactive
pavgselen
Register
Output
Operation
Control
Voltage data
Current data
FAULT data
Power data
Figure 8: Operational Block Diagram
15
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
When bypass_n_en = 1, it is important to define the number of
Configurable Settings
samples used to calculate RMS. This can be done in the field
n. The field n is the number of 32 kHz samples that are used to
calculate the RMS. The minimum effective n that is used when
calculating RMS is 4. If a value of less than 4 is chosen for n,
then 4 is internally used. The first useable RMS calculation on
start up with bypass_n_en = 1 is after 2 × n samples.
PHASE DELAY
Phase delay may be introduced on either the voltage or current
channel to account for known phase delay at other points in the
system using the ichan_del_en and chan_ del_sel fields. ichan_
del_en determines if the voltage channel or current channel will
be delayed. The chosen channel will be delayed by the configured
amount in chan_del_sel, up to 5° of delay.
Configuring the DIO Pins (I2C Devices)
AVERAGING CHANNEL
FLAGS TO BE ROUTED TO THE DIO PINS
The ACS37800 contains two averaging paths. VRMS, IRMS, and
PACTIVE can be routed to these average blocks as shown in Figure 8
using iavgselen and pavgselen.
When the device is configured to be in I2C mode (comm_sel in
EEPROM = 1), pins 9 and 10 become digital I/O pins, DIO_1
and DIO_0, respectively. The digital I/O pins are low true, mean-
ing that a voltage below the DIO Output Low Level maximum
(VOL(DIO)max) is to be interpreted as logic 1 and a voltage above
DIO Output High Level minimum (VOH(DIO)min) is to be inter-
preted as a logic 0. The Digital I/O pins can be configured in
EEPROM to represent the following functions:
AVERAGING TIME
Each averaging path on the ACS37800 consists of two averag-
ing blocks that each allow for a configurable number of averages
based on the EEPROM fields rms_avg_1 and rms_avg_2.
The output of the first averaging block feeds into the input of the
second averaging block. The output of each block is accessible
for each channel.
DIO_O
dio_0_sel value (EEPROM)
Function
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
FOR VRMS
0
1
2
ZC: zero crossing
ovrms: the VRMS overvoltage flag
uvrms: The VRMS undervoltage flag
This device has programmable overvoltage and undervoltage
RMS flags that will signal when the vrms is above or below the
respective thresholds. The vrms is compared to the overvoltage
and undervoltage RMS thresholds set by the fields overvreg and
undervreg to determine a flag condition. The number of suc-
cessive sample sets required to trigger either the overvoltage or
undervoltage RMS flag can be set by the vevent_cycs field.
The OR of ovrms and uvrms (if either flag is
triggered, the DIO_0 pin will be asserted)
3
ZC
DIO_0
OVRMS
UVRMS
DIO_0 / MOSI
MOSI
DIO_0_Sel[0..1]
Comm_Sel
The ovrms and uvrms flags can be routed to the DIO pins when
the device is used in I2C mode. See Configuring the DIO Pins.
DIO_1
OVERCURRRENT DETECTION FOR INSTANTA-
NEOUS CURRENT
dio_1_sel value (EEPROM)
Function
OCF: Overcurrent fault
0
1
2
The overcurrent fault threshold may be set from 0.65 × IPR to
2.0 × IPR. The user sets the trip point with the field fault. The
user can add a digital delay to the overcurrent fault with the field
flt_dly. Up to 32 µs delay can be added to the overcurrent fault.
uvrms: The VRMS undervoltage flag
ovrms: The VRMS overvoltage flag
The OR of ovrms and uvrms, and OCF_LAT [Latched
Overcurrent Fault] (if any of the three flags are
triggered, the DIO_1 pin will be asserted)
3
BYPASSING THE DYNAMIC FRAMING OF THE RMS
CALCULATION WINDOW
OCF
DIO_1
By default, the ACS37800 dynamically calculates the value of
N to be used in the RMS and power calculations based on the
zero crossings on the voltage channel. This functionality can be
disabled using the bypass_n_en field.
UVRMS
OVRMS
OCF_LAT
DIO_1 / CS
CS
DIO_1_Sel[0..1]
Comm_Sel
16
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
ZERO CROSSING OUTPUT CONFIGURATIONS
The dynamic calculation of N for the RMS and power calcula-
tions uses exclusively the voltage zero crossing, but both current
and voltage zero crossing can be flagged and reported on the DIO
pins.
Voltage Zero Crossing (VZC)
The voltage zero crossing has two basic modes of operation,
pulse mode and square wave mode.
Pulse Mode – VZC
In pulse mode, a voltage zero crossing is reported as a short
pulse. There are three available configurations to customize the
voltage zero crossing pulse mode operation: rising or falling edge
selection, every edge selection, and pulse width.
Figure 10: zerocrossedgesel = 1, Rising Zero Crossing
Pulse Every Edge
Rising Edge or Falling Edge Aligned Pulse
The EEPROM field halfcycle_en is used to output a pulse at
every zero crossing.
The EEPROM field zerocrossedgesel is used to select whether
the zero crossing output pulses are aligned to the rising zero
crossing of the voltage channel or the falling zero crossing of the
voltage channel.
Figure 11: halfcycle_en = 1, Both Rising and Falling
Zero Crossings Signaled
Figure 9: zerocrossedgesel = 0, Falling Zero Crossing
Pulse Width Selection
The EEPROM field delaycnt_sel is used to select the width of the
voltage zero crossing pulse.
Table 1: delaycnt_sel
Range
Value
32
Units
µs
0
1
256
µs
17
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
The current zero crossing has just one basic mode of operation:
pulse mode.
Square Wave Mode
Square wave mode can be configured using the EEPROM field
squarewave_en. In square wave mode, a voltage zero crossing
is reported as a square wave that changes state on each reported
zero crossing. The zerocrossedgesel EEPROM field can be used
to align the low to high transition of the flag with either the rising
voltage zero crossing or the falling voltage zero crossing.
Pulse Mode – CZC
In pulse mode, a current zero crossing is reported as a short
pulse. There are three available configurations to customize the
current zero crossing pulse mode operation: rising or falling edge
selection, every edge selection, and pulse width.
Rising Edge or Falling Edge Aligned Pulse
The EEPROM field zerocrossedgesel is used to select whether
the zero crossing output pulses are aligned to the rising zero
crossing of the current channel or the falling zero crossing of the
current channel.
Figure 12: zerocrossedgesel = 0, Square Wave Mode
Figure 14: zerocrossedgesel = 0, Falling Zero Crossing
Figure 13: zerocrossedgesel = 1, Square Wave Mode
Current Zero Crossing (CZC)
The current zero crossing function can be enabled using the
EEPROM field zerocrosschansel. When the zero crossing flag
is configured to flag zero crossings of the current path, this has
no effect on the RMS and power calculations; the voltage zero
crossing is still used for these calculations.
Figure 15: zerocrossedgesel = 1, Rising Zero crossing
18
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Pulse Every Edge
The EEPROM field halfcycle_en is used to output a pulse at
every zero crossing.
Figure 16: halfcycle_en = 1, Both Rising and Falling
Zero Crossings Signaled
CONFIGURING THE DEVICE FOR AC APPLICATIONS
form a resistor divider network where,
Device EEPROM Settings
For AC power monitoring applications using the ACS37800, the
following device settings are recommended:
ꢅꢆꢄꢂꢆꢄ
ꢀ
ꢁꢂ
= ꢀ
∗
ꢃꢁꢂꢄ
ꢅꢁꢆꢇ1 + ꢅꢁꢆꢇ2 + ꢅꢆꢄꢂꢆꢄ
DYNAMIC CALCULATION OF N
RISO1 and RISO2 should be equal. A value of 1 MΩ is appropriate
for many applications, but ultimately, the resistance value used
needs to comply with the required isolation of the system.
Set bypass_n_en = 0 (default). This setting enables the device to
dynamically calculate N based off the voltage zero crossings. See
the Register Details – EEPROM section for additional details.
RISO1
RISO2
Voltage Measurement
VINP
1 MΩ
1 MΩ
RECOMMENDED APPLICATION CIRCUITS
An important aspect to consider when designing in the
RSENSE
ACS37800 into AC applications is the design of the voltage mea-
surement path. Typically, a resistor divider network is employed
to provide both isolation and transform the high voltage signal
into the ±250 mV signal that the ACS37800 can measure.
Vin
VINN
There are two basic application circuits recommended based on
the isolation requirements of the system. The first, see Figure 17,
is to be used when the ACS37800 GND and the neutral terminal
of the voltage input are connected. RISO1, RISO2, and RSENSE
Figure 17: Voltage Channel Application Circuit; Device
GND is Connected to Neutral
19
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Another application circuit recommendation for the voltage chan- Additionally, the tolerance of the all resistors should be consid-
nel is shown in Figure 18. This is to be used in systems where ered when determining RSENSE. The minimum tolerance of the
the ACS37800 GND and the neutral terminal of the voltage input isolation resistors should be used along with the maximum toler-
are to be isolated. Here, RISO3 and RISO4 are added to the resistor
divider network.
ance of RSENSE.
If the RSENSE is not sized appropriately, this can lead to the
voltage input to the ACS38700 exceeding the maximum input
range, which can cause the instantaneous voltage measurement to
saturate. This can lead to errors in the RMS calculations as shown
in Figure 19.
ꢅꢆꢄꢂꢆꢄ
ꢀ
= ꢀ
∗
ꢁꢂ
ꢃꢁ ꢂꢄ
ꢅꢁꢆꢇ1 + ꢅꢁꢆꢇ2 + ꢅꢁꢆꢇ3 + ꢅꢁꢆꢇ4 + ꢅꢆꢄꢂꢆꢄ
RISO1, RISO2, RISO3, and RISO4 should be equal and their value is
determined by the isolation requirements of the system. A value
of 1 MΩ is appropriate for many applications, but ultimately, the
resistance value used needs to comply with the required isolation
of the system.
Input > Fullscale
Output Saturation
RISO1
RISO2
VINP
1 MΩ
1 MΩ
Input Waveform
RSENSE
Output Readpoints
Vin
Absolute Output
Readpoints
RISO3
RISO4
VINN
1 MΩ
1 MΩ
Figure 19: Output Saturation
Figure 18: Voltage Channel Application; Device GND is
Current Measurement
Isolated from Neutral
For the current path, there are two current ranges to consider: the
range of RMS current to be measured and the range required for
overcurrent fault detection.
To determine the value of RSENSE required for a particular appli-
cation using either of the recommended circuits, the following
equation can be used:
When considering the range of RMS current to be measured, the
Current Sensing Range (IPR) is not to be exceeded. This can lead
to saturation, as shown in Figure 19, and lead to error in the RMS
calculations.
∆ꢄ
(
)
ꢅꢃꢆ ꢇꢈꢉ
ꢀꢁꢂꢃꢁꢂ
=
∗ ꢀꢅꢁꢋ
ꢄ
) − ∆ꢄ
(
(
)
ꢊꢅꢃꢂ ꢇꢈꢉ
ꢅꢃꢆ ꢇꢈꢉ
Where ΔVINR(MAX) = 250 mV, VLINE(MAX) is the maximum VLINE
voltage to be measured, and RISO is the sum of all of the isolation
resistors.
The overcurrent fault detection can exceed IPR and is defined as
Fault Range Max, IFAULT(MAX). Once the current exceeds IPR, the
RMS calculations will no longer be accurate.
If using the overvoltage detection functionality of the ACS37800,
this should be considering when determining the maximum VLINE
voltage to be measured. For example, in an application when
the nominal VLINE is equal to 120 VRMS and a 50% over-voltage
detection is required, VLINE(MAX) is:
120 VRMS × √2 × 1.5 = 255 V,
where the √2 is used to approximate the peak voltage assuming a
sinusoidal input.
20
Allegro MicroSystems
955 Perimeter Road
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
CONFIGURING THE DEVICE FOR DC APPLICATIONS
OR FOR APPLICATIONS WITH NO VOLTAGE ZERO CROSSING
The follow recommendations are provided for DC applications,
value, which is set using EERPOM field n. See the Register
as well as any other applications where there is no voltage zero
crossing. Possible applications include current sensing only,
sensing of a rectified voltage signal, or applications where the
nominal frequency on the voltage channel is greater than 300 Hz.
Details – EEPROM section for additional details.
Voltage Measurement
RECOMMENDED APPLICATION CIRCUITS
Device EEPROM Settings
The recommended application circuit for the voltage channel in
DC operation is the same as the AC application circuit where
Device GND is connected to Neutral (refer to Figure 17).
For DC power monitoring applications using the ACS37800 or
applications only using the current measurement capability of the
ACS37800, the following device settings are recommended.
Current Measurement
FIXED SETTING OF N
The same considerations for AC applications can be used for the
current path for DC applications.
Set bypass_n_en = 1. This setting disables the dynamic calcula-
tion of n based off voltage zero crossings and sets n to a fixed
RMS AND POWER ACCURACY VS. OPERATION POINT
RMS and Power Output Error vs. Applied
Input
When using the ACS37800 to measure for RMS calculations and
power monitoring, it is important to consider the error specifica-
tions of the device.
For DC applications, the impact of offset and gain error on the
final output is straightforward, but for RMS and power calcula-
tions, the impact of any errors, specifically offset errors, becomes
dependent on the magnitude of the applied signal.
Figure 20 shows an example system where the maximum measur-
able power is ~1.3 kW, based on the system design. The over-
temperature offset performance of the ACS37800 causes an error
in the measured power that is larger when the applied power is
close to 0 W.
Figure 20: Measured Line Power [W] vs. Applied Line
Power, 15B5 Device
The offset performance of the voltage channel is such that its
contribution to this error is negligible. The current RMS measure-
ment and the power calculations are where this error is observed.
The following figures (Figure 21 through Figure 26) display the
measurement error for the RMS current and active power for
each available device variant.
21
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
15B5 I
and Power Error
RMS
°
°
°
°
°
°
Figure 21: I
Error [A] vs. Applied I
Figure 22: Line Power Error [W] vs. Applied Line Power [W]
RMS
RMS [A]
30B3 I
and Power Error
RMS
°
°
°
°
°
°
Figure 24: Line Power Error [W] vs. Applied Line Power
[W]
Figure 23: I
Error [A] vs. Applied I
RMS [A]
RMS
90B3 I
and Power Error
RMS
°
°
°
°
°
°
Figure 25: I
RMS
Error [A] vs. Applied I
Figure 26: Line Power Error [W] vs. Applied Line Power [W]
RMS [A]
22
Allegro MicroSystems
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
DIGITAL COMMUNICATION
Communication Interfaces
Registers and EEPROM
The ACS37800 supports communication over 1 MHz I2C and
10 MHz SPI. However, the communication protocol is fixed dur-
ing factory programming. The ACS37800 MISO pin continues to
drive the MISO line when CS goes high. This may prevent other
devices from communicating properly. It is recommended that the
ACS37800 be the only device on the SPI bus if using SPI com-
munication.
WRITE ACCESS
The ACS37800 supports factory and customer EEPROM space as
well as volatile registers. The customer access code must be sent
prior to writing these customer EEPROM spaces. In addition, the
device includes a set of free space EEPROM registers that are
accessible with or without writing the access code.
READ ACCESS
SPI
All EEPROM and volatile registers may be read at any time
regardless of the access code.
The SPI frame consists of:
• The Master writes on the MOSI line the 7-bit address of the
register to be read from or written to.
EEPROM
• The next bit on the MOSI line is the read/write (RW) indicator. At power up, all shadow registers are loaded from EEPROM,
A high state indicates a Read and a low state indicates a Write. including all configuration parameters. The shadow registers can
be written to in order to change the device behavior without hav-
• The device sends a 32-bit response on the MISO line. The
ing to perform an EEPROM write. Any changes made in shadow
contents correspond to the previous command.
memory are volatile and do not persist through a reset event.
• On the MOSI line, if the current command is a write, the
32 bits correspond to the Write data, and in the case of a read,
the data is ignored.
WRITING
The Timing Diagram for an EEPROM write is shown in Figure 27
and Figure 28.
CSN
SCLK
0
1
5
6
0
1
30
31
REGISTER ADDRESS
RW
WRITE DATA OR DC
MOSI
MISO
PREVIOUS CMD DATA
Figure 27: EEPROM Write – SPI Mode
SDA
SA[6:0]
A[6:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
ST
ꢀlave W A 0 Reꢂisteꢁ A Reꢂisteꢁ A Reꢂisteꢁ A Reꢂisteꢁ A Reꢂisteꢁ A SP
addꢁess
C
K
addꢁess C Data
ꢃꢄꢅ0ꢆ
C
K
Data
ꢃ1ꢇꢅꢈꢆ
C
K
Data
ꢃꢉꢊꢅ1ꢋꢆ
C
K
Data
ꢃꢊ1ꢅꢉꢌꢆ
C
K
K
Figure 28: EEPROM Write – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
23
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
READING
The timing diagram for an EEPROM read is shown in Figure 29
and Figure 30.
CSN
SCLK
0
1
5
6
0
1
30
31
REGISTER ADDRESS
RW
WRITE DATA OR DC
MOSI
MISO
PREVIOUS CMD DATA
Figure 29: EEPROM Read – SPI Mode
For SPI, the read data will be sent out
during the above command.
SA[6:0]
A[6:0]
SA[6:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
SDA
ST
ꢀlave W A 0 Reꢂisteꢁ A ST
ꢀlave R A Reꢂisteꢁ A Reꢂisteꢁ A Reꢂisteꢁ A Reꢂisteꢁ N SP
addꢁess
C
K
addꢁess C
addꢁess
C
K
Data
ꢃꢄꢅ0ꢆ
C
K
Data
ꢃ1ꢇꢅꢈꢆ
C
K
Data
ꢃꢉꢊꢅ1ꢋꢆ
C
K
Data
ꢃꢊ1ꢅꢉꢌꢆ
A
C
K
K
Figure 30: EEPROM Read – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
24
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
If for any reason the external slave address setting feature is not
EEPROM Error Checking and Correction (ECC)
desired, the DIO polling can be disabled by setting the i2c_dis_
slv_addr. When this bit is set, the ACS37800 will automatically
use the number stored in i2c_slv_addr as the I2C slave address
regardless of the voltage on the DIO pins. Note that the device
must be repowered for these changes to take effect.
Hamming code methodology is implemented for EEPROM
checking and correction (ECC). ECC is enabled after power-up.
The ACS37800 analyzes message data sent by the controller and
the ECC bits are added. The first 6 bits sent from the device to
the controller are dedicated to ECC. The device always returns
32 bits.
Table 2: DIO Startup Voltage Addressing
Slave Address
DIO_1 DIO_2 A6 A5 A4 A3 A2 A1 A0
(decimal)
EEPROM ECC Errors
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
97
Bits
Name
Description
97
31:28
–
No meaning
98
00 = No Error
01 = Error detected and message corrected
10 = Uncorrectable error
11 = No meaning
99
27:26
25:0
ECC
100
101
102
103
104
105
106
107
108
109
110
D[25:0]
EEPROM data
I2C Slave Addressing
The ACS37800 supports I2C communication over the SCL and
SDA lines at speeds of up to 400 kHz. When the device first
powers on, it measures the voltage level on the two DIO pins. It
converts both voltage levels into a 4-bit code for a total of sixteen
slave addresses. Table 2 shows the sixteen possible I2C configu-
rations that can be set with externally applied voltage. If both
pins are pulled to VCC, then the internal slave address stored in
EEPROM is used. By default, the value of i2c_slv_addr is pro-
grammed at the Allegro factory to 127, but this can be changed
with programming by the customer.
EEPROM
value
1
1
1
1
EE EE EE EE EE EE EE
25
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Isolated, Digital Output, Power Monitoring IC
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ACS37800
MEMORY MAP
EEPROM/Shadow Memory
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x0B
0x0C
ECC
ECC
crs_sns
sns_fine
qvo_fine
vchan_offset_code
rms_avg_2
rms_avg_1
0x0D
ECC
fltdly
fault
0x0E
ECC
undervreg
overvreg
vevent_cycs
0x0F
ECC
n
i2c_slv_addr
0x1B
0x1C
crs_sns
sns_fine
qvo_fine
vchan_offset_code
rms_avg_2
rms_avg_1
0x1D
fltdly
fault
0x1E
undervreg
overvreg
vevent_cycs
0x1F
n
i2c_slv_addr
26
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register Details – EEPROM
Register 0x0B/0x1B
Bits
8:0
Name
qvo_fine
sns_fine
crs_sns
iavgselen
pavgselen
ecc
Default Value
Device Specific
Device Specific
Description
Offset fine trimming on current channel
Fine gain trimming on the current channel
18:9
21:19
22
Selection Specific Coarse gain setting
0
0
–
Current Averaging selection
23
Power Averaging selection
Error Code Correction
31:26
qvo_fine
crs_sns
Offset adjustment for the current channel. This is a signed 9-bit
number with an input range of –256 to 255. With a step size
of 64 LSB, this equates to an offset trim range of –16384 to
Coarse gain adjustment for the current channel. This gain is
implemented in the analog domain before the ADC. This is a
3-bit number that allows for 8 gain selections. Adjustments to
16320 LSB, which is added to the icodes value. The current chan- crs_sns may impact the device’s performance over temperature.
nel’s offset trim should be applied before the gain is trimmed.
qvo_fine is further described in Table 3.
Datasheet limits apply only to the factory settings for crs_sns.
The gain settings map to 1×, 2×, 3×, 3.5×, 4×, 4.5×, 5.5×, and 8×.
crs_sns is further described in Table 5.
Table 3: qvo_fine
Table 5: crs_sns
Range
Value
Units
Range
Value
1×
Units
–256 to 255
–16,384 to 16,320
LSB
0
1
2
3
4
5
6
7
–
–
–
–
–
–
–
–
sns_fine
2×
Gain adjustment for the current channel. This is a signed 9-bit
number with an input range of –256 to 255. This gain adjustment
is implemented as a percentage multiplier centered around 1 (i.e.
writing a 0 to this field multiplies the gain by 1, leaving the gain
unaffected). The fine sensitivity parameter ranges from 50% to
150% of IP. The current channel’s offset trim should be applied
before the gain is trimmed. sns_fine is further described in Table 4.
3×
3.5×
4×
4.5×
5.5×
8×
Table 4: sns_fine
iavgselen
Range
Value
Units
Current Averaging selection enable. 0 will select vrms for averag-
ing. 1 will select irms for averaging.
–256 to 255
50 to 100
%
pavgselen
Power Averaging selection enable. 0 will select vrms for averag-
ing. 1 will select pactive for averaging.
27
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x0C/0x1C
Bits
6:0
Name
rms_avg_1
rms_avg_2
vchan_offset_code
ecc
Default Value
Description
0
0
Average of the rms voltage or current – stage 1
Average of the rms voltage or current – stage 2
16:7
24:17
31:26
Device Specific Controls the room offset for the voltage channel
Error Code Correction
–
rms_avg_1
vchan_offset_code
Number of averages for the first averaging stage (vrmsavgonesec
or irmsavgonesec). The value written into this field directly maps
to the number of averages ranging from 0 to 127. For optimal
performance, an even number of averages should be used. The
channel to be averaged is selected by the current average select
enable bit (iavgselen). rms_avg_1 is further described in Table 6.
This controls the offset of the voltage channel at room.
Table 8: vchan_offset_code
Range
Value
Units
–128 to 127
–2048 to 2032
codes
Table 6: rms_avg_1
Range
Value
Units
0 to 127
0 to 127
number of averages
rms_avg_2
Number of averages for the second averaging stage (vrmsavgone-
min or irmsavgonemin). This stage averages the outputs of the first
averaging stage. The value written into this field directly maps to
the number of averages ranging from 0 to 1023. For optimal per-
formance, an even number of averages should be used. The chan-
nel to be averaged is selected by the current average select enable
bit (iavgselen). rms_avg_2 is further described in Table 7.
Table 7: rms_avg_2
Range
Value
Units
0 to 1023
0 to 1023
number of averages
28
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x0D/0x1D
Bits
7
Name
ichan_del_en
chan_del_sel
fault
Default Value
Description
0
0
Enable phase delay on voltage or current channel
Sets phase delay on voltage or current channel
Sets the overcurrent fault threshold
Sets the overcurrent fault delay
Error Code Correction
11:9
20:13
23:21
31:26
70
0
fltdly
ecc
–
ichan_del_en
Table 12: fltdly
Enables delay for either the voltage or current channel. Setting to
1 enables delay for the current channel. ichan_del_en is further
described in Table 9.
Range
Value
0
Units
µs
0
1
2
3
4
5
6
7
0
µs
4.75
9.25
13.75
18.5
23.25
27.75
µs
Table 9: ichan_del_en
µs
Range
Value
Units
LSB
µs
0
1
0 – voltage channel
1 – current channel
µs
LSB
µs
chan_del_sel
µs
Sets the amount of delay applied to the voltage or current channel (set
by ichan_del_en). chan_del_sel is further described in Table 10.
Table 10: chan_del_sel
Range
Value
Units
0 to 7
0 to 219
µs
fault
Over-current fault threshold. This is an unsigned 8-bit number
with an input range of 0 to 255, which equates to a fault range of
65% to 200% of IP. The factory setting of this field is 70. fault is
further described in Table 11.
Table 11: fault
Range
Value
Units
0 to 255
56 to 225
% of IP
fltdly
Fault delay setting of the amount of delay applied before flagging
a fault condition. fltdly is further described in Table 12.
29
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x0E/0x1E
Bits
5:0
Name
vevent_cycs
overvreg
Default Value Description
0
0
0
0
0
0
0
0
–
Sets the number of qualifying cycles needed to flag overvoltage or undervoltage
Sets the overvoltage fault threshold
13:8
19:14
20
undervreg
Sets the undervoltage fault threshold
delaycnt_sel
halfcyclc_en
squarewave_en
zerocrosschansel
zerocrossedgesel
ecc
Sets the width of the voltage zero-crossing output pulse
Sets the zero crossing flag triggering on half or full cycle (default: full cycle)
Sets the zero crossing pulse characteristics (default: pulse)
Sets the channel that triggers the zero crossing flag (default: voltage)
Sets the edge that triggers zero crossing flag
21
22
23
24
31:26
Error Code Correction
vevent_cycs
delaycnt_sel
Sets the number of cycles required to assert the ovrms flag or
the uvrms. This is an unsigned 6-bit number with an input range
of 0 to 63. The value in this field directly maps to the number of
cycles. vevent_cycs is further described in Table 13.
Selection bit for the width of pulse for a voltage zero-crossing
event. When set to 0, the pulse is 32 µs. When set to 1, the
pulse is 256 µs. When the squarewave_en bit is set, this field is
ignored. delaycnt_sel is further described in Table 16.
Table 13: vevent_cycs
Table 16: delaycnt_sel
Range
Value
Units
Range
Value
32
Units
µs
0 to 63
1 to 64
cycles
0
1
256
µs
overvreg
halfcycle_en
Sets the threshold of the overvoltage rms flag (ovrms). This is a
6-bit number ranging from 0 to 63. This trip level spans the entire
range of the vrms register. The flag is set if the rms value is above
this threshold for the number of cycles selected in vevent_cycs.
overvreg is further described in Table 14.
Setting for the zero crossing flag. When set to 0, the voltage
zero-crossing will be indicated on every edge determined by
zerocrossingedgesel. When set to 1, the voltage zero-crossing will
be indicated on both rising and falling edges.
Table 14: overvreg
squarewave_en
Range
Value
Units
Setting for the zero crossing flag. When set to 0, the zero-cross-
ing event will be indicated by a pulse on the DIO pin. When set
to 1, the zero-crossing event will be indicated by a level change
on the DIO pin.
0 to 63
0 to 65536
LSB
undervreg
Sets the threshold of the undervoltage rms flag (uvrms). This is
a 6-bit number ranging from 0 to 63. This trip level spans one
entire range of the vrms register. The flag is set if the rms value is
below this threshold for the number of cycles selected in vevent_
cycs. undervreg is further described in Table 15.
zercrossingchansel
Determines which channel will trigger the zero crossing flag. 0
is the voltage channel. 1 is the current channel with zero cross-
ing flag for rising and falling with only one customizable register
delaycnt_sel.
Table 15: undervreg
zerocrossingedgesel
Range
Value
Units
0 to 63
0 to 65536
LSB
This determines whether the zero crossing flag triggers on rising
or falling. Note: if halfcycle_en = 1, this setting does not matter.
30
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Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x0F/0x1F
Bits
8:2
Name
i2c_slv_addr
i2c_dis_slv_addr
dio_0_sel
dio_1_sel
n
Default Value
Description
127
0
I2C slave address selection
9
Disable I2C slave address selection circuit
Digital output 0 multiplexor selection bits
Digital output 1 multiplexor selection bits
Sets the number of samples used in RMS calculations when bypass_n_en = 1
11:10
13:12
23:14
0
0
0
Set whether RMS is calculated based on voltage zero crossing or n samples from the
above registers
24
bypass_n_en
ecc
0
–
31:26
Error Code Correction
i2c_slv_addr
i2c_dis_slv_addr
Settings for the I2C slave address externally. When i2c_dis_slv_
addr is set to 0, the voltage on the DIO pins are measured at
power on and are used to set the device’s slave address.
When i2c_dis_slv_addr is set to 1, the address is set through
EEPROM field i2c_slv__addr[6:0]. This enables or disables the
analog I2C slave address feature at power on. When this bit is set,
the I2C slave address will map directly to i2c_slv_addr.
Each DIO pin has 4 voltage “bins” which may be used to set
the I2C slave address. These voltages may be set using resis-
tor divider circuits from VCC to GND. i2c_slv_addr is further
described in Table 17.
dio_0_sel
Determines which flags are output on the DIO0 pin. Only used
when the device is in I2C programming mode.
Table 17: i2c_slv_addr
DIO_1
(decimal) (decimal)
DIO_0
Slave Address
(decimal)
dio_1_sel
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
96
Determines which flags are output on the DIO1 pin. Only used
when the device is in I2C programming mode.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
EEPROM value
Ratio of VCC on DIO Pin
31
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Volatile Memory
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x20
0x21
irms
vrms
pimag
pactive
0x22
pfactor
papparent
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
numptsout
irmsavgonesec
irmsavgonemin
vrmsavgonesec
vrmsavgonemin
pactavgonesec
pactavgonemin
vcodes
icodes
pinstant
0x2D
0x2E
0x2F
access_code
0x30
0x31
32
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register Details – Volatile
Register 0x20
Bits
15:0
Name
vrms
irms
Description
Voltage RMS value
Current RMS value
31:16
vrms
irms
RMS voltage output. This field is an unsigned 16-bit fixed point
number with 16 fractional bits, where ΔVIN(MAX) = 0.84, and
ΔVIN(min) = –0.84. To convert the value (input voltage) to line
voltage, divide the input voltage by the RSENSE and RISO voltage
divider ratio using actual resistor values.
RMS current output. This field is a signed 16-bit fixed point num-
ber with 15 fractional bits, where IIP(MAX) = 0.84, and IIP(MIN)
-0.84.
=
Table 19: irms
Register
Range
Valid Range
Value
Units
Table 18: vrms
Register
Range
Valid Range
Value
Units
0 to ~1
0 to ~0.84
[0 to ~1] × IPR(MAX) ×1.19
A
0 to ~1
0 to ~0.84
[0 to ~1] × ΔVIN(MAX) ×1.19
mV
Register 0x21
Bits
15:0
Name
Description
Active power
Reactive power
pactive
pimag
31:16
pactive
pimag
Active power output. This field is a signed 16-bit fixed point
number with 15 fractional bits, where positive MaxPow = 0.704,
and negative MaxPow = –0.704. To convert the value (input
power) to line power, divide the input power by the RSENSE and
RISO voltage divider ratio using actual resistor values.
Reactive power output. This field is an unsigned 16-bit fixed
point number with 16 fractional bits, where MaxPow = 0.704. To
convert the value (input power) to line power, divide the input
power by the RSENSE and RISO voltage divider ratio using actual
resistor values.
Table 20: pactive
Table 21: pimag
Register
Range
Valid Range
Value
Units
Register
Range
Valid Range
Value
Units
–1 to ~1
–0.704 to ~0.704 [1 to ~1] × MaxPow × 1.42
mW
0 to ~1
0 to ~0.704
[0 to ~1] × MaxPow × 1.42
mVA
33
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x22
Bits
15:0
26:16
27
Name
papparent
pfactor
Description
Apparent power magnitude
Power factor
posangle
pospf
Sign of the power angle
Sign of the power factor
28
papparent
posangle
Apparent power output magnitude. This field is an unsigned
Bit to represent leading or lagging. A 0 represents the current
16-bit fixed point number with 16 fractional bits, where MaxPow leading and a 1 represents the current lagging.
= 0.704. To convert the value (input power) to line power, divide
pospf
the input power by the RSENSE and RISO voltage divider ratio
using actual resistor values.
Sign bit to represent if the power is being generated (0) or con-
sumed (1).
Table 22: papparent
Register
Range
Valid Range
Value
Units
0 to ~1
0 to ~0.704
[0 to ~1] × MaxPow × 1.42 mVAR
pfactor
Power factor output. This field is a signed 11-bit fixed point num-
ber with 10 fractional bits. It ranges from –1 to ~1 with a step
size of 2-10. pfactor is further described in Table 23.
Table 23: pfactor
Range
Value
Units
–1 to ~1
–1 to ~1
–
Register 0x25
Bits
Name
numptsout
Description
9:0
Number of samples of current and voltage used for calculations
numptsout
Number of points used in the rms calculation. This will be the
dynamic value that is evaluated internal to the device based on
full cycle zero crossings of the voltage channel. numptsout is
further described in Table 24.
Table 24: numptsout
Range
Value
Units
0 to 1023
0 to 1023
samples
34
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x26
Bits
Name
Description
Averaged voltage RMS value; duration set by rms_avg_1.
This register will be zero if iavgselen = 1
15:0
vrmsavgonesec
Averaged current RMS value; duration set by rms_avg_1.
This register will be zero if iavgselen = 0
31:16
irmsavgonesec
vrmsavgonesec
irmsavgonesec
Voltage RMS value averaged according to rms_avg_1. This regis- Current RMS value averaged according to rms_avg_1. This regis-
ter will be zero if iavgselen = 1.
ter will be zero if iavgselen = 0.
Register 0x27
Bits
Name
Description
Averaged voltage RMS value; duration set by rms_avg_2.
This register will be zero if iavgselen = 1
15:0
vrmsavgonemin
Averaged current RMS value; duration set by rms_avg_2.
This register will be zero if iavgselen = 0
31:16
irmsavgonemin
vrmsavgonemin
irmsavgonemin
Voltage RMS value averaged according to rms_avg_2. This regis- Current RMS value averaged according to rms_avg_2. This regis-
ter will be zero if iavgselen = 1.
ter will be zero if iavgselen = 0.
Register 0x28
Bits
Name
Description
Active Power value averaged over up to one second; duration set by rms_avg_1
15:0
pactavgonesec
pactavgonesec
Active power value averaged according to rms_avg_1.
Register 0x29
Bits
Name
Description
15:0
pactavgonemin
Active Power value averaged over up to one minute; duration set by rms_avg_2
pactavgonemin
Active power value averaged according to rms_avg_2.
35
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x2A
Bits
15:0
Name
vcodes
icodes
Description
Instantaneous voltage measurement
Instantaneous current measurement
31:16
vcodes
This field contains the instantaneous voltage measurement before
any RMS calculations are done. It is a 16-bit signed fixed point
number with 15 fractional bits, where ΔVIN(MAX) = 0.84 and
ΔVIN(min) = –0.84. To convert the value (input voltage) to line
voltage, divide the input voltage by the RSENSE and RISO voltage
divider ratio using the resistor values.
Table 25: vcodes
Register
Range
Valid Range
Value
Units
–1 to ~1
-0.84 to ~0.84
[–1 to ~1] × ΔVIN(MAX) ×1.19
mV
icodes
This field contains the instantaneous current measurement before
any RMS calculations are done. This field is a signed 16-bit fixed
point number with 15 fractional bits, where IIP(MAX) = 0.84, and
IIP(MIN)= –0.84.
Table 26: icodes
Register
Range
Valid Range
Value
Units
–1 to ~1
-0.84 to ~0.84
[–1 to ~1] × IPR(MAX) ×1.19
A
Register 0x2C
Bits
Name
pinstant
Description
Instantaneous power – Multiplication of vcodes and icodes
15:0
pinstant
This field contains the instantaneous power measurement before
any RMS calculations are done. This field is a signed 16-bit fixed
point number with 15 fractional bits, where postive MaxPow =
0.704, and negative MaxPow = –0.704. To convert the value
(input power) to line power, divide the input power by the RSENSE
and RISO voltage divider ratio using the resistor values.
Table 27: pinstant
Register
Range
Valid Range
Value
Units
–1 to ~1
–0.704 to ~0.704 [–1 to ~1] × MaxPow × 1.42 mVAR
36
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x2D
Bits
0
Name
Description
zerocrossout
faultout
Zero-crossing output
Current fault output
Current fault output latched
Overvoltage flag
1
2
faultlatched
overvoltage
undervoltage
3
4
Undervoltage flag
zerocrossout
overvoltage
Flag for the zero-crossing events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel. This flag will still fol-
low the halfcycle_en and squarewave_en settings.
Flag for the overvoltage events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel and will only be set
when fault is present.
faultout
undervoltage
Flag for the overcurrent events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel and will only be set
when fault is present.
Flag for the undervoltage events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel and will only be set
when fault is present.
faultlatched
Flag for the overcurrent events. This bit will latch and will remain
1 as soon as an overcurrent event is detected. This can be reset by
writing a 1 to this field. This will be present and active regardless
of DIO settings.
Register 0x2F
Bits
Name
Description
Access code register:
Customer code: 0x4F70656E
31:0
access_code
Register 0x30
Bits
Name
Description
Customer write access enabled.
customer_access 0 = Non-Customer mode.
1 = Customer mode.
0
37
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
THERMAL PERFORMANCE
The thermal capacity of the ACS37800 should be verified by the
Thermal Rise vs. Primary Current
end user in the application’s specific conditions. The maximum
junction temperature, TJ(MAX) (165℃), should not be exceeded.
Further information on this application testing is available in
the DC and Transient Current Capability application note on the
Allegro website.
Self-heating due to the flow of current should be considered dur-
ing the design of any current sensing system. The sensor, printed
circuit board (PCB), and contacts to the PCB will generate heat
as current moves through the system.
The thermal response is highly dependent on PCB layout, copper
thickness, cooling techniques, and the profile of the injected current.
The current profile includes peak current, current “on-time”, and
duty cycle. While the data presented in this section was collected
with direct current (DC), these numbers may be used to approximate
thermal response for both AC signals and current pulses.
ASEK37800 Evaluation Board Layout
Thermal data shown in Figure 31 and Figure 32 was collected
using the ASEK37800 Evaluation Board (TED-0003306). This
board includes 750 mm2 of 4 oz. copper (0.0694 mm) connected
to pins 1 through 4, and to pins 5 through 8, with thermal vias
connecting the layers. Top and Bottom layers of the PCB are
shown below in Figure 33.
The plot in Figure 31 shows the measured rise in steady-state die
temperature of the ACS37800 versus continuous current at an ambi-
ent temperature, TA, of 25 °C. The thermal offset curves may be
directly applied to other values of TA. Conversely, Figure 32 shows
the maximum continuous current at a given TA. Surges beyond the
maximum current listed in Figure 32 are allowed given the maxi-
mum junction temperature, TJ(MAX) (165℃), is not exceeded.
140
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
Continuous Current ꢂꢅꢄ
Figure 31: Self Heating in the MA Package
Due to Current Flow
80
70
60
50
40
30
20
10
0
Figure 33: Top and Bottom Layers
for ASEK37800 Evaluation Board
25
50
75
100
125
150
175
Gerber files for the ASEK37800 evaluation board are available
for download from the Allegro website. See the technical docu-
ꢁꢃꢄient ꢅeꢃperature ꢀ°Cꢂ
Figure 32: Maximum Continuous Current at a Given TA ments section of the ACS37800 device webpage.
38
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
RECOMMENDED PCB LAYOUT
NOT TO SCALE
All dimensions in millimeters.
15.75
9.54
1.27
0.65
Package Outline
Slot in PCB to maintain >8 mm creepage
once part is on PCB
2.25
7.25
1.27
3.56
17.27
Current
In
Current
Out
Perimeter holes for stitching to the other,
matching current trace design, layers of
the PCB for enhanced thermal capability.
21.51
Figure 34: Recommended PCB Layout
39
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MS-013AA)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
8°
10.30 0.20
E
0°
16
0.33
0.20
D
D1
D2
7.50 0.10
10.30 0.33
A
1.27
0.40
1.40 REF
1
2
0.90
D
Branded Face
0.25 BSC
SEATING PLANE
16×
CC
GAUGE PLANE
2.65 MAX
0.10
C
SEATING
PLANE
0.30
0.10
1.27 BSC
0.51
0.31
1.27
0.65
16
XXXXXXX
Lot Number
2.25
1
B
Standard Branding Reference View
9.50
Lines 1, 2 = 12 characters
Line 1: Part Number
Line 2: First 8 characters of Assembly Lot Number
A
Terminal #1 mark area
B
C
Branding scale and appearance at supplier discretion
1
2
Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
PCB Layout Reference View
Hall elements (D1, D2), not to scale
D
E
Active Area Depth 0.293 mm
Figure 35: Package MA, 16-Pin SOICW
40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Revision History
Number
Date
Description
–
November 30, 2020 Initial release
Copyright 2020, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
41
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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