AMT49502 [ALLEGRO]
80 V Automotive Half-Bridge MOSFET Driver;
| 型号： | AMT49502 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 80 V Automotive Half-Bridge MOSFET Driver |
| 文件： | 总45页 (文件大小：2035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
FEATURES AND BENEFITS
DESCRIPTION
The AMT49502 is an N-channel power MOSFET driver
capable of controlling MOSFETs connected in a half-bridge
arrangement and is specifically designed for automotive
applicationswithhigh-powerinductiveloads,suchasbrushDC
motors,BLDCmotors,VR/SRmotors,solenoids,andactuators.
• Half-bridge MOSFET driver
• Bootstrap gate drive for N-channel MOSFET bridge
• Independent control of high-side and low-side gate drives
with cross-conduction capability
• Charge pump regulator for low supply voltage operation
• 5.5 to 80 V supply voltage operating range
• Integrated logic I/O supply
• SPI-compatible serial interface
• Bridge control by direct logic inputs or serial interface
• Programmable gate drive
Auniquechargepumpregulatorprovidesfullgatedriveoverthe
fullsupplyvoltagerangefrom5.5to80Vformostapplications.
A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs.
EachMOSFETcanbe independentlycontrolledbylogic-level
inputs or through the SPI-compatible serial interface. Fully
independent control allows both external FETs to be turned
on at the same time.
• Current sense amplifier
• Programmable diagnostics
• A2SIL™ product—device features for
safety-critical systems
• AEC-Q100 Grade 0 qualified
2
-
Integrated diagnostics provide indication of multiple internal
faults, system faults, and power bridge faults, and can be
configured to protect the power MOSFETs under most short
circuit conditions.
In addition to providing full access to the bridge control, the
serialinterfaceisalsousedtoalterprogrammablesettingssuch
as VDS threshold and fault blank time. Detailed diagnostic
information can be read through the serial interface.
PACKAGE:
24-lead TSSOP with
exposed pad (suffix LP)
The AMT49502 was developed in accordance with
ISO26262:2011asahardwaresafetyelementoutofcontextwith
ASIL B capability (pending assessment) for use in automotive
safety-related systems when integrated and used in the manner
prescribedintheapplicablesafetyapplicationnoteanddatasheet.
The AMT49502 is supplied in a 24-lead eTSSOP (suffix LP).
This package is lead (Pb) free, with 100% matte-tin leadframe
plating (suffix –T).
Not to scale
VBAT
VBAT
Control
Control
Load
Load
AMT49502
AMT49502
DSP
or
DSP
or
µC
µC
Diagnostics
Diagnostics
Current Sense
Current Sense
Figure 1: Typical Applications
AMT49502-DS, Rev. 1
MCO-0000796
June 15, 2020
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SELECTION GUIDE
Part Number
I/O Logic
3.3 V
Packing
Package
AMT49502KLPTR-3
AMT49502KLPTR-5
7.8 mm × 4.4 mm, 1.2 mm max. height
24-lead TSSOP with exposed thermal pad
4000 pieces per reel
5 V
ABSOLUTE MAXIMUM RATINGS [1]
Characteristic
Symbol
VBB
Notes
Rating
Unit
V
Load Supply Voltage
–0.3 to 80
–0.3 to 16
–0.3 to 16
Regulator Output
VREG
VCP1
VREG
V
Charge Pump Capacitor Terminal
CP1
CP2
V
VCP1 – 0.3 to
VREG + 0.3
Charge Pump Capacitor Terminal
VCP2
V
Battery-Compliant Logic Input Terminals
Logic Input Terminals
VIB
VI
HS, LSn, RESETn, ENABLE
–0.3 to 80
–0.3 to 6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
STRn, SCK, SDI
Logic Output Terminal
VO
SDO
–0.3 to 6
Diagnostics Output
VDIAG
VCSI
VCSO
VBRG
VC
DIAG
–0.3 to 80
Sense Amplifier Inputs
CSP, CSM
–4 to 6.5
Sense Amplifier Output
CSO
–0.3 to 6
Bridge Drain Monitor Terminal
Bootstrap Supply Terminal
VBRG
–5 to 85
C
–0.3 to VREG + 80
VC – 16 to VC + 0.3
–18 to VC + 0.3
VC – 16 to VC + 0.3
–18 to VC + 0.3
VREG – 16 to 18
–8 to 18
GH
High-Side Gate Drive Output Terminal
High-Side Source (Load) Terminal
Low-Side Gate Drive Output Terminal
Bridge Low-Side Source Terminal
VGH
GH (transient)
S
VS
S (transient)
GL
VGL
GL (transient)
LSS
VREG – 16 to 18
–8 to 18
VLSS
LSS (transient)
Limited by power dissipation
Ambient Operating Temperature Range
TA
–40 to 150
Maximum Continuous Junction Temperature
TJ(max)
165
Overtemperature event not exceeding 10 seconds,
lifetime duration not exceeding 10 hours,
guaranteed by design characterization.
Transient Junction Temperature
Storage Temperature Range
TJt
180
°C
°C
Tstg
–55 to 150
[1] With respect to GND. Ratings apply when no other circuit operating constraints are present.
THERMAL CHARACTERISTICS: May require derating at maximum conditions
Characteristic
Symbol
Test Conditions [2]
Value
Unit
4-layer PCB based on JEDEC standard
28
°C/W
RθJA
2-layer PCB with 3.8 in.2 copper each side
38
2
°C/W
°C/W
Package Thermal Resistance
RθJP
[2] Additional thermal information available on the Allegro website.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
Table of Contents
Gate Drive Control .......................................................... 18
Logic Control Inputs ........................................................ 19
Output Disable................................................................ 19
Sleep Mode.................................................................... 19
Current Sense Amplifier................................................... 20
Diagnostic Monitors......................................................... 20
DIAG Output .................................................................. 20
Status and Diagnostic Registers ....................................... 21
Chip-Level Protection ...................................................... 21
Operational Monitors....................................................... 22
Power Bridge and Load Faults.......................................... 23
Fault Action.................................................................... 26
Fault Masks ................................................................... 27
Serial Interface................................................................ 28
Configuration Registers ................................................... 30
Stop On Fault Register .................................................... 30
Diagnostic Registers ....................................................... 30
Control Register.............................................................. 30
Status Register............................................................... 31
Serial Register Reference............................................... 32
Application Information ................................................... 40
Bootstrap Capacitor Selection .......................................... 40
Bootstrap Charging ......................................................... 40
VREG Capacitor Selection............................................... 40
Current Sense Amplifier Configuration............................... 41
Current Sense Amplifier Output Signals ............................. 41
Input/Output Structures................................................... 42
Layout Recommendations.............................................. 43
Package Outline Drawing ............................................... 44
Features and Benefits....................................................... 1
Description........................................................................ 1
Package............................................................................ 1
Typical Application ............................................................ 1
Selection Guide................................................................. 2
Absolute Maximum Ratings.............................................. 2
Thermal Characteristics.................................................... 2
Pinout Diagram and Terminal List Table ........................... 4
Functional Block Diagram................................................. 5
Electrical Characteristics................................................... 6
Supply and Reference ....................................................... 6
Gate Output Drive............................................................. 7
Logic Inputs and Outputs ................................................... 8
Logic I/O – Dynamic Parameters......................................... 8
Current Sense Amplifier..................................................... 9
Diagnostics and Protection............................................... 10
Timing Diagrams............................................................. 12
Logic Truth Tables........................................................... 14
Functional Description .................................................... 15
Input and Output Terminal Functions ................................. 15
Power Supplies............................................................... 16
Pump Regulator.............................................................. 16
Gate Drives.................................................................... 16
Operational Configurations............................................... 16
Bootstrap Supply ............................................................ 17
Bootstrap Charge Cycle Considerations............................. 17
Top-Off Charge Pump...................................................... 17
High-Side Gate Drive....................................................... 18
Low-Side Gate Drive ....................................................... 18
Gate Drive Passive Pull-Down.......................................... 18
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
PINOUT DIAGRAM AND TERMINAL LIST TABLE
ꢀꢁ ꢅꢆRꢇ
ꢀ3 ꢅꢆꢆ
ꢀꢀ ꢈP1
ꢇNꢋ
ꢋꢌAꢇ
ꢉNAꢆꢊꢉ
RꢉSꢉꢍn
HS
1
ꢀ
3
ꢁ
5
ꢂ
ꢃ
ꢄ
9
ꢀ1 ꢈPꢀ
ꢀ0 ꢅRꢉꢇ
19
1ꢄ
ꢈ
S
ꢊSn
PAꢋ
Sꢋꢌ
1ꢃ ꢇH
1ꢂ ꢇꢊ
Sꢈꢎ
Sꢋꢏ
15 ꢊSS
1ꢁ ꢈSP
13 ꢈSM
SꢍRn 10
ꢏꢏS 11
ꢈSꢏ 1ꢀ
24-Lead eTSSOP (suffix LP)
Pinout Diagram
Terminal List Table
Name
C
Number
19
22
21
13
12
14
2
Function
Bootstrap Capacitor
CP1
Pump Capacitor CCP Connection
Pump Capacitor CCP Connection
Current Sense Amp -Input
Current Sense Amp Output
Current Sense Amp +Input
Diagnostic Output
CP2
CSM
CSO
CSP
DIAG
ENABLE
GH
3
Gate drive output control Input
High-side Gate Drive Output
Low-side Gate Drive Output
Power Ground
17
16
1
GL
GND
HS
5
High-side control Input
Low-side control Input
LSn
6
LSS
15
11
4
Low-side Source
OOS
RESETn
S
Sense amp offet output
Standby Mode Control Input
Load Connection
18
8
SCK
SDI
Serial Clock Input
7
Serial Data Input
SDO
STRn
VBB
VBRG
VREG
PAD
9
Serial Data Output
10
23
24
20
–
Serial Strobe (chip select) Input
Main Power Supply
High-side Drain voltage sense
Regulated gate drive supply
Thermal pad; connect to GND
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ꢀꢀP
ꢃꢄꢄ
ꢃRꢆꢇ
ꢃꢄAꢅ
ꢃꢊꢁ
ꢃꢋꢎ
ꢀharge
Pꢈmꢉ
Regꢈlator
ꢁogic
Sꢈꢉꢉly
Regꢈlator
ꢀRꢆꢇ
ꢃꢄRꢇ
ꢀ
ꢀharge
Pꢈmꢉ
ꢆNAꢄꢁꢆ
HS
ꢊriꢐe
ꢇH
S
ꢃꢊS
Monitor
HS
ꢄootstraꢉ
Monitor
ꢀontrol
ꢁogic
ꢁSn
ꢃꢊS
Monitor
RꢆSꢆꢅn
ꢎꢎS
ꢁS
ꢇꢁ
ꢊriꢐe
ꢅimers
ꢁSS
ꢀSP
SꢅRn
Sꢀꢏ
Sꢊꢋ
ꢃꢎꢎS
ꢊAꢀ
ꢊAꢀ
Serial
ꢋnterꢌace
Sꢊꢎ
ꢀSM
ꢀSꢎ
ꢊꢋAꢇ
ꢊiagnostics ꢍ
Protection
PAꢊ
ꢇNꢊ
Figure 2: Functional Block Diagram
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS: Valid for TJ = –40 to 150°C, VBB = 5.5 to 80 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY AND REFERENCE
Operating; outputs active
5.5
5
–
–
–
80
80
80
V
V
V
VBB Functional Operating Range
VBB Quiescent Current
VBB
Operating; outputs disabled
No unsafe states
0
RESETn = high, VBB = 48 V,
All gate drive outputs low
IBBQ
IBBS
VDL
–
–
8
–
20
30
mA
µA
V
RESETn ≤ 300 mV, sleep mode, VBB < 70 V
Internal Logic Supply Regulator
Voltage [3][4]
3.1
3.3
3.5
AMT49502KLPTR-3
3
4.5
9
3.3
5
3.6
5.5
11.7
11.7
11.7
1.0
2.8
750
–
V
V
Logic I/O Regulator Voltage [3][4]
VIO
AMT49502KLPTR-5; VBB > 6 V
6.5 V < VBB, IVREG = 0 to 33 mA
6 V < VBB ≤ 6.5 V, IVREG = 0 to 20 mA
5.5 V < VBB ≤ 6 V, IVREG = 0 to 15 mA
ID = 10 mA
11
V
VREG Output Voltage
VREG
9
11
V
9
11
V
0.4
1.35
250
43
0.7
2.2
500
100
V
Bootstrap Diode Forward Voltage
VfBOOT
ID = 100 mA
V
Bootstrap Diode Current Limit
IDBOOT
ITOCPM
mA
µA
Top-Off Charge Pump Current Limit
High-Side Gate Drive Static Load
Resistance
RGSH
tOSC
250
45
–
–
kΩ
System Clock Period
50
55
ns
Continued on the next page…
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 80 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GATE OUTPUT DRIVE
Turn-On Time (High-Side)
tr(HS)
tr(LS)
tf(HS)
tf(LS)
CLOAD = 15 nF, 2 V to 8 V, VC – VS = 11 V
CLOAD = 15 nF, 2 V to 8 V, VREG – VLSS = 11 V
CLOAD = 15 nF, 8 V to 2 V, VC – VS = 11 V
CLOAD = 15 nF, 8 V to 2 V, VREG – VLSS = 11 V
86
86
235
235
97
97
–
434
434
205
205
–250
–250
13.9
22.5
2100
2100
2.8
ns
ns
ns
ns
mA
mA
Ω
Turn-On Time (Low-Side)
Turn-Off Time (High-Side)
44
Turn-Off Time (Low-Side)
44
IPUPK(HS) VC – VS = 11 V
–1150
–1150
5.6
Pull-Up Peak Source Current (High-Side)
Pull-Up Peak Source Current (Low-Side)
IPUPK(LS) VREG – VLSS = 11 V
–
TJ = 25°C, IGH = –150 mA[1]
TJ = 150°C, IGH = –150 mA[1]
–
Pull-Up On Resistance
RDS(on)UP
9.1
–
Ω
IPDPK(HS) VC – VS = 11 V
570
570
1.25
2.1
–
mA
mA
Ω
Pull-Down Peak Sink Current (High-Side)
Pull-Down Peak Sink Current (Low-Side)
IPDPK(LS) VREG – VLSS = 11 V
–
TJ = 25°C, IGL = 150 mA
RDS(on)DN
–
Pull-Down On Resistance
TJ = 150°C, IGL = 150 mA
–
4.7
Ω
Turn-On Time Set Point Range
Minimum Turn-On Time
tR
60
–
300
75
ns
ns
ns
mA
mA
mA
mA
ns
ns
ns
mA
mA
mA
mA
V
tRM
tRS
TR = 0
45
60
16
–120
–
Turn-On Time Mean Step Size
TR > 0
12
22
VGS = 0 V, IR1 = 15
Programmable set point range
VGS = 0 V, IR2 = 15
Programmable set point range
–511
–8
–86
–120
–86
–120
300
75
Turn-On Current I1
Turn-On Current I2
IR1
–511
–8
–120
–
IR2
Turn-Off Time Set Point Range
Minimum Turn-Off Time
tF
60
–
tFM
tFS
TF = 0
45
60
16
120
–
Turn-Off Time Mean Step Size
TF > 0
12
22
VGS = 9 V, IF1 = 15
Programmable set point range
VGS = 9 V, IF2 = 15
Programmable set point range
Bootstrap capacitor fully charged
–10 µA < IGH < 10 µA
84
148
120
148
120
–
Turn-Off Current I1
Turn-Off Current I2
IF1
8
84
120
–
IF2
8
GH Output Voltage High
GH Output Voltage Low
GL Output Voltage High
GL Output Voltage Low
GH Passive Pull-Down
GL Passive Pull-Down
GH Active Pull-Down
GL Active Pull-Down
VGHH
VGHL
VC – 0.02
–
–
–
VS + 0.02
–
V
VGLH
VREG – 0.02
–
–
V
VGLL
–10 µA < IGL < 10 µA
VGH – VS = 0.1 V
VGL – VLSS = 0.1 V
VC-S > 3 V
–
V
LSS + 0.02
1.8
V
RGHPD
RGLPD
RGHPA
RGLPA
0.25
0.25
0.7
–
MΩ
MΩ
Ω
–
1.8
3.5
3.5
6.4
VVREG-LSS > 3 V
0.7
6.4
Ω
Input Change to unloaded Gate output change
(Figure 5)
Turn-Off Propagation Delay
Turn-On Propagation Delay
tP(off)
tP(on)
30
30
–
–
103
103
ns
ns
Input Change to unloaded Gate output change
(Figure 5)
Propagation Delay Matching (On-to-Off)
Propagation Delay Matching (GH-to-GL)
ΔtOO
ΔtHL
–
–
–
–
25
25
ns
ns
Same state change
Continued on the next page…
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 80 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
LOGIC INPUT AND OUTPUTS
Except RESETn
RESETn
–
–
–
0.3 × VIO
V
V
Input Low Voltage
VIL
VIH
–
0.8
–
Except RESETn
RESETn
0.7 × VIO
–
V
Input High Voltage
2.4
–
–
V
Except RESETn
RESETn
250
550
500
50
100
50
100
50
50
0.2
–
–
mV
mV
kΩ
µA
kΩ
µA
kΩ
kΩ
V
Input Hysteresis
VIhys
200
–
RPD
IPD
0 < VIN < VIO
VIO < VIN < 80 V
0 < VIN < VIO
VIO < VIN < 80 V
0 < VIN < VIO
–
–
Input Pull-Down HS, ENABLE, RESETn
–
–
RPD
IPD
–
–
Input Pull-Up LSn
–
–
Input Pull-Down SDI, SCK
RPDS
RPUS
VOL
VOHS
IOS
–
–
Input Pull-Up STRn (to VIO
)
–
–
Output Low Voltage
IOL = 1 mA
–
0.4
–
Output High Voltage
IOS = –1 mA[1]
VIO – 0.4
V
Output Leakage SDO [1]
0 V < VOS < VIO, STRn = 1
–1
–
–
1
µA
mA
mA
µA
mA
0 V < VOD < 12 V, DIAG active
18 V ≤ VOD < 80 V, DIAG active
0 V < VOD < 12 V, DIAG inactive
18 V ≤ VOD < 80 V, DIAG inactive
10
–
17
2.5
1
Output Current Limit (DIAG)
Output Leakage [1] (DIAG)
IOLDLIM
–
–1
–
–
IOD
–
2.5
LOGIC I/O – DYNAMIC PARAMETERS
Reset Pulse Width
tRST
tRSD
0.5
30
–
–
–
35
–
–
–
–
–
–
–
–
–
–
–
–
4.5
–
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Reset Shutdown Time
Input Pulse Filter Time
tPIN
HS, LSn
–
Clock High Time
tSCKH
tSCKL
tSTLD
tSTLG
tSTRH
tSDOE
tSDOD
tSDOV
tSDOH
tSDIS
tSDIH
tEN
A in Figure 4
50
50
100
30
350
–
–
Clock Low Time
B in Figure 4
–
Strobe Lead Time
C in Figure 4
–
Strobe Lag Time
D in Figure 4
–
Strobe High Time
E in Figure 4
–
Data Out Enable Time
F in Figure 4, CLOAD = 10 pF
G in Figure 4
40
30
40
–
Data Out Disable Time
–
Data Out Valid Time From Clock Falling
Data Out Hold Time From Clock Falling
Data In Set-Up Time To Clock Rising
Data In Hold Time From Clock Rising
Wake Up From Sleep
H in Figure 4, CLOAD = 10 pF
I in Figure 4
–
5
J in Figure 4
15
10
–
–
K in Figure 4
–
CCP = 2.2 µF, CREG = 10 µF
3
Continued on the next page…
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 80 V, unless otherwise specified
Characteristics
CURRENT SENSE AMPLIFIER
Input Offset Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VIOS
–6.5
–
–
+6.5
–
mV
Input Offset Voltage Drift Over
Temperature
ΔVIOS
±4
µV/°C
Input Bias Current [1]
IBIAS
IOS
VID = 0 V, VCM in range
–50
–1.5
–1.5
–
–
–
5
+1.5
+2
µA
µA
V
Input Offset Current [1]
VID = 0 V, VCM in range
VID = 0 V
Input Common-Mode Range (DC)
VCM
–
Default power-up value
Programmable range, SAG[2:0], nominal
VCM in range
35
–
–
V/V
V/V
%
Gain
AV
EA
10
50
Gain Error
–1.6
–
–
+1.6
–
Default power-up value
Programmable range, SAO[3:0], nominal
VCM in range, VOOS > 0 V
2.5
–
V
Output Offset
Output Offset Error
VOOS
0
2.5
+10
V
EVO
BW
–10
±2
%
Small Signal –3 dB Bandwidth
at Gain = 25
VIN = 10 mVpp
2
–
–
–
–
1
MHz
µs
VCSO = 1 Vpp square wave,
Gain = 20, COUT = 50 pF
Output Settling Time (to within 40 mV)
tSET
Output Dynamic Range
Output Voltage Clamp
Output Current Sink [1]
VCSOUT
VCSC
–100 µA < ICSO < 100 µA
ICSO = –2 mA
0.3
4.9
–
5.2
–
4.8
5.7
V
V
ICSsink
VID = 0 V, VCSO = 1.5 V, Gain = 20
230
470
µA
VOOS = 1.5 V, VID = –50 mV, VCSO = 1.5 V,
Gain = 20
Output Current Sink (Boosted) [1][5]
Output Current Source [1]
ICSsinkb
1.8
–
–
4.4
mA
mA
VOOS = 0 V, VID = 200 mV, VCSO = 1.5 V,
Gain = 20
ICSsource
–5.5
–1.8
VID = 0 V, 100 kHz, Gain = 20
56
77
65
–
–
–
dB
dB
VBB Supply Ripple Rejection Ratio
DC Common-Mode Rejection Ratio
PSRR
CMRR
VCSP = VCSM = 0 V, DC, Gain = 20
VCM step from 0 to 200 mV,
Gain = 20
52
100
–
dB
VCM = 200 mVpp, 100 kHz, Gain = 20
VCM = 200 mVpp, 1 MHz, Gain = 20
VCM = 200 mVpp, 10 MHz, Gain = 20
–
–
–
62
43
25
–
–
–
dB
dB
dB
AC Common-Mode Rejection Ratio
CMRR
Common Mode Recovery Time
(to within 100 mV)
VCM step from –4 V to +1 V,
Gain = 20, COUT = 50 pF
tCMrec
SR
–
1.8
–
–
–
–
2.1
–
µs
V/µs
µs
VID step from 0 to 175 mV,
Gain = 20, COUT = 50 pF
Output Slew Rate 10% to 90%
Input Overload Recovery
(to within 40 mV)
VID step from 250 mV to 0 V,
Gain = 20, COUT = 50 pF
tIDrec
2.1
Continued on the next page…
9
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 80 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
DIAGNOSTICS AND PROTECTION
VRON
VROFF
VROV
VREG rising
VREG falling
VREG rising
7.6
6.9
15.2
1130
52
7.95
7.2
15.9
1500
54
8.3
7.5
16.6
1850
58
V
V
VREG Undervoltage
VREG Overvoltage Warning
VREG Overvoltage Hysteresis
V
VROVHys
mV
V
VPO = 0, VBRG rising
VPO = 1, VBRG rising
VBRG Overvoltage Warning Threshold
VBRG Overvoltage Hysteresis
VBRG Undervoltage Threshold
VBRGOV
VBRGOVHys
VBRGUV
57
60
63
V
1.9
18
2.8
19
3.6
20
V
VPU = 0, VBRG falling
VPU = 1, VBRG falling
V
32
34
36
V
VBRG Undervoltage Hysteresis
VBB POR Voltage
VBRGUVHys
VBBR
1.2
–
1.6
–
1.9
3.8
8
V
VBB
V
VBOOT rising, VBOOT = VC – VS
VBOOT falling, VBOOT = VC – VS
6.2
5.15
7
V
Bootstrap Undervoltage
VBCUV
6
6.65
V
VBOOT
– 1.35
VBOOT
– 1
VBOOT
– 0.85
Gate Drive Undervoltage Warning HS
Gate Drive Undervoltage Warning LS
VGSHUV
VGSLUV
VGSHOV
VGSLOV
VGSH falling
VGSL falling
VGSH rising
VGSL rising
V
V
V
V
VREG
– 1.35
VREG
– 1
VREG
– 0.85
Off-State Gate Drive Overvoltage
Warning HS
VS + 0.85 VS + 1.2
VS + 1.8
Off-State Gate Drive Overvoltage
Warning LS
VLSS + 0.85 VLSS + 1.2 VLSS + 1.8
VIOON
VIOOFF
VIOON
VIOOFF
VBRG
AMT49502KLPTR-3, VIO rising
AMT49502KLPTR-3, VIO falling
AMT49502KLPTR-5, VIO rising
AMT49502KLPTR-5, VIO falling
When VDS monitor is active
VDSTH = default, VBB = 12 V
Sleep mode VBB < 70 V
2.8
2.4
4.3
3.7
5.5
–
2.9
2.6
4.5
3.9
VBB
–
3.1
2.8
4.7
4.1
80
V
V
VIO Undervoltage Threshold
V
V
VBRG Input Voltage
VBRG Input Current
V
IVBRG
5
mA
µA
V
IVBRGQ
–
–
5
Default power-up value
1.1
0
1.2
–
1.3
3.15
Programmable range, 7 V ≤ VBRG < 80 V
V
VDS Threshold – High Side
VDSTH
Programmable range VT[5:0]
5.5 V ≤ VBRG < 7 V [6]
0
–
2.5
V
High-side on, VDSTH ≥1 V, VBRG > 7 V
High-side on, VDSTH < 1 V
–200
–150
1.1
±100
±50
1.2
200
150
1.3
mV
mV
V
High-Side VDS Threshold Offset [2]
VDS Threshold – Low Side
VDSTHO
Default power-up value
VDSTL
Programmable range, VBB ≥ 5.5 V [6]
Low-side on, VDSTL ≥ 1 V, VBRG > 7 V
Low-side on, VDSTL < 1 V
0
–
3.15
200
150
V
–200
–150
±100
±50
mV
mV
Low-Side VDS Threshold Offset [2]
VDSTLO
Continued on the next page…
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 80 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
DIAGNOSTICS AND PROTECTION (CONTINUED)
Default power-up value (Figure 6)
Programmable range TVD[9:0], nominal
Default power-up value
86.96
0
102.3
–
117.65
102.3
0.75
4.8
µs
µs
V
VDS and VGS Qualify Time
Overcurrent Voltage
tVDQ
0.45
0.3
6.75
125
–
0.6
–
VOCT
Programmable range, OCT[3:0], nominal
V
Overcurrent Qualify Time
tOCQ
8.6
135
15
9.45
145
–
µs
°C
°C
°C
°C
Temperature Warning Threshold
Temperature Warning Hysteresis
Overtemperature Threshold
Overtemperature Hysteresis
TJWH
Temperature increasing
TJWHhys Recovery = TJWH – TJWHhys
TJF
Temperature increasing
Recovery = TJF – TJHys
165
–
175
15
185
–
TJHys
[1] For input and output current specifications, negative current is defined as coming out of (being sourced by) the specified device terminal.
[2] VDS offset is the difference between the programmed threshold, VDSTH or VDSTL and the actual trip voltage.
[3] VIO, VDL derived from VBB for internal use only. VDL not accessible on any device terminal.
[4] Verified by design and characterization. Not production tested.
[5] If the amplifier output voltage (VCSO) is more positive than the value demanded by the applied differential input (VID) and output offset (VOOS
conditions, then output current sink capability is boosted to enhance negative-going transient response.
)
[6] Maximum value of VDS threshold that should be set in the configuration registers for correct operation when VBRG is within the stated range.
11
Allegro MicroSystems
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
ꢁꢂSꢋ ꢃ ꢍꢄꢁꢂSP ꢅ ꢁꢂSMꢆ ꢐ Aꢁꢏ ꢅ ꢁꢋꢋS
ꢂSP
ꢂSꢋ
ꢁꢀꢉ
RS
ꢁꢂM ꢃ ꢄꢁꢂSP ꢅ ꢁꢂSMꢆ ꢇ ꢈ
Aꢁ
ꢁꢂSꢉ
ꢋꢋS
ꢂSM
Aꢁ set ꢌy
SAꢊꢍꢈꢎ0ꢏ
ꢁꢂSP
ꢁ
ꢋꢋS set ꢌy
ꢁꢋꢋS
ꢁꢂSꢋ
SAꢋꢍ3ꢎ0ꢏ
ꢁꢂSM
ꢀPH
AMT49502
ꢊNꢉ
Figure 3: Sense Amplifier Voltage Definitions
STRn
C
A
B
D
E
SCK
SDI
J
K
X
D15
X
D14
X
X
D0
X
F
I
G
SDO
Z
D15’
D14’
D0’
Z
H
Figure 4: Serial Interface Timing (X = don’t care, Z = high impedance (tri-state))
HS
ꢀSn
tPꢂoꢃꢃꢄ
tPꢂonꢄ
tPꢂoꢃꢃꢄ
ꢁH
ꢁꢀ
tPꢂoꢃꢃꢄ
tPꢂonꢄ
tPꢂoꢃꢃꢄ
Synchronoꢅs Rectiꢃication
High-Side PꢆM
ꢀow-Side PꢆM
Figure 5: Gate Drive Timing – Control Inputs
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
MOSFET turn on
No fault present
MOSFET turn on
Fault present
MOSFET on
Transient disturbance
MOSFET on
Fault occurs
No fault present
Gx
VDS
tVDQ
tVDQ
Fault Bit
Figure 6a: VDS Fault Monitor – Blank Mode Timing (VDQ = 1)
MOSFET turn on
No fault present
MOSFET turn on
Fault present
MOSFET on
Transient disturbance
MOSFET on
Fault occurs
No fault present
Gx
VDS
tVDQ
tVDQ
tVDQ
tVDQ
Fault Bit
Figure 6b: VDS Fault Monitor – Debounce Mode Timing (VDQ = 0)
13
Allegro MicroSystems
955 Perimeter Road
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
LOGIC TRUTH TABLES
Table 1: Control Logic (Control by Logic Inputs)
Table 2: Control Logic (Control by Serial Register)
HS
0
LSn
1
GH
LO
LO
HI
GL
LO
HI
S
Z
HSR
LSR
GH
LO
LO
HI
GL
LO
HI
S
Z
0
0
1
1
0
1
0
1
0
0
LO
HI
LO
HI
1
1
LO
HI
LO
HI
1
0
HI
HI [1]
HI
HI [1]
HI = high-side FET active
LO = low-side FET active
HI = high-side FET active
LO = low-side FET active
Z = high impedance, both FETs off
All control register bits set to 0, RESETn = 1, ENABLE = 1
Z = high impedance, both FETs off
HS = 0, LSN = 1, RESETn = 1, ENABLE = 1
[1] Load connection assumed between S terminal and drain of
low-side MOSFET.
[1] Load connection assumed between S terminal and drain of
low-side MOSFET.
Table 3: Control combination logic table – Logic Inputs and Serial Register
Terminal Register Internal
Terminal Register Internal
Internal control signals (HI, LO) are derived by combining
the logic states applied to the control input terminals (HS,
LSn) with the bit patterns held in the Control register (HSR,
LSR).
HS
0
HSR
HI
0
LSn
1
LSR
LO
0
0
1
0
1
0
1
0
1
0
1
1
1
Normally the input terminals or the Control register method
is used for control with the other being held inactive (all
termials or bits at logic 0).
1
1
0
1
1
1
0
1
ENABLE
HI
0
LO
0
GH
L
GL
L
S
Z
Comment
1
1
1
1
0
Bridge Disabled
Bridge Sinking
0
1
L
H
L
LO
HI
U [1]
Z
1
0
H
H
L
Bridge Sourcing
Cross-Conduction
Bridge Disabled
1
1
H
L
X
X
RESETn = 1
HI = high-side FET active
LO = low-side FET active
X = don’t care
Z = high impedance, both FETs off
U = undefined, both FETs on
[1] If the MOSFETs are configured as a half bridge the state of S will be undefined.
If the load is connected between the S terminal and drain of low-side MOSFET then S will be HI
14
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
FUNCTIONAL DESCRIPTION
The AMT49502 is a half-bridge (H-bridge) MOSFET driver
(pre-driver) requiring a single unregulated supply of 5.5 to
80 V. It includes an integrated linear regulator to supply the
internal logic. All logic inputs are compatible with 3.3 V logic
(AMT49502KLPTR-3) or 5 V logic (AMT49502KLPTR-5)
depending on part number selection.
decoupled with ceramic capacitors connected close to the supply
and ground terminals.
VBRG: Sense input to the top of the external MOSFET bridge.
Allows accurate measurement of the voltage at the drain of the
high-side MOSFET in the bridge.
CP1, CP2: Pump capacitor connection for charge pump. Con-
nect a ceramic capacitor with a recommended nominal value of
2.2 µF between CP1 and CP2. This should have a rated working
voltage of at least 25 V and a tolerance of ±20% or better.
The two high-current gate drives are capable of driving a wide
range of N-channel power MOSFETs, and are configured as a
half-bridge driver with one high-side drive and one low-side
drive. The AMT49502 provides all necessary circuits to ensure
that the gate-source voltage of both high-side and low-side exter-
nal FETs are above 10 V, at supply voltages down to 7 V. For
extreme battery voltage drop conditions, correct functional opera-
tion is guaranteed at supply voltages down to 5.5 V, but with a
reduced gate drive voltage.
VREG: Regulated voltage, 11 V, used to supply the low-side gate
drivers and to provide current for the above supply charge pump.
A sufficiently large storage capacitor must be connected to this
terminal to provide the required transient charging current.
GND: Analog, digital, and power ground. Connect to supply
Gate drives can be controlled directly through the logic input ter-
minals or through an SPI-compatible serial interface. Fully inde-
pendent control allows both external FETs to be turned on at the
same time. All logic inputs, except RESETn, are standard CMOS
levels and can be compatible with 3.3 V (AMT49502KLPTR-3)
or 5 V (AMT49502KLPTR-5) logic outputs depending on part
number selection. The logic inputs are battery voltage compliant,
meaning they can be shorted to ground or supply without dam-
age, up to the maximum battery voltage of 80 V.
ground–see Layout Recommendations.
C: High-side connection for the bootstrap capacitor and positive
supply for the high-side gate driver.
GH: High-side, gate-drive output for an external N-channel
MOSFET.
S: Source connection for high-side MOSFET providing the nega-
tive supply connections for the floating high-side driver.
GL: Low-side gate-drive output for an external N-channel MOS-
FET.
A low-power sleep mode allows the AMT49502, the power
bridge, and the load to remain connected to a vehicle battery sup-
ply without the need for an additional supply switch.
LSS: Low-side return path for discharge of the capacitance on the
low-side MOSFET gate, connected to the source of the low-side
external MOSFET independently through a low-impedance track.
The AMT49502 includes several diagnostic features to provide
indication and/or protection against undervoltage, overtempera-
ture, and power bridge faults. A single diagnostic output provides
basic fault indication and detailed diagnostic information is avail-
able through the serial interface. The serial interface also provides
access to programmable fault blanking time and programmable
VDS threshold for short detection.
HS: Logic inputs with pull-down to control the high-side gate
drive. Battery voltage compliant terminal.
LSn: Logic input with pull-up to control the low-side gate drive.
Active-low input. Battery voltage compliant terminal.
The AMT49502 includes a low-side current sense amplifier
with programmable gain and offset. The amplifier is specifically
designed for current sensing in the presence of high voltage and
current transients.
ENABLE: Logic input to enable the gate drive outputs. Battery
voltage compliant terminal.
RESETn: Clears latched fault states that may have disabled the
outputs when taken low for the reset pulse width, tRST. Forces
low-power shutdown (sleep) when held low for more than the
RESET shutdown time, tRSD. Battery voltage compliant terminal.
Input and Output Terminal Functions
VBB: Main power supply for internal regulators and charge
pump. The main power supply should be connected to VBB
through a reverse voltage protection circuit and should be
SDI: Serial data logic input with pull-down. 16-bit serial word
input msb first.
15
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
terminals. This capacitor should have a nominal value of 2.2 µF,
rated working voltage of at least 50 V, and a tolerance of ±20%
or better. At supply voltage greater than 14 V, the pump regulator
stops boosting and becomes a linear regulator.
SDO: Serial data output. High impedance when STRn is high.
Outputs bit 15 of the diagnostic register, the fault flag, as soon as
STRn goes low.
SCK: Serial clock logic input with pull-down. Data is latched
in from SDI on the rising edge of SCK. There must be 16 rising
edges per write and SCK must be held high when STRn changes.
The regulated voltage, VREG, is available on the VREG terminal.
A sufficiently large storage capacitor (see Applications section)
must be connected to this terminal to provide the transient charg-
ing current to the low side drivers and the bootstrap capacitors.
STRn: Serial data strobe and serial access enable logic input
with pull-up. When STRn is high, any activity on SCK or SDI
is ignored and SDO is high impedance, allowing multiple SDI
slaves to have common SDI, SCK, and SDO connections.
Gate Drives
The AMT49502 is designed to drive external, low on-resistance,
power N-channel MOSFETs. It will supply the large transient
currents necessary to quickly charge and discharge the external
MOSFET gate capacitance in order to reduce dissipation in the
external MOSFET during switching. The charge current for the
low-side drive is provided by the capacitor on the VREG termi-
nal. The charge current for the high-side drives is provided by
the bootstrap capacitor connected between the C and S terminals.
MOSFET gate charge and discharge rates may be controlled by
setting a group of parameters via the serial interface or by using
an external gate resistor between the gate drive output and the
gate terminal of the MOSFET.
CSP, CSM: Current sense amplifier inputs.
CSO: Current sense amplifier output.
OOS: Monitor point for programmable analogue output offset
voltage applied to current sense amplifiers.
DIAG: Diagnostic output. Provides general fault flag output.
Power Supplies
A single power supply voltage is required. The main power sup-
ply, VBB, should be connected to VBB through a reverse voltage
protection circuit. A 100 nF ceramic decoupling capacitor must
be connected close to the supply and ground terminals.
Operational Configurations
A low power independent internal regulator provides the
supply voltage, VDL, to the internal logic. A second integrated
linear regulator provides the supply voltage, VIO, to all logic
inputs and push-pull outputs. This digital I/O is set to 3.3 V
(AMT49502KLPTR-3) or 5 V (AMT49502KLPTR-5).
The high-side and low-side gate drives are completely indepen-
dent. The AMT49502 permits any combination of active high-
side and low-side MOSFETs and does not provide any lockout
or internally generated dead time. This allows the AMT49502 to
be used in a complemetary half-bridge configuration or to drive
independent high-side and low-side MOSFETs.
All internal logic is guaranteed to operate correctly to below the
regulator undervoltage levels, ensuring that the AMT49502 will
continue to operate safely until all logic is reset when a power-
on-reset state is present.
In a simple half-bridge configuration, this allows more precise
control of the timing of the MOSFET switching. In some circum-
stances, simultaneous activation of both high-side and low-
side MOSFETs can be used to reduce diode conduction during
synchronous rectification, which improves overall efficiency and
reduces electromagnetic emissions. The precise timing and any
required dead time must be provided by the external controller.
The AMT49502 will operate within specified parameters with
VBB from 7 to 80 V and will function correctly with a supply
down to 5.5 V. This provides a rugged solution for use in the
harsh automotive environment.
An example of independent driving is to use one gate drive
output as a PWM control and the other as an on-off control. For
example, the low-side drive can be used to enable current flow
through the load and the high-side drive can be used to provide
PWM current control. This example is shown in Figure 7. The
low-side MOSFET enables or disables the flow of current, and
the high-side MOSFET is used with the low-side recirculation
diode to provide PWM current control.
Pump Regulator
The gate drivers are powered by an internal regulator which
limits the supply to the drivers and therefore the maximum gate
voltage. This regulator uses a charge pump scheme with switch-
ing frequency of 62.5 kHz. At low supply voltage, the regulated
supply is maintained by a charge pump boost converter which
requires a pump capacitor connected between the CP1 and CP2
16
Allegro MicroSystems
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www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
If for any reason the bootstrap capacitor cannot be sufficiently
ꢂꢃAꢄ
charged, a bootstrap fault will occur—see Diagnostics section for
further details.
Note that when the AMT49502 is used in the configuration shown
in Figure 7 with an inductive load, the bootstrap capacitor is
charged in two ways depending on the current flowing in the load.
ꢀontrol
ꢀoad
AMT49502
ꢅSP
or
ꢆꢀ
When no current is flowing in the load, the high-side MOSFET
will be off and the bootstrap capacitor can be charged directly
through the load by turning on the low-side MOSFET. This pro-
cedure should be followed before the first attempt to turn on the
high-side MOSFET.
ꢅiagnostics
ꢀꢁrrent Sense
When current is flowing in the load and is controlled by PWM
switching the high-side MOSFET, the bootstrap capacitor is
charged through the load during a PWM off time. During the
PWM off time, the current will continue to flow through the load
inductance, pulling the voltage at the S terminal to a negative
value in order to forward bias the recirculation diode.
Figure 7: PWM Load current control
Note that in this configuration the low-side VDS monitor should
be disabled by setting the LO bit to 1 in the Mask 1 register. This
is necessary as the reference voltage for the drain of the low-side
MOSFET is the S terminal, which will be pulled to the supply
when the high-side MOSFET is on and will cause a false low-
side VDS fault if the low-side VDS monitor is active.
Top-Off Charge Pump
If the high-side MOSFET is used as an enabling switch—for
example, with a simple resistive load or when using low-side
PWM switching—then once the MOSFET has been switched on,
it will be held in the on state by an additional charge pump in the
AMT49502 referred to as the “top-off” charge pump.
Bootstrap Supply
When the high-side drivers are active, the reference voltage for
the driver will rise to close to the bridge supply voltage. The
supply to the driver will then have to be above the bridge supply
voltage to ensure that the driver remains active. This temporary
high-side supply is provided by a bootstrap capacitor connected
between the bootstrap supply terminal, C, and the high-side refer-
ence terminal, S.
The top-off charge pump will allow the high-side drive to
maintain the gate voltage on the external MOSFET indefinitely
if required. This is a low current trickle charge pump and is only
operated after a high side has been turned on. A small amount of
bias current is drawn from the C terminal to operate the floating
high-side circuit and the charge pump simply provides enough
drive to ensure the bootstrap voltage, and hence the gate voltage,
will not droop due to this bias current.
The bootstrap capacitor is independently charged to approxi-
mately VREG when the associated reference S terminal is low.
When the output swings high, the voltage on the bootstrap supply
terminal rises with the output to provide the boosted gate voltage
needed for the high-side N-channel power MOSFETs.
In some applications, a safety resistor is added between the gate
and source of each MOSFET in the bridge. When a high-side
MOSFET is held in the on state, the current through the associ-
ated high-side gate-source resistor (RGSH) is provided by the high
side driver and therefore appears as a static resistive load on the
top-off charge pump. The minimum value of RGSH for which the
top-off charge pump can provide current, without dropping below
the bootstrap undervoltage threshold, is defined in the Electrical
Characteristics table.
Bootstrap Charge Cycle Considerations
The user must ensure that the bootstrap capacitor does not
become discharged below the bootstrap undervoltage threshold,
VBCUV, or a bootstrap fault will be indicated and the outputs
disabled. This can happen if the S terminal is not low enough
for a long enough period to charge the bootstrap capacitor—for
example, when the PWM duty cycles is very high and the charge
time for the bootstrap capacitor is insufficient to ensure a suffi-
cient recharge to match the MOSFET gate charge transfer during
turn on.
In all cases, the charge required for initial turn-on of the high-side
gate is always supplied by the bootstrap capacitor. If the bootstrap
capacitor becomes discharged, the top-off charge pump alone will
not provide sufficient current to allow the MOSFET to turn on.
17
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955 Perimeter Road
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
High-Side Gate Drive
Gate Drive Control
A high-side gate-drive output for external N-channel MOSFETs is
provided on the GH terminal. GH = 1 (or “high”) means that the
upper half of the driver is turned on and its drain will source cur-
rent to the gate of the high-side MOSFET in the external load-driv-
ing bridge, turning it on. GH = 0 (or “low”) means that the lower
half of the driver is turned on and its drain will sink current from
the external MOSFET’s gate circuit to the S terminal, turning it off.
MOSFET gate drives are controlled according to the values set in
Config 6, 7, and 8 registers.
MOSFET off-to-on transitions are controlled as detailed in Figure
8a. When a gate drive is commanded to turn on a current, I1 (as
defined by IR1[3:0]), is sourced on the GH or GL terminal for a
duration, t1 (defined by TR[3:0]). These parameters should typically
be set to quickly charge the MOSFET input capacitance to the start
of the Miller region as drain-source voltage does not change during
this period. Thereafter the current sourced on GH or GL is set to a
value of I2 (as defined by IR2[3:0]) and remains at this value while
the MOSFET transitions through the Miller region and reaches the
fully on state. For low-side gate drives, the MOSFET fully on state
is defined as the voltage on GL gate drive output rising to a value
within 1 V(typ) of VREG. For the high-side gate drives the MOSFET
fully on state is defined as the voltage on GH gate drive output ris-
ing to a value within 1 V(typ) of the C terminal. I2 should be set to
achieve the required input capacitance charge time. Once in the fully
on state, the GH or GL output switches from current to voltage drive
to hold the MOSFET in the on state.
The reference point for the high-side drive is the load connections,
S. This terminal senses the voltage at the load connections. This
terminal is also connected to the negative side of the bootstrap
capacitor and is the negative supply reference connections for the
floating high-side driver. The discharge current from the high-side
MOSFET gate capacitance flows through these connections which
should have low-impedance traces to the MOSFET bridge.
Low-Side Gate Drive
The low-side gate-drive output on GL is referenced to the LSS
terminal. This output is designed to drive an external N-channel
power MOSFET. GL = 1 (or “high”) means that the upper half of
the driver is turned on and its drain will source current to the gate
of the low-side MOSFET in the external power bridge, turning it
on. GL = 0 (or “low”) means that the lower half of the driver is
turned on and its drain will sink current from the external MOS-
FET’s gate circuit to the LSS terminal, turning it off.
If the values of IR1[3:0] and IR2[3:0] are set to 0, GH or GL
produces maximum drive to turn on the MOSFET as quickly as
possible without attempting to control the MOSFET input capaci-
tance charge time (Figure 8b). The value of TR[3:0] has no effect
on switching speed.
The LSS terminal provides the return path for discharge of the
capacitance on the low-side MOSFET gate. This terminal is
connected independently to the source of the low-side external
MOSFETs through a low-impedance track.
MOSFET on-to-off transitions are controlled as detailed in Figure
8c. When a gate drive is commanded to turn off a current, I1
(as defined by IF1[3:0]), is sunk by the GH or GL terminal for
a duration, t1 (defined by TF[3:0]). These parameters should
typically be set to quickly discharge the MOSFET input capaci-
tance to the start of the Miller region as drain-source voltage
does not change during this period. Thereafter, the current sunk
by GH or GL is set to a value of I2 (as defined by IF2[3:0]) and
remains at this value while the MOSFET transitions through the
Miller region and reaches the fully off state. For the low-side
gate drives, the MOSFET fully off state is defined as the voltage
on the GL gate drive output falling to a value within 1 V(typ)
of LSS. For the high-side gate drives, the MOSFET fully off
is defined as the voltage on the GH gate drive output falling
to a value within 1 V(typ) of the S terminal. I2 should be set to
achieve the required MOSFET input capacitance discharge time.
Once in the fully off condition, the GH or GL output switches
An integrated slew control feature allows the MOSFET gate
charge and discharge rates to be controlled via the serial interface
as detailed in the Gate Drive Control section.
Either the internal slew control or an external resistor between
the gate drive output and the gate connection to the MOSFET (as
close as possible to the MOSFET) can be used to control the slew
rate seen at the gate, thereby controlling the di/dt and dv/dt of the
voltage at the S terminal.
Gate Drive Passive Pull-Down
Each gate drive output includes a discharge circuit to ensure that
any external MOSFET connected to the gate drive output is held
off when the power is removed. This discharge circuit appears as
950 kΩ between the gate drive and the source connections for each from current to voltage drive to hold the MOSFET in the off
MOSFET. It is only active when the AMT49502 is not driving the
state. If the values of IF1[3:0] and IF2[3:0] are set to 0, GH or
output to ensure that any charge accumulated on the MOSFET gate GL produces maximum drive to turn off the MOSFET as quickly
has a discharge path even when the power is not connected.
as possible without attempting to control the MOSFET input
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
capacitance discharge time (Figure 8d). The value of TF[3:0] has
no effect on switching speed.
Logic Control Inputs
Two logic level digital inputs provide direct control for the gate
drives, one for each drive. These are standard CMOS levels refer-
enced to the voltage of the logic I/O regulator. All have a typical
hysteresis of 500 mV to improve noise performance. Each input
can be shorted to the VBB supply, up to the absolute maximum
supply voltage, without damage to the input.
Gate Drive
Command
I
I
2
OFF
ON
State
1
Miller Region
V
GS
Input HS is active high and controls the high-side drive. LSn is
active low and controls the low-side drive. HS has a pull-down
resistor and LSn has a pull-up resistor to ensure an off state
should the control signal become disconnected. The logical rela-
tionship between the inputs and the gate drive outputs is defined
in Table 1.
V
DS
t
Figure 8a: Off-to-On Transition (Gate Drive)
Gate Drive
Command
The gate drive outputs can also be controlled through the serial
interface by setting the appropriate bit in the control register. In
the control register, all bits are active high. The logical relation-
ship between the register bit setting and the gate drive outputs is
defined in Table 2.
OFF
ON
State
V
Miller Region
GS
The logic inputs are combined, using logical OR, with the corre-
sponding bits in the serial interface control register to determine
the state of the gate drive. The logical relationship between the
combination of logic input and register bit setting and the gate
drive outputs is defined in Table 3. In most applications, either
the logic inputs or the serial control will be used. When using
only the logic inputs to control the bridge, the serial register
should be left in the reset condition with all control bits set to 0.
When using only the serial interface to control the bridge, the
inputs should be tied such that the active low inputs are pulled
high and the active high inputs connected to GND, i.e., HS tied to
GND and LSn tied high.
V
DS
Figure 8b: Off-to-On Transition (Switched)
Gate Drive
Command
I
I
2
State
ON
OFF
1
Miller Region
V
GS
V
t
DS
Output Disable
The ENABLE input is connected directly to the gate drive output
command signal, bypassing all gate drive control logic. This can
be used to provide a fast output disable (emergency cutoff).
Figure 8c: On-to-Off Transition (Gate Drive)
Gate Drive
Command
Sleep Mode
State
ON
OFF
RESETn is an active-low input which allows the AMT49502
to enter sleep mode, in which the current consumption from the
VBB supply and internal logic regulator is reduced to its mini-
mum level. When RESETn is held low for longer than the reset
shutdown time, tRSD, the regulator and all internal circuitry is
disabled and the AMT49502 enters sleep mode. In sleep mode,
the latched faults and corresponding fault flags are cleared.
When coming out of sleep mode, the protection logic ensures
V
Miller Region
GS
V
DS
Figure 8d: On-to-Off Transition (Switched)
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AMT49502
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that the gate drive outputs are off until the charge pump reaches
its correct operating condition. The charge pump will stabilize in
approximately 2 ms under nominal conditions.
Diagnostic Monitors
Multiple diagnostic features provide three levels of fault moni-
toring. These include critical protection for the AMT49502,
monitors for operational voltages and states, and detection of the
power bridge and load fault conditions. All diagnostics, except
for POR, serial transfer error, EEPROM fault, and overtempera-
ture, can be masked by setting the appropriate bit in the mask
registers.
To allow the AMT49502 to start up without the need for an exter-
nal logic input, the RESETn terminal can be pulled to VBB with
an external pull-up resistor.
RESETn can also be used to clear any fault conditions without
entering sleep mode by taking it low for the reset pulse width,
tRST. Any latched short detection fault, which disables the out-
puts, will be cleared, as will the serial fault register.
Table 4: Diagnostic Functions
Name
Diagnostic
Level
Current Sense Amplifier
Internal logic supply undervoltage causing
power-on reset
POR
Chip
A programmable gain, differential sense amplifier is provided
to allow the use of low-value sense resistors or current shunt as
a low-side current sensing element. The input common mode
range of the CSP and CSM inputs and programmable output
offset allow below ground current sensing typically required for
low-side current sense in PWM control of motors, or other induc-
tive loads, during switching transients. The output of the sense
amplifier is available at the CSO output and can be used in peak
or average current control systems. The output can drive up to
4.8 V to permit maximum dynamic range with higher input volt-
age A-to-D converters.
SE
EE
OT
TW
Serial transmission error
Chip
Chip
EEPROM error
Chip junction over temperature
High chip junction temperature warning
Chip
Monitor
VBRG supply overvoltage
(Load dump detection)
VSO
Monitor
VSU
VRO
VRU
VLU
OC
VBRG supply Undervoltage
VREG output overvoltage
VREG output undervoltage
Logic I/O regulator undervoltage
Over current
Monitor
Monitor
Monitor
Monitor
Bridge
Bridge
Bridge
Bridge
Bridge
Bridge
Bridge
Bridge
The gain of the sense amplifier is defined by the contents of the
SAG[2:0] variable as:
VBS
HU
Bootstrap undervoltage
SAG
Gain
10
SAG
Gain
30
High-side VGS undervoltage
Low-side VGS undervoltage
High-side VDS overvoltage
Low-side VDS overvoltage
High-side off-state VGS overvoltage
Low-side off-sate VGS overvoltage
0
1
2
3
4
5
6
7
LU
15
35
HO
20
40
LO
25
50
HGO
LGO
The output offset, VOOS, of the sense amplifier is defined by the
contents of the SAO[3:0] variable as:
The fault status is available from the status and diagnostic regis-
ters accessed through the serial interface.
SAO
VOOS
0
SAO
8
VOOS
750 mV
1 V
0
1
2
3
4
5
6
7
0
9
DIAG Output
100 mV
100 mV
200 mV
300 mV
400 mV
500 mV
10
11
12
13
14
15
1.25 V
1.5 V
1.75 V
2 V
The DIAG terminal provides a single diagnostic output signal
that outputs a general logic-level fault flag. DIAG remains low
while any fault except SE or OC is present or if one of the latched
faults has been detected and the general fault flag has not been
reset since then. When the general fault flag is reset, the DIAG
output will be high.
2.25 V
2.5 V
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When power is first applied to the AMT49502, the internal logic is
prevented from operating, and all gate drive outputs are held in the
Status and Diagnostic Registers
The serial interface allows detailed diagnostic information to be
read from the diagnostic registers on the SDO output terminal at
any time.
off state until the internal regulator voltage, VDL, exceeds the logic
supply undervoltage lockout rising (turn-on) threshold. At this
point, all serial control registers will be reset to their power-on state
and all fault states will be reset. The FF bit and the POR bit in the
status register will be set to one to indicate that a power-on-reset
has taken place. Other Diagnostic and Status register bits including
VIO, VREG, and VBB undervoltages may immediately then be set
as a result of startup conditions within the part. It is recommended
A system status register provides a summary of all faults in a
single read transaction. The status register is always output on
SDO when any register is written.
The first bit (bit 15) of the status register contains a common fault
flag, FF, which will be high if any of the fault bits in the status
register have been set. This allows fault condition to be detected
using the serial interface by simply taking STRn low. As soon as
STRn goes low, the first bit in the status register can be read on
SDO to determine if a fault has been detected at any time since
the last fault register reset. In all cases the fault bits in the diag-
nostic registers are latched and only cleared after a fault register
reset.
that the Diagnostic and Status registers are read after VIO, VREG
,
and VBB have settled within their respective operating ranges to
clear any fault indications of this type. The AMT49502 then goes
into its fully operational state and begins operating as specified.
Once the AMT49502 is operational, the internal logic supply
continues to be monitored. If, during the operational state, VDL
drops below logic supply undervoltage lockout falling (turn-
off) threshold, derived from VBBR, then the logical function of
the AMT49502 cannot be guaranteed and the outputs will be
immediately disabled. The AMT49502 will enter a power-down
state and all internal activity, other than the logic regulator volt-
age monitor will be suspended. If the logic supply undervoltage
is a transient event, then the AMT49502 will follow the power-
up sequence above as the voltage rises. As long as VBB remains
above the POR voltage, VBBRmax, the logic within the AMT49502
will remain active.
FF provides an indication that a fault has occurred since the last
fault reset and one or more fault bits have been set.
Note that FF (bit 15) does not provide the same function as the
general fault flag output on the DIAG terminal. The fault flag
output on the DIAG terminal provides an indication that either a
fault is present or the outputs have been disabled due to a latched
fault state. FF provides an indication that a fault has occurred
since the last fault reset and one or more fault bits have been set.
CHIP FAULT STATE: OVERTEMPERATURE
Chip-Level Protection
If the chip temperature rises above the over temperature thresh-
old, TJF, the over temperature bit, OT, will be set in the status
register. If FOT = 1 when an overtemperature is detected, all gate
drive outputs will be disabled automatically. If FOT = 0, then no
circuitry will be disabled and action must be taken by the user to
limit the power dissipation in some way so as to prevent overtem-
perature damage to the chip and unpredictable device operation.
When the temperature drops below TJF by more than the hystere-
sis value, TJFHys, the fault state is cleared, and when FOT = 1, the
outputs re-enabled. The overtemperature bit remains in the status
register until reset.
Chip-wide parameters critical for correct operation of the
AMT49502 are monitored. These include maximum chip tem-
perature, minimum internal logic supply voltage, and the serial
interface transmission. These three monitors are necessary to
ensure that the AMT49502 is able to respond as specified.
CHIP FAULT STATE: INTERNAL LOGIC UNDERVOLTAGE
The AMT49502 has an independent internal logic regulator to
supply the internal logic. This is to ensure that external events,
other than loss of supply, do not prevent the AMT49502 from
operating correctly. The internal logic supply regulator will
continue to operate with a low supply voltage, for example, if the
main supply voltage drops to a very low value during a severe
cold crank event. In extreme low supply circumstances, or during
power-up or power-down, an undervoltage detector ensures that
the AMT49502 operates correctly. The logic supply undervoltage
lockout cannot be masked as it is essential to guarantee correct
operation over the full supply range.
CHIP FAULT STATE: SERIAL ERROR
If there are more than 16 rising edges on SCK or if STRn goes
high and there are fewer than 16 rising edges on SCK or the
parity is not odd, then the write will be cancelled without writing
data to the registers and the SE bit will be set to indicate a data
transfer error. If the transfer is a write, then the status register will
not be reset. If the transfer is a diagnostic register read, then the
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addressed register will not be reset.
up. If FVRU = 1, all gate drives will be low until VREG is greater
than the rising threshold, VRON. If FVRU = 0, the gate drive out-
puts will be active as soon as there is sufficient voltage on VREG
to activate the gate drive outputs.
If a serial error is detected and FSE = 1, then all gate drive
outputs will be driven low (disabled) until the next valid frame is
sent to the AMT49502. If FSE = 0, then no further action will be
taken.
Note that this is sufficient to turn on standard threshold external power
MOSFETs at a battery voltage as low as 5.5 V, but the on-resistance of
the MOSFET may be higher than its specified maximum.
CHIP FAULT STATE: EEPROM
Configuration and calibration information is stored within
internal EEPROM and loaded into working registers to configure
the device at power up. As part of this process, a data integ-
rity check is carried out. If the check returns a single bit error,
automatic error correction is applied and the part starts up. If the
check returns a multiple bit error, all gate drives are disabled, the
general fault flag is set low, and the EEPROM error bit, EE, is set
in the Status register. EEPROM faults can only be cleared by a
power-on-reset (POR).
The VREG undervoltage monitor can be disabled by setting the
VRU bit in the mask register. Although not recommended, setting
VRU to 1 or FVRU to 0 can allow the AMT49502 to operate
below its minimum specified supply voltage level with a severely
impaired gate drive. The specified electrical parameters will not
be valid in this condition.
The output of the VREG regulator is also monitored to detect any
overvoltage applied to the VREG terminal.
If VREG goes above the VREG overvoltage threshold, VROV, the
VREG overvoltage bit, VRO, will be set in the diagnostic regis-
ter. If FVRO = 1, all gate drive outputs go low, the motor drive is
disabled, and the motor coasts. If FVRO = 0, no action is taken
and the outputs are protected from overvoltage by independent
Zener clamps. When VREG falls below VROV by more than the
hysteresis voltage, VROVHys, the fault state is cleared but the VRO
bit remains in the diagnostic register until cleared.
Operational Monitors
Parameters related to the safe operation of the AMT49502 in a
system are monitored. These include parameters associated with
external active and passive components, power supplies, and
interaction with external controllers.
Voltages relating to driving the external power MOSFETs are
monitored, specifically VREG, the bootstrap capacitor voltage,
and the VGS of each gate drive output. The bridge supply voltage,
VBRG, is monitored for both overvoltage and undervoltage events.
MONITOR: TEMPERATURE WARNING
If the chip temperature rises above the temperature warning
threshold, TJW, the hot warning bit, TW, will be set in the status
register and if FTW = 1, all gate drives will be low. If FTW = 0,
gate drives will remain active. When the temperature drops below
TJW by more than the hysteresis value, TJWHys, the fault state is
cleared and the TW bit remains in the status register until reset.
MONITOR: VREG VOLTAGE
The internal charge-pump regulator supplies the low-side gate
driver and the bootstrap charge current. It is critical to ensure that
the regulated voltage, VREG, at the VREG terminal is sufficiently
high before enabling any of the outputs.
If VREG goes below the VREG undervoltage threshold, VROFF
the VREG undervoltage bit, VRU, will be set in the diagnostic
register.
,
MONITOR: VBRG SUPPLY
OVERVOLTAGE AND UNDERVOLTAGE
The main battery voltage supply to the bridge, VBRG, is moni-
tored by the AMT49502 on the VBRG terminal to indicate if
the supply voltage has exceeded its normal operating range (for
example, during a load dump transient). If VBRG rises above the
VBRG overvoltage warning threshold, VBRGOV, then the gen-
eral fault flag will be set, the VSO bit will be set in Diagnostic 2
register, the VS bit (which indicates the logical OR of the VSO
and VSU bits) will be set in the Status register. When VBRG drops
below the falling VBRG overvoltage falling threshold, VBRGOV
– VBRGOVHys, the general fault flag will be cleared but the VSO
and VS bits will remain set until the Diagnostic 2 register is read.
If a VREG undervoltage state is present and FVRU = 1, all
gate drive outputs go low. When VREG rises above the rising
threshold, VRUON, the fault is cleared and, if FVRU = 1, the
gate drive outputs are re-enabled. The VRU bit remains in the
diagnostic register until cleared. If FVRU = 0, fault reporting
will be the same but the gate drive outputs are not disabled and
appropriate action to avoid potential misoperation or damage to
the AMT49502 and/or bridge MOSFETs must be taken by the
external controller.
The VREG undervoltage monitor circuit is active during power
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The VBRG overvoltage warning threshold can be set to one of
two levels using the VPO bit.
OCT[3:0], RS is the sense resistor value in Ω and AV is the sense
amp gain defined by SAG[2:0].
The output from the overcurrent comparator is filtered by an
overcurrent qualifier circuit. This circuit uses a timer to verify
that the output from the comparator is indicating a valid over-
current event. The qualifier can operate in one of two ways,
debounce or blanking, selected by the OCQ bit.
If VBRG falls below the VBRG undervoltage warning threshold,
VBRGUV, then the VSU bit will be set in the Diagnostic 2 regis-
ter and the VS bit (which indicates the logical OR of the VSO
and VSU bits) will be set in the Status register. If FVSU = 1,
the general fault flag will be set and all the drive outputs will be
driven low (disabled) causing the motor to coast. When VBRG
moves above the rising VBRG undervoltage threshold, VBRGUV
+ VBRGUVHys, the general fault flag will be cleared and the gate
drive outputs will be re-enabled but the VSU and VS bits will
remain set until the Diagnostic 2 register is read. If FVSU = 0,
fault reporting will be the same but the gate drive outputs will not
be disabled. The VBRG undervoltage warning threshold can be
set to one of two level using the VPU bit.
In the default debounce mode, a timer is started each time the
comparator output indicates an overcurrent. This timer is reset
when the comparator changes back to indicate normal operation.
If the debounce timer reaches the end of the timeout period, set
by tOCQ, then the overcurrent event is considered valid and the
overcurrent bit, OC, will be set in the Diag 2 register.
In the optional blanking mode, a timer is started when a low-
side gate drive is turned on. The output from the comparator
is ignored (blanked) for the duration of the timeout period, set
by tOCQ. If a comparator output indicates an overcurrent event
when the blanking timer is not active then the overcurrent event
is considered valid and the overcurrent bit, OC, will be set in the
Diag 2 register.
MONITOR: VIO UNDERVOLTAGE
The logic I/O voltage, VIO, is monitored to ensure that the logic
interface voltage is high enough to permit correct operation of
the logic input buffers. If VIO drops below the falling undervolt-
age threshold, VIOOFF, the regulator undervoltage bit, VLU, will
be set in the status register, the general fault flag will be set low,
and all gate drive outputs will be disabled. When VIO rises above
the rising threshold, VIOON, the gate drive outputs will revert to
the commanded state and the general fault flag will be reset. The
VLU fault bit remains in the status register until cleared.
When a valid overcurrent is detected with FOC = 1, the general
fault flag is not affected, all gate drive outputs are driven inactive
(low), and the OC bit is set. If FOC = 0, and an overcurrent is
detected, the general fault flag is not affected, the outputs remain
active, and only the OC bit is set.
Power Bridge and Load Faults
BRIDGE: BOOTSTRAP CAPACITOR UNDERVOLT-
AGE FAULT
BRIDGE: OVERCURRENT DETECT
The AMT49502 monitors the bootstrap capacitor charge volt-
age to ensure sufficient high-side drive. The user must ensure
that the bootstrap capacitor does not become discharged below
the bootstrap undervoltage threshold, VBCUV, or a bootstrap
fault will be indicated and the outputs disabled. This can happen
with very high PWM duty cycles when the charge time for the
bootstrap capacitor is insufficient to ensure a sufficient recharge
to match the MOSFET gate charge transfer during turn on. The
user must also ensure that the bootstrap capacitor is sufficiently
charged before attempting to turn on the high-side MOSFET. If
the bootstrap voltage is below the undervoltage threshold when
the high-side MOSFET is being switched on, then the bootstrap
undervoltage is immediately detected.
The output from the sense amplifier can be compared to an over-
current threshold voltage, VOCT, to provide indication of overcur-
rent events. VOCT, is generated by a 4-bit DAC with a resolution
of 300 mV and defined by the contents of the OC[3:0] variable
and the contents of the SAO[3:0] variable. VOCT is approximately
defined as:
VOCT = [(n + 1) × 300 mV]
where n is a positive integer defined by OCT[3:0]
Any offset programmed on SAO[3:0] is applied to both the cur-
rent sense amplifier output, VCSO, and the Overcurrent threshold,
VOCT, and has no effect on the overcurrent threshold, IOCT. The
relationship between the threshold voltage and the threshold cur-
rent is approximately defined as:
The action taken when a valid bootstrap undervoltage fault is
detected and the fault reset conditions depend on the state of the
FVBU bit.
IOCT = VOCT / (RS × AV)
If FVBU = 0, the fault state will be latched, the bootstrap under-
where VOCT is the overcurrent threshold voltage programmed by
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voltage fault bit in the status register, VBS, will be set, and the
high-side MOSFET will be disabled. The fault state, but not the
bootstrap undervoltage fault bit, will be reset by a low pulse on
the RESETn input or the next time the MOSFET is commanded
to switch on. If the MOSFET is being driven with a PWM signal,
then this will usually mean that the MOSFET will be turned on
again each PWM cycle. If this is the case, and the fault condi-
tion remains, then a valid fault will again be detected and the
sequence will repeat. The fault state will be reset by a low pulse
on the RESETn input, by a serial read of the diagnostic or status
register, or by a power-on reset.
drain of the low-side MOSFET, as shown in Figure 6, the low-
side VDS monitor should be disabled by setting the LO bit to 1 in
the Mask 1 register. This is necessary as the reference voltage for
the drain of the low-side MOSFET is the S terminal which will
be pulled to the supply when the high-side MOSFET is on and
will cause a false low-side VDS fault if the low-side VDS moni-
tor is active.
The drain-source voltage for the high-side MOSFET is measured
between the S terminal and the VBRG terminal. Using the VBRG
terminal rather than the VBB avoids adding any reverse diode
voltage or high-side current sense voltage to the real high-side
drain-source voltage and avoids false VDS fault detection.
If FVBU = 1, the fault will be latched, the associated bootstrap
undervoltage fault bit will be set, and all MOSFETs will be dis-
abled. The fault state will be reset by a low pulse on the RESETn
input, by a serial read of the Diagnostic 2 register, or by a power-
on reset.
The VBRG terminal is an independent sense input to the top of
the MOSFET bridge. It should be connected independently and
directly to the common connection point for the drain of the power
bridge MOSFET at the positive supply connection point in the
bridge. The input current to the VBRG terminal is proportional to
the drain-source threshold voltage, VDST, and is approximately:
The bootstrap undervoltage monitor can be disabled by setting
the VBS bit in the mask register. Although not recommended, this
can allow the AMT49502 to operate below its minimum speci-
fied supply voltage level with a severely impaired gate drive. The
specified electrical parameters may not be valid in this condition.
IVBRG = 72 × VDSTH + 52
where IVBRG is the current into the VBRG terminal in µA and
VDSTH is the drain-source threshold voltage described above.
BRIDGE: MOSFET VDS OVERVOLTAGE FAULT
Note that the VBRG terminal can withstand a negative voltage
up to –5 V. This allows the terminal to remain connected directly
to the top of the power bridge during reverse battery conditions
where the body diodes of the power MOSFETs are used to clamp
the negative voltage.
Faults on the external MOSFETs are determined by monitoring
the drain-source voltage of the MOSFET and comparing it to a
drain-source overvoltage threshold. There are two thresholds:
VDSTH for the high-side MOSFET and VDSTL for the low-side
MOSFET. VDSTH and VDSTL are generated by internal DACs and
are defined by the values in the VTH[5:0] and the VTL[5:0] vari-
ables respectively. These variables provide the input to two 6-bit
DACs with a least significant bit value of typically 50 mV. The
output of the DAC produces the threshold voltage approximately
defined as:
The output from each VDS overvoltage comparator is filtered by
a VDS fault qualifier circuit. This circuit uses a timer to verify
that the output from the comparator is indicating a valid VDS
fault. The duration of the VDS fault qualifying timer, tVDQ, is
determined by the contents of the TVD[9:0] variable. tVDQ is
approximately defined as:
VDSTH = n × 50 mV
tVDQ = n × 100 ns
where n is a positive integer defined by VT[5:0]
where n is a positive integer defined by TVD[9:0].
or:
The qualifier can operate in one of two ways: debounce mode or
blanking mode, selected by the VDQ bit.
VDSTL = n × 50 mV
where n is a positive integer defined by VT[5:0].
In the default debounce mode, a timer is started each time the
comparator output indicates a VDS fault detection when the
corresponding MOSFET is active. This timer is reset when
the comparator changes back to indicate normal operation. If
the debounce timer reaches the end of the timeout period, set
by tVDQ, then the VDS fault is considered valid and the corre-
sponding VDS fault bit, LO or HO, will be set in the diagnostic
register.
The drain-source voltage for the low-side MOSFET is measured
between the D terminal and the LSS terminal. Using the LSS
terminal rather than the ground connection avoids adding any
low-side current sense voltage to the real low-side drain-source
voltage and avoids false VDS fault detection.
When the AMT49502 is used in applications where the load is
connected between the source of the high-side MOSFET and the
24
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
In the optional blanking mode, a timer is started when a gate
drive is turned on. The output from the VDS overvoltage com-
parator for the MOSFET being switched on is ignored (blanked)
for the duration of the timeout period, set by tVDQ. If the com-
parator output indicates an overvoltage event when the MOSFET
is switched on and the blanking timer is not active, then the VDS
fault is considered valid and the corresponding VDS fault bit, LO
or HO, will be set in the diagnostic register.
esis voltage, VGSUVHys, the general fault flags goes inactive. The
fault bits remain in the diagnostic register until cleared.
For the high-side VGS comparator, the VGSUV threshold is set
1 V(typ) below the voltage on the C terminal, and for the low-side
gate comparator, the VGSUV threshold is set 1 V(typ) below VREG
.
The output from each VGS undervoltage comparator is filtered
by a VGS fault qualifier circuit. This circuit uses a timer to verify
that the output from the comparator is indicating a valid VGS
fault. The duration of the VGS fault qualifying timer, tVDQ, is
determined by the contents of the TVD[9:0] variable. tVDQ is
approximately defined as:
The VDQ and TVD[9:0] qualifier parameters apply to the VDS
overvoltage, VGS undervoltage and the off-state VGS overvolt-
age monitors.
If a valid VDS fault is detected, the fault will be latched and the
associated MOSFET will be disabled. This state will remain until
reset depending on the value set in the FDSO bit.
tVDQ = n ×100 ns
where n is a positive integer defined by TVD[9:0].
The qualifier can operate in one of two ways: debounce mode or
blanking mode, selected by the VDQ bit.
If FDSO = 1, the fault state will only be reset by a low pulse on
the RESETn input, by a serial read of the diagnostic register, or
by a power-on reset.
In debounce mode (the default setting), a timer is started each time
the comparator output indicates a VGS fault detection when the
corresponding MOSFET is active. This timer is reset when the
comparator changes back to indicate VGS is within 1 V of the volt-
age on the C terminal (high-side gate drive) or VREG (low-side gate
drive). If the debounce timer reaches the end of the timeout period,
set by tVDQ, then the VGS fault is considered valid.
If FDSO = 0, the fault state, but not the VDS fault bit, will be
reset the next time the MOSFET is commanded to switch on. If
the MOSFET is being driven with a PWM signal, then this will
usually mean that the MOSFET will be turned on again each
PWM cycle. If this is the case, and the fault conditions remains,
then a valid fault will again be detected after the timeout period
and the sequence will repeat. The fault state will be reset by a
low pulse on the RESETn input, by a serial read of the diagnostic
register, or by a power-on reset.
In blanking mode (optional), a timer is started when any gate
drive is turned on. The outputs from the VGS undervoltage com-
parators for all MOSFETs are ignored (blanked) for the duration
of the timer’s active period, set by tVDQ. If any comparator output
indicates a VGS fault and the blanking timer is not active, then
the VGS fault is considered valid.
If FDSO = 0, care must be taken to avoid damage to the MOSFET
where the VDS fault is detected. Although the MOSFET will be
switched off as soon as the fault is detected at the end of the fault
validation timeout, it is possible that it could still be damaged by
excessive power dissipation and heating. To limit any damage to
the external MOSFETs or the load, the MOSFET should be fully
disabled by logic inputs from the external controller.
The VDQ and TVD[9:0] qualifier parameters apply to the VDS
overvoltage, VGS undervoltage, and the off-state VGS overvolt-
age monitors.
BRIDGE: OFF-STATE VGS OVERVOLTAGE
BRIDGE: VGS UNDERVOLTAGE
To ensure that the gate drives are successfully driven low when
requested by the microcontroller, each gate drive output voltage
is independently monitored, when commanded off, to ensure the
voltage, VGS, is below the overvoltage threshold and it is not suf-
ficient to start conduction in the MOSFET.
To ensure that the gate drive output is operating correctly, each
gate drive output voltage is independently monitored, when
active, to ensure the drive voltage, VGS, is sufficient to fully
enhance the power MOSFET in the external bridge.
If VGS on any active gate drive output goes below the gate drive
undervoltage warning, VGSUV, the general fault flag will be active
and the corresponding gate drive undervoltage bit, HU or LU,
will be set in the diagnostic register. If FGSU = 1, all gate drive
outputs will be inactive (low). If FGSU = 0, no other action will
be taken. When VGS rises above VGSUV by more than the hyster-
If VGS on any inactive gate drive output does not fall below the
off-state VGS overvoltage warning, VGSOV, the general fault flag
will be active and the corresponding bit, HGO or LGO, will be
set in Diagnostic 0 register. In addition, the FF and GSO bits will
be set in the Status register. No further action will be taken. The
fault bits remain set in the diagnostic register until cleared.
25
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
For the high-side VGS comparator, the VGSOV threshold is set
1 V(typ) above the voltage on the S terminal, and for the low-side
VGS comparator, the VGSOV is set 1 V(typ) above the voltage on
LSS terminal.
MOSFET FAULT STATE: SHORT TO GROUND
A short from the load connection to ground is detected by moni-
toring the voltage across the high-side MOSFET using the S
terminal and the voltage at VBRG. This drain-source voltage is
then compared to the high-side Drain-Source Threshold Voltage,
VDSTH. If the blanking timer is active, the output from the VDS
overvoltage comparator will be ignored for tVDQ. While the high-
side VDS fault is detected, the VDS fault bit, HO, will be set in
the diagnostic register and the high-side MOSFET will be dis-
abled. When FDSO is set to 1, both MOSFETs will be disabled.
The output from each off-state VGS overvoltage comparator is
filtered by a VGS fault qualifier circuit. This circuit uses a timer
to verify that the output from the comparator is indicating a valid
off-state VGS fault. The duration of the VGS fault qualifying
timer, tVDQ, is determined by the contents of the TVD[9:0] vari-
able. tVDQ is approximately defined as:
Fault Action
tVDQ = n × 100 ns
where n is a positive integer defined by TVD[9:0].
The action taken when one of the diagnostic functions indicates a
fault is listed in Table 5.
The qualifier can operate in one of two ways: debounce mode or
blanking mode, selected by the VDQ bit.
When a fault is detected a corresponding fault state is consid-
ered to exist. In some cases the fault state only exists during the
time the fault is detected. In other cases, when the fault is only
detected for a short time, the fault state is latched (stored) until
reset. The faults that are latched are indicated in table 5. Latched
fault states are always reset when RESETn is taken low, a power-
on-reset state is present or when the associated fault bit is read
through the serial interface. Any fault bits that have been set in
the status or diagnostic register are only reset when a power-
on-reset state is present or when the associated fault bit is read
through the serial interface. RESETn low will not reset the fault
bits in the status or diagnostic registers.
In debounce mode (the default setting), a timer is started each time
the comparator output indicates a VGS fault detection when the
corresponding MOSFET is commanded off. This timer is reset
when the comparator changes back to indicate VGS is within
1 V(typ) of the voltage on the S terminal (high-side) or LSS termi-
nal (low-side). If the debounce timer reaches the end of the timeout
period, set by tVDQ, then the VGS fault is considered valid.
In blanking mode (optional), a timer is started when any gate
drive is turned off. The outputs from the off-state VGS overvolt-
age comparators for both MOSFETs are ignored (blanked) for the
duration of the timer’s active period, set by tVDQ. If any com-
parator output indicates a VGS fault and the blanking time is not
active, then the VGS fault is considered valid.
For most of the diagnostic functions, the action taken when a fault
state is detected can be programmed to force the gate drive outputs
into the inactive (low) state or to leave them active. The action is
selected by a 1 or a 0 in specific stop on fault (SoF) bit associated
with the diagnostic. The specific SoF bits for each diagnostic and
the action taken for each setting are listed in Table 5.
The VDQ and TVD[9:0] qualifier parameters apply to the VGS
undervoltage, VDS overvoltage, and the off-state VGS overvolt-
age monitors.
The fault condition power-on-reset is considered critical to the
safe operation of the AMT49502 and the system. If this fault is
detected, then the gate drive outputs are automatically driven low
and both MOSFETs in the bridge held in the off state. This state
will remain until the fault is removed.
MOSFET FAULT STATE: SHORT TO SUPPLY
A short from the load connections to the battery or VBB connec-
tion is detected by monitoring the voltage across the low-side
MOSFET using the S terminal and the LSS terminal. This drain-
source voltage is then compared to the low-side Drain-Source
Threshold Voltage, VDSTL. If the blanking timer is active, the
output from the VDS overvoltage comparator will be ignored for
tVDQ. While the low-side VDS fault is detected, the VDS fault
bit, LO, will be set in the diagnostic register and the low-side
MOSFET will be disabled. When FDSO is set to 1, both MOS-
FETs will be disabled.
Setting any of the FVRU, FVRO, FVSU, FOT, FTW, FSE, FVBU,
FOC, FDSO, or FGSU bits in the Stop-on-Fault register to 0 such
that the gate drive outputs are not disabled in the event of the cor-
responding fault being detected means that the AMT49502 will not
take any action to protect itself or the external bridge MOSFETs
and damage may occur. Appropriate action must be taken by the
external controller.
26
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
Fault Masks
Individual diagnostics—except power-on reset, EEPROM error,
serial transmission error and over temperature—can be disabled
by setting the corresponding bit in the mask register. Power-on-
reset cannot be disabled because the diagnostics and the output
control depend on the logic regulator to operate correctly. If a bit
is set to one in the mask register, then the corresponding diagnos-
tic will be completely disabled. No fault states for the disabled
diagnostic will be generated and no fault flags or diagnostic bits
will be set. See Mask Register definition for bit allocation. Care
must be taken when diagnostics are disabled to avoid potentially
damaging conditions.
Table 5: Fault Actions
Disable Outputs
Fault
Description
SoF Bit
Name
Fault State
Latched
SoF Bit = 0 SoF Bit = 1
No Fault
–
–
No
Yes [1]
No [3]
No
No
–
Power-on-Reset
Yes [1]
Yes [1]
Yes [1]
Yes [1]
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
Yes
VREG Undervoltage
VREG Overvoltage
VIO Undervoltage
VBRG Overvoltage
VBRG Undervoltage
Overtemperature
FVRU
FVRO
–
Yes [1]
No
–
FVSU
FOT
FTW
FSE
FVBU
FOC
FDSO
FGSU
–
No [3]
No [3]
No
Yes [1]
Yes [1]
Yes [1]
Yes [1]
Yes [1]
Yes [1]
Yes [1]
Yes [1]
No
Temperature Warning
Serial Transmission Error
Bootstrap Undervoltage
Overcurrent
No
Yes [2]
No
VDS Overvoltage
VGS Undervoltage
Off-State VGS Overvoltage
EEPROM
Yes [2]
No [3]
No
–
Yes [1]
Yes [1]
[1] Both gate drives low, both MOSFETs off.
[2] Gate drive to the affected MOSFET low, only the affected MOSFET off.
[3] Stated fault condition may damage the AMT49502 and/or bridge MOSFETs unless
appropriate action taken by the external controller.
27
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL INTERFACE
Table 6: Serial Register Definition*
15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
14
0
0
0
0
1
1
1
1
0
0
0
0
1
1
13
0
0
1
1
0
0
1
1
0
0
1
1
0
0
12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11
10
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0: Not Used
1: Config 1
2: Config 2
3: Config 3
4: Config 4
5: Config 5
6: Config 6
7: Config 7
8: Config 8
WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
0
0
0
0
0
OCT3
0
OCT2
0
OCT1
0
OCT0
1
VTH5
0
VTH4
1
VTH3
1
VTH2
0
VTH1
0
VTH0
0
OCQ
0
VDQ
0
VTL5
0
VTL4
1
VTL3
1
VTL2
0
VTL1
0
VTL0
0
0
0
TVD9
1
TVD8
1
TVD7
1
TVD6
1
TVD5
1
TVD4
1
TVD3
1
TVD2
1
TVD1
1
TVD0
1
VPO
1
VPU
0
0
0
0
0
0
0
0
0
SAO3
1
SAO2
1
SAO1
1
SAO0
1
SAG2
1
SAG1
0
SAG0
1
0
0
0
0
0
0
0
0
0
TR3
0
TR2
0
TR1
0
TR0
1
TF3
0
TF2
0
TF1
0
TF0
1
IR13
0
IR12
0
IR11
0
IR10
0
IF13
0
IF12
0
IF11
0
IF10
0
IR23
0
IR22
0
IR21
0
IR20
0
IF23
0
IF22
0
IF21
0
IF20
0
FVRU
1
FVRO
1
FVSU
1
FOT
1
FTW
1
FSE
1
FVBU
1
FOC
1
FDSO
1
FGSU
1
9: Stop on
Fault
VBS
0
TW
0
HGO
0
LGO
0
HU
0
LU
0
10: Mask 0
11: Mask 1
12: Diag 0
13: Diag 1
0
0
0
0
0
0
0
VRO
0
VRU
0
VSO
0
VSU
0
VLU
0
HO
0
LO
0
0
0
HGO
0
LGO
0
HU
0
LU
0
0
0
0
0
0
0
0
0
VRO
0
VRU
0
HO
0
LO
0
0
0
0
0
0
VSO
0
VSU
0
VBS
0
OC
0
14: Diag 2
1
1
1
0
0
P
0
0
0
0
*Power-on reset value shown below each input register bit.
Continued on the next page...
28
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
Table 6:Serial Register Definition (continued)
15
14
13
12
11
10
0
9
0
8
0
7
0
0
6
0
5
0
4
0
3
0
2
1
0
HSR
0
LSR
0
15: Control
Status
1
1
1
1
WR
P
FF
1
POR
1
SE
0
EE
0
OT
0
TW
0
VS
0
GSO
0
VR
0
VLU
0
OC
0
VBS
0
GSU
0
DSO
0
P
*Power-on reset value shown below each input register bit.
A three-wire synchronous serial interface, compatible with SPI, is fifth bit, WR (D[11]), is the write/read bit. When WR is 1, the
following 10 bits, D[10:1], clocked in from the SDI terminal are
written to the addressed register. When WR is 0, then no data is
written to the serial registers and the contents of the addressed
register are clocked out on the SDO terminal.
used to control the features of the AMT49502. The SDO terminal
can be used during a serial transfer to provide diagnostic feed-
back and readback of the register contents.
The AMT49502 can be operated without the serial interface
using the default settings and the logic control inputs; however,
application-specific configurations are only possible by setting
the appropriate register bits through the serial interface. In addi-
tion to setting the configuration bits, the serial interface can also
be used to control the bridge MOSFETs directly.
The last bit in any serial transfer, D[0], is a parity bit (P) that is
set to ensure odd parity in the complete 16-bit word. Odd parity
means that the total number of 1s in any transfer should always
be an odd number. This ensures that there is always at least one
bit set to 1 and one bit set to 0 and allows detection of stuck-at
faults on the serial input and output data connections. The parity
bit is not stored but generated on each transfer.
The serial interface timing requirements are specified in the Electri-
cal Characteristics table and illustrated in Figure 4. Data is received
on the SDI terminal and clocked through a shift register on the
rising edge of the clock signal input on the SCK terminal. STRn
is normally held high, and is only brought low to initiate a serial
transfer. No data is clocked through the shift register when STRn
is high, allowing multiple slave units to use common SDI and
SCK connections. Each slave then requires an independent STRn
connection. The SDO output assumes a high-impedance state when
STRn is high, allowing a common data readback connection.
In addition to the addressable registers, a read-only status register
is output on SDO for all register addresses when WR is set to 1.
For all serial transfers, the five bits output on SDO will always be
the first five bits from the status register. Register data is output
on the SDO terminal msb first while STRn is low and changes
to the next bit on each falling edge of SCK. The first bit, which
is always the FF bit from the status register, is output as soon as
STRn goes low.
Registers 12, 13, and 14 contain diagnostic fault indicators and
are read-only. If the WR bit for these registers is set to 1, then the
data input through SDI is ignored and the contents of the status
register are clocked out on the SDO terminal then reset as for a
normal write. No other action is taken. If the WR bit for these
registers is set to 0, then the data input through SDI is ignored
and the contents of the addressed register are clocked out on the
SDO terminal and the addressed register is reset.
When 16 data bits have been clocked into the shift register, STRn
must be taken high to latch the data into the selected register.
When this occurs, the internal control circuits act on the new data
and the registers are reset depending on the type of transfer.
If there are more than 16 rising edges on SCK, or if STRn goes
high and there are fewer than 16 rising edges on SCK—either
being described as a framing error—the write will be cancelled
without latching data to the register. The Status register will not
be reset.
If a framing or parity error is detected, the SE bit is set in the
Status register to indicate a data transfer error. This fault condi-
tion can be cleared by a subsequent valid serial write or by a
power-on-reset.
The first four bits, D[15:12], in a serial word are the register
address bits, giving the possibility of 16 register addresses. The
29
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
• IF2[3:0] , a 4-bit integer to set the MOSFET turn-off I2 current
in 8 mA increments.
Configuration Registers
Eight registers are used to configure the operating parameters of
the AMT49502.
Stop On Fault Register
Config 1: Bridge monitor setting:
A register to control whether the gate drive outputs are to remain
enabled or disabled in response to faults. One bit per fault type
defines stop on fault behaviour for VRU, VRO, VSU, OT, TW, SE,
VBS, OC, DSO, and GSU diagnostics.
• OCT[3:0], a 4-bit integer to set the overcurrent threshold volt-
age, VOCT, in 300 mV increments.
• VTH[5:0], a 6-bit integer to set the drain-source threshold
voltage, VDSTH, in 50 mV increments.
Diagnostic Registers
In addition to the read-only status register, five registers provide
detailed diagnostic management and reporting. Two mask registers
allow individual diagnostics to be disabled and three read-only
diagnostic registers provide fault bits for individual diagnostic tests
and monitors. If a bit is set to one in the mask register, then the cor-
responding diagnostic will be completely disabled. No fault states
for the disabled diagnostic will be generated and no fault flags or
diagnostic bits will be set. These bits in the diagnostic registers are
reset on completion of a successful read of the register.
Config 2: Bridge monitor setting:
• OCQ,selectstheovercurrentqualifiermode,blankordebounce.
• VDQ, selects the VDS and VGS qualifier mode, blank or
debounce.
• VTL[5:0], a 6-bit integer to set the low-side drain-source
threshold voltage, VDSTL, in 50 mV increments.
Config 3: Bridge monitor setting:
Mask 0:
• TVD[9:0], a 10-bit integer to set the VDS and VGS fault veri-
fication time, tVDQ, in 100 ns increments.
Individual bits to disable bootstrap undervoltage (VBS), temperature
warning (TW), the VGS undervoltage diagnostic monitors (HU and
LU), and the off-state VGS overvoltage monitors (HGO and LGO).
Config 4: Regulator configuration:
• VPO, selects the VBRG overvoltage warning threshold.
• VPU, selects the VBRG undervoltage threshold.
Config 5: Sense amplifier setting:
Mask 1:
Individual bits to disable the voltage regulator (VRO, VRU,
VSO, VSU, and VIO) and the VDS overvoltage diagnostic moni-
tors (HO and LO).
• SAO[3:0], a 4-bit integer to set the sense amplifier offset up
between 0 and 2.5 V.
Diagnostic 0 (read only):
• SAG[2:0],a3-bitintegertosetthesenseamplifiergainbetween
10 and 50 V/V.
Individual bits indicating faults detected in VGS undervoltage
diagnostic monitors (HU and LU) and off-state VGS overvoltage
monitors (HGO and LGO).
Config 6: Gate drive time setting:
Diagnostic 1 (read only):
• TR[3:0], a 4-bit integer to set the high-side and low-side I1 time
in 16 ns increments.
Individual bits indicating faults detected in voltage regulator
(VRO and VRU) and VDS overvoltage diagnostic monitors (HO
and LO).
• TF[3:0], a 4-bit integer to set the high-side and low-side I1 time
in 16 ns increments.
Diagnostic 2 (read only):
Config 7: Gate drive current setting:
Individual bits indicating faults detected in the VBRG supply
voltage (VSO and VSU), bootstrap undervoltage (VBS), and
overcurrent (OC).
• IR1[3:0] , a 4-bit integer to set the MOSFET turn-on I1 current
in 8 mA increments.
• IF1[3:0] , a 4-bit integer to set the MOSFET turn-off I1 current
in 8 mA increments.
Control Register
The Control register contains one control bit for each MOSFET:
• HSR and LSR, MOSFET Control bits.
Config 8: Gate drive current setting:
• IR2[3:0] , a 4-bit integer to set the MOSFET turn-on I2 current
in 8 mA increments.
30
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AMT49502
80 V Automotive Half-Bridge MOSFET Driver
The first most significant bit in the register is the diagnostic status
flag, FF. This is high if any bits in the status register are set. When
Status Register
There is one status register in addition to the 16 addressable
registers. When any register transfer takes place, the first five
bits output on SDO are always the most significant five bits of
the status register regardless of whether the addressed register is
being read or written (see serial timing diagram).
STRn goes low to start a serial write, the SDO outputs the
diagnostic status flag. This allows the main controller to poll the
AMT49502 through the serial interface to determine if a fault has
been detected. If no faults have been detected, then the serial
transfer may be terminated without generating a serial read fault
by ensuring that SCK remains high while STRn is low. When
STRn goes high, the transfer will be terminated and SDO will go
into its high-impedance state.
The content of the remaining eleven bits will depend on the state
of the WR bit input on SDI. When WR is 1, the addressed register
will be written and the remaining eleven bits output on SDO will
be the least significant ten bits of the status register followed by a
parity bit. When WR is 0, the addressed register will be read and
the remaining eleven bits will be the contents of the addressed
register followed by a parity bit.
The second most significant bit is the POR bit. At power-up or
after a power-on-reset, the FF bit and the POR bit are set, indi-
cating to the external controller that a power-on-reset has taken
place. All other diagnostic bits are reset and all other registers are
returned to their default state. Note that a power-on-reset only
occurs when the output of the internal logic regulator rises above
its undervoltage threshold. Power-on-reset is not affected by the
state of the VBB supply or the VREG regulator output. In general
VIO, VREG, and VBB undervoltages may immediately be set as a
result of startup conditions within the part.
The read-only status register provides a summary of the chip
status by indicating if any diagnostic monitors have detected a
fault. The most significant three bits of the status register (FF,
POR, SE, and EE) indicate critical system faults. Bits OT and
TW provide indicators for specific individual monitors and the
remaining bits are derived from the contents of the three diagnos-
tic registers. The contents and mapping to the diagnostic registers
are listed in Table 7.
The third bit in the status register is the SE bit, which indicates
that the previous serial transfer was not completed successfully.
Table 7: Status Register Mapping
Status
Register
Bit
Related Diagnostic
The fourth bit in the Status register is the EE bit, which indicates
that an EEPROM error was detected at device power-up.
Diagnostic
Register Bits
FF
POR
SE
Status Flag
None
None
Bits OT, TW, and VLU are the fault bits for the two temperature
monitors and the logic I/O regulator monitor, respectively. If one
or more of these faults, along with the POR and SE faults, are
no longer present, then the corresponding fault bits will be reset
following a successful read of the status register. Resetting only
affects latched fault bits for faults that are no longer present. For
any static faults that are still present, for example overtemperature,
the fault flag will remain set after the reset.
Power-On-Reset
Serial Error
None
EE
EEPROM Error
Overtemperature
Temperature Warning
VBRG Monitor
Off-State VGS OV
VREG Monitor
Logic I/O Regulator UV
Overcurrent
None
OT
None
TW
None
VS
VSO, VSU
HGO, LGO
VRU, VRO
None
GSO
VR
The remaining bits, GSO, VS, VR, OC, VBS, GSU, and DSO,
are all derived from the contents of the diagnostic registers and
are only cleared when the corresponding contents of the diagnos-
tic register are read; they cannot be reset by reading the Status
register. A fault indicated on any of the related diagnostic register
bits will set the corresponding status bit to 1. The related diagnos-
tic register must be read to determine the exact fault and clear the
fault if the fault condition has cleared.
VLU
OC
OC
VBS
GSU
DSO
Bootstrap UV
VBS
VGS UV
HU, LU
HO, LO
VDS OV
UV = Undervoltage, OV = Overvoltage
31
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
P
P
P
OCT3
0
OCT2
0
OCT1
0
OCT0
1
VTH5
0
VTH4
1
VTH3
1
VTH2
0
VTH1
0
VTH0
0
1: Config 1
2: Config 2
3: Config 3
4: Config 4
0
0
0
1
WR
WR
WR
WR
VDQ
0
OCQ
0
VTL5 VTL4 VTL3 VTL2 VTL1 VTL0
0
0
1
0
0
0
0
1
1
0
0
0
TVD9
1
TVD8
1
TVD7
1
TVD6
1
TVD5
1
TVD4
1
TVD3
1
TVD2
1
TVD1
1
TVD0
1
0
0
1
1
VPO
1
VPU
0
0
1
0
0
0
0
0
0
0
0
0
0
Config 1
VTL[5:0]
Low-side VDS overvoltage threshold.
OCT[3:0]
Overcurrent threshold.
VDSTL = n × 50 mV
VOCT = (n + 1) × 300 mV
where n is a positive integer defined by VTL[5:0],
e.g. for the power-on-reset condition.
VTL[5:0] = [01 1000] then VDSTL = 1.2 V.
The range of VDSTL is 0 to 3.15 V.
where n is a positive integer defined by OCT[3:0]
e.g. for the power-on-reset condition.
OCT[3:0] = [0001] then VOCT = 0.6 V.
The range of VOCT is 0.3 to 4.8 V.
Config 3
VTH[5:0]
High-side VDS overvoltage threshold.
TVD[9:0]
VDS and VGS verification time.
VDSTH = n × 50 mV
tVDQ = n × 100 ns
where n is a positive integer defined by VTH[5:0],
e.g. for the power-on-reset condition.
VTH[5:0] = [01 1000] then VDST = 1.2 V.
The range of VDST is 0 to 3.15 V.
where n is a positive integer defined by TVD[9:0],
e.g. for the power-on-reset condition.
TVD[9:0] = [11 1111 1111] then tVDQ = 102.3 µs.
The range of tVDQ is 0 to 102.3 µs.
Config 2
Config 4
OCQ
OCQ
0
Overcurrent time qualifier mode.
VPO
VPO
0
VBRG overvoltage warning threshold.
Qualifier
Debounce
Blank
Default
VBRG Overvoltage
Default
D
52 V
58 V
1
1
D
VPU
VPU
0
VBRG undervoltage threshold.
VBRG Undervoltage
VDQ
VDQ
0
VDS and VGS Fault qualifier mode.
Default
VDS Fault Qualifier
Debounce
Blank
Default
20 V
36 V
D
D
1
1
32
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
7
6
5
4
0
3
2
1
0
SAO2
1
SAO3
1
SAO1 SAO0
SAG2 SAG1 SAG0
5: Config 5
0
1
0
1
WR
P
0
1
1
1
0
1
0
Config 2
SAO[3:0] Sense Amp Offset.
Where SAO is a positive integer defined by SAO[3:0].
SAG[2:0] Sense Amp Offset.
Where SAG is a positive integer defined by SAG[2:0].
SAO
0
Offset
Default
SAG
0
Gain
10
15
20
25
30
35
40
50
Default
0 mV
1
0 mV
1
2
100 mV
100 mV
200 mV
300 mV
400 mV
500 mV
750 mV
1.0 V
2
3
3
4
4
5
5
D
6
6
7
7
8
9
10
11
12
13
14
15
1.25 V
1.5 V
1.75 V
2.0 V
2.25 V
2.5 V
D
33
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
P
TR3
0
TR2
0
TR1
0
TR0
1
TF3
0
TF2
0
TF1
0
TF0
1
6: Config 6
7: Config 7
8: Config 8
0
1
1
0
WR
WR
0
0
0
0
0
0
IR13
0
IR12
0
IR11
0
IR10
0
IF13
0
IF12
0
IF11
0
IF10
0
0
1
1
1
IR23
0
IR22
0
IR21
0
IR20
0
IF23
0
IF22
0
IF21
0
IF20
0
1
0
0
0
WR
P
Config 6
Config 8
TR[3:0]
IR2[3:0]
MOSFET turn-on t1 time.
MOSFET turn-on I2 current.
t1 = (n × 16 ns) + 60 ns
I2 = n × –8 mA
where n is a positive integer defined by TR[3:0],
e.g. if TR[3:0] = [0001] then t1 = 76 ns.
The range of t1 is 60 to 300 ns.
where n is a positive integer defined by IR2[3:0],
e.g. if IR2[3:0] = [1000] then I2 = –64 mA.
The range of I2 is –8 to –120 mA.
Selecting a value of 0 will set maximum gate drive to
turn on the MOSFET as quickly as possible.
TF[3:0]
MOSFET turn-off t1 time.
t1 = (n × 16 ns) + 60 ns
IF2[3:0]
MOSFET turn-off I2 current.
where n is a positive integer defined by TF[3:0],
e.g. for the power-on-reset condition.
TF[3:0] = [0001] then t1 = 76 ns.
I2 = n × 8 mA
where n is a positive integer defined by IF2[3:0],
e.g. if IF2[3:0] = [1000] then I2 = 64 mA.
The range of I2 is 8 to 120 mA.
The range of t1 is 60 to 300 ns.
Selecting a value of 0 will set maximum gate drive to
turn on the MOSFET as quickly as possible.
Config 7
IR1[3:0]
MOSFET turn-on I1 current.
I1 = n × –8 mA
where n is a positive integer defined by IR1[3:0],
e.g. if IR1[3:0] = [1000] then I1 = –64 mA
The range of I1 is –8 mA to –120 mA.
Selecting a value of 0 will set maximum gate drive to
turn on the MOSFET as quickly as possible.
IF1[3:0]
MOSFET turn-off I1 current.
I1 = n × 8 mA
where n is a positive integer defined by IF1[3:0],
e.g. if IF1[3:0] = [1000] then I1 = 64 mA.
The range of I1 is 8 to 120 mA.
Selecting a value of 0 will set maximum gate drive to
turn on the MOSFET as quickly as possible.
34
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FVRO
1
FVSU
1
FDSO
1
FGSU
1
FVRU
1
FOT
1
FTW
1
FSE
1
FVBU FOC
9: Stop On
Fault
1
0
1
1
WR
P
1
1
Stop On Fault
VREG Undervoltage
VREG Overvoltage
VBRG Undervoltage
Overtemperature
Temperature Warning
Serial Error
FVRU
FVRO
FVSU
FOT
FTW
FSE
Bootstrap Undervoltage
Overcurrent
FVBU
FOC
VDS Overvoltage
VGS Undervoltage
FDSO
FGSU
35
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
P
VBS
0
TW
0
HU
0
LU
0
HGO
0
LGO
0
10: Mask 0
11: Mask 1
1
0
1
0
WR
WR
0
0
0
0
0
VRU
0
VSO
0
HO
0
LO
0
VRO
0
VSU
0
VLU
0
1
0
1
1
0
0
Mask 0
Mask 1
Bootstrap Undervoltage
Temperature Warning
VREG Overvoltage
VREG Undervoltage
VBRG Overvoltage
VBRG Undervoltage
Logic I/O Undervoltage
VBS
TW
VRO
VRU
VSO
VSU
VLU
HO
High-Side Off-State VGS Overvoltage
Low-Side Of-State VGS Overvoltage
High-Side VGS Undervoltage
HGO
LGO
HU
Low-Side VGS Undervoltage
High-Side VDS Overvoltage
Low-Side VDS Overvoltage
LU
LO
xxx
0
Fault Mask
Default
Fault detection permitted
Fault detection disabled
D
1
36
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
0
7
0
6
5
0
4
3
2
1
0
HU
0
LU
0
HGO
0
LGO
0
12: Diag 0
1
1
0
0
0
P
0
0
0
0
VRU
0
HO
0
LO
0
VRO
0
13: Diag 1
14: Diag 2
1
1
1
1
0
1
1
0
0
0
P
P
0
0
0
0
0
0
0
0
0
0
VSO
0
VSU
0
VBS
0
OC
0
0
Diag 0 (read only)
High-Side Off-State VGS Overvoltage
Low-Side Off-State VGS Overvoltage
High-Side VGS Undervoltage
HGO
LGO
HU
Low-Side VGS Undervoltage
LU
Diag 1 (read only)
VREG Overvoltage
VRO
VRU
HO
VREG Undervoltage
High-Side VDS Overvoltage
Low-Side VDS Overvoltage
LO
Diag 2 (read only)
VBRG Overvoltage
VSO
VSU
VBS
OC
VBRG Undervoltage
Bootstrap Undervoltage
Overcurrent On Sense Amp
xxx
0
Status
No fault detected
Fault detected
1
37
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
HSR
0
LSR
0
15: Control
1
1
1
1
WR
P
0
0
Control
High-side gate drive
Low-side gate drive
HSR
LSR
See Table 2 and Table 3 for control logic operation.
38
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
SERIAL REGISTER REFERENCE (continued)
15
14
13
12
11
10
9
8
7
0
6
5
4
3
2
1
0
FF
1
POR
1
SE
0
EE
0
OT
0
TW
0
VS
0
GSO
0
VR
0
VLU
0
OC
0
VBS
0
GSU
0
DSO
0
Status
(read only)
P
Status (read only)
Status Register Bit Mapping
Diagnostic Register Flag
Power-On-Reset
Serial Error
FF
Status
Register Bit
Related Diagnostic
Register Bits
POR
SE
FF
POR
SE
None
None
Eeprom Fault
EE
None
Overtemperature
OT
EE
None
High Temperature Warning
VBRG Faults
TW
VS
OT
None
TW
None
Off-State VGS Overvoltage
VREG Out Of Range
Logic I/O Regulator Undervoltage
Overcurrent
GSO
VR
VS
VSO, VSU
HGO, LGO
VRU, VRO
None
GSO
VR
VLU
OC
VLU
OC
OC
Bootstrap Undervoltage
VGS Undervoltage
VBS
GSU
DSO
VBS
GSU
DSO
VBS
HU, LU
HO, LO
VDS Overvoltage
U = Undervoltage, O = Overvoltage
xxx
0
Status
No fault detected
Fault detected
1
39
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
APPLICATION INFORMATION
Bootstrap Capacitor Selection
CBOOT × ∆V
tCHARGE
=
The AMT49502 requires a bootstrap capacitor C. To simplify this
description of the bootstrap capacitor selection criteria, generic
naming is used here. So, for example, CBOOT, QBOOT, and VBOOT
refer to the bootstrap capacitor, and QGATE refers to the high-side
MOSFET. CBOOT must be correctly selected to ensure proper
operation of the device—too large and time will be wasted charg-
ing the capacitor, resulting in a limit on the maximum duty cycle
and PWM frequency; too small and there can be a large volt-
age drop at the time the charge is transferred from CBOOT to the
MOSFET gate.
100
where CBOOT is the value of the bootstrap capacitor in nF and ∆V
is the required voltage of the bootstrap capacitor. At power up and
when the drivers have been disabled for a long time, the bootstrap
capacitor can be completely discharged. In this case, ∆V can be
considered to be the full high-side drive voltage, 12 V. Otherwise,
∆V is the amount of voltage dropped during the charge transfer,
which should be 400 mV or less. The capacitor is charged when-
ever the S terminal is pulled low and current flows from the capaci-
tor connected to the VREG terminal through the internal bootstrap
To keep the voltage drop due to charge sharing small, the charge
in the bootstrap capacitor, QBOOT, should be much larger than
QGATE, the charge required by the gate:
diode circuit to CBOOT
.
VREG Capacitor Selection
QBOOT >> QGATE
A factor of 20 is a reasonable value, so
QBOOT = CBOOT × VBOOT = QGATE × 20
The internal reference, VREG, supplies current for the low-side
gate-drive circuits and the charging current for the bootstrap
capacitors. When a low-side MOSFET is turned on, the gate-
drive circuit will provide the high transient current to the gate that
is necessary to turn the MOSFET on quickly. This current, which
can be several hundred milliamperes, cannot be provided directly
by the limited output of the VREG regulator but must be supplied
by an external capacitor, CREG, connected between the VREG
terminal and GND.
or
QGATE × 20
CBOOT
=
VBOOT
where VBOOT is the voltage across the bootstrap capacitor.
The turn-on current for the high-side MOSFET is similar in value
but is mainly supplied by the bootstrap capacitor. However, the
bootstrap capacitor must then be recharged from CREG through
the VREG terminal. Unfortunately, the bootstrap recharge can
occur a very short time after the low-side turn on occurs. This
means that the value of CREG between VREG and GND should
be high enough to minimize the transient voltage drop on
VREG for the combination of a low-side MOSFET turn on and
a bootstrap capacitor recharge. For block commutation control
(trapezoidal drive), where only one high side and one low side
are switching during each PWM period, a minimum value of 20 ×
CBOOT is reasonable. For sinusoidal control schemes, a minimum
value of 40 × CBOOT is recommended. As the maximum work-
ing voltage of CREG will never exceed VREG, the part’s voltage
rating can be as low as 15 V. However, it is recommended that
a capacitor rated to at least twice the maximum working volt-
age should be used to reduce any impact operating voltage may
have on capacitance value. For best performance, CREG should be
ceramic rather than electrolytic. CREG should be mounted as close
to the VREG terminal as possible.
The voltage drop, ∆V, across the bootstrap capacitor as the MOS-
FET is being turned on, can be approximated by:
QGATE
∆V
=
CBOOT
so for a factor of 20, ∆V will be 5% of VBOOT
.
The maximum voltage across the bootstrap capacitor under
normal operating conditions is VREG (max). However in some
circumstances the voltage may transiently reach a maximum of
18 V, which is the clamp voltage of the Zener diode between the
C terminal and the S terminal. In most applications with a good
ceramic capacitor, the working voltage can be limited to 16 V.
Bootstrap Charging
It is necessary to ensure the high-side bootstrap capacitor is com-
pletely charged before a high-side PWM cycle is requested. The time
required to charge the capacitor, tCHARGE, in µs, is approximated by:
40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
• AV = 20 (SAG[2:0] = 0b010)
Current Sense Amplifier Configuration
• VOOS = 1 V (SAO[3:0] = 0b1001)
Amplifier gain, AV, and output offset zero point voltage, VOOS
,
may be set to a range of values by the SAG[2:0] and SAO[3:0]
variables respectively as defined in the Current Sense Ampli-
fiers section above. It is important that both values are selected
to ensure the absolute voltage at the CSO output, VCSO, remains
within the amplifier’s dynamic range, VCSOUT, and the dynamic
range of any downstream signal processing circuitry. Allowance
must be made for both positive and negative current flows within
the sense resistor.
VID ranges between –20 mV and +40 mV and VCSO between
0.6 V and 1.8 V. VCSO remains within the amplifier dynamic
range, VCSOUT, of 0.3 V to 4.8 V. However, if AV is increased
to 50, VCSO attempts to drive to 0 V and 3.0 V, the amplifier
dynamic range limits are not complied with, and the amplifier
output saturates at its negative limit. This situation could be rem-
edied by reducing AV to 30 (0.4 V < VCSO < 2.2 V) or increasing
VOOS to 1.5 V (0.5 V < VCSO < 3.5 V).
With reference to Figure 3, the relationship between phase cur-
rent IPH, sense resistor value, RS, and differential amplifier input
voltage, VID is given by:
Current Sense Amplifier Output Signals
As defined in Figure 3, the current sense amplifier output signals
on the CSO pin is internally referenced to the output offset which
can be made available on the CSO terminal by setting the SAT bit
to 1. The sense amp output voltage and the output offset voltage
may be measured consecutively with respect to ground, and the
values subtracted to give the required output signal voltages as
VID = VCSP – VCSM = IPH × RS
The current sense amplifier’s output voltage on CSO with respect
to the programmed value of output offset is:
VCSD = (VCSP – VCSM) × AV
VCSD = VCSO – VOOS
.
The absolute voltage on CSO when SAT = 1 with respect to
ground is therefore:
The Input Offset Voltage, VIOS, and the associated drift, ΔVIOS
,
VCSO = [(VCSP – VCSM) × AV] + VOOS
multiplied by the selected amplifier gain, AV, represent the offset
and offset drift limits that apply to VCSD. The Output Offset Error
limits, EVO, and Output Offset Drift limits, VOOSD, apply directly
to VOOS. EVO and VOOSD do not affect current sense output
accuracy.
If, for example, the following parameter values are assumed:
• RS = 1 mΩ
• IPH = –20A to +40A
41
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
INPUT/OUTPUT STRUCTURES
ꢂ
ꢄ0 ꢆ
ꢎH
S
90 ꢆ
ꢆꢉRꢎ
ꢆꢉꢉ
ꢂP1
ꢂPꢄ
ꢆRꢊꢎ
ꢇ ꢆ
ꢆRꢊꢎ
ꢅ.5 ꢆ
90 ꢆ
ꢄ0 ꢆ
ꢄ0 ꢆ
90 ꢆ
ꢄ0 ꢆ
ꢄ0 ꢆ
ꢎꢌ
ꢌSS
Figure 9a: Gate Drive Outputs
Figure 9b: Supplies
ꢆꢁꢈ
ꢆꢁꢈ
ꢆꢁꢈ
ꢉꢁAS
50 kΩ
ꢄ kΩ
RꢊSꢊꢋn
ꢄ kΩ
ꢄ kΩ
Sꢀꢁ
ꢊNAꢉꢌꢊ
HS
SꢋRn
Sꢂꢃ
50 kΩ
50 kΩ
ꢅ.5 ꢆ
ꢇ ꢆ
ꢅ.5 ꢆ
ꢇ ꢆ
ꢍ0 ꢆ
Figure 9c: SDI, SCK Inputs
Figure 9d: STRn Inputs
Figure 9e: RESETn, ENABLE, HS Inputs
ꢆꢁꢈ
ꢆꢁꢈ
ꢉꢁAS
50 kΩ
ꢄ kΩ
50 Ω
ꢄ5 Ω
ꢌSn
Sꢀꢈ
ꢀꢁAꢎ
ꢍ0 ꢆ
ꢅ.5 ꢆ
ꢍ0 ꢆ
Figure 9f: SDO Output
Figure 9g: DIAG Output
Figure 9h: LSn Input
ꢇ ꢆ
ꢂSM
ꢂSꢈ
ꢈꢈS
ꢂSP
ꢇ ꢆ
ꢅ.5 ꢆ
ꢅ.5 ꢆ
Figure 9i: CSM, CSP Inputs
Figure 9j: CSO, OOS Outputs
42
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
LAYOUT RECOMMENDATIONS
Careful consideration must be given to PCB layout when design-
ing high-frequency, fast-switching, high-current circuits:
• Supply decoupling should be connected between VREG and
GND as close to the AMT49502 terminals as possible.
• Check the pick voltage excrusion of the transients on the LSS
terminal with reference to the GND terminal using a close-
grounded (‘tip & barrel’) probe. If the voltage at any LSS
terminal exceeds the absolute maximum in the datasheet,
add additional clamping and/or capacitance between the LSS
terminal and the GND terminal.
• The exposed thermal pad should be connected to the GND
terminal.
• Minimize stray inductance by using short, wide copper tracks
at the drain and source terminals of all power MOSFETs. This
includes load lead connections and the input power bus. This
will minimize voltages induced by fast switching of large load
currents.
• Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore the traces from
GH, GL, S, and LSS should be as short as possible to reduce
the track indictance.
• Consider the addition of small (100 nF) ceramic decoupling
capacitor across the source and drain of the power MOSFETs
to limit fast transient voltage spikes caused by track
inductance.
• Provide an independent connection between the LSS terminal
to the source of the low-side MOSFET in the power bridge.
Connection of the LSS terminal directly to the GND terminal
is not recommended as this may inject noise into sensitive
functions such as the various voltage monitors.
• Keep the gate discharge return connections S and LSS
as short as possible. Any inductance on these tracks will
cause negative transitions on the corresponding AMT49502
terminals, which may exceed the absolute maximum ratings. If
this is likely, consider the use of clamping diodes to limit the
negative excursion on these terminals with respect to the GND
terminal.
• A low-cost diode can be placed in the connection to VBB
to provide reverse battery protection. In reverse battery
conditions, it is possible to use the body diodes of the power
MOSFETs to clamp the reverse voltage to approximately 4 V.
In this case, the additional diode in the VBB connection will
prevent damage to the AMT49502 and the VBRG input will
survive the reverse voltage.
• Supply decoupling, typically a 100 nF ceramic capacitor,
should be connected between VBB and GND as close to the
AMT49502 terminals as possible.
ꢍꢁtional reꢎerse
ꢏattery ꢁrotection
ꢃ Sꢀꢁꢁly
ꢇꢈꢈ
ꢇRꢉꢅ
ꢇꢈRꢅ
ꢅH
S
ꢆoad
AMꢊꢋ950ꢌ
ꢅꢆ
ꢆSS
Sꢀꢁꢁly
ꢂommon
RS
ꢅNꢄ PAꢄ
ꢂontroller Sꢀꢁꢁly ꢅroꢀnd
Power ꢅroꢀnd
Figure 10: Supply Routing Suggestions
43
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 ADT)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
7.80 0.10
4.32 NOM
8º
0º
24
0.20
0.09
B
3 NOM 4.40 0.10 6.40 0.20
A
1.00 REF
0.60 0.15
1
2
0.25 BSC
SEATING PLANE
GAUGE PLANE
C
24X
1.20 MAX
SEATING
0.10
C
PLANE
0.30
0.19
0.65 BSC
0.15
0.00
0.45
0.65
1.65
A
B
C
Terminal #1 mark area
Exposed thermal pad (bottom surface); dimensions may vary with device
Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
3.00
6.10
4.32
C
PCB Layout Reference View
Figure 11: Package LP, 24-Lead TSSOP with Exposed Pad
44
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49502
80 V Automotive Half-Bridge MOSFET Driver
Revision History
Number
Date
Description
–
1
March 23, 2020
June 15, 2020
Initial release
Added AEC-Q100 qualification to Features and Benefits (page 1)
Copyright 2020, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
45
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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