AMT49701GEVATR [ALLEGRO]
Quad DMOS Full-Bridge PWM Motor Driver;
| 型号： | AMT49701GEVATR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Quad DMOS Full-Bridge PWM Motor Driver |
| 文件： | 总13页 (文件大小：776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
FEATURES AND BENEFITS
DESCRIPTION
• 18 V output rating
• 4 full bridges
• Dual stepper motor driver
• High-current outputs
• 3.3 and 5 V compatible logic
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Thermal shutdown circuitry
• Crossover-current protection
• Overcurrent protection
• Low-profile QFN package
The AMT49701 is a quad DMOS full-bridge driver capable
of driving up to two stepper motors or four DC motors. Each
full-bridge output is rated up to 1 A and 18 V. The AMT49701
includesfixedoff-timepulse-widthmodulation(PWM)current
regulators, along with 2- bit nonlinear DACs (digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps, and DC motors in forward, reverse, and
coast modes. The PWM current regulator uses the Allegro™
patented mixed decay mode for reduced audible motor noise,
increased step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltagelockout(UVLO)andcrossover-currentprotection.
Special power-up sequencing is not required.
PACKAGE:
Package EV, 36-pin QFN
0.90 mm nominal height
with exposed thermal pad
TheAMT49701issuppliedintheEVpackage,a6 mm × 6 mm,
36-pin QFN package with a nominal overall package height
of 0.90 mm, and with an exposed thermal pad for enhanced
thermal performance. The package is lead (Pb) free, with 100%
matte-tin leadframe plating.
Not to scale
0.1 µF
0.1 µF
VMOTOR 5-12 V
0.22 µF
100 µF
PHASE1
I01
OUT1A
OUT1B
OUT2A
OUT2B
I11
PHASE2
I02
Bipolar Stepper Motors
I12
Microprocessor
OUT3A
OUT3B
OUT4A
OUT4B
PHASE3
I03
AMT49701
I13
PHASE4
I04
SENSE2
I14
RS2
RS1
RS3
RS4
VREF1
VREF2
VREF3
VREF4
VDD
SENSE1
SENSE3
SENSE4
VREF
Figure 1: Typical Application Circuit
AMT49701-DS, Rev. 1
MCO-0000273
September 12, 2018
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
SELECTION GUIDE
Part Number
Package
Packing
AMT49701GEVATR
36-pin QFN package with exposed pad
Tape and reel, 1500 pieces per 7-inch reel
ABSOLUTE MAXIMUM RATINGS
Characteristic
Load Supply Voltage
Output Current
Symbol
Notes
Rating
–0.5 to 18
1.0
Units
VBB
V
A
IOUT
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Logic Input Voltage Range
VIN
–0.3 to 7
0.5
V
V
SENSEx Pin Voltage
VSENSEx
Pulsed tw < 1 µs
Range G
2.5
V
VREFx Pin Voltage
VREFx
TA
2.5
V
Operating Temperature Range
Junction Temperature
–40 to 105
150
°C
°C
°C
TJ(max)
Tstg
Storage Temperature Range
–40 to 125
THERMAL CHARACTERISTICS (may require derating at maximum conditions)
Characteristic
Symbol
Test Conditions
Min. Units
27 °C/W
Package Thermal Resistance
RθJA
EV package, 4-layer PCB based on JEDEC standard
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
EV Package
4-layer PCB
(RθJA = 27 ºC/W)
0
25
50
75
100
125
150
175
Temperature (°C)
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
0.1 µF
0.1 µF
To
VBB2
100 µF
0.22 µF
DMOS
FULL-BRIDGE 1
VCP
VREG
VDD
OSC
CHARGE PUMP
OUT1A
OUT1B
PHASE1
I01
I11
CONTROL LOGIC
BRIDGES 1 AND 2
PHASE2
I02
SENSE1
GATE
DRIVE
DMOS
FULL-BRIDGE 2
I12
Sense1
PWM LATCH
BLANKING
3
VREF1
OUT2A
OUT2B
3
VREF2
PWM LATCH
BLANKING
Sense2
PHASE3
I03
VREG VCP
SENSE2
Sense2
I13
CONTROL LOGIC
BRIDGES 3 AND 4
VBB2
OUT3A
OUT3B
PHASE4
I04
DMOS
FULL-BRIDGE 3
I14
GATE
DRIVE
SENSE3
Sense3
Sense3
3
VBB2
PWM LATCH
BLANKING
VREF3
VREF4
OUT4A
OUT4B
DMOS
FULL-BRIDGE 4
3
PWM LATCH
BLANKING
Sense4
SENSE4
Sense4
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS [1]: Valid at TA = 25°C, VBB = 18 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Logic Supply Voltage Range
Symbol
VBB
Test Conditions
Min.
4.0
3.0
–
Typ. [2]
Max.
18
Units
V
Operating
Operating
–
–
VDD
5.5
430
430
1.2
5
V
Source driver, IOUT = –1 A, TJ = 25°C
Sink driver, IOUT = 1 A, TJ = 25°C
IOUT = 1 A
355
355
–
mΩ
mΩ
V
Output On-Resistance
RDS(on)
–
Vf, Outputs
–
Output Leakage
IDSS
Outputs, VOUT = 0 to VBB
–5
–
µA
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
–
4.0
6.0
mA
VBB Supply Current
IBB
Outputs off
–
–
0.6
5.5
1.0
8.0
mA
mA
VDD Supply Current
IDD
CONTROL LOGIC
VIN(1)
VIN(0)
IIN
2
–
–
–
–
0.8
5
V
V
Logic Input Voltage
Logic Input Current
VIN = 0 to 5 V
–5
150
250
0.7
0.0
–
<1
300
425
1
µA
mV
ns
µs
V
Logic Input Hysteresis
Crossover Delay
Vhys
500
1000
1.3
1.5
±1
5
tCOD
tBLANK
VREFx
IREF
Blank Time
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Operating
–
VREF = 1.5
–
μA
%
VREF = 1.5, phase current = 100%
VREF = 1.5, phase current = 67%
VREF = 1.5, phase current = 33%
–5
–5
–15
–
Current Trip-Level Error [3]
VERR
–
5
%
–
15
%
PROTECTION CIRCUITS
VBB UVLO Threshold
VUV(VBB)
VUV(VBB)hys
VUV(VDD)
VBB rising
VDD rising
3.18
265
2.55
75
3.33
330
2.70
125
–
3.48
415
2.85
175
–
V
mV
V
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
VUV(VDD)hys
mV
A
Overcurrent Protection Threshold
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1.8
155
–
TJTSD
165
15
175
–
°C
°C
TJTSDhys
[1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
[2] Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
[3]
V
= [(VREF/3) – VSENSE] / (VREF/3).
ERR
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Device Operation. The AMT49701 is designed to operate
two stepper motors, four DC motors, or one stepper and two
DC motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse-width-
modulated (PWM) control circuitry. Each full-bridge peak cur-
rent is set by the value of an external current sense resistor, RSx ,
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the time the drivers remain off.
The off-time (toff) is 8.1 µs.
Blanking. This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, tBLANK , is
approximately 1 μs.
and a reference voltage, VREFx
.
Internal PWM Current Control. Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP. Initially, a diagonal pair
of source and sink DMOS outputs are enabled, and current flows
through the motor winding and RSx. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
Control Logic. Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent VREF input, so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
The maximum value of current limiting is set by the selection of
RS and voltage at the VREF input with a transconductance func-
tion, approximated by:
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than VBB to drive the source-side
DMOS gates. A 0.1 μF ceramic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic
capacitor is required between VCP and VBBx to act as a reservoir
to operate the high-side DMOS devices.
I
TripMax = VREF / (3 × RS)
Each current step is a percentage of the maximum current,
I
TripMax. The actual current at each step ITrip is approximated by:
ITrip = (% ITripMax / 100) × ITripMax
Shutdown. In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
where % ITripMax is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of
±500 mV on each SENSEx pin is not exceeded.
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
remainder of the off-time. During transitions from fast decay to
slow decay, the drivers are forced off for approximately 600 ns.
This feature is added to prevent shoot-through in the bridge. As
shown in Figure 2, during this “dead time” portion, synchronous
rectification is not active, and the device operates in fast decay
and slow decay only.
Synchronous Rectification
When a PWM-off cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The AMT49701 synchronous
rectification feature will turn on the appropriate MOSFETs during
the current decay, and effectively short out the body diodes with
the low RDS(on) driver. This significantly lowers power dissipa-
tion. When a zero current level is detected, synchronous rectifica- Overcurrent Protection
tion is turned off to prevent reversal of the load current.
An overcurrent monitor protects the AMT49701 from damage
due to output shorts. If a short is detected, the AMT49701 latches
the fault and disables the outputs. The latched fault can only
be cleared by cycling the power to VBB. During OCP events,
Absolute Maximum Ratings may be exceeded for a short period
of time before outputs are latched off.
Mixed Decay Operation
The bridges operate in mixed decay mode. Referring to Figure
2, as the trip point is reached, the device goes into fast decay
mode for 30.1% of the fixed off-time period. After this fast decay
portion, tFD, the device switches to slow decay mode for the
VPHASE
+
See Enlargement A
IOUT
0
–
Fixed Off-Time 8.1 µs
5.7 µs
2.4 µs
ITrip
IOUT
SDSR
FDSR
FDDT
SDDT
SDDT
AMT4970x
Enlargement A
Figure 2: Mixed Decay Mode Operation
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
STEP SEQUENCING DIAGRAMS
100.0
66.7
100.0
66.7
Phase 1
(%)
Phase 1
(%)
0
0
–66.7
–66.7
–100.0
–100.0
100.0
66.7
100.0
66.7
Phase 2
(%)
Phase 2
(%)
0
0
–66.7
–66.7
–100.0
–100.0
Full step 2 phase
Modified full step 2 phase
Half step 2 phase
Modified half step 2 phase
Figure 3: Step Sequencing for Full-Step Increments
Figure 4: Step Sequencing for Half-Step Increments
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
100.0
66.7
33.3
Phase 1
(%)
0
–33.3
–66.7
–100.0
100.0
66.7
33.3
Phase 2
(%)
0
–33.3
–66.7
–100.0
Figure 5: Step Sequence for Quarter-Step Increments
Table 1: Step Sequencing Settings
Phase 1
(%ITripMax
Phase 2
(%ITripMax)
Full
1/2
1/4
I0x
I1x
PHASE
I0x
I1x
PHASE
)
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
H
H
L
L
L
L
L
H
H
H
L
X
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
L
L
L
H
H
H
L
L
L
L
L
0
0
0
0
X
1
1
1
1
1
1
1
X
0
0
0
1
2
3
4
2
3
4
5
6
7
8
L
L
L
L
H
H
H
L
L
L
L/H*
L
0
33
100/66*
100
H
L
L/H*
L
H
L
*Denotes modified step mode
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
APPLICATIONS INFORMATION
pad and the groundplane directly under the AMT49701, that area
becomes an ideal location for a star ground point.
DC Motor Control. Each of the 4 full bridges has independent
PWM current control circuitry that makes the AMT49701 capa-
ble of driving up to four DC motors at currents up to 500 mA.
Control of the DC motors is accomplished by tying the I0x and
I1x pins together, creating an equivalent ENABLE function with
maximum current defined by the voltage on the corresponding
VREF pin. The DC motors can be driven via a PWM signal on
this enable signal, or on the corresponding PHASE pin. Motor
control includes forward, reverse, and coast.
A low-impedance ground will prevent ground bounce during
high-current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below illustrates how to create a star ground under
the device to serve both as low-impedance ground point and
thermal path.
The two input capacitors should be placed in parallel and as
close to the device supply pins as possible. The ceramic capaci-
tor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high-frequency current components.
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
AMT49701 must be soldered directly onto the board. On the
underside of the AMT49701 package is an exposed pad, which
provides a path for enhanced thermal dissipation. The thermal
pad should be soldered directly to an exposed surface on the
PCB. Thermal vias are used to transfer heat to other layers of the
PCB.
Solder
AMT49701
Trace (2 oz.)
Grounding. In order to minimize the effects of ground bounce
and offset issues, it is important to have a low-impedance single-
point ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
VBB
VBB
CVCP
CIN3
CVCP
GND
CCP
GND
CCP
CIN3
RS1
RS3
1
OUT3A
OUT3B
OUT1A
OUT1B
I04
I13
OUT3A
SENSE3
OUT3B
U1
OUT1A
SENSE1
OUT1B
AMT49701
RS1
RS3
PAD
VBB1
OUT2B
VBB2
OUT4B
CIN1
CIN2
RS4
CIN1
RS2
CIN2
RS4
SENSE2
OUT2A
SENSE4
OUT4A
I14
OUT2B
OUT2A
OUT4B
OUT4A
RS2
PHASE4
GND
Figure 6: Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the AMT49701 (U1)
is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to
the ground plane on the other side of the PCB, so the two copper areas together form the star ground.
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
Sense Pins. The sense resistors, RSx, should have a very low
impedance path to ground, because they must carry a large cur-
rent while supporting very accurate voltage measurements by
the current sense comparators. Long ground traces will cause
additional voltage drops, adversely affecting the ability of the
comparators to accurately measure the current in the windings.
As shown in the layout in Figure 6, the SENSEx pins have very
short traces to the RSx resistors and very thick, low-impedance
traces directly to the star ground beneath the device. If possible,
there should be no other components on the sense circuits.
Note: When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
PINOUT DIAGRAM AND TERMINAL LIST TABLE
Package EV
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
I12
I11
PHASE1
PHASE2
GND
PGND
VCP
CP1
CP2
I01
Package is not to scale
VREF4
VREF3
VREF2
VREF1
VDD
PAD
I02
I03
10 PHASE3
Terminal List Table
Number
2
Pin Name
Pin Description
DMOS Full-Bridge 1 Output A
Sense Resistor Terminal for Bridge 1
DMOS Full-Bridge 1 Output B
Load Supply Voltage
OUT1A
SENSE1
OUT1B
VBB1
3
4
5
6
7
8
9
OUT2B
SENSE2
OUT2A
PHASE4
PHASE3
VDD
VREF1
VREF2
VREF3
VREF4
GND*
PHASE2
PHASE1
FAULTn
I14
DMOS Full-Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full-Bridge 2 Output A
Control Input
Control Input
Logic Supply
Analog Input
Analog Input
Analog Input
Analog Input
Analog and Digital Ground
Control Input
Control Input
Open Drain Fault Output (JP package only)
Control Input
10
11
12
13
14
15
16
17
18
–
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
OUT4A
SENSE4
OUT4B
VBB2
OUT3B
SENSE3
OUT3A
I13
I12
I11
PGND*
VCP
CP1
DMOS Full-Bridge 4 Output A
Sense Resistor Terminal for Bridge 4
DMOS Full-Bridge 4 Output B
Load Supply Voltage
DMOS Full-Bridge 3 Output B
Sense Resistor Terminal for Bridge 3
DMOS Full-Bridge 3 Output A
Control Input
Control Input
Control Input
Power Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Control Input
Control Input
Control Input
CP2
I01
I02
I03
I04
Control Input
Exposed pad for enhanced thermal perfor-
mance. Should be soldered to the PCB.
–
PAD
* GND, PGND, and thermal pad must be connected together externally under the device.
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
EV PACKAGE, 36-PIN QFN WITH EXPOSED THERMAL PAD
0.30
0.50
1.15
6.00 ±0.15
36
36
1
2
1
A
2
6.00 ±0.15
4.15 5.80
C
D
37X
4.15
5.80
SEATING
PLANE
0.08 C
0.90 ±0.10
+0.05
–0.07
0.25
0.50
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VJJD-3, except pin count)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.55 ±0.20
B
A
B
Terminal #1 mark area
4.15
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
2
1
Reference land pattern layout (reference IPC7351
C
QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can
improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
36
4.15
D
Coplanarity includes exposed thermal pad and terminals
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49701
Quad DMOS Full-Bridge PWM Motor Driver
Revision History
Number
Date
Description
–
1
August 30, 2017
Initial release
September 12, 2018 Minor editorial updates
Copyright ©2018, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
13
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955 Perimeter Road
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www.allegromicro.com
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