APS12450LLHALX-0SLA_技术文档

APS12450

2

-

Three-Wire Hall-Effect Latch with Advanced Diagnostics

FEATURES AND BENEFITS

• Functional safety

DESCRIPTION

The APS12450 three-wire planar Hall-effect sensor integrated

circuits(ICs)weredevelopedinaccordancewithISO26262:2011

as a hardware safety element out of context with ASIL B

capability (pending assessment) for use in automotive safety-

related systems when integrated and used in the manner

prescribed in the applicable safety manual and datasheet. The

enhanced three-wire interface provides interconnect open/

short diagnostics and a fault state to communicate diagnostic

information while maintaining compatibility with legacy

three-wire systems. The continuous background diagnostics

are transparent to the host system and results in a reduced

fault tolerant time.

□ Developed in accordance with ISO 26262:2011 to meet

ASIL B requirements (pending assessment)

□ Integrated background diagnostics for:

○ Signal path

○ Regulator

○ Hall plate and bias

○ Overtemperature detection

○ Nonvolatile memory

□ Defined fault state

• Multiple product options

□ Magnetic polarity, switchpoints, and hysteresis

□ Temperature coefficient

□ Output polarity

TheAPS12450productoptionsincludemagneticswitchpoints,

temperature coefficient, and output polarity. The response can

be matched to SmCo, NdFeB, or low-cost ferrite magnets. For

situations where a functionally equivalent three-wire switch

device is preferred, refer to the APS11450.

• Reduces module bill-of-materials (BOM) and assembly cost

□ ASIL B sensor can replace redundant sensors

□ Integrated overvoltage clamp and reverse-battery diode

Continued on the next page…

PACKAGES

TYPICAL APPLICATIONS

• Automotive and industrial safety systems

• Seat/window motors

3-pin SOT23-W (LH)

3-pin ultramini SIP (UA)

• Sun roof/convertible top/tailgate/liftgate actuation

• Brake and clutch by wire actuators

• Engine management actuators

• Electric power steering (EPS)

• Transmission shift actuator

Not to scale

VCC

REGULATOR

To All Subcircuits

Schmitt Output

Low-Pass

Filter

VOUT

(Internal)

O

UTPUT

CONTROL

S

AMPLE, HOLD

&

H

AM^ALP^L

.

SYSTEM DIAGNOSTICS

A

VERAGING

CLOCK LOGIC

GND

Functional Block Diagram

APS12450-DS, Rev. 1

MCO-0000562

April 23, 2019

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

FEATURES AND BENEFITS (continued)

• Automotive-grade ruggedness and fault tolerance

□ Extended AEC-Q100 Grade 0 qualification

○ Operation to 175°C junction temperature

□ 3 to 30 V operating voltage range

DESCRIPTION (continued)

APS12450 sensors are engineered to operate in the harshest

environmentswithminimalexternalcomponents.Theyarequalified

beyond the requirements of AEC-Q100 Grade 0 and will survive

extended operation at 175°C junction temperature.

□ ±8 kV HBM ESD

□ Overtemperature indication

These monolithic ICs include on-chip reverse-battery protection,

overvoltage protection (e.g., 40 V load dump), ESD protection,

overtemperature detection, and an internal voltage regulator for

operation directly from an automotive battery bus. These integrated

features reduce the end-product bill-of-materials (BOM) and

assembly cost.

Packageoptionsincludeindustry-standardsurface-mountSOT(LH)

and through-hole SIP (UA) packages. Both packages are RoHS-

compliantandlead(Pb)freewith100%matte-tin-platedleadframes.

SELECTION GUIDE ^[1]

Magnetic

Operate Point,

B_OP(typ)

Output Polarity

Temperature

Coefficient

Part Number

Package

Packing

(B > B_OP

)

APS12450LLHALX-0SLA

APS12450LLHALT-0SLA

APS12450LUAA-0SLA

APS12450LLHALX-1SLA

APS12450LLHALT-1SLA

APS12450LUAA-1SLA

APS12450LLHALX-3SLA

APS12450LLHALT-3SLA

APS12450LUAA-3SLA

3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel

3-pin SOT23W surface mount

3-pin SIP through-hole

7-in. reel, 3000 pieces/reel

bulk, 500 pieces/bag

Low

0%/°C

22 G

50 G

3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel

3-pin SOT23W surface mount

3-pin SIP through-hole

7-in. reel, 3000 pieces/reel

bulk, 500 pieces/bag

Low

3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel

3-pin SOT23W surface mount

3-pin SIP through-hole

7-in. reel, 3000 pieces/reel

bulk, 500 pieces/bag

150 G

^[1]Contact Allegro MicroSystems for options not listed in the selection guide.

RoHS

COMPLIANT

2

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

ꢀoꢁꢂlete Part

ꢃꢄꢁꢅer ꢆorꢁat

Allegro Iden�ﬁer (Device Family)

APS – Digital Posi�on Sensor

Allegro Device Number

12450 – ASIL B Hall-eﬀect Latch

Conﬁgura�on Op�ons

-

A P S 1 2 4 5 0

L L H A L T 0 S L C

Temperature Coeﬃcient

A – Flat

B – -0.035 %/°C

C – -0.12 %/°C

D – -0.2 %/°C

Output Polarity for B > B_OP

H – High (Output Oﬀ)

L – Low (Output On)

Opera�ng Mode

S – Unipolar South Sensing

N – Unipolar North Sensing

Device Switch Threshold Magnitude

0 – 22 G B_OP, -22 G B_RP(typ.)

1 – 50 G B_OP, -50 G B_RP(typ.)

3 – 150 G B_OP, -150 G B_RP(typ.)

Instruc�ons (Packing)

LT – 7-in. reel, 3,000 pieces/reel (LH Only)

LX – 13-in. reel, 10,000 pieces/reel (LH Only)

TN – 13-in. reel, 4,000 pieces/reel (UA Only)

(no op�on code) – bulk, 500 pieces/bag (UA only)

Package Designa�on

LHA – 3-pin SOT23W Surface Mount

UAA – 3-pin SIP Through-Hole

Ambient Opera�ng Temperature Range

L – -40°C to +150°C

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Notes

Rating

35

Unit

V

Supply Voltage ^[2]

V_CC

V_RCC

Reverse Supply Voltage

Forward Output Voltage

Reverse Output Voltage

Output Current Sink

–30

V

V_OUT

30

V

V_ROUT

I_OUT(SINK)

–0.3

12

V

VCC to VOUT

For 500 hours

mA

°C

165

Maximum Junction Temperature

Storage Temperature

T_J(MAX)

T_stg

175

–65 to 170

^[2]This rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings

specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.

3

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

PINOUT DIAGRAMS AND TERMINAL LIST

3

ꢀ

1

ꢀ

3

1

LH Package, 3-Pin SOT23W Pinout

UA Package, 3-Pin SIP Pinout

Terminal List Table

Pin Number

Name

Function

LH

1

UA

1

VCC

VOUT

GND

Supply voltage

Output

2

3

2

Ground

4

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for T_J< T_J(max),

unless otherwise specified

Characteristics

SUPPLY AND STARTUP

Supply Voltage ^[2]

Symbol

Test Conditions

Min.

Typ. ^[1]

Max.

Unit

V_CC

Operating, T_J< 165°C

3.0

–

30

V

Supply Current

I_CC

4.5

mA

V_CC> V_CC(min), B < B_RP(min) – 10 G,

B > B_OP(max) + 10 G

Power-On Time ^[3]

t_on

–

150

µs

Power-On State

Output Rise Time

Output Fall Time

Output On Voltage

Output Off Voltage

POS

t_RISE

t < t_on(max)

V_OUT(FAULT)

–

2

4

15

30

90

µs

%

See Applications Circuit, Figure 9;

V_PU= V_CC, R_PU= 3 kΩ, C_OUT= 1 nF, I_OUT< 12 mA

t_FALL

V_OUT(LOW)

V_OUT(HIGH)

10

70

20

80

Output ratiometric to V_PU

V_PU= V_CC, τ < 3 µs ^[5], I_OUT< 12 mA

;

Overshoot percentage relative to V_PU(see Figure 8);

V_{OUT(HIGH)OVER}

t_VOUT(H)OVER

–

2

–

5

%

V_PU= V_CC, τ < 3 µs ^[5], I_OUT< 12 mA

Output Off Voltage Overshoot ^[4]

Duration of output voltage overshoot (V_{OUT(HIGH)OVER}

)

µs

ON-BOARD PROTECTION

Fault Reaction Time

t_DIAG

–

25

2

60

–

µs

Diagnostics Fault Retry Time ^[6]

t_DIAGF

ms

Fault Mode Output Voltage

(Fault State)

> V_OUT(HIGH)

V_OUT(FAULT)

V_PU= V_CC, τ < 3 µs, I_OUT< 12 mA

V_PU

–

V

MAX

Overtemperature Shutdown

Overtemperature Hysteresis

T_SD

Temperature increasing

–

205

25

–

°C

T_JHYS

–

^[1]Typical data is at T_A= 25°C and V_CC= 12 V and is for design information only.

[2]

V

represents the voltage between the VCC pin and the GND pin.

CC

^[3]Power-On Time (t_ON) is measured from V_CC= V_CC(min) to 50% of the output transition from V_PUto final value. Adding a bypass capacitor will

increase Power-On Time.

^[4]The overshoot specification pertains only to conditions where the overshoot is greater than the V_OUT(HIGH)MAXspecification.

[5]

τ is the time constant of the RC circuit; τ = R_PU× C_OUT

The diagnostics fault retry repeats continuously until a fault condition is no longer observed. See Diagnostics Mode Operation section for details.

.

[6]

TRANSIENT PROTECTION CHARACTERISTICS: Valid for T_A= 25°C and C_BYP= 0.1 µF, unless otherwise specified

Characteristics

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

PROTECTION

Forward Supply Zener

Clamp Voltage

V_Z

I_CC(max) + 3 mA

35

–

V

Reverse Supply Zener

Clamp Voltage

V_RCC

I_CC= –1 mA

–

–30

–5

V

Reverse Supply Current

I_RCC

V_RCC= –30 V

mA

5

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for T_J< T_J(max),

unless otherwise specified

Characteristics

Symbol

Test Conditions

Min.

–

Typ. ^[1]

0

Max.

–

Unit ^[2]

%/°C

kHz

G

(A) Flat

(B) SmCo

(C) NdFeB

(D) Ferrite

–

–0.035

–0.12

–0.2

10

–

Sensitivity Temperature

Coefficient

Relative to sensitivity

at 25°C

TC_SENS

–

Analog Signal Bandwidth

Operate Point

f_(-3dB)

–

APS12450–0SxA

APS12450–1SxA

APS12450–3SxA

APS12450–0SxA

APS12450–1SxA

APS12450–3SxA

APS12450–0SxA

APS12450–1SxA

APS12450–3SxA

B_OP+ B_RP

5

22

40

90

180

–5

–15

–100

80

180

360

30

–

B_OP

15

100

–40

–90

–180

10

30

200

-30

–

50

G

150

–22

–50

–150

45

G

Release Point

Hysteresis

B_RP

G

B_HYS

100

300

–

G

Symmetry

Jitter ^[3]

B_SYM

–

G

B_OP= 22 G, B = 100 G_PK-PK, 1000 Hz

0.25

%

^[1]Typical data is at T_A= 25°C and V_CC= 12 V, unless otherwise noted; for design information only.

^[2]1 G (gauss) = 0.1 mT (millitesla).

^[3]Output edge repeatability as a percentage of the period.

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions*

Value

Unit

Package LH, on 1-layer PCB based on JEDEC standard

228

110

165

°C/W

Package Thermal Resistance

R_θJA

Package LH, on 2-layer PCB with 0.463 in.²of copper area each side

Package UA, on 1-layer PCB with copper limited to solder pads

°C/W

*Additional thermal information available on the Allegro website.

6

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

CHARACTERISTIC PERFORMANCE DATA

V_OUT(HIGH)vs. T_A

V_OUT(HIGH)vs. V_CC

90

88

86

84

82

80

78

76

74

72

70

88

86

84

82

80

78

76

74

72

70

T_A(°C)

-40

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

V

_OUT(LOW)vs. T_A

V_OUT(LOW)vs. V_CC

30

28

26

24

22

20

18

16

14

12

10

30

28

26

24

22

20

18

16

14

12

10

T_A(°C)

-40

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

V_OUT(FAULT)vs. T_A

V

_OUT(FAULT)vs. V_CC

102

100

98

102

100

98

96

T_A(°C)

-40

94

V_CC(V)

92

25

3

150

30

90

0

5

10

15

20

25

30

35

-50

-20

10

40

70

100

130

160

Supply Voltage, V_CC(V)

Ambient Temperature, T_A(°C)

t_DIAGFvs. T_A

t_DIAGFvs. V_CC

4

3.5

3

4

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

T_A(°C)

-40

V_CC(V)

3

25

0.5

0

0.5

0

30

150

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

7

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

CHARACTERISTIC PERFORMANCE DATA (continued)

I_CCvs. T_A

I_CCvs. V_CC

4.5

4

3.5

3

3.5

3

2.5

2

2.5

2

V_CC(V)

3

T_A(°C)

-40

1.5

1

1.5

1

12

24

30

25

0.5

0

0.5

0

150

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

t_onvs. T_A

t_RISE& t_FALLvs. T_A

150

135

120

105

90

15

12.5

10

7.5

5

75

60

45

30

2.5

0

Fall

15

Rise

0

-50

-20

10

40

70

100

130

160

-50

-20

10

40

70

100

130

160

Ambient Temperature, T_A(°C)

8

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

CHARACTERISTIC PERFORMANCE DATA

APS12450–0SxA

B_{OP(0S_A)}vs. T_A

B_{OP(0S_A)}vs. V_CC

40

35

30

25

20

15

10

5

35

30

25

20

15

10

5

T_A(°C)

-40

V_CC(V)

3

25

30

150

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{RP(0S_A)}vs. T_A

B_{RP(0S_A)}vs. V_CC

-5

T_A(°C)

-40

-10

-15

-20

-25

-30

-35

-40

-10

-15

-20

-25

-30

-35

-40

25

150

V_CC(V)

3

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{HYS(0S_A)}vs. T_A

B_{HYS(0S_A)}vs. V_CC

80

70

60

50

40

30

20

10

80

70

60

50

40

30

20

10

T_A(°C)

-40

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{SYM(0S_A)}vs. T_A

B_{SYM(0S_A)}vs. V_CC

25

20

15

10

5

25

20

15

10

5

0

-5

T_A(°C)

-40

-10

-15

-20

-25

-10

-15

-20

-25

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

9

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

CHARACTERISTIC PERFORMANCE DATA

APS12450–1SxA

B_{OP(1S_A)}vs. T_A

B_{OP(1S_A)}vs. V_CC

90

82.5

75

82.5

75

67.5

60

67.5

60

52.5

45

52.5

45

T_A(°C)

-40

37.5

30

37.5

30

V_CC(V)

3

25

22.5

15

22.5

15

30

150

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{RP(1S_A)}vs. T_A

B_{RP(1S_A)}vs. V_CC

-15

-22.5

-30

-15

-22.5

-30

T_A(°C)

-40

25

-37.5

-45

-37.5

-45

150

-52.5

-60

-52.5

-60

-67.5

-75

-67.5

-75

V_CC(V)

3

-82.5

-90

-82.5

-90

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{HYS(1S_A)}vs. T_A

B_{HYS(1S_A)}vs. V_CC

180

155

130

105

80

180

155

130

105

80

T_A(°C)

-40

V_CC(V)

3

55

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{SYM(1S_A)}vs. T_A

B_{SYM(1S_A)}vs. V_CC

25

20

15

10

5

25

20

15

10

5

0

-5

T_A(°C)

-40

-10

-15

-20

-25

-10

-15

-20

-25

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

10

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

CHARACTERISTIC PERFORMANCE DATA

APS12450–3SxA

B_{OP(3S_A)}vs. T_A

B_{OP(3S_A)}vs. V_CC

180

170

160

150

140

130

120

110

100

170

160

150

140

130

120

110

100

T_A(°C)

-40

V_CC(V)

3

25

30

150

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{RP(3S_A)}vs. T_A

B_{RP(3S_A)}vs. V_CC

-100

-110

-120

-130

-140

-150

-160

-170

-180

-100

-110

-120

-130

-140

-150

-160

-170

-180

T_A(°C)

-40

25

150

V_CC(V)

3

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{HYS(3S_A)}vs. T_A

B_{HYS(3S_A)}vs. V_CC

360

340

320

300

280

260

240

220

200

360

340

320

300

280

260

240

220

200

T_A(°C)

-40

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

B_{SYM(3S_A)}vs. T_A

B_{SYM(3S_A)}vs. V_CC

25

20

15

10

5

25

20

15

10

5

0

-5

T_A(°C)

-40

-10

-15

-20

-25

-10

-15

-20

-25

V_CC(V)

3

25

150

30

-50

-20

10

40

70

100

130

160

0

5

10

15

20

25

30

35

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

11

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

FUNCTIONAL DESCRIPTION

Figure 1 shows the output switching behavior relative to increas-

ing and decreasing magnetic field. On the horizontal axis, the

B+ direction indicates increasing south polarity magnetic field

strength. Figure 2 shows the sensing orientation of the magnetic

field, relative to the device package.

Operation

The output of these devices switches when a magnetic field perpen-

dicular to the Hall-effect sensor exceeds the operate point threshold

(B_OP). When the magnetic field is reduced below the release point

(B_RP), the device output switches to the alternate state. The output

state (polarity) and magnetic field polarity depends on the selected

device options. The device is a latch, therefore B_OPand B_RPwill be

in opposite magnetic field polarities.

Note that this device latches; that is, a south pole of sufficient

strength towards the branded face of the device turns the device

on, and the device remains on with removal of the south pole.

The difference between operate (B_OP) and release (B_RP) points is

the hysteresis (B_HYS). Hysteresis allows clean switching of the

output even in the presence of external mechanical vibration and

electrical noise. The hysteresis is set to double the programmed

operating point.

Figure 1 shows the potential unipolar and omnipolar options and

output polarity options of the APS12450 that can be configured.

The direction of the applied magnetic field is perpendicular to the

branded face of the APS12450 (see Figure 2).

Standard Polaritꢁ

ꢀnverted Polaritꢁ

ꢅꢄ

ꢅ_{ꢃUꢆꢇHꢊꢋHꢉ}

ꢅ_{ꢃUꢆꢇꢀꢃꢈꢉ}

ꢁ-

ꢇnorthꢉ

0

ꢁꢄ

ꢇsoꢌthꢉ

ꢁꢍ

ꢇnorthꢉ

0

ꢁꢄ

ꢇsoꢌthꢉ

ꢁ_HꢂS

Figure 1: Hall latch magnetic and output polarity options

B- indicates increasing north polarity magnetic ﬁeld strength, and

B+ indicates increasing south polarity magnetic ﬁeld strength.

Y

X

A

B

Z

Figure 2: Magnetic Sensing Orientations

APS12450 LH (Panel A), APS12450 UA (Panel B)

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

FUNCTIONAL SAFETY

The APS12450 was developed in accordance with ISO 26262:2011 The signal path monitoring system verifies two internal state

transitions (B_OPand B_RPwithin limits) under normal operation.

In cases when these output transitions do not occur, or if another

internal fault is detected, the output will go to the fault state (see

“Three-Wire Diagnostic Output” section).

as a hardware safety element out of context with ASIL B capability

(pending assessment) for use in automotive safety-related systems

when integrated and used in the manner prescribed in the appli-

cable safety manual and datasheet.

In the event of an internal fault, the device will continuously run

the diagnostics routine every 2 ms (t_DIAGF). The periodic recov-

ery attempt sequence allows the device to continually check for

the presence of a fault and return to normal operation if the fault

condition clears.

Diagnostics Mode Operation

The APS12450 features a proprietary diagnostics routine that

meets ASIL B safety requirements (pending assessment). This

internal diagnostics routine continuously runs in the background,

monitoring all key subsystems of the IC. These subsystems are

shown in Table 1 and Figure 3. The diagnostic scheme runs at

high speed and provides minimal impact on device performance.

Signal path diagnostics are injected and measured in less than

2 μs, while all other diagnostics are running in real time in the

background. The Hall element biasing circuit and voltage regula-

tor are checked for valid operation, and the digital and non‐vola-

tile memory blocks are checked for valid device configuration.

In the case where the fault is no longer present, the output will

resume normal operation. However, if the fault is persistent, the

device will not exit fault mode and the output voltage will con-

tinue to be V_OUT(FAULT)

.

When a system rating higher than ASIL B is required, additional

external safety measures may be employed (e.g., sensor redun-

dancy and rationality checks, etc.). Refer to the device safety

manual for additional details about the diagnostics.

Table 1: Diagnostics Coverage

Feature

Coverage

1

2

3

4

5

6

Hall plate

Connectivity and biasing of Hall plate

Signal path

Signal path and Schmitt trigger

Voltage regulator

Digital subsystem

Entire system

Output

Regulator voltage for normal operation

Digital subsystem and non-volatile memory

Overtemperature and redundancies for single point failures

Output verified through valid regulations states (external monitor)

VCC

3

5

REGULATOR

To All Subcircuits

Schmitt Output

(Internal)

Low-Pass

Filter

VOUT

4

1

2

S

6

O

UTPUT

AMPLE, HOLD

&

H

AM^ALP^L

.

CONTROL

SYSTEM

D

IAGNOSTICS

A

VERAGING

CLOCK LOGIC

GND

Figure 3: Diagnostics Coverage Block Diagram

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

Power-On Behavior

Temperature Coefficient and Magnet Selection

During Power-on, the output voltage is in the fault state

(V_OUT(FAULT)), which is the pull-up voltage (V_PU), until the

device is ready to respond appropriately to the input magnetic

field (t > t_ON). If the device powers-on with the field within the

hysteresis band, the output will switch from V_OUT(FAULT)to the

off state (V_OUT(HIGH)) with standard output polarity as shown in

Figure 4. For inverted output polarity operation, the output will

switch from V_OUT(FAULT)to V_OUT(LOW)(not shown).

The APS12450 allows the user to select the magnetic temperature

coefficient to compensate for drifts of SmCo, NdFeB, and ferrite

magnets over temperature, as indicated in the Magnetic Char-

acteristics specifications table. This compensation improves the

magnetic system performance over the entire temperature range.

For example, the magnetic field strength from NdFeB decreases

as the temperature increases from 25°C to 150°C. This lower

magnetic field strength means that a lower switching threshold

is required to maintain switching at the same distance from the

magnet to the sensor. Correspondingly, higher switching thresh-

olds are required at cold temperatures, as low as –40°C, due to

the higher magnetic field strength from the NdFeB magnet. The

APS12450 compensates the switching thresholds over tempera-

ture as described above. It is recommended that system design-

ers evaluate their magnetic circuit over the expected operating

temperature range to ensure the magnetic switching requirements

are met.

ꢀ

POS

V_{OUT(FAULT )}

B ꢁ B_RP

B_RPꢁ B ꢁ B_OP

V_OUT(HIGH)

Output Undeﬁned for V_CCꢁ V_CC(MIꢀ)

V_OUT(LOW)

B ꢂ B_OP

t

ꢀ

V_CC(MIꢀ)

A sample calculation is provided in the “Applications Informa-

tion” section.

0

t_Oꢀ

Figure 4: Power-On Sequence

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

V_PULL-UPof 5 V, the output state levels will be 1.0 V and 4.0 V

Three-Wire Diagnostic Output

±0.5 V. The output RC time constant (τ) must be less than 3 µs

(e.g., R_PU= 3 kΩ and C_OUT= 1 nF), and V_PUmust be equal to

V_CC(recommend pulling up V_OUTdirectly to V_CC).

Three-wire diagnostic output enables the user to identify various

fault conditions external to the IC, in addition to the internal fault

detection. The output low (V_OUT(LOW)) and high (V_OUT(HIGH)

)

Under normal operation (Figure 5), the output switches between

the V_OUT(LOW)(20%) and V_OUT(HIGH)(80%) states.

states are ratiometric to the pull-up voltage, with low and high

states being 20% and 80% respectively. For example, a V_CCand

ꢀ_{ꢂUꢃꢊꢑAUꢆꢃ ꢌ}ꢊꢀ_PU

ꢌ

ꢀ_{ꢂUꢃꢊHꢋꢄHꢌ}ꢊꢍ0ꢎꢌ

R_PUꢆꢆ-UP

ꢀꢁꢁ

ꢄNꢅ

ꢁ_ꢇꢈPASS

ꢀꢂUꢃ

ꢀ_{ꢂUꢃꢊꢆꢂꢏꢌ}ꢊꢐ0ꢎꢌ

ꢄNꢅ

Normal

ꢂꢉeration

ꢁ_ꢂUꢃ

Figure 5: The APS12450 diagnostic output under normal operation (no fault detected)

With various opens and shorts on any of the IC pins, the output

Any output voltage levels outside of the valid V_OUT(HIGH)and

V_OUT(LOW)ranges indicates a fault as shown in Figure 6. The

observed voltage on VOUT relative to potential fault conditions

are summarized in Table 2.

will no longer be controlled by the IC. The output itself may

continue to switch, depending on the external connectivity fault;

however, the output level(s) observed will deviate from the 20%

and 80% (of V_PU) output levels.

The output relative to the fault condition is summarized in Table 2

below.

If an internal fault is detected via diagnostics monitoring, the

output will be set to the fault state, V_OUT(FAULT), which is equal

Table 2: Fault Conditions and Resulting Output

Level

to the pull-up voltage, V_PU

.

Fault

Output Level

ꢀ V

20% or 80% of V_PU

,

V_{OUT(FAULT )}

No Fault

V_PUꢃ V_CC

respectively

Fault State

Range ꢁor valiꢂ V_OUT(HIGH)

External Fault

Short, VCC-VOUT

Short, VOUT-GND

Short, VCC-GND

Open, VCC

V_CC

GND

V_PU

V_OUT(HIGH)(max)

V_OUT(HIGH)(min)

90% V_PU

70% V_PU

V_OUT(LOW)(max)

V_OUT(LOW)(min)

0

30% V_PU

10% V_PU

Open, VOUT

Range ꢁor valiꢂ V_OUT(LOW)

External Fault

Open, GND

Internal Fault

Note: V_OUT(FAULT)≤ V_PULL-UPand V_PULL-UP= V_CC

.

Figure 6: APS12450 valid (normal) and

fault condition output levels

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

Fault Detection and Retry

The fault detection diagnostics runs continuously in the background

during normal operation after the device has powered-on. In the

event a fault is detected, the output will immediately change to the

V_OUT(FAULT)state. The diagnostics will continue to retry the diag-

nostics approximately every 2 ms. If the fault recovers, the output

will return to normal operation. See Figure 7.

V_{OUT(FAULT )}

V_OUT(HIGH)

Output switcꢀes accorꢁing

to external magne�c ﬁeld

Output switcꢀes accorꢁing

to external magne�c ﬁeld

V_{OUT(LOW )}

t

Bacꢂgrounꢁ

Diagnos�csꢃ

Bacꢂgrounꢁ

Diagnos�csꢃ

2 ms

t

Failure Detecteꢁ

Device Recovers

Diag Retryꢃꢃ

ꢃ

4x Diagnos�c Cycles completed every 0.025 ms (nom.)

ꢃꢃ Diagnos�c Fault Retry Time interval is 2 ms (nom.)

Figure 7: Fault Detection and Retry

this condition is not out of specification. The Output Off Voltage

Overshoot specification pertains only to conditions where the over-

shoot is greater than the V_OUT(HIGH)MAXspecification.

Output Overshoot

When the output switches from V_OUT(LOW)to V_OUT(HIGH)

,

depending upon the RC circuit, a small overshoot can occur

(V_OUT(H)OVER). V_OUT(H)OVERis specified as a percentage of

V_PULL-UP(and/or V_CC, which need to be the same). Therefore

with an RC Time Constant (τ) of 3 µs (see the “Applications

Information” section), a nominal overshoot of 2% is possible.

With V_PULL-UPat 5.0 V, the output may overshoot by 0.1 V, for

less than 5 µs (t_VOUT(H)OVER). Figure 7 demonstrates output edge

profile.

For example, with a 5 V pull-up, if V_OUT(HIGH)is at the upper limit

(90%), V_OUT(HIGH)will be 4.5 V. With a τ of 3 µs at room tem-

perature, the output can briefly reach 4.6 V until it settles to 4.5 V.

Since V_OUT(HIGH)is valid between 70% and 90%, or 3.5 and 4.5 V,

Figure 8: Output Overshoot

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

APPLICATIONS INFORMATION

Temperature Compensation

Typical Applications

For the LH and UA packages, an external bypass capacitor,

C_BYP, should be connected (in close proximity to the Hall sen-

sor) between the supply and ground of the device to reduce both

external noise and noise generated by the chopper stabilization

technique. As is shown in Figure 9, a 0.1 µF bypass capacitor is

typical, with an optional output capacitor, C_OUT(recommended

1 nF).

To calculate the typical effect of the TC_SENSon B_OP(or B_RP),

simply multiply the B_OPat the starting temperature by TC_SENS

and the change in temperature.

Sample B_OPcalculation for TC_SENScompensation from 25°C to

150°C, for TC_SENS= –0.12%/°C, and B_OP(25C)= 180 G:

ΔT_A= 150°C – 25°C = 125°C

B_OP(150C)= B_OP(25C)+ (B_OP(25C)× TC × ΔT_A)

= 180 G + (180 G × –0.12%/°C × 125°C)

= 180 G + (–27 G)

The time constant of the RC circuit (τ) on output must be less

than 3 µs, where:

τ

= R_PULLUP× C_OUT

= 3 kΩ × 1 nF

= 3 µs

= 153 G

The resistor, R_PULLUP, must be between 2 and 30 kΩ.

ꢈ_PUꢋꢋ-UP

ꢈ_ꢁꢁ

Diagnostic Output*

R_SꢓRꢀꢓS

ꢊoꢄtionalꢍ

V_CC

V_PU

3 to 30 V

V_CC

R_PUꢋꢋ-UP

ꢈꢁꢁ

C_BYP

C_OUT

R_PU

0.1 µF

ꢓꢁU

τ_RC< 3 µs

ꢈꢂUꢉ

ꢁ_ꢏꢐPASS

0.1 ꢑꢒ

Aꢆꢁ

I_OUT< 12 mA

τ_RC< 3 µs

2 kΩ < R < 30 kΩ

ꢎPꢀꢂ

ꢁ_ꢂUꢉ

ꢊoꢄtionalꢍ

ꢎNꢆ

R_S

100 Ω*

ꢀꢁ ꢂꢃtꢄꢃtꢅ ꢆiagnostic ꢂꢃtꢄꢃt

switching ꢇetween ꢈ_{ꢂUꢉꢊꢋꢂꢌꢍ}and ꢈ_{ꢂUꢉꢊHꢀꢎHꢍ}

* The following application circuit conditions are required

• The τ of the RC on output must be < 3 µs.

• 2 kΩ < R_PU< 30 kΩ.

• V_PU= V_CC(recommend pulling VOUT up

to VCC).

Figure 9: Typical Applications Circuits

Diagnostic Output

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

Extensive applications information on magnets and Hall-effect

sensors is available in:

• Hall-Effect IC Applications Guide, AN27701

• Guidelines For Designing Subassemblies Using Hall-Effect

Devices, AN27703.1

• Soldering Methods for Allegro’s Products – SMT and Through-

Hole, AN26009

• Functional Safety Challenges to the Automotive Supply Chain

(https://www.allegromicro.com/en/Design-Center/Technical-

Documents/General-Semiconductor-Information/Functional-

Safety-Challenges-Automotive-Supply-Chain.aspx)

All are provided on the Allegro website:

www.allegromicro.com

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

Chopper Stabilization Technique

A limiting factor for switchpoint accuracy when using Hall-

effect technology is the small-signal voltage developed across

the Hall plate. This voltage is proportionally small relative to the

offset that can be produced at the output of the Hall sensor. This

makes it difficult to process the signal and maintain an accurate,

reliable output over the specified temperature and voltage range.

Chopper stabilization is a proven approach used to minimize

Hall offset.

subsequent demodulation acts as a modulation process for the

offset causing the magnetically induced signal to recover its origi-

nal spectrum at baseband while the DC offset becomes a high-

frequency signal. Then, using a low-pass filter, the signal passes

while the modulated DC offset is suppressed. Allegro’s innovative

chopper-stabilization technique uses a high-frequency clock.

The high-frequency operation allows a greater sampling rate that

produces higher accuracy, reduced jitter, and faster signal pro-

cessing. Additionally, filtering is more effective and results in a

lower noise analog signal at the sensor output. Devices such as the

APS12450 that use this approach have an extremely stable quies-

cent Hall output voltage, are immune to thermal stress, and have

precise recoverability after temperature cycling. This technique is

made possible through the use of a BiCMOS process which allows

the use of low offset and low noise amplifiers in combination with

high-density logic and sample-and-hold circuits.

The technique, dynamic quadrature offset cancellation, removes

key sources of the output drift induced by temperature and

package stress. This offset reduction technique is based on a

signal modulation-demodulation process. “Figure 10: Model of

Chopper Stabilization Circuit (Dynamic Offset Cancellation)”

illustrates how it is implemented.

The undesired offset signal is separated from the magnetically

induced signal in the frequency domain through modulation. The

Regulator

Clock/Logic

Low-Pass

Filter

Hall Element

Amp

Figure 10: Model of Chopper Stabilization Circuit

(Dynamic Oﬀset Cancellation)

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

POWER DERATING

The device must be operated below the maximum junction

temperature, T_J(max). Reliable operation may require derating

supplied power and/or improving the heat dissipation properties

of the application.

Finally, using equation 1, solve for maximum allowable V_CCfor

the given conditions:

V

_CC(est) = P_Dꢀ(max)ꢀ÷ꢀI_CCꢀ(max)ꢀ=ꢀ91ꢀmWꢀ÷ꢀ4ꢀmAꢀ=ꢀ22.8ꢀV

The result indicates that, at T_A, the application and device can

Thermal Resistance (junction to ambient), R_θJA, is a figure of

merit summarizing the ability of the application and the device to

dissipate heat from the junction (die), through all paths to ambi-

ent air. R_θJAis dominated by the Effective Thermal Conductivity,

K, of the printed circuit board which includes adjacent devices

and board layout. Thermal resistance from the die junction to

case, R_θJC, is a relatively small component of R_θJA. Ambient air

temperature, T_A, and air motion are significant external factors in

determining a reliable thermal operating point.

dissipate adequate amounts of heat at voltages ≤ V_CC(est).

If the application requires V_CC> V_CC(est)then R_θJAmust by

improved. This can be accomplished by adjusting the layout,

PCB materials, or by controlling the ambient temperature.

Determining Maximum T_A

In cases where the V_CC(max) level is known, and the system

designer would like to determine the maximum allowable ambi-

ent temperature T_A(max), for example, in a worst-case scenario

with conditions V_CC(max) = 40 V, I_CC(max) = 4 mA, and R_θJA

= 228°C/W for the LH package using equation 1, the largest pos-

sible amount of dissipated power is:

The following three equations can be used to determine operation

points for given power and thermal conditions.

P_D= V_IN× I_IN

∆Tꢀ=ꢀP_D× R_θJA

T_J= T_Aꢀ+ꢀ∆Tꢀꢀ

(1)

(2)

(3)

ꢀ

P_D= V_IN× I_IN

P_D= 40 V × 4 mA = 160 mW

Then, by rearranging equation 3 and substituting with equation 2:

For example, given common conditions: T_A= 25°C, V_CC= 12 V,

I

_CC= 4 mA, and R_θJA= 110°C/W for the LH package, then:

T_A(max) = T_Jꢀ(max)ꢀ–ꢀΔT

P_D= V_CC× I_CC= 12 V × 4 mA = 48 mW

T_A(max) = 165°C – (160 mW × 228°C/W)

ꢀ

∆Tꢀ=ꢀP_D× R_θJA= 48 mW × 110°C/W = 5.28°C

T_J= T_Aꢀ+ꢀ∆Tꢀ=ꢀ25°Cꢀ+ꢀ5.28°Cꢀ=ꢀ31.28°C

T_Aꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ36.5°Cꢀ=ꢀ128.5°C

In another example, the maximum supply voltage is equal to

V

_CC(min). Therefore, V_CC(max) = 3 V and I_CC(max) = 4 mA.

Determining Maximum V_CC

By using equation 1 the largest possible amount of dissipated

power is:

For a given ambient temperature, T_A, the maximum allow-

able power dissipation as a function of V_CCcan be calculated.

P_D(max) represents the maximum allowable power level without

exceeding T_J(max) at a selected R_θJAand T_A.

P_D= V_IN× I_IN

P_Dꢀ=ꢀ3ꢀVꢀ×ꢀ4ꢀmAꢀ=ꢀ12ꢀmW

Example: V_CCat T_A= 150°C, package UA, using low-K PCB.

Then, by rearranging equation 3 and substituting with equation 2:

Using the worst-case ratings for the device, specifically: R_θJA

=

T_A(max) = T_Jꢀ(max)ꢀ–ꢀΔT

165°C/W, T_J(max) = 165°C, V_CC(max) = 24 V, and I_CC(max) =

4 mA, calculate the maximum allowable power level, P_D(max).

First, using equation 3:

T_A(max) = 165°C – (12 mW × 228°C/W)

T_Aꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ11.6°Cꢀ=ꢀ162.3°C

∆Tꢀ(max)ꢀ=ꢀT_J(max) – T_A= 165°C – 150°C = 15°C

The example above indicates that at V_CC= 3 V and I_CC= 4 mA,

the T_A(max) can be as high as 162.3°C without exceeding

T_J(max). However the T_A(max) rating of the device is 150°C;

the device performance is not guaranteed above T_A= 150°C.

This provides the allowable increase to T_Jresulting from internal

power dissipation. Then, from equation 2:

P_Dꢀ(max)ꢀ=ꢀ∆Tꢀ(max)ꢀ÷ꢀR_θJAꢀ=ꢀ15°Cꢀ÷ꢀ165°C/Wꢀ=ꢀ91ꢀmW

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Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

Package LH, 3-Pin SOT23W

ꢭꢀꢁꢔꢐꢂ

ꢮꢀꢁꢕꢂ

ꢐꢁꢓꢕꢂ

ꢚ

ꢔꢁꢖꢓ

ꢖꢯꢟꢖꢯ

ꢱ

A

ꢭꢀꢁꢀꢐꢀ

ꢮꢀꢁꢀꢂꢱ

ꢀꢁꢔꢞꢀ

ꢚ

ꢀꢁꢓꢳ

ꢚ

ꢭꢀꢁꢔꢀ

ꢐꢁꢓꢀ

ꢭꢀꢁꢔꢓ

ꢮꢀꢁꢀꢳ

ꢐꢁꢖꢀ

ꢔꢁꢓꢔ

ꢮꢀꢁꢐꢀ

ꢀꢁꢕꢀ

ꢀꢁꢐꢂ MIꢲ

ꢔꢁꢀꢀ

ꢐ

ꢔ

ꢀꢁꢂꢂ ꢃꢄꢅ

ꢀꢁꢐꢂ ꢑꢍꢒ

ꢀꢁꢓꢂ

ꢊꢒꢑ ꢩꢆꢣꢤꢇꢎ ꢃꢉꢡꢉꢙꢉꢌꢗꢉ Vꢏꢉꢪ

ꢍꢉꢆꢎꢏꢌꢈ ꢊꢋꢆꢌꢉ

Gꢆꢇꢈꢉ ꢊꢋꢆꢌꢉ

ꢑ

ꢑꢙꢆꢌꢢꢉꢢ ꢅꢆꢗꢉ

ꢞꢰ ꢔꢀꢯ ꢟꢂꢯ

ꢔꢁꢀꢀ ꢟꢀꢁꢔꢱ

ꢭꢀꢁꢔꢀ

XXX

ꢔ

ꢀꢁꢀꢂ

ꢮꢀꢁꢀꢂ

ꢒ

ꢍꢎꢆꢌꢢꢆꢙꢢ ꢑꢙꢆꢌꢢꢏꢌꢈ ꢃꢉꢡꢉꢙꢉꢌꢗꢉ Vꢏꢉꢪ

ꢀꢁꢓꢂ ꢑꢍꢒ

ꢀꢁꢖꢀ ꢟꢀꢁꢔꢀ

ꢩꢏꢌꢉ ꢔ ꢫ Tꢜꢙꢉꢉ ꢢꢏꢈꢏꢎ ꢆꢥꢥꢏꢈꢌꢉꢢ ꢬꢙꢆꢌꢢ ꢌꢇꢠꢬꢉꢙ

ꢅꢤꢙ ꢙꢉꢡꢉꢙꢉꢌꢗꢉ ꢤꢌꢋꢣꢧ ꢌꢤꢎ ꢡꢤꢙ ꢎꢤꢤꢋꢏꢌꢈ ꢇꢥꢉ (ꢙꢉꢡꢉꢙꢉꢌꢗꢉ ꢚꢴGꢵꢀꢀꢀꢀꢳꢐꢞꢝ ꢃꢉꢘꢁ ꢔ)ꢁ

ꢚꢏꢠꢉꢌꢥꢏꢤꢌꢥ ꢏꢌ ꢠꢏꢋꢋꢏꢠꢉꢎꢉꢙꢥꢁ

ꢚꢏꢠꢉꢌꢥꢏꢤꢌꢥ ꢉꢶꢗꢋꢇꢥꢏꢘꢉ ꢤꢡ ꢠꢤꢋꢢ ꢡꢋꢆꢥꢜꢝ ꢈꢆꢎꢉ ꢬꢇꢙꢙꢥꢝ ꢆꢌꢢ ꢢꢆꢠꢬꢆꢙ ꢛꢙꢤꢎꢙꢇꢥꢏꢤꢌꢥꢁ

ꢄꢶꢆꢗꢎ ꢗꢆꢥꢉ ꢆꢌꢢ ꢋꢉꢆꢢ ꢗꢤꢌꢡꢏꢈꢇꢙꢆꢎꢏꢤꢌ ꢆꢎ ꢥꢇꢛꢛꢋꢏꢉꢙ ꢢꢏꢥꢗꢙꢉꢎꢏꢤꢌ ꢪꢏꢎꢜꢏꢌ ꢋꢏꢠꢏꢎꢥ ꢥꢜꢤꢪꢌꢁ

Aꢗꢎꢏꢘꢉ Aꢙꢉꢆ ꢚꢉꢛꢎꢜꢝ ꢀꢁꢐꢞ ꢟꢀꢁꢀꢖ ꢠꢠ

A

ꢑ

ꢃꢉꢡꢉꢙꢉꢌꢗꢉ ꢋꢆꢌꢢ ꢛꢆꢎꢎꢉꢙꢌ ꢋꢆꢣꢤꢇꢎ

Aꢋꢋ ꢛꢆꢢꢥ ꢆ ꢠꢏꢌꢏꢠꢇꢠ ꢤꢡ ꢀꢁꢐꢀ ꢠꢠ ꢡꢙꢤꢠ ꢆꢋꢋ ꢆꢢꢦꢆꢗꢉꢌꢎ ꢛꢆꢢꢥꢧ ꢆꢢꢦꢇꢥꢎ ꢆꢥ ꢌꢉꢗꢉꢥꢥꢆꢙꢣ

ꢎꢤ ꢠꢉꢉꢎ ꢆꢛꢛꢋꢏꢗꢆꢎꢏꢤꢌ ꢛꢙꢤꢗꢉꢥꢥ ꢙꢉꢨꢇꢏꢙꢉꢠꢉꢌꢎꢥ ꢆꢌꢢ ꢊꢒꢑ ꢋꢆꢣꢤꢇꢎ ꢎꢤꢋꢉꢙꢆꢌꢗꢉꢥ

ꢒ

ꢚ

ꢑꢙꢆꢌꢢꢏꢌꢈ ꢥꢗꢆꢋꢉ ꢆꢌꢢ ꢆꢛꢛꢉꢆꢙꢆꢌꢗꢉ ꢆꢎ ꢥꢇꢛꢛꢋꢏꢉꢙ ꢢꢏꢥꢗꢙꢉꢎꢏꢤꢌ

Hꢆꢋꢋ ꢉꢋꢉꢠꢉꢌꢎꢝ ꢌꢤꢎ ꢎꢤ ꢥꢗꢆꢋꢉ

21

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

Package UA, 3-Pin SIP, Matrix HD Style

ꢳꢆꢃꢆꢣ

ꢇꢃꢆꢵ

ꢴꢆꢃꢆꢈ

ꢇꢈꢉ

ꢌ

ꢊ

ꢟ

ꢀꢃꢆꢇ ꢅOM

ꢂꢃꢈꢀ ꢋꢆꢃꢆꢈ

ꢂꢆꢉ

ꢂꢃꢇꢇ ꢅOM

ꢟ

Mꢘꢚꢑ ꢟꢯꢏꢠꢎꢘꢔ

ꢰꢒꢐ Iꢐꢑꢏꢐꢎ

ꢳꢆꢃꢆꢣ

ꢴꢆꢃꢆꢈ

ꢁꢃꢆꢀ

ꢇꢈꢉ

ꢌꢔꢍꢐꢑꢏꢑ

ꢥꢍꢠꢏ

XXX

ꢆꢃꢄꢵ ꢫꢟꢥ

A

ꢂꢃꢆꢀ

MAX

ꢂ

ꢮꢎꢍꢐꢑꢍꢔꢑ ꢌꢔꢍꢐꢑꢒꢐꢤ ꢫꢏꢦꢏꢔꢏꢐꢠꢏ Vꢒꢏꢭ

ꢖ

ꢱꢒꢐꢏ ꢂꢲ ꢱꢘꢤꢘ A

ꢱꢒꢐꢏ ꢀꢲ Tꢡꢔꢏꢏ ꢑꢒꢤꢒꢎ ꢍꢜꢜꢒꢤꢐꢏꢑ ꢓꢔꢍꢐꢑ ꢐꢕꢗꢓꢏꢔ

ꢂ

ꢀ

ꢁ

ꢂꢇꢃꢵꢵ ꢋꢆꢃꢀꢈ

ꢳꢆꢃꢆꢁ

ꢴꢆꢃꢆꢝ

ꢆꢃꢇꢂ

ꢥꢘꢔ ꢔꢏꢦꢏꢔꢏꢐꢠꢏ ꢘꢐꢚꢧꢨ ꢐꢘꢎ ꢦꢘꢔ ꢎꢘꢘꢚꢒꢐꢤ ꢕꢜꢏ (ꢔꢏꢦꢏꢔꢏꢐꢠꢏ ꢖꢩGꢪꢆꢆꢆꢆꢇꢆꢇꢢ ꢫꢏꢙꢃ ꢂ)ꢃ

ꢖꢒꢗꢏꢐꢜꢒꢘꢐꢜ ꢒꢐ ꢗꢒꢚꢚꢒꢗꢏꢎꢏꢔꢜꢃ

ꢖꢒꢗꢏꢐꢜꢒꢘꢐꢜ ꢏꢬꢠꢚꢕꢜꢒꢙꢏ ꢘꢦ ꢗꢘꢚꢑ ꢦꢚꢍꢜꢡꢢ ꢤꢍꢎꢏ ꢓꢕꢔꢔꢜꢢ ꢍꢐꢑ ꢑꢍꢗꢓꢍꢔ ꢛꢔꢘꢎꢔꢕꢜꢒꢘꢐꢜꢃ

ꢟꢬꢍꢠꢎ ꢠꢍꢜꢏ ꢍꢐꢑ ꢚꢏꢍꢑ ꢠꢘꢐꢦꢒꢤꢕꢔꢍꢎꢒꢘꢐ ꢍꢎ ꢜꢕꢛꢛꢚꢒꢏꢔ ꢑꢒꢜꢠꢔꢏꢎꢒꢘꢐ ꢭꢒꢎꢡꢒꢐ ꢚꢒꢗꢒꢎꢜ ꢜꢡꢘꢭꢐꢃ

ꢳꢆꢃꢆꢈ

ꢴꢆꢃꢆꢄ

ꢆꢃꢇꢁ

ꢖꢍꢗꢓꢍꢔ ꢔꢏꢗꢘꢙꢍꢚ ꢛꢔꢘꢎꢔꢕꢜꢒꢘꢐ (ꢝꢞ)

Gꢍꢎꢏ ꢍꢐꢑ ꢎꢒꢏ ꢓꢍꢔ ꢓꢕꢔꢔ ꢍꢔꢏꢍ

A

ꢀ

ꢁ

ꢖ

Aꢠꢎꢒꢙꢏ Aꢔꢏꢍ ꢖꢏꢛꢎꢡꢢ ꢆꢃꢈꢆ ꢋꢆꢃꢆꢣ ꢗꢗ

ꢌꢔꢍꢐꢑꢒꢐꢤ ꢜꢠꢍꢚꢏ ꢍꢐꢑ ꢍꢛꢛꢏꢍꢔꢍꢐꢠꢏ ꢍꢎ ꢜꢕꢛꢛꢚꢒꢏꢔ ꢑꢒꢜꢠꢔꢏꢎꢒꢘꢐ

Hꢍꢚꢚ ꢏꢚꢏꢗꢏꢐꢎ (ꢐꢘꢎ ꢎꢘ ꢜꢠꢍꢚꢏ)

ꢟ

ꢂꢃꢀꢄ ꢅOM

22

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Three-Wire Hall-Effect Latch with Advanced Diagnostics

APS12450

REVISION HISTORY

Number

Date

Description

–

1

January 31, 2019

April 23, 2019

Initial release

Updated ASIL status

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit

improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor

for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

23

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com


型号：	APS12450LLHALX-0SLA
厂家：	ALLEGRO MICROSYSTEMS
描述：	Three-Wire Hall-Effect Latch with Advanced Diagnostics 输出元件传感器换能器
文件：	总23页 (文件大小：1158K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

APS12450LLHALX-0SLA [ALLEGRO]

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