UCN5816EP [ALLEGRO]

4-TO-16 LINE LATCHED DECODER/DRIVERS; 4至16线锁存译码器/驱动器
UCN5816EP
型号: UCN5816EP
厂家: ALLEGRO MICROSYSTEMS    ALLEGRO MICROSYSTEMS
描述:

4-TO-16 LINE LATCHED DECODER/DRIVERS
4至16线锁存译码器/驱动器

驱动器
文件: 总4页 (文件大小:90K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
5816  
4-TO-16 LINE  
LATCHED DECODER/DRIVERS  
The UCN5816A and UCN5816EP 4-to-16 line latched decoder/  
drivers combine low-power CMOS inputs and logic with 16 high-  
current, high-voltage bipolar outputs. The CMOS inputs cause minimal  
loading and are compatible with standard CMOS, PMOS, and NMOS  
logic. TTL or DTL circuits may require the use of appropriate pull-up  
resistors to ensure an input logic high. The logic operates over a  
supply range of 5 V to 12 V. A CHIP ENABLE function can be used  
with two devices for 5-to-32 line decoding applications.  
UCN5816EP  
DIODE  
COMMON  
0-7  
IN  
LATCHES  
25  
5
6
7
8
A
K
DIODE  
COMMON  
8-15  
OUT  
0
24  
23  
K
OUT  
15  
OUT  
1
The 16 bipolar power outputs are open-collector 60 V Darlington  
drivers capable of sinking 350 mA continuously. Internal transient-  
suppression diodes provide protection for use with inductive loads.  
For ink-jet printer applications, the A5817SEP addressable 28-line  
decoder/driver is recommended.  
OUT  
14  
22  
OUT  
2
DECODER  
21 OUT  
13  
12  
11  
OUT  
OUT  
9
3
OUT  
OUT  
20  
19  
10  
11  
4
OUT  
5
The UCN5816A is supplied in a 28-pin dual in-line plastic package  
with 0.600" (15.24 mm) row spacing. The UCN5816EP is furnished in  
a 28-lead plastic chip carrier (quad pack) for minimum-area surface-  
mount applications. Both devices will drive 350 mA loads continuously  
over the full operating temperature range.  
Dwg. PP-030  
FEATURES  
Addressable Data Entry  
60 V Minimum Output Breakdown  
CMOS, PMOS, NMOS, TTL Compatible Inputs  
Low-Power CMOS Logic and Latches  
Output Transient Protection  
ABSOLUTE MAXIMUM RATINGS  
at TA = 25°C  
Output Enable and Strobe Functions  
Output Voltage, VCE . . . . . . . . . . . . . . 60 V  
Logic Supply Voltage, VDD . . . . . . . . . 15 V  
Input Voltage Range,  
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V  
Output Current, IC . . . . . . . . . . . . . 500 mA  
Package Power Dissipation,  
PD . . . . . . . . . . . . . . . . . . . See Graph  
Operating Temperature Range,  
TA . . . . . . . . . . . . . . . -20°C to +85°C  
Storage Temperature Range,  
TS . . . . . . . . . . . . . . -55°C to +150°C  
Always order by complete part number:  
Caution: CMOS devices have input static  
protection but are susceptible to damage when  
exposed to extremely high static electrical  
charges.  
Part Number  
UCN5816A  
UCN5816EP  
Package  
28-Pin DIP  
28-Lead PLCC  
5816  
4-TO-16 LINE LATCHED DECODER/DRIVERS  
3.0  
UCN5816A  
GROUND  
1
28 GROUND  
2.5  
2.0  
1.5  
1.0  
0.5  
0
CHIP  
ENABLE  
2
3
CE  
27 IN  
26 IN  
D
C
SUFFIX 'A', R  
= 45  
STROBE  
ST  
V
LATCHES  
LOGIC  
SUPPLY  
4
25  
24  
DD  
IN  
IN  
B
A
θ
OUTPUT  
ENABLE  
JA  
5
6
OE  
°
DIODE  
0-7  
COMMON  
DIODE  
COMMON  
C/W  
8-15  
K
23  
22  
21  
K
7
8
OUT  
15  
DECODER  
OUT  
0
SUFFIX 'EP', R  
= 55  
OUT  
14  
OUT  
1
2
OUT  
13  
9
10  
11  
20  
OUT  
OUT  
OUT  
OUT  
12  
19  
18  
θ
3
4
JA  
°
OUT  
11  
C/W  
12  
13  
17 OUT  
OUT  
OUT  
10  
9
5
6
16  
15  
OUT  
OUT  
14  
8
OUT  
7
25  
50  
75  
100  
125  
150  
Dwg. PP-031  
AMBIENT TEMPERATURE IN °C  
Dwg. GP-028-1A  
TYPICAL INPUT CIRCUITS  
TYPICAL OUTPUT DRIVER  
V
DD  
V
DD  
K
IN  
OUT  
IN  
Dwg. EP-010-3  
Dwg. EP-010-4A  
Dwg. EP-021-4  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
Copyright © 1984, 1995, Allegro MicroSystems, Inc.  
5816  
4-TO-16 LINE LATCHED DECODER/DRIVERS  
ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V (unless otherwise specified).  
Limits  
Characteristic  
Symbol  
ICEX  
Test Conditions  
VCE = 60 V, TA = +25°C  
IC = 100 mA  
Min.  
Typ.  
Max.  
Units  
µA  
V
Output Leakage Current  
Output Saturation Voltage  
50  
VCE(SAT)  
0.9  
1.1  
1.3  
1.1  
1.3  
1.6  
0.8  
IC = 200 mA  
V
IC = 350 mA, VDD = 7.0 V  
V
Input Voltage  
VIN(0)  
VIN(1)  
-0.3  
10.5  
3.5  
50  
V
VDD = 12 V  
V
V
DD = 5.0 V  
VDD = 12 V  
DD = 5.0 V  
5.3  
V
Input Resistance  
Supply Current  
RIN  
200  
600  
2.0  
1.0  
kΩ  
kΩ  
mA  
mA  
µA  
V
100  
IDD(ON)  
VDD = 12 V, Outputs Open  
VDD = 5.0 V, Outputs Open  
3.0  
1.5  
100  
IDD(OFF)  
All Drivers OFF, All Inputs = 0 V,  
OE = VDD = 5.0 V  
All Drivers OFF, All Inputs = 0 V,  
OE = VDD = 12 V  
200  
µA  
Clamp Diode  
IR  
VR = 60 V, TA = +25°C  
VR = 60 V, TA = +70°C  
IF = 350 mA  
50  
100  
2.0  
µA  
µA  
V
Leakage Current  
Clamp Diode  
VF  
1.5  
Forward Voltage  
5816  
4-TO-16 LINE LATCHED DECODER/DRIVERS  
Information present at the inputs is  
CLEAR  
F
transferred to the latches when the STROBE  
is high. The latches will continue to accept  
new data as long as the STROBE is held  
high. With the STROBE in the low state, no  
information can be loaded into the latches.  
Depending on the four address inputs, the  
4-to-16 line decoder enables one of the  
16 output sink drivers. When the OUTPUT  
ENABLE is high, all of the outputs are  
disabled (OFF) without affecting the informa-  
tion stored in the latches. When the OUT-  
PUT ENABLE is low, the outputs are con-  
trolled by the information in the latches.  
When the CHIP ENABLE is low, all of the  
outputs are disabled (OFF). With two de-  
coder/drivers and an inverter, the CHIP  
ENABLE function can be used for 5-to-32 line  
decoding applications.  
STROBE  
A
C
G
B
B
C
C
A
B
OUTPUT  
ENABLE  
G
IN  
N
E
E
D
OUT  
N
p/o Dwg. No. A-10,895A  
TIMING CONDITIONS  
(Logic Levels are VDD and Ground)  
A. Minimum Data Active Time Before Strobe Enabled  
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns  
B. Minimum Data Active Time After Strobe Disabled  
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns  
C. Minimum Strobe Pulse Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns  
D. Typical Time Between Strobe Activation and Output On to  
Off Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns  
E. Typical Time Between Strobe Activation and Output Off to  
On Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns  
G. Minimum Data Pulse Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns  
TRUTH TABLE  
CHIP  
IND  
INC  
INB  
INA  
OUTPUT  
OUTPUTS  
(OFF unless otherwise specified)  
OUT0ON  
STROBE  
ENABLE  
(MSB)  
(LSB)  
ENABLE  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
OUT1 ON  
OUT2 ON  
OUT3 ON  
OUT4 ON  
OUT5 ON  
OUT6 ON  
OUT7 ON  
OUT8 ON  
OUT9 ON  
OUT10 ON  
OUT11 ON  
OUT12 ON  
OUT13 ON  
OUT14 ON  
OUT15 ON  
QO  
All OFF  
All OFF  
QO = The output condition prior to the high-to-low transition of the STROBE input.  
X = Irrelevant  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  

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