UCQ5821A [ALLEGRO]
BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS; 采用BiMOS II 8位串行输入，锁存驱动程序
| 型号： | UCQ5821A |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS |
| 文件： | 总7页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5821
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A merged combination of bipolar and MOS technology gives
these devices an interface flexibility beyond the reach of standard
logic buffers and power driver arrays. The UCN5821A and
UCN5821LW each have an eight-bit CMOS shift register and
CMOS control circuitry, eight CMOS data latches, and eight
bipolar current-sinking Darlington output drivers.
16 OUT
15 OUT
1
2
3
4
CLOCK
CLK
1
SERIAL
DATA IN
2
3
LOGIC
GROUND
OUT
14
LOGIC
SUPPLY
BiMOS II devices have much higher data-input rates than the
original BiMOS circuits. With a 5 V logic supply, they will
typically operate at better than 5 MHz. With a 12 V supply,
significantly higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS and NMOS logic levels. TTL
circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
13 OUT
12 OUT
11 OUT
V
4
5
6
7
8
DD
SERIAL
DATA OUT
5
6
ST
STROBE
OUTPUT
ENABLE
OUT
OUT
10
9
7
8
OE
POWER
GROUND
SUB
Dwg. PP-026A
The UCN5821A are furnished in a standard 16-pin plastic
DIP; the UCN5821LW are in a 16-lead wide-body SOIC for sur-
face-mount applications. The UCN5821A is also available for
operation from -40°C to +85°C. To order, change the prefix from
‘UCN’ to ‘UCQ’.
Note the DIP package and the SOIC package are
electrically identical and share common terminal
number assignments.
ABSOLUTE MAXIMUM RATINGS
at 25°C Free-Air Temperature
FEATURES
Output Voltage, VOUT ..................... 50 V
Logic Supply Voltage, VDD ............. 15 V
■ To 3.3 MHz Data Input Rate
■ CMOS, NMOS, TTL Compatible
■ Internal Pull-Down Resistors
■ Low-Power CMOS Logic & Latches
■ High-Voltage Current-Sink Outputs
■ Automotive Capable
Input Voltage Range,
VIN .................. -0.3 V to VDD + 0.3 V
Continuous Output Current,
IOUT ..................................... 500 mA
Package Power Dissipation, PD
Package Code ‘A’ .................. 2.1 W
Package Code ‘LW’ ............... 1.5 W
Operating Temperature Range,
TA ............................ -20°C to +85°C
Storage Temperature Range,
TS .......................... -55°C to +150°C
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
Always order by complete part number, e.g., UCN5821A .
www.allegromicro.com
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
FUNCTIONAL BLOCK DIAGRAM
V
DD
LOGIC
SUPPLY
V
4
DD
CLOCK
1
2
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
5
6
LOGIC
GROUND
STROBE
3
OUTPUT ENABLE
(ACTIVE LOW)
7
MOS
STROBE &
OUTPUT
ENABLE
BIPOLAR
POWER
GROUND
8
12
OUT OUT
16
15
14
13
11
OUT OUT OUT
8
10
9
SUB
OUT OUT OUT
Dwg. FP-013A
1
2
3
4
5
6
7
NOTE — There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.
Dwg. EP-010-3
V
DD
CLOCK &
SERIAL
DATA IN
Number of Outputs ON
UCN5821A Max. Allowable Duty Cycle
at Ambient Temperature of
(I
= 200 mA
= 12 V)
OUT
V
25°C
40°C
50°C
60°C
70°C
DD
8
7
6
5
4
3
2
1
90%
79%
90%
72%
82%
96%
100%
100%
100%
100%
100%
65%
74%
86%
100%
100%
100%
100%
100%
57%
65%
76%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
91%
100%
100%
100%
100%
Dwg. EP-010-4A
Number of Outputs ON UCN5821LW Max. Allowable Duty Cycle
TYPICAL OUTPUT DRIVER
(I
= 200 mA
= 12 V)
at Ambient Temperature of
OUT
OUT
V
25°C
40°C
50°C
60°C
70°C
DD
8
7
6
5
4
3
2
1
67%
77%
90%
100%
100%
100%
100%
100%
59%
68%
79%
54%
62%
72%
49%
56%
65%
78%
98%
100%
100%
100%
43%
49%
57%
68%
86%
100%
100%
100%
7.2K
3K
95%
86%
100%
100%
100%
100%
100%
100%
100%
100%
SUB
Dwg. No. A-14,314
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise specified).
Limits
Characteristic
Symbol
Test Conditions
Min.
Max.
Units
Output Leakage
ICEX
VOUT = 50 V
—
50
µA
Current
VOUT = 50 V, TA = +70°C
IOUT = 100 mA
—
—
100
1.1
1.3
1.6
0.8
—
µA
V
Collector-Emitter
VCE(SAT)
Saturation Voltage
IOUT = 200 mA
—
V
IOUT = 350 mA, VDD = 7.0 V
—
V
Input Voltage
VIN(0)
VIN(1)
—
V
VDD = 12 V
10.5
3.5
50
50
—
V
VDD = 5.0 V
—
V
Input Resistance
Supply Current
rIN
VDD = 12 V
—
kΩ
kΩ
mA
mA
mA
mA
mA
VDD = 5.0 V
—
IDD(ON)
One Driver ON, VDD = 12 V
One Driver ON, VDD = 10 V
One Driver ON, VDD = 5.0 V
VDD = 5.0 V, All Drivers OFF, All Inputs = 0 V
VDD = 12 V, All Drivers OFF, All Inputs = 0 V
4.5
3.9
2.4
1.6
2.9
—
—
IDD(OFF)
—
—
www.allegromicro.com
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
Serial Data present at the input is
transferred to the shift register on the
logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.
CLOCK
D
A
B
DATA IN
STROBE
F
E
C
OUTPUT
ENABLE
G
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.
OUT
N
Dwg. No. A-12,627
TIMING CONDITIONS
(VDD = 5.0 V, TA = +25°C, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ....................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
When the ENABLE input is high, all
of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.
(Data Hold Time) ........................................................................... 75 ns
C. Minimum Data Pulse Width ..............................................................150 ns
D. Minimum Clock Pulse Width ............................................................150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 30 ns
F. Minimum Strobe Pulse Width ........................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition .......................................................................... 1.0 µs
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data Clock
Input Input I
Data Strobe
Output Input
Output
Enable
I
I
.............. I
I
I
I
.............. I
I
I
I
..............
I
8
1
2
3
8
1
2
3
8
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
.............. R
.............. R
.............. R
.............. X
R
R
R
X
1
1
2
2
2
3
7
7
8
7
7
8
X
R
X
1
L
R
R
R
.............. R
1
2
3
8
P
P
P
.............. P
P
H
P
X
P
X
P
X
.............. P
.............. X
L
P
P
P
..............
..............
P
8
1
2
3
8
8
1
2
3
8
1
2
3
H
H
H
H
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5821A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
9
16
0.430
MAX
0.280
0.240
0.300
BSC
1
8
0.100
BSC
0.070
0.005
MIN
0.045
0.775
0.735
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
9
16
10.92
MAX
7.11
6.10
7.62
BSC
1
8
2.54
BSC
1.77
0.13
MIN
1.15
19.68
18.67
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-16A mm
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
www.allegromicro.com
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5821LW
Dimensions in Inches
(for reference only)
16
9
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
BSC
3
0° TO 8°
0.4133
0.3977
0.0926
0.1043
Dwg. MA-008-16A in
0.0040 MIN.
16
Dimensions in Millimeters
(controlling dimensions)
9
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
BSC
3
0° TO 8°
10.50
10.10
2.65
2.35
Dwg. MA-008-16A mm
0.10 MIN.
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
相关型号：
UCQS10A045
Rectifier Diode, Schottky, 1 Phase, 2 Element, 5A, 45V V(RRM), Silicon, TO-263AB, TO-263, 3 PIN
NIEC
UCQS30A045
Rectifier Diode, Schottky, 1 Phase, 2 Element, 15A, 45V V(RRM), Silicon, TO-263AB, TO-263, 3 PIN
NIEC
UCQS30A065
Rectifier Diode, Schottky, 1 Phase, 2 Element, 15A, 65V V(RRM), Silicon, TO-263AB, TO-263, 3 PIN
NIEC
©2020 ICPDF网 联系我们和版权申明