AS29LV800T-80SI_技术文档

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&

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ꢙꢁꢛꢃ(ꢆꢁꢜ

• Organization: 1M×8/ 512K×16

• Sector architecture

• Low power consumption

- 200 nA typical automatic sleep mode current

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO (availability TBD)

• Detection of program/ erase cycle completion

- DQ7 DATApolling

- DQ6 toggle bit

- DQ2 toggle bit

- RY/ BYoutput

• Erase suspend/ resume

- One 16K; two 8K; one 32K; and fifteen 64K byte sectors

- One 8K; two 4K; one 16K; and fifteen 32K word sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/ write operations

• Sector protection

• High speed 70/ 80/ 90/ 120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/ verifies data at specified address

• Automated on-chip erase algorithm

- Automatically preprograms/ erases chip or specified sectors

• Hardware RESET pin

- Resets internal state machine to read mode

- Supports reading data from or programming data to

a sector not being erased

• Low V write lock-out below 1.5V

CC

• 10 year data retention at 150C

• 100,000 write/ erase cycle endurance

ꢍꢞ)#%ꢇꢅꢚꢞ%*ꢇ'#ꢛ)ꢆꢛꢄ

Sector protect/

erase voltage

switches

RY/ BY

DQ0–DQ15

V

CC

V

SS

Erase voltage

generator

Input/ output

buffers

RESET

Program/ erase

control

WE

BYTE

Program voltage

generator

Command

register

STB

Chip enable

Output enable

Logic

Data latch

CE

OE

A-1

Y decoder

Y gating

STB

V_CCdetector

Timer

X decoder

Cell matrix

A0–A18

ꢀꢁꢚꢁ%ꢃ#ꢞ$ꢇ)(#'ꢁ

1

29LV800-70R 29LV800-80 29LV800-90 29LV800-120 Unit

Maximum access time

t

70

30

80

30

90

35

120

50

ns

AA

Maximum chip enable access time

Maximum output enable access time

ꢗꢉꢘꢏꢆꢓꢋꢌꢈꢏꢒꢉꢖꢁꢋꢈꢌꢆꢏꢉꢄꢌꢍꢆꢏꢉꢁꢙꢉꢚꢔꢛꢉꢈꢁꢉꢚꢔꢜꢝ

t

CE

t

OE

9/ 26/ 01; V.1.5

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48-pin TSOP

ꢊꢐ !"ꢝ#ꢛꢛ

44-pin SO (availability TBD)

RY/ BY

A18

A17

A7

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RESET

WE

A8

2

3

4

A9

A6

5

A10

A11

A12

A13

A14

A15

A16

BYTE

A5

6

A4

7

A3

8

A2

9

A1

10

11

12

13

14

15

16

17

18

19

20

21

22

A0

CE

V

SS

OE

DQ0

DQ15/ A-1

DQ7

DQ8

DQ14

DQ6

DQ1

DQ9

DQ13

DQ5

DQ2

DQ10

DQ3

DQ12

DQ4

DQ11

V

CC

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The AS29LV800 is an 8 megabit, 3.0 volt Flash memory organized as 1 Megabyte of 8 bits/ 512Kbytes of 16 bits each. For

flexible erase and program capability, the 8 megabits of data is divided into nineteen sectors: one 16K, two 8K, one 32K, and

fifteen 64k byte sectors; or one 8K, two 4K, one 16K, and fifteen 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16

data appears on DQ0–DQ15. The AS29LV800 is offered in JEDEC standard 48-pin TSOP and 44-pin SO (availability TBD)

packages. This device is designed to be programmed and erased in-system with a single 3.0V V supply. The device can also be

CC

reprogrammed in standard EPROM programmers.

The AS29LV800 offers access times of 70/ 80/ 90/ 120 ns, allowing 0-wait state operation of high speed microprocessors. To

eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word

mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = low.

The AS29LV800 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the

command register using standard microprocessor write timings. An internal state-machine uses register contents to control the

erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase

operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command

sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and

verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms

the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies

proper cell margin.

Boot sector architecture enables the system to boot from either the top (AS29LV800T) or the bottom (AS29LV800B) sector.

Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other

sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase

operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend,

which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip erase

command will automatically erase all unprotected sectors.

A factory shipped AS29LV800 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into

the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1.

Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other

sectors.

The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated

voltages are provided for the Program and Erase operations. A low V detector automatically inhibits write operations during

CC

power transtitions. The RY/ BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase

operations. The device automatically resets to the read mode after program/ erase operations are completed. DQ2 indicates

which sectors are being erased.

The AS29LV800 resists accidental erasure or spurious programming signals resulting from power transitions. Control register

architecture permits alteration of memory contents only after successful completion of specific command sequences. During

power up, the device is set to read mode with all program/ erase commands disabled when V is less than V

(lockout

CC

LKO

voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write commands,

CE and WE must be logical zero and OE a logical 1.

When the device’s hardware RESET pin is driven low, any program/ erase operation in progress is terminated and the internal

state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an

automated on-chip program/ erase algorithm, data in address locations being operated on may become corrupted and requires

rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV800 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are

programmed one at a time using EPROM programming mechanism of hot electron injection.

9/ 26/ 01; V.1.5

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Mode

CE

L

OE

L

WE

A0

L

A1

L

A6

L

A9

RESET

H

DQ

ID read MFR code

ID read device code

Read

H

V

Code

ID

L

H

L

V

H

ID

L

H

A0

X

A1

X

A6

X

A9

X

H

D

OUT

Standby

H

L

X

H

X

H

High Z

Output disable

Write

H

X

H

L

A0

L

A1

H

A6

L

A9

H

D

IN

Enable sector protect

Sector unprotect

L

V

Pulse/ L

V

H

X

ID

L

V

L

H

V

H

ID

Temporary sector

unprotect

X

V

X

ID

†

Verify sector protect

Verify sector unprotect

Hardware Reset

L

X

L

X

H

X

L

X

H

X

L

V

H

L

Code

ID

†

H

X

V

Code

ID

X

High Z

L = Low (<V ) = logic 0; H = High (>V ) = logic 1; V = 10.0 ± 1.0V; X = don’t care.

IL

IH

ID

In ×16 mode, BYTE = V . In ×8 mode, BYTE = V with DQ8-DQ14 in high Z and DQ15 = A-1.

IH

IL

†

Verification of sector protect/ unprotect during A9 = V

ID.

&ꢁꢒꢏꢉꢒꢏꢙꢅꢍꢅꢈꢅꢁꢍꢕ

Item

Description

Selected by A9 = V (9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.

ID

ID MFR code,

device code

When A0 is low (V ) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.

IL

When A0 is high (V ), D

represents the device code for the AS29LV800.

IH

OUT

Selected with CE = OE = L, WE = H. Data is valid in t

time after addresses are stable, t after CE is low

CE

ACC

Read mode

Standby

and t after OE is low.

OE

Selected with CE = H. Part is powered down, and I reduced to <1.0 µA when CE = V ± 0.3V = RESET. If

CC

activated during an automated on-chip algorithm, the device completes the operation before entering

standby.

Output disable Part remains powered up; but outputs disabled with OE pulled high.

Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command

register. Contents of command register serve as inputs to the internal state machine. Address latching occurs

on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,

Write

whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.

Hardware protection circuitry implemented with external programming equipment causes the device to

disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector

protect algorithm on page 14.

Enable

sector protect

Disables sector protection for all sectors using external programming equipment. All sectors must be

protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect

algorithm on page 14.

Sector

unprotect

Verifies write protection for sector. Sectors are protected from program/ erase operations on commercial

programming equipment. Determine if sector protection exists in a system by writing the ID read command

sequence and reading location XXX02h, where address bits A12–18 select the defined sector addresses. A

logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

Verify sector

protect/

unprotect

9/ 26/ 01; V.1.5

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Item

Description

Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET

to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected

sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal

of +10V from RESET.

Temporary

sector

unprotect

Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data

may be corrupted.

RESET

Deep

power down

Hold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.

Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is

available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new

data is returned within standard access times.

Automatic

sleep mode

$ꢋꢏꢞꢅ(ꢋꢏꢉꢕꢏꢎꢈꢁꢄꢉꢌꢄꢎꢇꢅꢈꢏꢎꢈꢓꢄꢏ

Bottom boot sector architecture (AS29LV800B)

Top boot sector architecture (AS29LV800T)

Size

Sector

0

×8

×16

(Kbytes)

×8

×16

(Kbytes)

64

32

8

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–FFFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

16

8

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–F7FFFh

F8000h–F9FFFh

FA000h–FBFFFh

FC000h–FFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7BFFFh

7C000h–7CFFFh

7D000h–7DFFFh

7E000h–7FFFFh

1

2

8

3

32

64

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

8

16

In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A18–A-1 if BYTE = V ; address range is

IL

A18–A0 if BYTE = V .

IH

9/ 26/ 01; V.1.5

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)*ꢉꢐꢏꢎꢈꢁꢄꢉꢌꢒꢒꢄꢏꢕꢕꢉꢈꢌ(ꢋꢏ

Bottom boot sector address

(AS29LV800B)

Top boot sector address

(AS29LV800T)

Sector

0

A18

0

A17

0

A16

0

A15

0

A14 A13

A12

X

0

A18

0

A17

0

A16

0

A15 A13

A14

X

0

A12

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

2

0

1

0

1

3

0

1

X

0

1

4

0

1

X

0

1

0

5

0

1

0

1

0

6

0

1

0

1

7

0

1

0

1

8

0

1

0

1

0

9

0

1

0

1

0

10

11

12

13

14

15

16

17

18

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

ꢘ+ꢊ*ꢉꢎꢁꢒꢏꢕ

Mode

A18–A12

A6

L

A1

L

A0

L

Code

52h

MFR code (Alliance Semiconductor)

X

×8 T boot

×8 B boot

×16 T boot

×16 B boot

L

H

DAh

L

5Bh

Device code

L

22DAh

225Bh

L

01h protected

00h unprotected

Sector protection

Sector address

L

H

L

Key: L =Low (<V ); H = High (>V ); X =Don’t care

IL

IH

9/ 26/ 01; V.1.5

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ꢀꢁꢑꢑꢌꢍꢒꢉꢙꢁꢄꢑꢌꢈ

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

5th bus cycle

6th bus cycle

Required bus

Command sequence

Reset/ Read

write cycles

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Read

Address

1

XXXh

F0h

Read Data

×16

Reset/ Read

×8

555h

AAAh

2AAh

555h

AAAh

Read

Data

3

AAh

55h

F0h

90h

Read Address

01h

Device code

22DAh (T)

225Bh (B)

×16

×8

555h

AAAh

2AAh

555h

AAAh

02h

Device code

DAh (T) 5Bh

(B)

×16

555h

AAAh

2AAh

555h

AAAh

0052h

52h

Autoselect

00h

MFR code

3

ID Read

×8

XXX02h

Sector protection

0001h = protected

0000h = unprotected

×16

×8

555h

AAAh

2AAh

555h

AAAh

XXX04h

Sector protection

0001h=protected

0000h=unprotected

×16

555h

AAAh

555

2AAh

555h

2AA

555

555h

AAAh

555

Program

×8

4

3

AAh

55h

A0h

20h

Program Address Program Data

×16

Unlock bypass

×8

AAA

Program

address

Program

data

Unlock bypass program

Unlock bypass reset

2

XXX

A0h

90h

XXX

00h

55h

×16

Chip Erase

×8

555h

AAAh

555h

AAAh

XXXh

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAh

2AAh

555h

2AAh

555h

AAAh

6

AAh

80h

55h

10h

30h

AAAh

×16

Sector Erase

×8

555h

AAh

AAAh

Sector

Address

55h

Sector Erase Suspend

Sector Erase Resume

1

B0h

30h

1

2

3

4

5

6

Bus operations defined in "Mode definitions," on page 3.

Reading from and programming to non-erasing sectors allowed in Erase Suspend mode.

Address bits A11-A18 = X = Don’t Care for all address commands except where Program Address and Sector Address are required.

Data bits DQ15-DQ8 are don’t care for unlock and command cycles.

The Unlock Bypass command must be initiated before the Unlock Bypass Program command.

The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.

9/ 26/ 01; V.1.5

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Item

Description

Initiate read or reset operations by writing the Read/ Reset command sequence into the command

register. This allows the microprocessor to retrieve data from the memory. Device remains in read

mode until command register contents are altered.

Reset/ Read

Device automatically powers up in read/ reset state. This feature allows only reads, therefore

ensuring no spurious memory content alterations during power up.

AS29LV800 provides manufacturer and device codes in two ways. External PROM programmers

typically access the device codes by driving +10V on A9. AS29LV800 also contains an ID Read

command to read the device code with only +3V, since multiplexing +10V on address lines is

generally undesirable.

Initiate device ID read by writing the ID Read command sequence into the command register.

Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command

sequence with a read sequence from address XXX01h to return device code.

ID Read

To verify write protect status on sectors, read address XXX02h. Sector addresses A18–A12 produce

a 1 on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/ Reset command sequence.

Holding RESET low for 500 ns resets the device, terminating any operation in progress; data

handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven

low. RY/ BY remains low until internal state machine resets. After RESET is set high, there is a delay

of 50 ns for the device to permit read operations.

Hardware Reset

Programming the AS29LV800 is a four bus cycle operation performed on a byte-by-byte or word-

by-word basis. Two unlock write cycles precede the Program Setup command and program data

write cycle. Upon execution of the program command, no additional CPU controls or timings are

necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched

on the rising edge of CE or WE, whichever is first. The AS29LV800’s automated on-chip program

algorithm provides adequate internally-generated programming pulses and verifies the

programmed cell margin.

Check programming status by sampling data on the RY/ BY pin, or either the DATA polling (DQ7)

or toggle bit (DQ6) at the program address location. The programming operation is complete if

DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/ BY pin = high.

Byte/ word

Programming

The AS29LV800 ignores commands written during programming. A hardware reset occurring

during programming may corrupt the data at the programmed location.

AS29LV800 allows programming in any sequence, across any sector boundary. Changing data from

0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1

(exceeded programming time limits); reading this data after a read/ reset operation returns a 0.

When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this

state, a Reset command returns the device to read mode.

9/ 26/ 01; V.1.5

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P. 8 of 25

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Item

Description

The unlock bypass feature increases the speed at which the system programs bytes or words to the

device because it bypasses the first two unlock cycles of the standard program command sequence.

To initiate the unlock bypass command sequence, two unlock cycles must be written, then

followed by a third cycle which has the unlock bypass command, 20h.

The device then begins the unlock bypass mode. In order to program in this mode, a two cycle

unlock bypass program sequence is required. The first cycle has the unlock bypass program

command, A0h. It is followed by a second cycle which has the program address and data. To

program additional data, the same sequence must be followed.

Unlock Bypass

Command Sequence

The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the

Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by

issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first

cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for

both cycles. The device then returns to reading array data.

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional

unlock write cycles; and finally the Chip Erase command.

Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip

erase algorithm is invoked with the Chip Erase command sequence, AS29LV800 automatically

programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV800

returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding

time limit.

Chip Erase

Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional

unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by

addressing any location in the sector. The address is latched on the falling edge of WE; the

command, 30h is latched on the rising edge of WE. The sector erase operation begins after a sector

erase time-out.

To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to

erase after following the six bus cycle operation above. Timing between writes of additional sectors

must be less than the erase time-out period, or the AS29LV800 ignores the command and erasure

begins. During the time-out period any falling edge of WE resets the time-out. Any command

(other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV800 to read

mode, and the device ignores the sector erase command string. Erase such ignored sectors by

restarting the Sector Erase command on the ignored sectors.

Sector Erase

The entire array need not be written with 0s prior to erasure. AS29LV800 writes 0s to the entire

sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected

sectors unaffected. AS29LV800 requires no CPU control or timing signals during sector erase

operations.

Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the

sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling

address must be performed on addresses that fall within the sectors being erased. AS29LV800

returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 9 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

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Item

Description

Erase Suspend allows interruption of sector erase operations to read data from or program data to a

sector not being erased. Erase suspend applies only during sector erase operations, including the

time-out period. Writing an Erase Suspend command during sector erase time-out results in

immediate termination of the time-out period and suspension of erase operation.

AS29LV800 ignores any commands during erase suspend other than Read/ Reset, Program or Erase

Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are

Don’t Care when writing Erase Suspend or Erase Resume commands.

AS29LV800 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command.

To determine completion of erase suspend, either check DQ6 after selecting an address of a sector

not being erased, or poll RY/ BY. Check DQ2 in conjunction with DQ6 to determine if a sector is

being erased. AS29LV800 ignores redundant writes of Erase Suspend.

Erase Suspend

While in erase-suspend mode, AS29LV800 allows reading data (erase-suspend-read mode) from or

programming data (erase-suspend-program mode) to any sector not undergoing sector erase;

these operations are treated as standard read or standard programming mode. AS29LV800 defaults

to erase-suspend-read mode while an erase operation has been suspended.

Write the Resume command 30h to continue operation of sector erase. AS29LV800 ignores

redundant writes of the Resume command. AS29LV800 permits multiple suspend/ resume

operations during sector erase.

When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated

for about <1 µs. When attempting to erase a protected sector, DATA polling and

Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode

without altering the specified sectors.

Sector Protect

Ready/ Busy

RY/ BY indicates whether an automated on-chip algorithm is in progress (RY/ BY = low) or

completed (RY/ BY = high). The device does not accept Program/ Erase commands when

RY/ BY = low. RY/ BY= high when device is in erase suspend mode. RY/ BY = high when device

exceeds time limit, indicating that a program or erase operation has failed. RY/ BY is an open drain

output, enabling multiple RY/ BY pins to be tied in parallel with a pull up resistor to V .

CC

9/ 26/ 01; V.1.5

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P. 10 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢐꢈꢌꢈꢓꢕꢉꢁꢂꢏꢄꢌꢈꢅꢁꢍꢕ

Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects

complement of data last written when read during the automated on-chip program algorithm (0

during erase algorithm); reflects true data when read after completion of an automated on-chip

program algorithm (1 after completion of erase agorithm).

DATA polling (DQ7)

Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE

toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth

pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase;

after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors,

DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors

are protected).

Toggle bit 1 (DQ6)

Indicates unsuccessful completion of program/ erase operation (DQ5 = 1). DATA polling remains

active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or

sector erase, the sector is defective (in this case, reset the device and execute a program or erase

command sequence to continue working with functional sectors). Attempting to program 0 to 1

will set DQ5 = 1.

Exceeding time limit

(DQ5)

Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands

will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and

after each Sector Erase command to verify that the command was accepted.

Sector erase timer

(DQ3)

During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being

erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles

only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use

DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend

mode.

Toggle bit 2 (DQ2)

,ꢄꢅꢈꢏꢉꢁꢂꢏꢄꢌꢈꢅꢁꢍꢉꢕꢈꢌꢈꢓꢕ

Standard mode

Status

DQ7

0

DQ6

DQ5

DQ3

N/ A

1

DQ2

RY/ BY

Auto programming

Toggle

No toggle

Data

0

No toggle

0

1

0

1

†

Program/ erase in auto erase

Read erasing sector

0

Toggle

1

0

N/ A

Data

N/ A

Toggle

Data

Erase suspend mode

Read non-erasing sector

Program in erase suspend

Auto programming (byte)

Program/ erase in auto erase

Data

DQ7

0

Data

†

Toggle

0

1

Toggle

No toggle

†

Toggle

Exceeded time limits

Program in erase suspend

(non-erase suspended sector)

DQ7

Toggle

1

N/ A

No toggle

1

DQ2 toggles when an erase-suspended sector is read repeatedly.

DQ6 toggles when any address is read repeatedly.

DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.

†

DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.

9/ 26/ 01; V.1.5

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P. 11 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢓꢈꢁꢑꢌꢈꢏꢒꢉꢁꢍ-ꢎꢇꢅꢂꢉꢂꢄꢁꢆꢄꢌꢑꢑꢅꢍꢆꢉꢌꢋꢆꢁꢄꢅꢈꢇꢑ

ꢊꢓꢈꢁꢑꢌꢈꢏꢒꢉꢁꢍ-ꢎꢇꢅꢂꢉꢏꢄꢌꢕꢏꢉꢌꢋꢆꢁꢄꢅꢈꢇꢑ

START

Write erase command sequence

(see below)

Write program command sequence

(see below)

DATA polling or toggle bit

successfully completed

DATA polling or toggle bit

successfully completed

Erase complete

Individual sector/ multiple sector

Increment

address

erase command sequence

Chip erase command sequence

×16 mode (address/ data):

Last

NO

555h/ AAh

2AAh/ 55h

555h/ 80h

555h/ AAh

2AAh/ 55h

555h/ 10h

555h/ AAh

2AAh/ 55h

address?

YES

Programming completed

555h/ 80h

Program command sequence

×16 mode (address/ data):

555h/ AAh

2AAh/ 55h

Sector address/ 30h

555h/ A0h

Program address/ program data

Sector address/ 30h

optional sector erase commands

†

The system software should check the status of DQ3 prior to and following each

subsequent sector erase command to ensure command completion. The device may

not have accepted the command if DQ3 is high on second status check.

9/ 26/ 01; V.1.5

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P. 12 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

.ꢄꢁꢆꢄꢌꢑꢑꢅꢍꢆꢉꢓꢕꢅꢍꢆꢉꢓꢍꢋꢁꢎ/ꢉ(ꢃꢂꢌꢕꢕꢉꢎꢁꢑꢑꢌꢍꢒ

Unlock bypass command sequence

x16 mode (address/ data)

START

555h/ AAh

2AAh/ 55h

555h/ 20h

Write unlock

bypass command

(3 cycles)

Write unlock

bypass program command

(2 cycles)

Unlock bypass program

command sequence

x16 mode (address/ data)

DATA polling or

toggle bit

xxxh/ A0h

successfully completed

program address/

program data

Increment

address

Last

NO

address?

Unlock bypass reset

command sequence

x16 mode (address/ data)

YES

xxxh/ 90h

xxxh/ 00h

Write unlock

bypass reset command

(2 cycles)

Programming completed

9/ 26/ 01; V.1.5

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P. 13 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

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ꢉꢐꢏꢎꢈꢁꢄꢉꢂꢄꢁꢈꢏꢎꢈꢉꢌꢋꢆꢁꢄꢅꢈꢇꢑꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢉꢐꢏꢎꢈꢁꢄꢉꢓꢍꢂꢄꢁꢈꢏꢎꢈꢉꢌꢋꢆꢁꢄꢅꢈꢇꢑ

START

PLSCNT = 1

RESET# = V

ID

RESET# = V

ID

Wait 1 µs

No

Protect all sectors:

The shaded portion of

the sector protct

No

First Write

Cycle=60h?

Temporary sector

unprotect mode

First Write

Cycle=60h?

Temporary sector

unprotect mode

algorithm must be

Yes

Set up sector

Yes

initiated for all

unprotected sectors

before calling the

sector unprotect

address

No

All sectors

protected?

Sector protect:

write 60h to sector

address with

A6=0, A1=1,

A0=0

Yes

Sector unprotect:

write 60h to sector

address with

A6=1, A1=1,

A0=0

Wait 150 µs

Verify sector

protect; write 40h

to sector address

with A6=0,

Wait 15 ms

Increment

PLSCNT

Set up first

sector address

A1=1, A0=0

Verify sector

unprotect; write 40h

to sector address

with A6=1,

Read from sector

address with A6=0,

A1=1, A0=0

Increment

PLSCNT

No

A1=1, A0=0

No

Read from sector

address with A6=1,

A1=1, A0=0

Data=01h?

Yes

PLSCNT=25?

No

Set up next

Yes

sector address

No

Protect

another

Yes

PLSCNT

=1000?

Data=00h?

Yes

sector?

Device failed

No

Yes

Remove V

from RESET#

ID

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V

ID

Sector protect

complete

from RESET#

Write reset

command

Sector unprotect

complete

9/ 26/ 01; V.1.5

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P. 14 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

*ꢊ0ꢊꢉꢂꢁꢋꢋꢅꢍꢆꢉꢌꢋꢆꢁꢄꢅꢈꢇꢑ

0ꢁꢆꢆꢋꢏꢉ(ꢅꢈꢉꢌꢋꢆꢁꢄꢅꢈꢇꢑ

Read byte (DQ0–DQ7)

Address = don’t care

†

Address = VA

DQ7

=

DQ6

YES

NO

=

DONE

data

toggle

?

NO

YES

DQ5

=

DQ5

NO

=

1

?

YES

Read byte (DQ0–DQ7)

Address = VA

Read byte (DQ0–DQ7)

Address = don’t care

DQ7

data^‡

?

DQ6

†

YES

NO

=

DONE

†

toggle

?

†

NO

FAIL

YES

FAIL

†

‡

VA = Byte address for programming. VA = any of the sector

addresses within the sector being erased during Sector Erase. VA

= valid address equals any non-protected sector group address

during Chip Erase.

†

DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling

when DQ5 changes to 1.

DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not

change simultaneously.

9/ 26/ 01; V.1.5

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P. 15 of 25

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*ꢀꢉꢏꢋꢏꢎꢈꢄꢅꢎꢌꢋꢉꢎꢇꢌꢄꢌꢎꢈꢏꢄꢅꢕꢈꢅꢎꢕ

Parameter

ꢝ_ꢀꢀꢉ1ꢉ ꢔ2Mꢚꢔꢜꢝ

Symbol Test conditions

= V to V , V = V

CC MAX

Min

-

Max

Unit

Input load current

I

V

±1

35

µA

LI

IN

SS

CC CC

A9 Input load current

I

V

= V , A9 = 10V

CC MAX

µA

LIT

CC

Output leakage current

I

V

= V to V , V = V

CC MAX

-

±1

20

µA

LO

OUT

SS

CC CC

Active current, read @ 5MHz

Active current, program/ erase

I

CE = V , OE = V

IH

mA

CC1

IL

I

CE = V , OE = V

100

CC2

IL

IH

CE = V , OE = V ;

1

IL

IH

Automatic sleep mode

I

-

5

µA

CC3

V = 0.3V, V = V - 0.3V

IL

IH

CC

Standby current

I

CE = V - 0.3V, RESET = V - .3V

-

5

µA

V

SB

CC

3

Deep power down current

I

RESET = 0.3V

-

5

PD

Input low voltage

Input high voltage

Output low voltage

Output high voltage

V

-0.5

0.8

IL

V

0.7×V

V + 0.3

CC

V

IH

CC

V

I

= 4.0mA, V = V

CC MIN

-

0.45

V

OL

CC

V

I

= -2.0 mA, V = V

0.85×V

CC

-

V

OH

CC

CC MIN

Low V lock out voltage

V

1.5

9

-

V

CC

LKO

Input HV select voltage

V

11

V

ID

1 Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA.

9/ 26/ 01; V.1.5

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P. 16 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢀꢉꢂꢌꢄꢌꢑꢏꢈꢏꢄꢕꢉNꢉꢄꢏꢌꢒꢉꢎꢃꢎꢋꢏ

-70R

-80

-90

-120

Max Min Max Unit

JEDEC

Std

Symbol Symbol Parameter

Min

Max

-

Min

Max

-

Min

t

Read cycle time

70

-

80

-

90

-

120

-

ns

AVAV

AVQV

ELQV

GLQV

RC

Address to output delay

Chip enable to output

70

30

-

80

30

-

90

35

-

120

50

-

ACC

CE

-

Output enable to output

Output enable setup time

Chip enable to output High Z

Output enable to output High Z

-

OE

OES

DF

0

-

0

-

0

-

0

-

t

20

30

EHQZ

GHQZ

-

DF

Output hold time from addresses,

first occurrence of CE or OE

t

0

-

0

-

0

-

0

-

ns

AXQX

OH

Output enable hold time: Read

10

t

Output enable hold time:

Toggle and data polling

OEH

t

RESET high to output delay

RESET pin low to read mode

RESET pulse

-

50

10

-

50

10

-

50

10

-

50

10

-

ns

µs

ns

PHQV

RH

READY

RP

500

ꢘꢏꢌꢒꢉ5ꢌꢖꢏꢙꢁꢄꢑ

t

RC

Addresses stable

Addresses

CE

t

ACC

t

DF

t

OES

OE

t

OEH

WE

t

OH

CE

High Z

Outputs

Output valid

t

RH

RESET

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 17 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢀꢉꢂꢌꢄꢌꢑꢏꢈꢏꢄꢕꢉNꢉ5ꢄꢅꢈꢏꢉꢎꢃꢎꢋꢏ

,+ꢉꢎꢁꢍꢈꢄꢁꢋꢋꢏꢒ

-70R

Max

-80

-90

-120

JEDEC

Symbol

Std

Symbol Parameter

Min

70

0

Min

Max

Min

90

0

Max

Min

120

0

Max

Unit

ns

t

Write cycle time

-

80

0

-

AVAV

WC

AS

Address setup time

Address hold time

Data setup time

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

45

35

0

45

35

0

45

0

50

0

AH

DS

Data hold time

DH

Read recover time before write

CE setup time

0

GHWL

CS

0

CE hold time

0

WHEH

WLWH

WHWL

CH

Write pulse width

Write pulse width high

35

30

35

30

35

30

50

30

WP

WPH

,ꢄꢅꢈꢏꢉ5ꢌꢖꢏꢙꢁꢄꢑ

,+ꢉꢎꢁꢍꢈꢄꢁꢋꢋꢏꢒ

3rd bus cycle

DATA polling

t

WC

555h

AS

Program address

Addresses

CE

t

AH

t

CH

t

; t

GHWL OES

OE

t

WP

t

WHWH1 or 2

WE

t

CS

WPH

t

DH

Program

data

A0h

DQ7

D

OUT

DATA

t

DS

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 18 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢀꢉꢂꢌꢄꢌꢑꢏꢈꢏꢄꢕꢉNꢉ5ꢄꢅꢈꢏꢉꢎꢃꢎꢋꢏꢉ

ꢀ+ꢉꢎꢁꢍꢈꢄꢁꢋꢋꢏꢒ

-70R

-80

-90

-120

JEDEC

Std

Symbol Symbol Parameter

Min

70

0

Max

Min

80

0

Max

Min

90

0

Max

Min

120

0

Max

Unit

ns

t

Write cycle time

Address setup time

Address hold time

Data setup time

-

AVAV

AVEL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

WC

AS

45

35

0

45

35

0

45

0

50

0

AH

DS

Data hold time

DH

GHEL

WS

WH

CP

Read recover time before write

WE setup time

0

WE hold time

0

CE pulse width

35

30

35

30

35

30

50

30

CE pulse width high

EHEL

CPH

,ꢄꢅꢈꢏꢉ5ꢌꢖꢏꢙꢁꢄꢑꢉ

ꢀ+ꢉꢎꢁꢍꢈꢄꢁꢋꢋꢏꢒ

DATA polling

Addresses

WE

555h

Program address

t

AH

t

AS

WC

t

, t

GHEL OES

OE

t

CP

t

WHWH1 or 2

CE

t

CPH

t

DH

Program

data

DATA

A0h

DQ7

D

OUT

t

DS

9/ 26/ 01; V.1.5

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P. 19 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢀꢉꢂꢌꢄꢌꢑꢏꢈꢏꢄꢕꢉNꢉꢈꢏꢑꢂꢁꢄꢌꢄꢃꢉꢕꢏꢎꢈꢁꢄꢉꢓꢍꢂꢄꢁꢈꢏꢎꢈ

-70R/ 80/ 90/ 120

JEDEC

Symbol

Std Symbol

Parameter

rise and fall time

Min

Max

-

Unit

ns

t

500

V

VIDR

ID

RESET setup time for temporary sector

unprotect

t

4

-

µs

RSP

0ꢏꢑꢂꢁꢄꢌꢄꢃꢉꢕꢏꢎꢈꢁꢄꢉꢓꢍꢂꢄꢁꢈꢏꢎꢈꢉ5ꢌꢖꢏꢙꢁꢄꢑ

10V

0 or 3V

RESET

0 or 3V

t

VIDR

Program/ erase command sequence

CE

WE

t

RSP

RY/ BY

ꢊꢀꢉꢂꢌꢄꢌꢑꢏꢈꢏꢄꢕꢉNꢉꢘ+ꢐ+0ꢉ

-70R/ 80/ 90/ 120

JEDEC

Symbol

Std Symbol

Parameter

Min

Max

-

Unit

ns

t

RESET pulse

500

RP

-

50

10

ns

RESET High time before Read

RESET Low to Read mode

RH

µs

READY

ꢘ+ꢐ+0ꢉ5ꢌꢖꢏꢙꢁꢄꢑ

t

RP

t

RP

RESET

t

READY

RY/ BY

DQ

t

RH

status

valid data

+ꢄꢌꢕꢏꢉ5ꢌꢖꢏꢙꢁꢄꢑ

ꢟꢗꢜꢉꢑꢁꢒꢏ

t

WC

555h

AS

2AAh

Addresses

CE

555h

AH

555h

2AAh

Sector address

t

GHWL

OE

t

WC

WP

WE

t

WPH

t

CS

10h for Chip Erase

t

DH

AAh

55h

80h

AAh

55h

30h

Data

t

DS

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 20 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢀꢉ.ꢌꢄꢌꢑꢏꢈꢏꢄꢕꢉNꢉꢘ+ꢊ*789:ꢐ7ꢉ

-70R/ 80/ 90/ 120

JEDEC

Symbol Std Symbol

Parameter

setup time

Min

50

0

Max

Unit

µs

-

t

-

V

VCS

RB

CC

ns

Recovery time from RY/ BY

ns

90

Program/ erase valid to RY/ BY delay

BUSY

ꢘ7897ꢉ5ꢌꢖꢏꢙꢁꢄꢑ

CE

Rising edge of last WE signal

WE

Program/ erase

operation

RY/ BY

tri-stated open-drain

t

BUSY

t

RB

V

CC

t

VCS

*ꢊ0ꢊꢉꢂꢁꢋꢋꢅꢍꢆꢉ5ꢌꢖꢏꢙꢁꢄꢑ

t

CH

CE

t

DF

OE

t

OEH

WE

DQ7

t

CE

t

OH

Output

High Z

Input DQ7

Output DQ7

t

WHWH1 or 2

0ꢁꢆꢆꢋꢏꢉ(ꢅꢈꢉ5ꢌꢖꢏꢙꢁꢄꢑ

CE

t

OEH

WE

OE

DQ6

t

OE

toggle

no toggle

t

DH

9/ 26/ 01; V.1.5

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P. 21 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢀꢉꢈꢏꢕꢈꢉꢎꢁꢍꢒꢅꢈꢅꢁꢍꢕ

=ꢚꢔꢛꢝ

ꢗ>ꢚꢛꢜ?

ꢁꢄꢉꢏ@ꢓꢅꢖꢌꢋꢏꢍꢈ

^ꢔ2;Ω

*ꢏꢖꢅꢎꢏꢉꢓꢍꢒꢏꢄꢉꢈꢏꢕꢈ

ꢜꢔ ;Ω

ꢀ_"<

ꢗ>ꢚꢛꢜ?

ꢁꢄꢉꢏ@ꢓꢅꢖꢌꢋꢏꢍꢈ

ꢝ_ꢐꢐ

0ꢏꢕꢈꢉꢕꢂꢏꢎꢅꢙꢅꢎꢌꢈꢅꢁꢍꢕꢉ

Test Condition

-70R,-80

-90, -120

1 TTL gate

100

Unit

Output Load

Output Load Capacitance C (including jig capacitance)

L

30

pF

ns

V

Input Rise and Fall Times

5

Input Pulse Levels

0.0-3.0

1.5

Input timing measurement reference levels

Output timing measurement reference levels

V

1.5

V

+ꢄꢌꢕꢏꢉꢌꢍꢒꢉꢂꢄꢁꢆꢄꢌꢑꢑꢅꢍꢆꢉꢂꢏꢄꢙꢁꢄꢑꢌꢍꢎꢏ

Limits

Parameter

Min

Typical

Max

15

Unit

sec

Sector erase and verify-1 time (excludes 00h programming

prior to erase)

-

1.0

Byte

-

10

15

300

360

27

-

µs

Programming time

Word

Chip programming time

7.2

sec

1

Erase/ program cycles

100,000

cycles

1 Erase/ program cycle test is not verified on each shipped unit.

"ꢌꢈꢎꢇꢓꢂꢉꢈꢁꢋꢏꢄꢌꢍꢎꢏꢉ

Parameter

Min

-1.0

-0.5

-100

Max

+12.0

Unit

V

Input voltage with respect to V on A9, OE, and RESET pin

SS

V

Input voltage with respect to V on all DQ, address, and control pins

SS

VCC+0.5

+100

Current

mA

Includes all pins except V . Test conditions: V = 3.0V, one pin at a time.

CC

9/ 26/ 01; V.1.5

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P. 22 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢘꢏꢎꢁꢑꢑꢏꢍꢒꢏꢒꢉꢁꢂꢏꢄꢌꢈꢅꢍꢆꢉꢎꢁꢍꢒꢅꢈꢅꢁꢍꢕ

Parameter

Comments

Symbol

Min

+2.7

+3.0

0

Max

+3.6

0

Unit

V

$ꢁꢄꢉꢙꢓꢋꢋꢉꢖꢁꢋꢈꢌꢆꢏꢉꢄꢌꢍꢆꢏ

V

cc

$ꢁꢄꢉꢄꢏꢆꢓꢋꢌꢈꢏꢒꢉꢖꢁꢋꢈꢌꢆꢏꢉꢄꢌꢍꢆꢏ

Supply voltage

V

cc

V

SS

V

1.9

V

+ 0.3

V

IH

CC

Input voltage

V

–0.5

0.8

IL

ꢊ(ꢕꢁꢋꢓꢈꢏꢉꢑꢌꢞꢅꢑꢓꢑꢉꢄꢌꢈꢅꢍꢆꢕ

Parameter

Symbol

Min

–0.5

-0.5

–55

–65

-

Max

Unit

V

Input voltage (Input or DQ pin)

Input voltage (A9 pin, OE, RESET)

Power supply voltage

V

V + 0.5

IN

CC

V

+12.5

+4.0

+125

+150

150

V

IN

V

CC

Operating temperature

T

°C

mA

OPR

Storage temperature (plastic)

Short circuit output current

T

STG

I

OUT

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

0ꢐ%.ꢉꢂꢅꢍꢉꢎꢌꢂꢌꢎꢅꢈꢌꢍꢎꢏ

Symbol

Parameter

Test setup

= 0

Typ

6

Max

7.5

12

Unit

pF

C

Input capacitance

Output capacitance

Control pin capacitance

V

IN

C

V

= 0

8.5

8

pF

OUT

C

V

= 0

10

pF

IN2

IN

ꢐ%ꢉꢂꢅꢍꢉꢎꢌꢂꢌꢎꢅꢈꢌꢍꢎꢏꢉAꢌꢖꢌꢅꢋꢌ(ꢅꢋꢅꢈꢃꢉ09*B

Symbol

Parameter

Test setup

= 0

Typ

6

Max

7.5

12

Unit

pF

C

Input capacitance

Output capacitance

Control pin capacitance

V

IN

C

V

= 0

8.5

8

pF

OUT

C

V

= 0

10

pF

IN2

IN

*ꢌꢈꢌꢉꢄꢏꢈꢏꢍꢈꢅꢁꢍ

Parameter

Temp.(°C)

150°

Min

10

Unit

years

Minimum pattern data retention time

125°

20

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 23 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

.ꢌꢎ/ꢌꢆꢏꢉꢒꢅꢑꢏꢍꢕꢅꢁꢍꢕC

e

b

0ꢇꢅꢍꢉꢕꢑꢌꢋꢋꢉꢁꢓꢈꢋꢅꢍꢏꢉꢂꢌꢎ/ꢌꢆꢏꢉA0ꢐ%.-)B

48-pin

12×20

c

Min

–

Max

1.20

0.15

1.05

0.27

A

A1

A2

b

A2

A

A1

L

0.05

0.95

0.17

pin 1

pin 48

D

Hd

c

0.15 nominal

18.20 18.60

0.50 nominal

D

e

E

11.90

12.10

20.20

0.70

5°

pin 24

pin 25

Hd

L

19.80

0.50

0°

48-pin

α

E

.ꢌꢎ/ꢌꢆꢏꢉꢒꢅꢑꢏꢍꢕꢅꢁꢍꢕCꢉꢐꢑꢌꢋꢋꢉ%ꢓꢈꢋꢅꢍꢏꢉ.ꢋꢌꢕꢈꢅꢎꢉAꢐ%BꢉAꢌꢖꢌꢅꢋꢌ(ꢅꢋꢅꢈꢃꢉ09*B

c

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

JEDEC MO - 175 AA

44-pin SO

Min (mm) Max (mm)

H

e

SO

e

A

A1

A2

b

–

3.1

–

0.05

2.5

2.9

0.45

0–10°

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

0.25

d

c

0.09

28.0

12.4

0.25

28.4

12.8

d

e

A

2

l

A

E

He

l

1.27 (typical)

16.05 (typical)

0.73 1.3

A

1

b

E

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 24 of 25

ꢋꢀꢈꢌꢍꢎꢏꢉꢉ

&

ꢊꢐ !"ꢝ#ꢛꢛꢉꢁꢄꢒꢏꢄꢅꢍꢆꢉꢎꢁꢒꢏꢕ

70 ns

80 ns

90 ns

120 ns

Package \ Access Time

(commercial/ industrial) (commercial/ industrial) (commercial/ industrial) (commercial/ industrial)

1

TSOP, 12×20 mm, 48-pin

Top boot configuration

AS29LV800T-70R TC

AS29LV800T-70RTI

AS29LV800T-80TC

AS29LV800T-80TI

AS29LV800T-90TC

AS29LV800T-90TI

AS29LV800T-120TC

AS29LV800T-120TI

TSOP, 12×20 mm, 48-pin

Bottom boot configuration

AS29LV800B-70RTC

AS29LV800B-70RTI

AS29LV800B-80TC

AS29LV800B-80TI

AS29LV800B-90TC

AS29LV800B-90TI

AS29LV800B-120TC

AS29LV800B-120TI

2

SO , 13.3 mm, 44-pinTop boot

AS29LV800T-70RSC

AS29LV800T-70RSI

AS29LV800T-80SC

AS29LV800T-80SI

AS29LV800T-90SC

AS29LV800T-90SI

AS29LV800T-120SC

AS29LV800T-120SI

configuration

SO, 13.3 mm, 44-pin

Bottom boot configuration

AS29LV800B-70RSC

AS29LV800B-70RSI

AS29LV800B-80SC

AS29LV800B-80SI

AS29LV800B-90SC

AS29LV800B-90SI

AS29LV800B-120SC

AS29LV800B-120SI

ꢗꢉꢐꢓꢙꢙꢙꢅꢞꢉOꢘPꢉꢒꢏꢍꢁꢈꢏꢕꢉꢄꢏꢆꢓꢋꢌꢈꢏꢒꢉꢖꢁꢋꢈꢌꢆꢏꢉꢄꢌꢍꢆꢏꢔ

ꢉꢐꢇꢌꢒꢏꢒꢉꢌꢄꢏꢌꢉꢅꢍꢒꢅꢎꢌꢈꢏꢕꢉꢌꢒꢖꢌꢍꢎꢏꢒꢉꢅꢍꢙꢁꢄꢑꢌꢈꢅꢁꢍꢔꢉꢊꢖꢌꢅꢋꢌ(ꢅꢋꢅꢈꢃꢉꢁꢙꢉꢐ%ꢉꢂꢌꢎ/ꢌꢆꢏꢉꢅꢕꢉ09*ꢔ

ꢊꢐ !"ꢝ#ꢛꢛꢉꢂꢌꢄꢈꢉꢍꢓꢑ(ꢏꢄꢅꢍꢆꢉꢕꢃꢕꢈꢏꢑ

AS29LV

800

X

–XXX

X

Options:

B = Burn-in

H = High I (<1mA)

Blank= Standard

3V Flash

EEPROM

prefix

Package:

S = SO

Temperature range:

C = Commercial: 0°C to 70°C

Device T= Top boot configuration

number B= Bottom boot configuration access time

Address

SB

T = TSOP I = Industrial: -40°C to 85°C

9/ 26/ 01; V.1.5

ꢋꢚꢚ#ꢛ$%ꢁꢇꢀꢁꢄ#%ꢞ$'(%ꢃꢞꢆ

P. 25 of 25

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trade-

marks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.

The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under

development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate

as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or

implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as

express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of

products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products

for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting sys-

tems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.


型号：	AS29LV800T-80SI
厂家：	ALLIANCE SEMICONDUCTOR CORPORATION
描述：	Flash, 512KX16, 80ns, PDSO44, PLASTIC, MO-175AA, SO-44 光电二极管内存集成电路
文件：	总25页 (文件大小：231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS29LV800T-80SI [ALSC]

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