AS4C1M16S-CI [ALSC]
Programmable Mode registers;
| 型号： | AS4C1M16S-CI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Programmable Mode registers |
| 文件： | 总54页 (文件大小：1530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C1M16S-C&I
Revision History
Revision Details
Date
Rev 1.0
Rev 2.0
Preliminary datasheet
Add 166MHZ and industrial parts.
February 2015
March 2015
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
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Rev. 2.0 March /2015
0
AS4C1M16S-C&I
1M x 16 bit Synchronous DRAM (SDRAM)
Advanced (Rev. 2.0, March /2015)
Features
Overview
Fast access time: 5.4/5.4ns
Fast clock rate: 166/143 MHz
Self refresh mode: standard
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Industrial Temperature: -40~85 C
The 16Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 16 Mbits. It is
internally configured as a dual 512K word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 512K x 16 bit banks is organized
as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue
for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The SDRAM provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth and particularly well suited
to high performance PC applications
°
JEDEC standard +3.3V 0.3V power supply
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
-Pb and Halogen Free
Table 1. Key Specifications
AS4C1M16S-C&I
-6/7
tCK3
tAC3
tRAS
tRC
Clock Cycle time(min.)
Access time from CLK (max.)
Row Active time(min.)
Row Cycle time(min.)
6/7
ns
5.4/5.4 ns
42/42 ns
60/63 ns
Table 2.Ordering Information
Part Number
Frequency Package
Temperature Temp Range
AS4C1M16S-7TCN
AS4C1M16S-6TIN
143MHz
166MHz
50-Pin TSOPII Commercial
50-Pin TSOPII Industrial
0~70
-40~85
℃
℃
T: indicates TSOP II package
C: Commercial
I: Industrial
N: indicates Pb and Halogen Free
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Figure 1 Pin Assignment (Top View)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE#
CAS#
RAS#
CS#
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
UDQM
CLK
CKE
NC
A9
A11
A8
A10/AP
A0
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
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Figure 2. Block Diagram
CLOCK
BUFFER
CLK
CKE
2048x256x16
CELL ARRAY
(BANK #0)
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
Column Decoder
DQ0
DQs
COLUMN
COUNTER
Buffer
A10/AP
MODE
REGISTER
DQ15
LDQM, UDQM
ADDRESS
BUFFER
A0
A9
A11
2048x256x16
CELL ARRAY
(BANK #1)
REFRESH
COUNTER
Column Decoder
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Pin Descriptions
Table 3. Pin Details
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device enters
Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
A11
Input
Input
Bank Activate: A11 (BA) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A10
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 512K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS#
Input
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS#
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
WE#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access
is started by asserting CAS# "LOW." Then, the Read or Write command is
selected by asserting WE# "LOW" or "HIGH."
Input
Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK. The
WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
LDQM,
UDQM
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O
buffer controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is
sampled HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during
a write cycle. Output data is masked (two-clock latency) when LDQM/UDQM is
sampled HIGH during a read cycle. UDQM masks DQ15-DQ8, and LDQM masks
DQ7-DQ0.
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DQ0-DQ15 Input/Output
Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
No Connect: These pins should be left unconnected.
VDDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V 0.3V )
VSSQ
VDD
VSS
Supply
Supply
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: 3.3V 0.3V
Ground
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Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table
4 shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
BankActivate
State CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
Idle(3)
Any
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
V
X
X
V
V
V
V
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
H
L
X
H
L
X
X
L
L
H
H
H
L
H
L
BankPrecharge
PrechargeAll
L
Any
H
L
L
Write
Active(3)
Active(3)
Active(3)
Active(3)
Idle
L
H
H
H
H
L
L
Write and AutoPrecharge
Read
H
L
L
L
L
H
H
L
Read and Autoprecharge
Mode Register Set
No-Operation
H
L
OP code
L
Any
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
L
H
H
X
L
H
L
Burst Stop
Active(4)
Device Deselect
AutoRefresh
Any
X
H
H
X
H
X
V
Idle
SelfRefresh Entry
SelfRefresh Exit
Idle
L
L
Idle
H
X
H
X
V
X
H
X
V
(SelfRefresh)
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any(5)
Active
H
H
L
L
X
X
X
X
X
X
X
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
Clock Suspend Mode Exit
Power Down Mode Exit
L
L
H
H
X
X
X
X
X
X
X
X
Any
(PowerDown)
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
H
Note: 1. V=Valid, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by A11 signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
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Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", A11 = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BA signals. By latching the
row address on A0 to A10 at the time of this command, the selected row access is initiated. The read
or write operation in the same bank can occur after a time delay of tRCD (min.) from the time of bank
activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by tRC (min.).
The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to
reduce chip area; therefore it restricts the back-to-back activation of the two banks. tRRD (min.)
specifies the minimum time required between activating different banks. After this command is used,
the Write command and the Block Write command perform the no mask write operation.
T0
T1
T2
T3
Tn+3 Tn+4
Tn+5
Tn+6
CLK
Bank A
Bank A
Bank B
Bank A
ADDRESS
Row Addr.
Col Addr.
Row Addr.
Row Addr.
RAS# - CAS# delay(tRCD
)
RAS# - RAS# delay time(tRRD)
Bank A
Activate
Bank B
Activate
Bank A
Activate
R/W A with
AutoPrecharge
NOP
NOP
NOP
NOP
COMMAND
RAS# - Cycle time(tRC
)
AutoPrecharge
Begin
Don’t Care
Figure 3. BankActivate Command Cycle
(Burst Length = n)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by A11 signal. The precharged bank
is switched from the active state to the idle state. This command can be asserted anytime after tRAS
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank
can be active is specified by tRAS (max.). Therefore, the precharge function must be performed in any
active bank within tRAS (max.). At the end of precharge, the precharged bank is still in the idle state
and is ready to be activated again.
3
4
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if both
banks are not in the active state. Both banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in
an active bank. The bank must be active for at least tRCD (min.) before the Read command is issued.
During read bursts, the valid data-out element from the starting column address will be available
following the CAS# latency after the issue of the Read command. Each subsequent data-out element
will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-
impedance at the end of the burst unless other command is initiated. The burst length, burst
sequence, and CAS# latency are determined by the mode register, which is already programmed. A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
CAS# Latency=3
tCK3, DQ
DOUT A3
Figure 4. Burst Read Operation
(Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank or
the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DOUT A0
DOUT B0
DOUT A0
DOUT B1
DOUT B0
DOUT B2
DOUT B1
DOUT B3
DOUT B2
CAS# Latency=3
tCK3, DQ
DOUT B3
Figure 5. Read Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read data
and the Write command (refer to the following three figures). If the data output of the burst read
occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least one
clock prior to the Write command to avoid internal bus contention.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
DQM
Bank A
Activate
NOP
NOP
NOP
NOP
READ A
WRITE A
DIN A0
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DIN A1
DIN A2
DIN A3
Figure 6. Read to Write Interval
(Burst Length 4, CAS# Latency = 2)
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
NOP
READ A
NOP
NOP
WRITE B
DIN B0
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
Figure 7. Read to Write Interval
(Burst Length 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DIN B0
NOP
NOP
COMMAND
CAS# Latency=3
tCK3, DQ
DOUT A0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
Don’t Care
≧
Figure 8. Read to Write Interval
(Burst Length
4, CAS# Latency = 3)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank
Row
Bank (s)
ADDRESS
tRP
READ A
NOP
NOP
NOP
Precharge
NOP
NOP
Activate
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
CAS# Latency=3
tCK3, DQ
DOUT A3
Figure 9. Read to Precharge
(CAS# Latency = 2, 3)
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5
6
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of tRP (min.) + burst length . At full-page burst, only the read operation is performed in this
{
}
command and the auto precharge function is ignored.
Write command
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row
in an active bank. The bank must be active for at least tRCD (min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
don’t care
DIN A1
DIN A2
DIN A3
DQ
The first data element and the write
are registered on the same clock edge
Figure 10. Burst Write Operation
(Burst Length = 4)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
DIN A0
WRITE B
DIN B0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DIN B1
DIN B2
DIN B3
DQ
Figure 11. Write Interrupted by a Write
(Burst Length = 4)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
DIN A0
READ B
don’t care
don’t care
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DOUT B0
DOUT B1
DOUT B0
DOUT B2
DOUT B1
DOUT B3
DOUT B2
CAS# Latency=3
tCK3, DQ
don’t care
DIN A0
DOUT B3
Input data must be removed from the DQ at
least one clock cycle before the Read data
appears on the outputs to avoid data contention
Figure 12. Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element is
registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the last
data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command
is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DQM
tRP
WRITE
NOP
NOP
Precharge
Bank (s)
NOP
NOP
Activate
NOP
COMMAND
Bank
Col n
ROW
ADDRESS
DQ
tWR
DIN
n
DIN
N+1
Don’t Care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of (burst length -1) + tWR + tRP (min.) . At full-page burst, only the write operation is performed
{
}
in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Bank A
Activate
Bank A
Activate
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tDAL
DIN A0
DIN A1
DQ
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 14. Burst Write with Auto-Precharge
(Burst Length = 2)
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8
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in
the Mode register to make SDRAM useful for a variety of different applications. The default values of
the Mode Register after power-up are undefined; therefore this command must be issued at the
power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the
mode register. Two clock cycles are required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as both banks are in the idle state.
Table 5. Mode Register Bitmap
A11
0
A10
RFU* WBL
A9
A8
Test Mode
A7
A6
A5
A4
A3
BT
A2
A1
A0
CAS# Latency
Burst Length
A9
0
1
Write Burst Mode
Burst
A8 A7
Test Mode
Normal
Vendor Use Only
Vendor Use Only
A3 Burst Type
0
1
0
0
0
1
0
1
Sequential
Interleave
Single Bit
A6
A5
0
0
1
1
A4
0
1
0
1
CAS# Latency
Reserved
Reserved
2 clocks
A2
0
0
0
0
A1
0
0
1
1
A0
Burst Length
0
0
0
0
1
0
1
0
1
1
1
2
4
8
3 clocks
Reserved
0
0
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
CS#
tMRD
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
DQ
tRP
Hi-Z
Mode Register
Set Command
Any
Command
PrechargeAll
Don’t Care
Figure 15. Mode Register Set Cycle
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Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 1, 2, 4, 8, or full page.
Table 6. Burst length
A2
0
A1
0
A0
0
Burst Length
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Full Page
1
0
1
1
1
0
1
1
1
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential
Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length
of 4 and 8.
Table 7. Addressing Mode Select Field
A3
0
Addressing Mode
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 8. Burst Definition
Start Address
Burst
Length
Sequential
Interleave
A2
X
X
X
X
X
X
0
0
0
0
1
A1
X
X
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
2
4
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
n, n+1, n+2, n+3, …255, 0,
1, 2, … n-1, n, …
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
1
0
0
1
8
1
1
1
1
Full page location = 0-255
Not Support
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CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field. tCAC
(min) CAS# Latency X tCK
Table 9. CAS Latency
A6
0
A5
0
A4
0
CAS# Latency
Reserved
Reserved
2 clocks
0
0
1
0
1
0
0
1
1
3 clocks
1
X
X
Reserved
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
Table 10. Test Mode field
A8
0
A7
0
Test Mode
normal mode
0
1
Vendor Use Only
Vendor Use Only
1
X
Write Burst Length (A9)
This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-Read-Burst-Write
mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected.
Table 11. Write Burst Length
A9
0
Write Burst Mode
Burst-Read-Burst-Write
Burst-Read-Single-Write
1
Note: A11 should stay “L” during mode set cycle.
9
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).
This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command
is only effective in a read/write burst without the auto precharge function. The terminated read burst
ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write
burst is shown in the following figure.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
The burst ends after a delay equal to the CAS# Latency
CAS# Latency=2
tCK2, DQ
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
CAS# Latency=3
tCK3, DQ
DOUT A3
Figure 16. Termination of a Burst Read Operation (Burst Length
＞
4, CAS# Latency = 2, 3)
T7 T8
T0
T1
T2
T3
T4
T5
T6
CLK
Burst
Stop
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
don’t care
DIN A1
DIN A2
DQ
Figure 17. Termination of a Burst Write Operation
(Burst Length = X)
11 Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and
Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to
the No Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto refresh
operation is specified by tRC (min.). To provide the AutoRefresh command, both banks need to be in
the idle state and the device must not be in power down mode (CKE is high in the previous cycle).
This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP (min), must be met before successive auto refresh operations are
performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for
data retention and low power operation. Once the SelfRefresh command is registered, all the inputs
to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh
addressing and timing is internally generated to reduce power consumption. The SDRAM may
remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the
external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
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14 SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or
Device Deselect commands must be issued for tXSR (min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the
subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. tPDE (min.) is required when the device exits from the PowerDown mode. Any subsequent
commands can be issued after one clock cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every word
of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output buffers.
LDQM/UDQM is also used for device selection, byte selection and bus control in a memory system.
LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
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Table 12. Absolute Maximum Rating
Symbol
VIN, VOUT
VDD, VDDQ
Item
Values
- 1.0 ~ 4.6
-1.0 ~ 4.6
0 ~ 70
-40 ~ 85
- 55 ~ 125
260
Unit
V
Note
Input, Output Voltage
Power Supply Voltage
1
1
1
1
1
1
1
1
V
Commercial
Industrial
C
°
C
°
C
°
C
°
TA
Ambient Temperature
TSTG
TSOLDER
PD
Storage Temperature
Soldering Temperature
Power Dissipation
1
W
IOS
Short Circuit Output Current
50
mA
Table 13. Recommended D.C. Operating Conditions
(TA = -40~85 C)
°
Symbol
VDD
Parameter
Min.
3.0
Max.
Unit
V
Note
Power Supply Voltage
3.6
3.6
2
2
2
2
VDDQ
VIH
Power Supply Voltage(for I/O Buffer)
LVTTL Input High Voltage
LVTTL Input Low Voltage
3.0
V
2.0
VDDQ+0.3
0.8
V
VIL
- 0.3
V
Input Leakage Current
( 0V VIN VDD, All other pins not under test = 0V )
IIL
- 10
- 10
10
10
A
A
Output Leakage Current
Output disable, 0V VOUT VDDQ
IOZ
)
VOH
VOL
LVTTL Full Drive Output "H" Level Voltage
LVTTL Full Drive Output "L" Level Voltage
IOUT = -2mA
IOUT = 2mA
－
2.4
V
V
－
0.4
Table 14. Capacitance
(VDD = 3.3V, f = 1MHz, TA = 25 C)
°
Symbol
Parameter
Min.
Max.
Unit
pF
CI
Input Capacitance
Input/Output Capacitance
2
4
5
7
CI/O
pF
Note: These parameters are periodically sampled and are not 100% tested.
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Table 15. D.C. Characteristics
(VDD = 3.3V 0.3V, TA = -40~85 C)
°
-6
80
25
-7
70
25
Description/Test condition
Symbol
Unit Note
Max.
Operating Current
tRC tRC(min), Outputs Open
One bank active
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# VIH(min), CKE VIH
Input signals are changed every 2clks
Precharge Standby Current in power down mode
tCK = 15ns, CKE VIL(max)
IDD1
3
IDD2N
2
2
2
2
IDD2P
Precharge Standby Current in power down mode
tCK = , CKE VIL(max)
IDD2PS
Active Standby Current in non-power down mode
tCK = 15ns, CKE VIH(min), CS# VIH(min)
Input signals are changed every 2clks
Active Standby Current in non-power down mode
CKE VIH(min), CLK VIL(max), tCK =
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
mA
40
40
IDD3N
35
110
90
35
100
80
IDD3NS
IDD4
3, 4
3
IDD5
tRC tRC(min)
Self Refresh Current
CKE 0.2V ; for other inputs VIH VDD - 0.2V, VIL 0.2V
2
2
≧
IDD6
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Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
±
(VDD = 3.3V 0.3V, TA = -40~85 C) (Note: 5, 6, 7, 8)
°
-6
-7
Symbol
A.C. Parameter
Row cycle time
Unit Note
Min.
Max.
Min.
Max.
tRC
9
60
-
63
-
(same bank)
tRCD
RAS# to CAS# delay
(same bank)
9
18
18
12
42
-
21
21
14
42
-
ns
9
tRP
Precharge to refresh/row activate
command (same bank)
-
-
-
-
tRRD
Row activate to row activate delay
(different banks)
9
tRAS
tWR
tCK
Row activate to precharge time
(same bank)
100K
100K
Write recovery time
tCK
2
7.5
6
-
2
8
-
CL* = 2
-
-
10
Clock cycle time
CL* = 3
-
7
-
tCH
tCL
Clock high time
Clock low time
2.5
2.5
-
-
2.5
2.5
-
-
ns
11
-
-
Access time from CLK
(positive edge)
CL* = 2
CL* = 3
6
6.5
tAC
-
5.4
-
5.4
tCCD
tOH
tLZ
CAS# to CAS# Delay time
Data output hold time
1
-
1
-
tCK
2
-
2
-
10
Data output low impedance
Data output high impedance
1
-
1
-
tHZ
-
5.4
-
5.4
ns
8
tIS
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
PowerDown Exit set-up time
2
-
2
-
11
11
tIH
0.8
-
-
0.8
-
-
tPDE
tREFI
tXSR
tCK
s
tIS+ CK
t
tIS+tCK
Refresh Interval Time
-
15.6
-
15.6
Exit Self-Refresh to any Command
tRC+ IS
t
-
tRC+ IS
t
-
ns
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns.VIL (Min) = -1.0V for pulse
width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK
.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
6. A.C. Test Conditions
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Table 17. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Input Signal Levels
Reference to the Under Output Load (B)
2.4V / 0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2KΩ
Output
Output
Z0=50Ω
870Ω
30pF
30pF
Figure 18.1 LVTTL D.C. Test Load (A)
Figure 18.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11. Assumed input rise and fall time tT (tR & tF) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 s, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command.
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Timing Waveforms
Figure 19. AC Parameters for Write Timing
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCH
tCL
tIS
tIS
Begin Auto
Precharge Bank A
Begin Auto
Precharge Bank B
tIH
CS#
RAS#
CAS#
WE#
A11
tIH
RAx
RBx
RBx
RAy
RAy
A10
tIS
RAx
CAx
CBx
CAy
A0-A9
DQM
tRCD
tDAL
tIS
tRC
tWR
tIH
Hi-Z
DQ
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
Write with
Activate
Command
Bank A
Write with
Activate
Auto Precharge Command
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Auto Precharge
Command
Bank B
Command
Bank A
Bank B
Don’t Care
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Figure 20. AC Parameters for Read Timing
(Burst Length=2, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
CLK
CKE
tCH tCL
Begin Auto
Precharge Bank B
tIH
tIS
tIS
tIH
CS#
RAS#
CAS#
WE#
A11
A10
tIH
RAx
RBx
RBx
RAy
RAy
tIS
A0-A9
DQM
RAx
CAx
tRRD
CBx
tRAS
tRC
tAC
tLZ
tRCD
tRP
tHZ
Hi-Z
DQ
Bx0
Bx1
tHZ
Ax0
tOH
Ax1
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Don’t Care
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Figure 21. Auto Refresh
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
RAx
CAx
A0-A9
DQM
tRC
tRP
tRC
tRCD
DQ
Ax0
Ax1
Activate
Command
Bank A
Read
Command
Bank A
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Don’t Care
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Figure 22. Power on Sequene and Auto Refresh
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
Minimum for 2 Refresh Cycles are required
Is reguired
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
tRP
tMRD
Hi-Z
DQ
Precharge All
Command
Any
Command
1st Auto Refresh(*)
Command
2nd Auto Refresh(*)
Command
Inputs must be
Mode Register
Set Command
Stable for
200μs
Don’t Care
Note(*): The Auto Refresh command can be issue before or after Mode Register Set command
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Figure 23. Self Refresh Entry & Exit Cycle
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
CKE
*Note 2
*Note 8
tXSR
*Note 5
*Note 1
*Note 3,4
tPDE
tIS
tIH
*Note 6
tIS
*Note 7
CS#
RAS#
CAS#
WE#
A11
*Note 9
A10
A0-A9
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Exit
Auto Refresh
Self Refresh Entry
Don’t Care
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for valid setup time and hold time.
7. CS# starts from high.
8. Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
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March /2015
AS4C1M16S-C&I
Figure 24.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
RAx
CAx
A0-A9
DQM
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DQ
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 24.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
RAx
CAx
A0-A9
DQM
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DQ
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 25. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
RAx
CAx
A0-A9
DQM
Hi-Z
DAx0
Write
DAx1
DAx2
DAx3
DQ
Activate
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Command
Bank A
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
(Burst Length=4, CAS# Latency=2)
Figure 26. Power Down Mode and Clock Suspension
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tIH tIS
tPDE
Valid
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
CAx
A0-A9
DQM
tHZ
Ax3
Hi-Z
Ax0
Ax1
Ax2
DQ
ACTIVE
STANDBY
PRECHARGE
STANDBY
Precharge
Command
Bank A
Activate
Command
Bank A
Power Down
Mode Exit
Read
Command
Bank A
Clock Suspension
Start
Clock Suspension
End
Any
Command
Power Down
Mode Exit
Power Down
Mode Entry
Power Down
Mode Entry
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 27.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
RAw
RAz
RAz
CAw
CAx
CAy
CAz
A0-A9
DQM
Hi-Z
Aw0
Aw1
Aw2 Aw3
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
DQ
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 27.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
RAw
RAz
RAz
CAw
CAx
CAy
CAz
A0-A9
DQM
Hi-Z
Aw0
Aw1
Aw2 Aw3
Read
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
DQ
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Command
Bank A
Don’t Care
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Rev. 2.0
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AS4C1M16S-C&I
Figure 28. Random Column Write (Page within same Bank)
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBw
RBz
RBz
CBw
CBx
CBy
CBz
A0-A9
DQM
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1
DQ
Precharge
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 29.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RAx
RBy
RBy
RBx
CBx
CAx
CBy
A0-A9
DQM
tAC
tRCD
tRP
Hi-Z
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
DQ
Activate
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank B
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 29.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RAx
RBy
RBy
RBx
CBx
CAx
CBy
A0-A9
DQM
tAC
tRCD
tRP
Hi-Z
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
DQ
Activate
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank A
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 30. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBx
RAy
RAy
RAx
CAx
CBx
CAy
A0-A9
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
DQ
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Don’t Care
*tWR>tWR (min.)
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Rev. 2.0
March /2015
AS4C1M16S-C&I
(Burst Length=4, CAS# Latency=2)
Figure 31.1. Read and Write Cycle
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
CAx
CAy
CAz
A0-A9
DQM
Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
DQ
The Write Data
is Masked with a
Zero Clock
The Read Data
is Masked with a
Two Clock
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Write
Command
Bank A
Latency
Latency
Don’t Care
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 31.2. Read and Write Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
RAx
CAx
CAy
CAz
A0-A9
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
The Write Data
The Read Data
is Masked with a
Two Clock
Activate
Command
Bank A
Read
Command
Bank A
Write
Command
Bank A
is Masked with a
Zero Clock
Read
Command
Bank A
Latency
Latency
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 32.1. Interleaving Column Read Cycle
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBx
RBx
CAy
CBw
CBx
CBy
CAy
CBz
A0-A9
DQM
tRCD
tAC
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bw0
Bw1
Bx0
Bx1
By0
By1
Ay0
Ay1
Bz0
Bz1
Bz2
Bz3
DQ
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank B
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 32.2. Interleaved Column Read Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBx
RBx
CAx
CBx
CBy
CBz
CAy
A0-A9
DQM
tRCD
tAC
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
By0
By1
Bz0
Bz1
Ay0
Ay1
Ay2
Ay3
DQ
Precharge
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Activate
Command
Bank B
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 33. Interleaved Column Write Cycle
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBw
CAx RBw
CBw
CBx
CBy
CAy
CBz
tWR
A0-A9
DQM
tWR
tRCD
tRRD>tRRD (min)
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Hi-Z
DQ
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Activate
Precharge
Command
Bank B
Command
Bank A
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 34.1. Auto Precharge after Read Burst
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBx
RBy
RBy
RAz
RAz
RAx
CAx
CBx
CAy
CBy
A0-A9
DQM
tRP
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
DQ
Read with
Activate
Command
Bank A
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Auto precharge
Command
Bank A
Don’t Care
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Rev. 2.0
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AS4C1M16S-C&I
Figure 34.2. Auto Precharge after Read Burst
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
High
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
RAx
CAx
CBx
CAy
tRP
CBy
A0-A9
DQM
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
DQ
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Don’t Care
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AS4C1M16S-C&I
Figure 35. Auto Precharge after Write Burst
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
High
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
RAx
CAx
CBx
CAy
CBy
A0-A9
DQM
tDAL
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3
DQ
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Don’t Care
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 36.1. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
RAx
CAx
CBx
A0-A9
DQM
tRP
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6
DQ
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Full Page burst operation does not
Burst Stop
Command
Don’t Care
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
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Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 36.2. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
RAx
CAx
CBx
A0-A9
DQM
tRP
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
DQ
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
Burst Stop
Command
Don’t Care
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
45
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 37. Full Page Write Cycle
(Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
RAx
CAx
CBx
A0-A9
DQM
Data is ignored
Hi-Z
DAx
DAx+1 DAx+2 DAx+3 DAx-1
Activate
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
DQ
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Full Page burst operation does not
Don’t Care
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
46
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 38. Byte Read and Write Operation
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
CAx
CAy
CAz
A0-A9
LDQM
UDQM
Ax0
Ax1
Ax1
Ax2
Ax2
DAy1 Day2
Az1
Az1
Az2
Az2
DQ0-DQ7
DQ8-DQ15
Ax3
DAy0 DAy1
DAy3
Az0
Az3
Upper Byte
is masked
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Upper Byte
is masked
Lower Byte
is masked
Write
Command
Bank A
Lower Byte
is masked
Lower Byte
is masked
Don’t Care
Confidential
47
Rev. 2.0
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AS4C1M16S-C&I
Figure 39. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
High
CS#
RAS#
CAS#
WE#
A11
A10
RAv
RAv
RBw
RBw
RBu
RAu
RBv
RBv
RBu
CBu RAu
CAu
CBv
CAv
A0-A9
DQM
tRP
tRP
tRP
Bu0
Bu1
Bu2
Bu3
Au0
Au1
Au2
Au3
Bv0
Bv1
Bv2
Bv3
Av0
Av1
Av2
Av3
DQ
Read
Bank A
with Auto
Precharge
Read
Bank A
with Auto
Precharge
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Read
Bank B
Read
with Auto
Precharge
Bank B
with Auto
Precharge
Don’t Care
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AS4C1M16S-C&I
(Burst Length=Full Page, CAS# Latency=2)
Figure 40. Full Page Random Column Read
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBw
RAx
RAx
RBx
RBx
CAx
CBx
CAy
CBy
CAz
CBz
A0-A9
DQM
tRP
tRRD
tRCD
Hi-Z
Ax0
Ax1
Bx0
Ay0
Ay1
By0
By1
Az0
Az1
Az2
Bz0
Bz1
Bz2
DQ
Read
Command
Bank B
Activate
Command
Bank A
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Activate
Command
Bank B
Read
Read
Command
Bank A
Command
Bank A
Don’t Care
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AS4C1M16S-C&I
Figure 41. Full Page Random Column Write
(Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBw
RAx
RAx
RBx
RBx
CAx
CBx
CAy
CBy
CAz
CBz
A0-A9
DQM
tWR
tRP
tRRD
tRCD
DAx0 DAx1 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Hi-Z
DQ
Write
Command
Bank B
Activate
Command
Bank A
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Write
Write
Command
Bank A
Write Data
are masked
Command
Bank A
Don’t Care
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AS4C1M16S-C&I
Figure 42. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAy
RAy
RAz
RAz
RAx
CAx
CAy
A0-A9
DQM
tWR
tRP
tRP
DAx0 DAx1
Ay0
Ay1
Ay2
DQ
Precharge Termination
of a Read Burst
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Write Burst
Write Data are masked
Don’t Care
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AS4C1M16S-C&I
Figure 43. 50 Pin TSOP II Package Outline Drawing Information
50
26
L
L1
1
25
D
L
L1
e
S
B
y
Symbol
Dimension in inch
Dimension in mm
Min
－
Normal
－
Max
0.047
0.008
0.043
0.018
－
Min
－
Normal
－
Max
1.20
0.20
1.1
0.45
－
A
A1
A2
B
c
D
0.002
0.035
0.008
－
0.005
0.039
－
0.05
0.9
0.2
－
0.125
1.0
－
0.006
0.825
0.400
0.031
0.155
20.95
10.16
0.80
0.82
0.395
－
0.83
0.405
－
20.82
10.03
－
21.08
10.29
－
E
e
0.455
0.016
－
0.463
0.020
0.0315
0.035
－
0.471
0.024
－
11.56
0.40
－
11.76
0.50
0.80
0.88
－
11.96
0.60
－
HE
L
L1
S
－
－
－
－
－
0.004
－
0.10
y
－
－
8
0
8
0
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension: mm
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AS4C1M16S-C&I
PART NUMBERING SYSTEM
AS4C
DRAM
1M16S
6/7
T
C/I
N
C=Commercial
(0° C～70° C)
I=Industrial
Indicates Pb and
Halogen Free
1M16=1Mx16
S=SDRAM
6=166MHz
7=143MHz
T = TSOP II
(-40° C～85° C)
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt
are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and
its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in
this document. The data contained herein represents Alliance's best data and/or estimates at the time of
issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers
and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer.
Alliance does not assume any responsibility or liability arising out of the application or use of any product
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products including liability or warranties related to fitness for a particular purpose, merchantability, or
infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
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property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
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significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies
that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising
from such use.
Confidential
53
Rev. 2.0
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