AS4C32M32MD1-5BCN [ALSC]
Automatic and Controlled Precharge Command;
| 型号： | AS4C32M32MD1-5BCN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Automatic and Controlled Precharge Command |
| 文件： | 总43页 (文件大小：1239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C32M32MD1
Revision History AS4C32M32MD1 - 90-ball FBGA PACKAGE
Revision Details
Rev 1.0 Preliminary datasheet
Date
September 2014
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
-1-
Rev.1.0 Sep.2014
AS4C32M32MD1
32M x 32 bit MOBILE DDR Synchronous DRAM (SDRAM)
Confidential
Advanced (Rev. 1.0, Sep. /2014)
Feature
Description
-
-
-
-
-
4 banks x 8M x 32 organization
The AS4C32M32MD1 is a four bank mobile
DDR DRAM organized as 4 banks x 8M x 32. It
achieves high speed data transfer rates by
employing a chip architecture that pre-fetches
multiple bits and then synchronizes the output data
to a system clock.
Data Mask for Write Control (DM)
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8, 16 for Sequential Type
2, 4, 8, 16 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
-
All of the controls, address, circuits are
synchronized with the positive edge of an
externally sup-plied clock. I/O transactions are
possible on both edges of DQS.
-
-
-
-
-
-
-
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64ms
Available in 90-ball BGA
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS
latency and speed grade of the device.
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input
and output data, active on both edges
Differential clock inputs CLK and /CLK
Power Supply 1.7V - 1.95V
Drive Strength (DS) Option:Full, 1/2, 1/4, 3/4
Auto Temperature-Compensated Self Refresh
(Auto TCSR)
-
-
-
-
Additionally, the device supports low power
saving features like PASR, Auto-TCSR, DPD as
well as options for different drive strength. It’s
ideally suit-able for mobile application.
-
Partial-Array Self Refresh (PASR) Option: Full,
1/2, 1/4, 1/8, 1/16
-
-
Deep Power Down (DPD) mode
Operating Temperature Range
-
-
Commercial -25°C to 85°C (Extended)
Industrial -40°C to 85°C
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency CAS Latency
tRCD
tRP
(ns)
(ns)
400Mbps (max) 200 MHz (max)
3
15
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No Org Temperature Package
AS4C32M32MD1-5BCN 32M x 32 Commercial - 25°C to 85°C 90-ball BGA
(Extended)
AS4C32M32MD1-5BIN
32M x 32 Industrial -40°C to 85°C
90-ball BGA
Confidential
-2-
Rev.1.0 Sep.2014
AS4C32M32MD1
Block Diagram (32M x 32)
Row Addresses *Reduced Page size
Column Addresses
*
A0-A9 (A0-A8), AP, BA0, BA1
A0-A12 (A0-A13)*, BA0, BA1
Row address
buffer
Column address
counter
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Row decoder
Row decoder
Memory array
Bank A
Memory array
Bank B
Memory array
Bank C
Memory array
Bank D
8192 x 1024
x32 bits
8192 x 1024
x32 bits
8192 x 1024
x32 bits
8192 x 1024
x32 bits
Control logic & timing generator
Input buffer
Output buffer
DQ0-DQ31
CLK, CLK
Strobe
Gen.
DQS0 - DQS3
Data Strobe
Confidential
-3-
Rev.1.0 Sep.2014
AS4C32M32MD1
32MX32 90 BALL BGA
CONFIGURATION
Top View
9
8
7
6
5
ꢁꢂꢂꢂꢂꢂꢃꢂꢂꢂꢂꢂꢄ
ꢀ
:1C bmm!)7Y 26*!D T Q
2
3
4
8
9
:
A
B
C
D
E
F
B
C
D
E
F
G
H
I
K
L
M
N
O
Q
S
W T T
E R 42
E R 3:
E R 38
E R 36
E R T 4
E N 4
D L
W T T R
E R 41
E R 39
E R 37
E R 35
O D
W E E R
E R 28
E R 2:
E R 32
E R 34
B 242
X F
E R 27
E R 29
E R 31
E R 33
E R T 3
E N 3
W E E
W E E R
W T T R
W E E R
W T T R
W E E
D L F
W T T R
W E E R
3
Uftu
W E E R
W T T
D L
B 23
D B T
C B 1
S B T
C B 2
G
H
B :
B 22
D T
B 7
B 8
B 9
B 210B Q
B 1
E N 1
E R T 1
E R 7
E R 5
E R 3
E R 1
B 2
B 5
E N 2
E R T 2
E R :
B 6
B 3
E R 8
E R 6
E R 4
E R 2
W E E R
B 4
J
K
/
W T T R
W E E R
W T T R
W E E R
W T T
E R 9
E R 21
E R 23
E R 25
W T T R
W E E R
W T T R
W E E R
W T T R
W E E
E R 22
E R 24
E R 26
0
1
3
O p uf !2 ;!B 2 4 !jt!pomz!bwbjmbcmf!gps!sfevdfe!qbhf.tj{f!dpogjhvsbujpo/
O puf!3;!Uftu!!n vtu!!cf!u!jfe!up!W T T !ps!W T T R !jo!!opsn bm!!pqfsbujpot/
5
Pin Names
CLK, CLK
CKE
Differential Clock Input
Clock Enable
BA0, BA1
Bank Select
DQ0–DQ31
Data Input/Output
Data Mask
CS
Chip Select
DM0, DM1, DM3,
DM3
RAS
Row Address Strobe
Column Address Strobe
Write Enable
VDD
VSS
Power (1.7V - 1.95V)
Ground
CAS
WE
VDDQ
VSSQ
NC
Power for I/O’s (1.7V - 1.95V)
Ground for I/O’s
No Connect
DQS0, DQS1,
DQS2, DQS3
Data Strobe (Bidirectional)
A0–A13
Address Inputs
Confidential
-4-
Rev.1.0 Sep.2014
AS4C32M32MD1
Signal Pin Description
Pin
Type
Signal Polarity
Function
CLK
CLK
Input
Pulse
Positive
Edge
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
CKE
Input
Input
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Pulse Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS Input
WE
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A13
Input
Level
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
and A0-A13 defines the row address (RA0-RA13) for 32Mx32 reduced page size when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
and A0-A8 defines tthe column address (CA0-CA8) for 32Mx32 reduced page size when
sampled at the rising clock edge.
In addition to the column address, A10 is used to invoke autoprecharge operation at the
end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0,
BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
DQx
Input/
Level
Level
Level
Data Input/Output pins operate in the same manner as conventional DRAMs.
Output
BA0,
BA1
Input
—
—
Selects which bank is to be active.
LDQS,
UDQS
Input/
Data Input/Output are synchronous edges of the DQS. LDQS for DQ0-DQ7, UDQS for
DQ8-DQ15 in 32Mx16. DQS0 for DQ0-DQ7, DQS1 for DQ8-DQ15, and DQS2 for DQ16-
DQ23, DQS3 for DQ24-DQ31 in 16Mx32. Active on both edges for data input/output.
Center aligned to input data and edge aligned to output data.
Output
(DQS0~3)
UDM,
LDM
Input
Pulse Active High In Write mode, DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high. If it’s high, LDM cor-
responds to DQ0-DQ7, and UDM corresponds to data on DQ8-DQ15 in 32Mx16. DM0
corresponds to DQ0-DQ7, DM1 corresponds to data on DQ8-DQ15, DM2 corresponds
to DQ16-DQ23, and DM3 corresponds to data on DQ24-DQ31 in 16Mx32.
(DM0~3)
VDD, VSS Supply
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply
—
—
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
NC
Input
No connect.
Confidential
-5-
Rev.1.0 Sep.2014
ꢀ
AS4C32M32MD1
ꢀ
Mode Register Set
The mode register stores the data for controlling the various operating modes of the mobile DDR, includes CAS latency, addressing
mode, burst length, test mode, and various vendor specific options. The default value of the mode register is not defined.
Therefore the mode register must be written after power up to operate the mobile DDR. The device should be activated with the
CKE already high prior to writing into the Mode Register. The Mode Register is written by using the MRS command. The state of the
address signals registered in the same cycle as MRS command is written in the mode register. The value can be changed as long as
all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS latency (read latency
from column address) uses A6.. A4. BA0 must be set to low for normal operation.
A9.. AꢀꢁꢂLVꢂreserved for future use.
BA1 selects Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst length,
addressing modes and CAS latencies.
Mode Register Bitmap
$ꢀꢁꢃ$ꢀꢄꢅ$ꢆ3ꢇ
Address Bus
BA1
BA0
A9
0
A8
0
A7
0
A6
A5
A4
A3
BT
A2
A1
A0
0
0
CAS Latency
Burst Length
Mode Register
0
Register
Mode
Burst Type
A3
Access
BA1
Accessed Register
Type
0
1
Mode Register
0
1
Sequential
Interleaved
Extend. Mode Reg.
CAS Latency
A6
A5
A4
Latency
2
3
0
0
1
1
0
1
Burst Length
Length
A2
A1
A0
Sequential
Interleave
0
0
0
ꢀ
0
1
1
ꢁ
1
0
1
ꢁ
2
4
8
2
4
8
ꢀꢂ
ꢀꢂ
Confidential
-6-
Rev.1.0 Sep.2014
ꢀ
AS4C32M32MD1
ꢀ
EMRS
The Extended Mode Register is responsible for setting the Drive strength options and Partial array Self Refresh. The
EMRS can be programmed by performing a normal Mode Register Setup operation and setting the BA1=1 and BA0=0.
In order to save power consumption, the mobile DDR Sdram has five (PASR) options: Full array, 1/2, 1/4 ,3/4 of Full
Array. Additionally, the device has internal temperature sensor to control self refresh cycle atuomatically according to
the two temperature range; Max. 45 deg C, and Max. 85 deg C. This is the device internal Temperature Compensated
Self Refresh(TCSR). The device has four drive strength options: Full, 1/2, 1/4, 3/4.
Extended Mode Register Set
Address Bus
BA1
1
BA0
0
A9
A8
A7
A6
A5
A4
0
A3
0
A2
A1
A0
$ꢀꢁꢃ$ꢀꢄꢅ$ꢆ3ꢇ
PASR
0
DS
Mode Register
Extended Mode
Register Access
BA0
Accessed Register
BA1
Drive Strength
0
1
0
0
Mode Register
A6
A5
Drive Strength
,QWHUQDOꢂ7&65
Extend. Mode Reg.
6HOIꢂ5HIUHVKꢂF\FOHꢂLVꢂFRQWUꢃ
ROOHGꢂDXWRPDWLFDOO\ꢂE\ꢂLQWHU
QDOꢂWHPSHUDWXUHꢂVHQVRUꢂ
DQGꢂFRQWUROꢂFLUFXLWꢂDFFRUGLQJꢂ
WRꢂWKHꢂWZRꢂWHPSHUDWXUHꢈ
0
0
1
1
0
1
0
1
Full
1/2
1/4
ꢃꢄꢅ
All other Reserved
Partial Array Self Refresh
Size of Refreshed Area
A2
A1
A0
0
0
0
0
0
1
0
1
0
Full Array
1/2 of Full Array (Banks 0, 1)
1/4 of Full Array (Bank 0)
Reserved
0
1
1
1
0
0
1
0
1
Reserved
1/8 of Full Array (BA1=BA0=A11=0)
1/16 of Full Array (BA1=BA0=A11=A10=0)
Reserved
1
1
1
1
0
1
Confidential
-7-
Rev.1.0 Sep.2014
ꢀ
AS4C32M32MD1
ꢀ
Signal and Timing Description
General Description
The 1Gbit mobile DDR is a 128M byte mobile DDR SDRAM. It consists of four banks. Each bank is organized as 8192
rows x 1024 columns x 32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which is
then followed by a Read or Write command. The address bits registered coincident with the Activate command are used
to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A13.. A0 select the row.
Address bits A9.. A0 registered coincident with the Read or Write command are used to select the starting column loca-
tion for the burst access.
The regular Single Data Rate SDRAM read and write cycles only use the rising edge of the external clock input. For the
mobile SDRAM the special signals DQSx (Data Strobe) are used to mark the data valid window. During read bursts, the
data valid window coincides with the high or low level of the DQSx signals. During write bursts, the DQSx signal marks
the center of the valid data window. Data is available at every rising and falling edge of DQSx, therefore the data transfer
rate is doubled.
For Read accesses, the DQSx signals are aligned to the clock signal CLK.
Special Signal Description
Clock Signal
The mobile DDR operates with a differential clock (CLK and CLK) input. CLK is used to latch the address and command
signals. Data input and DMx signals are latched with DQSx. The minimum and maximum clock cycle time is defined by
t
.
CK
The minimum and maximum clock duty cycle are specified using the minimum clock high time t
and the minimum
CH
clock low time t respectively.
CL
Command Inputs and Addresses
Like single data rate SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a rising
edge of the clock determines a mobile DDR command.
Command and Address Signal Timing
VIH
CLK, CLK#
VIL
tIS
VIH
VTT
VIL
Address,
CS#, RAS#,
CAS#, WE#,
CKE
Valid
Valid
tIH
Confidential
-8-
Rev.1.0 Sep.2014
ꢀ
AS4C32M32MD1
ꢀ
Data Strobe and Data Mask
Operation at Burst Reads
The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The data
strobe signal goes 1 clock cycle low before data is driven by the mobile DDR and then toggles low to high and high to low
till the end of the burst. CAS latency is specified to the first low to high transition. The edges of the Output Data signals
and the edges of the data strobe signals during a read are nominally coincident with edges of the input clock.
The tolerance of these edges is specified by the parameters t
and t
and is referenced to the crossing point of
DQSCK
AC
timing parameter describes the skew between the data strobe edge and the output
the CLK and /CLK signal. The t
data edge.
DQSQ
The following table summarizes the mapping of LDQS, UDQS(DQS0 ~ DQS3) and LDM, UDM(DM0 ~ DM3) signals to
the data bus.
Mapping of DQS0~DQS3 and DM0~DM3
Data strobe signal
LDQS, DQS0
UDQS, DQS1
DQS2
Data mask signal
LDM, DM0
UDM, DM1
DM2
Controlled data bus
DQ7 .. DQ0
DQ8 .. DQ15
DQ16 .. DQ23
DQ24 .. DQ31
DQS3
DM3
The minimum time during which the output data is valid is critical for the receiving device. This also applies to the Data
Strobe DQS during a read since it is tightly coupled to the output data. The parameters t and t define the mini-
QH
DQSQ
mum output data valid window. Prior to a burst of read data, given that the device is not currently in burst read mode,
the data strobe signals transit from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble” t
.
RPRE
This transition happens one clock prior to the first edge of valid data.
Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe sig-
nals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble” t
.
RPST
Confidential
-9-
Rev.1.0 Sep.2014
ꢀ
AS4C32M32MD1
ꢀ
Data Output Timing - t
and t
DQSCK
AC
T0
T1
T2
T3
T3n
T4
T4n
T5
T5n
T2n
T6
CK#
CK
NOP1
CL = 3
NOP1
NOP1
NOP1
NOP1
NOP1
Command
READ
tHZ
tDQSCK
tDQSCK
tLZ
tRPRE
tRPST
DQS or LDQS/UDQS 2
t
LZ
All DQ values, collectively3
T3
T4
T5
T2
T2n
T3n
T5n
T4n
4
tAC
tAC
4
tHZ
Don’t Care
1. Commands other than NOP can be valid during this cycle.
Notes:
tDQSQ
2. DQ transitioning after DQS transitions define
window.
tDQSQ
t
3. All DQ must transition by
tAC
after DQS transitions, regardless of
AC
.
4.
is the DQ output window relative to CK and is the long-term component of DQ skew.
Confidential
-10-
Rev.1.0 Sep.2014
ꢀ
AS4C32M32MD1
Operation at Burst Write
ꢀ
During a write burst, control of the data strobe is driven by the memory controller. The LDQS, UDQS signals are centered with respect
to data and data mask. The tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the
setup and hold time parameters of data (t
same cycle when the corresponding LDM, UDM signal is high (i.e. the LDM,UDM mask to write latency is zero.)
& t
) and data mask (t ). The input data is masked in the
& t
QDQSS QDQSH
DMDQSS DMDQSH
LDQS, UDQS, LDM, and UDM Timing at Write
VIH
VTT
VIL
LDQS,
UDQS
tDMDQSS
tDMDQSS
VIH
VTT
VIL
LDM,
UDM
tDMDQSH
tDMDQSH
tQDQSH
tQDQSH
VIH
VTT
VIL
Q
+3
Q
Q+1
Q+2
tQDQSS
Q+4
DQx
tQDQSS
Input Data masked
Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal LDQS, UDQS changes
from Hi-Z to a valid logic low. This is referred to as the data strobe Write Preamble. Once the burst of write data is concluded, given no
subsequent burst write operation is initiated, the data strobe signal LDQS,UDQS transits from a valid logic low to Hi-Z. This is referred
the data strobe Write Postamble, t
write latency). This is different than the single data rate SDRAM where data is written in the same cycle as the Write command is issued.
. For mobile DRR data is written with a delay which is defined by the parameter t
WPST
DQSS,
DQS Pre/Postamble at Write
VIH
CLK,
/CLK
VIL
WR
tDQSS
tWPST
tWPREH
VIH
VTT
VIL
LDQS,
UDQS
"Preamble"
tWPRES
"Postamble"
VIH
VTT
VIL
Q
Q+1
Q+2
Q+3
DQx
Confidential
-11-
Rev.1.0 Sep.2014
AS4C32M32MD1
Power-Up Sequence
The following sequence is highly recommended for Power-Up :
1. Apply power and start clock. Maintain CKE and the other pins are in NOP conditions at the input
2. Apply V before or at the same time as V , apply V before or at the same time as V
, V
REF TT
DD
DDQ DDQ
3. Start clock, maintain stable conditions for 200 us
4. Apply NOP and set CKE to high
5. Apply All Bank Precharge command
6. Issue Auto Refresh command twice and must satisfy minimum t
7. Issue MRS (Mode Register Set command)
RFC
8. Issue a EMRS (Extended Mode Register Set command), not necessary
Power Up Sequence
Clock
AREF
NOP
AREF
NOP
PREA
MRS
EMRS
ACT
Command
t
t
t
MRD
t
t
RFC
200 us
MRD
RFC
RP
Mode Register Set Timing
The mobile DDR should be act ivated with CKE already high prior to writing into the mode register. Two clock cycles are required
complete the write operation in the mode register. The mode register contents can be changed using the same com mand and clock cycle
ong as all banks are in the idle state.
requirements during operation as l
Mode Register Set Timing
Clk
any
Comm.
PREA
NOP
MRS
NOP
NOP
NOP
Command
t
t
MRD
RP
Confidential
-12-
Rev.1.0 Sep.2014
AS4C32M32MD1
Bank Activation Command (ACT)
The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The mobile DDR has 4
independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank Activation command must be applied
before any Read or Write operation can be executed. The delay from the Bank Activation command to the first read or write command
must meet or exceed the minimum of RAS to CAS delay time (t
min. for read commands and t
min. for write commands).
RCDRD
RCDWR
Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The
minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank activation
delay time (t
RRD
min).
Activate to Read or Write Command Timing (one bank)
Clk
READ
or
WRITE
ACT
Command
PRE
NOP
ACT
t
RCDRD for read
t
RCDWR for write
Bank A
Row Add.
Bank A
Col. Add.
Bank A
Row Add.
Bank A
Addresses
t
RC
Activate Bank A to Activate Bank B Timing
Clk
ACT
Command
NOP
ACT
Bank A
Row Add.
Bank B
Row Add.
Addresses
t
RRD
Confidential
-13-
Rev.1.0 Sep.2014
AS4C32M32MD1
Precharge Command
This command is used to precharge or close a bank that has been activated. Precharge is initiated by issuing a Precharge command at
the rising edge of the clock. The Precharge command can be used to precharge each bank respectively or all banks simultaneously.
The Bank addresses BA0 and BA1 select the bank to be precharged. After a Precharge command, the analog delay t
until a new Activate command can be initiated to the same bank.
has to be met
RP
Table
Precharge Control
A10/AP
BA1
0
BA0
0
Precharged
0
0
0
0
1
Bank
Bank
A Only
B Only
0
1
1
0
Bank C Only
Bank D Only
All Banks
1
1
X
X
Precharge Command Timing
Clk
ACT
NOP
PRE
NOP
ACT
Command
Addresses
Bank A
Row Add
Bank A
Row Add
Bank A
tRAS
tRP
tRC
Confidential
-14-
Rev.1.0 Sep.2014
AS4C32M32MD1
Self Refresh
The Self Refresh mode can be used to retain the data in the mobile DDR if the chip is powered down. To set the mobile DDR into a
ode,
Refreshing m
Self
a Self Refresh command must be issued and CKE held low at the rising edge of the clock. Once the Self
Refresh
command is initiated, CKE must stay low to keep the device in Self Refresh mode. During the Self Refresh mode, all of the external control
signals are disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. An internal timing
generator guarantees the self refreshing of the memory content.
Self Refresh timing
Clk
Any
Comm.
NOP
DESEL
NOP
DESEL
NOP
Command
CKE
REFX
REFS
Confidential
-15-
Rev.1.0 Sep.2014
AS4C32M32MD1
Auto Refresh
The auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks must be precharged
and idle before the Auto Refresh command is applied. No control of the external address pins is required once this cycle has started. All
necessary addresses are generated in the device itself. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or
equal to the t RFC(min).
Autorefresh timing
Clk
PRE-
CHARGE
AUTO
REFRESH
NOP
Command
NOP
Command
CKE
Command is
AUTOREFRESH
or ACT
t
t
RFC
RP
Power Down Mode
The Power Down Mode is entered when CKE is set low and exited when CKE is set high. The CKE signal is sampled at the rising edge
of the clock. Once the Power Down Mode is initiated, all of the receiver circuits except CLK and the CKE circuits are gated off to reduce
power consumption. All banks can be set to idle state or stay activate during Power Down Mode, but burst activity may not be performed.
After exiting from Power Down Mode, at least one clock cycle of command delay must be inserted before starting a new command.
During Power Down Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer
than the refresh period (t
) of the device.
REF
Power Down Mode timing
Clk
Any
Command
NOP
DESEL
NOP
DESEL
PRE
NOP
NOP
Command
CKE
Power Down
Mode entry
Power Down
Mode exit
Confidential
-16-
Rev.1.0 Sep.2014
AS4C32M32MD1
Deep Power Down Mode
The Deep Power Down mode is an unique function with very low standby currents. All internal volatge generators inside
the mobile DDR are stopped and all memory data is lost in this mode. To enter the Deep Power Down mode all banks
must be precharged.
Deep Power Down Mode Entry
CLK
CKE
CS
WE
CAS
RAS
Addr.
DQM
DQ
input
DQ
output
High-Z
t RP
Precharge Command
Deep Power Down Entry
Deep Power Down Mode
Normal Mode
DP1.vsd
The deep power down mode has to be maintained for a minimum of 100µs.
Confidential
-17-
Rev.1.0 Sep.2014
AS4C32M32MD1
Deep Power Down Exit
The deep power down mode is exited by asserting CKE high.
After the exit, the following sequence is needed to enter a new command :
1. Maintain NOP input conditions for a minimum of 200 us
2. Issue precharge commands for all banks of the device
3. Issue two or more auto refresh commands and satisfy minimum t
RFC
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extende mode register
CLK
CK E
CS
RAS
CAS
WE
200
s
tRP
tRC
Deep Power Down
exit
All banks
precharge
Auto
refresh
Auto
refresh
Mode
Register Mode
Set
Extended
New
Command
Register Accepted
Set
Here
Confidential
-18-
Rev.1.0 Sep.2014
AS4C32M32MD1
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory (read cycle). The burst
length is programmable and set by address bits A0 - A3 during the Mode Register Setup command. The burst length controls the number
of words that will be output after a read command or the number of words to be input after a write command. One word is 32 bits wide.
The sequential burst length can be set to 2, 4 or 8 data words.
Burst Mode and Sequence
Starting Column Address
Order of Access within a Burst
Type = Sequential
Burst Length
2
A2
A1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 - 1
1 - 0
0
0
1
1
0
0
1
1
0
0
1
1
0 - 1 - 2 - 3
1 - 2 - 3 - 0
4
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0
0
0
0
1
1
1
1
0 - 1 - 2 - 3 - 4 - 5 - 6 - 7
1 - 2 - 3 - 4 - 5 - 6 - 7 - 0
2 - 3 - 4 - 5 - 6 - 7 - 0 - 1
3 - 4 - 5 - 6 - 7 - 0 - 1 - 2
4 - 5 - 6 - 7 - 0 - 1 - 2 - 3
5 - 6 - 7 - 0 - 1 - 2 - 3 - 4
6 - 7 - 0 - 1 - 2 - 3 - 4 - 5
7 - 0 - 1 - 2 - 3 - 4 - 5 - 6
8
Note: standard interleaved burst mode also available but not specified here.
Confidential
-19-
Rev.1.0 Sep.2014
AS4C32M32MD1
Burst Read Operation: (READ)
The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after t
from the bank activation.
RCD
The address inputs (A8.. A0) determine the starting address for the burst. The burst length (2, 4 or 8) must be defined in the Mode
Register. The first data after the READ command is available depending on the CAS latency. The subsequent data is clocked out on
the rising and falling edge of LDQS, UDQS until the burst is completed. The LDQS, UDQS signals are generated by the mobile DDR
during the Burst Read Operation.
Burst Read Operation
/CLK
CLK
Read
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
CL = 2
Burst length = 4
Read
Postamble
LDQS,
UDQS
Read
Preamble
CAS latency = 2
DQx
D-out D-out
D-out D-out
2
3
0
1
CL = 3
Read
Postamble
LDQS,
UDQS
Read
Preamble
CAS latency = 3
DQx
D-out D-out
D-out D-out
2
3
0
1
Confidential
-20-
Rev.1.0 Sep.2014
AS4C32M32MD1
Burst Write Operation (WRITE)
The Burst Write is initiated by issuing a WRITE command at the rising edge of the clock. The address inputs (A8 .. A0) determine
starting column address. Data for the first burst write cycle must be applied on the DQ pins on the first rise edge of LDQS, UDQS follow
WRITE command. The time between the WRITE command and the first corresponding edge of the data strobe is t
. The remaining
DQSS
data inputs must be supplied on each subsequent rising and falling edge of the data strobe until the burst length is completed. When the
burst has been finished, any additional data supplied to the DQ pins will be ignored.
Burst Write Operation
/CLK
CLK
COMMAND
WRITE
NOP
NOP
NOP
tDQSS
tWPST
LDQS,
UDQS
tWPRES
tWPREH
Data-in
0
Data-in
1
Data-in
2
Data-in
3
DQx
Burst length = 4
Confidential
-21-
Rev.1.0 Sep.2014
AS4C32M32MD1
Burst Stop Command (BST)
A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop Command
has the fewest restrictions, making it the easiest method to terminate a burst operation before it has been completed.
When the Burst Stop Command is issued during a burst read cycle, read data and LDQS, UDQS go to a high-Z state
after a delay which is equal to the CAS latency set in the Mode Register. The Burst Stop latency is equal to the CAS
latency CL.The Burst Stop command is not supported during a write burst operation. Burst Stop is also illegal during
Read with Auto-Precharge.
Burst Stop for Read
/CLK
CLK
READ
BST
NOP
NOP
NOP
NOP
NOP
NOP
Command
CL = 2
Burst St
op Latency = 2
LDQS,
UDQS
CAS latency = 2
DQx
D-out D-out
0
1
CL = 3
Burst Stop Latency = 3
LDQS,
UDQS
CAS latency = 3
DQx
D-out D-out
0
1
Confidential
-22-
Rev.1.0 Sep.2014
AS4C32M32MD1
Data Mask (LDM, UDM) Function
The mobile DDR has a Data Mask function that can be used only during write cycles. When the Data Mask is activated, active high
during burst write, the write operation is masked immediately. The LDM, UDM to data-mask latency zero. LDM and UDM can be issued
at the rising or negative edge of Data Strobe.
Data Mask Timing
/CLK
CLK
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
LDQS,
UDQS
D-in
0
D-in
2
D-in
3
D-in
4
D-in
5
D-in
6
D-in
1
D-in
7
DQx
LDM,
UDM
Burst length = 8
Data is masked out
Confidential
-23-
Rev.1.0 Sep.2014
AS4C32M32MD1
Read Concurrent Auto Precharge
Burst length = 4
CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
/CLK
CLK
BANK A
ACTIVATE
READ A
+ AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t RCD(min)
t RAS(min)
t RP
Begin of
Auto Precharge
BL / 2
LDQS,
UDQS
CL = 3
D-out
0
D-out
3
D-out D-out
DQx
1
2
Concurrent Read Auto Precharge Support
For same Bank
For different Bank
Asserted
Command
T4
NO
T5
NO
T6
NO
NO
NO
NO
T4
T5
T6
READ
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
READ+AP
ACTIVATE
PRECHARGE
YES
NO
YES
NO
YES
YES
YES
YES
Note: This table is for the case of Burst Length = 4, CAS Latency =3 and t
=2 clocks
WR
When READ with Auto Precharge is asserted, new commands can be asserted at T4,T5 and T6 as shown in Table
An Interrupt of a running READ burst with Auto Precharge i.e. at T4 and T5 to the same bank with another READ+AP command is
allowed, it will extend the begin of the internal Precharge operation to the last READ+AP command.
Interrupts of a running READ burst with Auto Precharge i.e. at T4 are not allowed when doing concurrent command to another active
bank. ACTIVATE or PRECHARGE commands to another bank are always possible while a READ with Auto Precharge operation is in
progress.
Confidential
-24-
Rev.1.0 Sep.2014
AS4C32M32MD1
Write with Autoprecharge (WRITEA)
If A8 is high when a Write command is issued, the Write with Auto-Precharge function is performed. The internal precharge begins after
the write recovery time t and t (min) are satisfied.
WR
RAS
If a Write with Auto Precharge command is initiated, the mobile DDR
edge of CLK after the last valid edge of DQS (completion of the burst) plus the write recovery time t
automatically enters the precharge operation at the first rising
. Once the precharge operation
WR
has started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (t ) has been satisfied.
RP
(min) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied.
If t
RAS
Write Burst with Auto Precharge
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
/CLK
CLK
BANK A
ACTIVATE
WRITE A
+ AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t RAS(min)
t WR
t RP
BL / 2
Begin of
Auto Precharge
LDQS,
UDQS
D-in
0
D-in
2
D-in
3
D-in
1
DQx
Note: t
starts at the first rising edge of clock after the last valid edge of the 4 DQSx.
WR
Table
Concurrent Write Auto Precharge Support
For same Bank
For different Bank
Asserted
Command
T3
NO
YES
NO
NO
NO
NO
T4
T5
T6
T7
T8
T3
NO
T4
T5
T6
T7
WRITE
WRITE+AP
READ
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
NO
YES
YES
NO
YES
YES
NO
YES
YES
YES
YES
YES
YES
NO
NO
READ+AP
ACTIVATE
PRECHARGE
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
When Write with Auto Precharge is asserted, new commands can be asserted at T3.. T8 as shown in Table .
An Interrupt of a running WRITE burst with Auto Precharge i.e. at T3 to the same bank with another WRITE+AP command is allowed
as long as the burst is running, it will extend the begin of the internal Precharge operation to the last WRITE+AP command.
Interrupts of a running WRITE burst with Auto Precharge i.e. at T3 are not allowed when doing concurrent WRITE s to another active
bank. Consecutive WRITE or WRITE+AP bursts (T4.. T7) to other open banks are possible. ACTIVATE or PRECHARGE commands to
another bank are always possible while a WRITE with Auto Precharge operation is in progress.
Confidential
-25-
Rev.1.0 Sep.2014
AS4C32M32MD1
Write interrupted by Read
/CLK
CLK
Write
tDQSS(min)
NOP
NOP
Read
NOP
NOP
NOP
Command
Last valid
data
tWTR
CL = 3
LDQS
UDQS
D-in
0
D-in
1
D-in
2
D-in
3
D-in
4
D-in
5
D-out
0
D-out
1
DQx
LDM
UDM
Data is masked
by Read
Data must be
masked
Burst length = 8
CL = 3
Confidential
-26-
Rev.1.0 Sep.2014
AS4C32M32MD1
Write Interrupted by a Precharge
A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank. Random column access is
allowed. A Write Recovery time (t ) is required from the last data to Precharge command. When Precharge command is asserted,
WR
any residual data from the burst write cycle must be masked by LDM., UDM.
Write interrupted by Precharge
/CLK
CLK
Write
bank A
Write
bank B
NOP
NOP
NOP
tWR
PRE
NOP
NOP
Command
tDQSSmin
tDQSSmin
Last valid
data
LDQS
UDQS
D-in
0
D-in
1
D-in
2
D-in
3
D-in
4
D-in
5
D-in
0
D-in
1
DQx
LDM
UDM
Data must be
masked
Data is masked
by Precharge
Burst length = 8
Confidential
-27-
Rev.1.0 Sep.2014
AS4C32M32MD1
Command Table
Table Command Overview
CKE
n-1
CKE
n
A0-9
A11,12
Operation
Code
CS# RAS# CAS# WE#
BA0
BA1
A10
DESEL
NOP
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
L
X
H
L
X
X
X
X
X
X
X
X
Device Deselect
No operation
Mode Register Setup
Extended Mode Register Setup
Bank Activate
MRS
0
0
OPCODE
OPCODE
EMRS
ACT
L
L
L
0
1
L
H
L
H
H
H
L
BA
BA
BA
BA
BA
X
BA
BA
BA
BA
BA
X
Row Address
Read
READ
READA
WRITE
H
H
H
H
H
L
L
H
L
Col.
Col.
Col.
Col.
X
Read with Auto Precharge
Write Command
L
L
Write Command with Auto Precharge WRITEA
L
L
H
X
L
Burst Stop
BST
H
H
H
L
L
Precharge Single Bank
Precharge All Banks
Autorefresh
PRE
L
BA
X
BA
X
X
PREAL
REF
L
L
H
X
X
X
L
H
H
X
X
X
Self Refresh Entry
REFX
L
L
X
X
X
L
L
H
H
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
Self Refresh Exit
SREFEX
PWDNEN
PWDNEX
Idle
H
H
L
L
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
Power Down Mode Entry (Note 1)
Power Down Mode Exit
H
L
X
valid
X
valid
X
valid
L
H
X
X
X
X
Deep Power Down Mode Entry
Deep Power Down Mode Exit
H
L
L
L
H
X
H
X
L
X
X
X
X
X
X
X
X
Deep pow-
er down
H
X
X
Note: 1: The Power Down Mode Entry command is illegal during Burst Read or Burst Write operations.
Confidential
-28-
Rev.1.0 Sep.2014
AS4C32M32MD1
Function Truth Table I
Current
State
Command
DESEL
Address
Action
Notes
X
X
X
NOP
3
3
3
1
1
NOP
BST
NOP
NOP
READ / READA
WRITE / WRITEA
ACT
BA,CA,A10
ILLEGAL
IDLE
BA,CA,A10
ILLEGAL
BA, RA
Bank Active
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA, A10
NOP
X
AUTO-Refresh or Self-Refresh
4
Op-Code
Mode Register Set or Extended Mode Register Set
X
NOP
NOP
X
NOP
BST
X
NOP
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
Begin Read, Determine Auto Precharge
Begin Write, Determine Auto Precharge
ILLEGAL
9
9
ROW
ACTIVE
BA, CA, A10
BA, RA
1, 5
6
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA, A10
Precharge / Precharge All
ILLEGAL
X
OP-Code
ILLEGAL
X
X
X
Continue burst to end
Continue burst to end
Terminate Burst
NOP
BST
Terminate burst, Begin New Read, Determine Auto-
Prechgarge
READ / READA
BA, CA, A10
7
READ
WRITE / WRITEA
ACT
BA, CA, A10
BA, RA
BA ,A10
X
ILLEGAL
2, 7
1
ILLEGAL
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
Terminate Burst / Precharge
ILLEGAL
Op-Code
X
ILLEGAL
Continue burst to end, Precharge
NOP
X
Continue burst to end, Precharge
BST
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
BA, CA, A10
BA, RA
BA ,A10
X
READ with
Auto
Precharge
1
1
PRE / PREAL
AREF / SREF
MRS / EMRS
Op-Code
Confidential
-29-
Rev.1.0 Sep.2014
AS4C32M32MD1
Function Truth Table I
Current
State
Command
DESEL
Address
Action
Notes
X
X
X
Continue burst to end
Continue burst to end
ILLEGAL
NOP
BST
Terminate Burst, Begin Read, Determine Auto-
Precharge.
READ / READA
BA, CA, A10
7, 8
2, 7
WRITE
Terminate Burst, Begin new Write, Determine Auto-
Precharge
WRITE / WRITEA
BA, CA, A10
BA, RA
ACT
ILLEGAL
1
8
,
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA A10
Terminate Burst , Precharge
X
ILLEGAL
OP-Code
ILLEGAL
X
Continue burst to end, Precharge
NOP
X
Continue burst to end, Precharge
BST
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
BA, CA, A10
BA, RA
WRITE with
Auto
Precharge
1
1
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA, A
X
10
OP-Code
X
NOP ( Row Active after t
NOP ( Row Active after t
NOP ( Row Active after t
ILLEGAL
)
)
)
RCD
RCD
RCD
NOP
X
BST
X
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
BA, CA, A10
BA, RA
1, 9
1, 9
1, 5
1, 6
ROW
ACTIVATING
ILLEGAL
ILLEGAL
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA, A
X
ILLEGAL
10
ILLEGAL
OP-Code
ILLEGAL
X
NOP ( Row Idle after t
NOP ( Row Idle after t
NOP ( Row Idle after t
ILLEGAL
)
)
)
RP
RP
RP
NOP
X
BST
X
READ / READA
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
1
1
1
PRECHARGE WRITE / WRITEA
ACT
ILLEGAL
ILLEGAL
PRE / PREAL
NOP ( Row Idle after t
ILLEGAL
)
1
RP
AREF / SREF
MRS / EMRS
OP-Code
ILLEGAL
Confidential
-30-
Rev.1.0 Sep.2014
AS4C32M32MD1
Function Truth Table I
Current
State
Command
DESEL
Address
Action
Notes
X
X
X
NOP (Row Active after t
NOP (Row Active after t
NOP (Row Active after t
)
)
)
WR
WR
WR
NOP
BST
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
Begin Read, Determine Auto-Prechgarge
2
WRITE
RECOVERING
BA, CA, A10
Begin Write, Determine Auto-Prechgarge
BA, RA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA ,A10
1, 10
X
OP-Code
X
NOP (Precharge after t
NOP (Precharge after t
NOP (Precharge after t
ILLEGAL
)
)
)
WR
WR
WR
NOP
X
BST
X
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
1, 2
1
WRITE
RECOVERING
with AUTO-
BA, CA, A10
ILLEGAL
PRECHARGE
BA, RA
ILLEGAL
1
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
BA ,A10
ILLEGAL
1
X
ILLEGAL
OP-Code
ILLEGAL
X
NOP (Idle after t
NOP (Idle after t
NOP (Idle after t
ILLEGAL
)
)
)
RC
RC
RC
NOP
X
BST
X
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
BA, CA, A10
BA, RA
BA ,A10
X
REFRESH
ILLEGAL
ILLEGAL
11
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
ILLEGAL
ILLEGAL
OP-Code
X
ILLEGAL
NOP (Idle after two clocks)
NOP (Idle after two clocks)
NOP (Idle after two clocks)
ILLEGAL
NOP
X
BST
X
READ / READA
WRITE / WRITEA
ACT
BA, CA, A10
BA, CA, A10
BA, RA
BA ,A10
X
(EXTENDED)
MODE
REGISTER
SET
ILLEGAL
ILLEGAL
PRE / PREAL
AREF / SREF
MRS / EMRS
ILLEGAL
ILLEGAL
OP-Code
ILLEGAL
Confidential
-31-
Rev.1.0 Sep.2014
AS4C32M32MD1
Note: All entries assume the CKE was High during the preceding clock cycle
Note: 1. Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank
Note: 2. Must satisfy bus contention, bus turn around, write recovery requirements.
Note: 3. If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and
CLK# will be disabled.
Note: 4. If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter SelfRefresh
Mode. All input buffers except CKE will be disabled.
Note: 5. Illegal, if t
Note: 6. Illegal, if t
Note: 7. Must satisfy burst interrupt condition.
is not satisfied.
is not satisfied.
RRD
RAS
Note: 8. Must mask two preceding data bits with the DM pin.
Note: 9. Illegal, if t
Note: 10. Illegal, if t
Note: 11. Illegal, if t
is not satisfied.
is not satisfied.
is not satisfied.
RCD
WR
RC
Abbreviations:
H
High Level
L
Low Level
X
Don't Care
V
Valid Data Input
Row Address
Bank Address
Precharge All
No Operation
Column Address
Address Line x
RA
BA
PA
NOP
CA
Ax
Confidential
-32-
Rev.1.0 Sep.2014
AS4C32M32MD1
FUNCTION TRUTH TABLE for CKE
Current
State
CKE
n-1
CKE
n
CS# RAS# CAS# WE#
Address
Action
Self Refresh Entry
Notes
H
L
L
H
H
H
H
H
L
L
H
L
L
L
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
X
H
H
H
L
X
H
H
H
L
Exit Self-Refresh
Exit Self-Refresh
ILLEGAL
L
SELF
REFRESH
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP ( Maintain Self Refresh)
INVALID
H
L
X
H
L
POWER
DOWN
Exit Power Down ( Idle after t
)
1
PDEX
L
NOP ( Maintain Power Down)
Refer to Function Truth Table
Enter Self Refresh
H
H
H
H
H
H
H
L
H
L
2
3
2
2
2
2
2
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power-Down
Enter Power-Down
ILLEGAL
ALL
BANKS
IDLE
L
L
L
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
ILLEGAL
X
H
X
X
X
X
X
X
Refer to Power Down in this table
Refer to Funtion Truth Table
All other states
H
Note: 1. CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any
commands other than EXIT are executed.
Note: 2. Power Down can be entered when all banks are idle (banks can be active or precharged)
Note: 3. Self Refresh can be entered only from the Precharge / Idle state.
Abbreviations:
H
High Level
L
Low Level
X
Don't Care
V
Valid Data Input
Row Address
Bank Address
Precharge All
No Operation
Column Address
RA
BA
PA
NOP
CA
Confidential
-33-
Rev.1.0 Sep.2014
AS4C32M32MD1
Mobile DDR SDRAM
operation State Diagram
DEEP
POWER
DOWN
ACT :
Active
DPDSX
Power
applied
ON
POWER
BST :
Burst
PCG.
ALL
BANKS
CKEL :
Enter Power-
Down
DPDS
CKEH :
Exit Power-Down
(E)MRS
SET
SELF
REFRESH
DPDS :
Enter Deep
Power-Down
MRS,
EMRS
REFS
DPDSX :
Exit Deep Power-
DownEMRS
REFSX
IDLE
ALL BANK
PCG.
CKEL
CKEH
EMRS :
Ext. Mode Reg.
Set
REFA
PCG.
POWER
DOWN
AUTO
REFRESH
MRS :
Mode Register Set
ACT
PRE :
Precharge
ACTIVE
POWER
DOWN
BURST
STOP
CKEL
PREALL :
Precharge All
Banks
CKEH
ROW
ACTIVE
BST
REFA :
Auto Refresh
WRITE
READ
REFS :
Enter Self Refresh
WRITE
READ
REFSX :
Exit Self Refresh
WRITE
READ
READ
READ :
Read w/o Auto
Precharge
WRITEA
READA
WRITEA
READA
READA :
Read with Auto
Precharge
READ A
WRITE A
PRE
PRE
PRE
WRITE :
Write w/o Auto
Precharge
WRITEA :
Write with Auto
Precharge
Precharge
ALL
COMMAND Input
AUTOMATIC
Sequence
Confidential
-34-
Rev.1.0 Sep.2014
AS4C32M32MD1
IDD Max Specifications and Conditions
Version
Conditions
Symbol
-5
Unit
Operating current - One bank Active-Precharge; tRC = tRC (min); tCK = tCK (min);
CKE = High; CS = High between valid command; Address inputs are switching every
2 clock cycles; Data bus inputs are stable
IDD0
100.0
mA
Precharge power-down standby current; All banks idle; CKE = Low; CS = High;
IDD2P
IDD2PS
IDD2N
600
600
18.0
14.0
5.0
uA
uA
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Precharge power-down standby current; Clock stopped; All banks idle; CKE = Low;
CS = High; CK = Low; CK# = High; Address and control inputs are switching;
Data bus inputs are stable
Precharge nonpower-down standby current; All banks idle; CKE = High; CS = High;
mA
mA
mA
mA
mA
mA
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current; Clock stopped; All banks idle;
CKE = High; CS = High; CK = Low; CK# = High; Address and control inputs are switching; IDD2NS
Data bus inputs are stable
Active power-down standby current; One bank active; CKE = Low; CS = High;
IDD3P
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Active power-down standby current; Clock stopped; One bank active; CKE =Low;
CS = High; CK = Low; CK# = High; Address and control inputs are switching;
Data bus inputs are stable
IDD3PS
IDD3N
5.0
Active nonpower-down standby current; One bank active; CKE = High; CS = High;
20.0
16.0
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Active nonpower-down standby current; Clock stopped; One bank active; CKE = High;
CS = High; CK = Low; CK# = High; Address and control inputs are switching;
Data bus inputs are stable
IDD3NS
Operating current - burst read; One bank active; Burst length = 4; tCK = tCK (min);
Continuous Read burst; Address inputs are switching every 2 clock cycles;
50% of data changing at every burst; lout = 0 m A
IDD4R
IDD4W
150.0
150.0
mA
mA
Operating current - burst write; One bank active; Burst length = 4; tCK = tCK (min);
Continuous Write burst; Address inputs are switching every 2 clock cycles;
50% of data changing at every burst
Auto refresh current; Burst refresh; CKE = High; Address and
tRFC = 110ns
tRFC = tREFI
IDD5
100.0
15.0
mA
mA
control inputs are switching; Data bus inputs are stable
IDD5A
Deep Power Down Current; Address and control inputs are stable;
IDD8
10.0
uA
Data bus inputs are stable
Confidential
-35-
Rev.1.0 Sep.2014
AS4C32M32MD1
Partial Array Self Refresh Current (PASR)
Extended Mode
Parameter & Test Condition
Symb.
max.
Unit
Note
Register A[2:0]
Tcase [oC]
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
85oC max.
45oC max.
85oC max.
45oC max.
85oC max.
45oC max.
ICC6
ICC6
ICC6
ICC6
ICC6
ICC6
1200
500
900
300
760
220
uA
uA
uA
uA
uA
uA
full array activations, all banks
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
1/2 array activations
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
1/4 array activation
Confidential
-36-
Rev.1.0 Sep.2014
AS4C32M32MD1
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-0.5 ~ 2.7
-0.5 ~ 2.7
-55 ~ +150
1.0
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Capacitance (V = 1.8V, T = 25°C, f = 1MHz)
DD
A
Parameter
Symbol
CIN1
Min
1.5
1.5
3.0
3.0
Max
3.0
Unit
Input capacitance (A0~A12, BA0~BA1,CKE, CS, RAS, CAS, WE )
Input capacitance ( CK, CK,)
pF
pF
pF
pF
CIN2
3.0
Data & DQS input/output capacitance (DQ0~DQ15
)
COUT
CIN3
5.0
Input capacitance (DMs)
5.0
Confidential
-37-
Rev.1.0 Sep.2014
AS4C32M32MD1
Power & DC Operating Conditions (LVCMOS In/Out)
Recommended operating conditions ( Voltage referenced to VSS= 0V )
Parameter
Symbol
VDD
VDDQ
VIH
Min
1.7
Typ
Max
1.95
Unit
V
Device Supply voltage
1.8
Output Supply voltage
Input logic high voltage
Input logic low voltage
Input Leakage current
Output Leakage current
1.7
1.8
1.95
V
0.7*VDDQ
-0.3
-
-
-
-
VDDQ+0.30
0.3*VDDQ
2
V
VIL
V
II
-2
uA
uA
IOZ
-5
5
AC Input Operating Conditions
Recommended operating conditions ( Voltage referenced to VSS= 0V, VDD= 1.7V-1.9V )
Parameter
Symbol
VIH
Min
VCCQ*0.8
-0.3
Typ
Max
Unit
V
Input High (Logic 1) Voltage; DQ
Input Low (Logic 0) Voltage; DQ
-
-
-
VCCQ+0.3
0.2* VDDQ
0.6*VDDQ
VIL
V
Clock Input Crossing Point Voltage; CK and CK
VIX
0.4*VDDQ
V
AC Operating Test Conditions
Recommended operating conditions ( Voltage referenced to VSS= 0V, VDD= 1.7V-1.9V )
Parameter
Value
0.8*VDDQ / 0.2*VDDQ
0.5*VDDQ
Unit
V
AC input levels (Vih/Vil)
Input timing measurement reference level
Input signal minimum slew rate
V
1.0
V/ns
V
Output timing measurement reference level
Output load condition
0.5*VDDQ
See below figures
1.8V
Vtt=0.5 x VDDQ
13.9K
V
OH (DC) = 0.9 x VDDQ, IOH = -0.1mA
OL (DC) = 0.1 x VDDQ, IOL = 0.1mA
Output
50
V
30pF
10.6K
Output
Z0=50
30pF
DC Output Load Circuit
AC Output Load Circuit
Confidential
-38-
Rev.1.0 Sep.2014
AS4C32M32MD1
AC Timing Parameters & Specification
AC CHARACTERISTICS
-5
SYMBOL MIN MAX
PARAMETER
UNITS NOTES
Output data access time from CK/CK
CK high-level width
tAC
tCH
2
0.45
0.45
5
5
ns
tCK
tCK
ns
3
0.55
0.55
-
CK low-level width
tCL
Clock cycle time
CL = 3
tCK (3)
tDH
1
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK
DQS input high pulse width
0.4
0.4
1.4
2
ns
5,6
5,6
tDS
ns
tDIPW
tDQSCK
tDQSH
tDQSL
ns
5
ns
0.4
0.4
0.6
0.6
tCK
tCK
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid,
per group, per access
tDQSQ
tDQSS
tHP
0.4
ns
tCK
ns
1
Write command to first DQS latching
transition
0.75
1.25
Half clock period
tCH,
tCL
Data-out high-impedance window
from CK/CK
tHZ
0.4
1
0.6
tCK
ns
Data-out low-impedance window
from CK/CK
tLZ
Address and control input hold time
Address and control input setup time
tIH
tIS
0.9
0.9
ns
ns
1
1
LOAD MODE REGISTER command
cycle time
tMRD
tQH
2
tCK
ns
DQ-DQS hold, DQS to first DQ to go
non-valid, per access
tHP
-tQHS
Data hold skew factor
tQHS
tRAS
0.5
ns
ns
ACTIVE to PRECHARGE command
40
15
70K
ACTIVE to READ with Auto precharge
command
tRAP
tRC
ns
ns
ACTIVE to ACTIVE/AUTO REFRESH
command period
55
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
tRFC
tRCD
tRP
72
15
15
ns
ns
ns
Confidential
-39-
Rev.1.0 Sep.2014
AS4C32M32MD1
AC CHARACTERISTICS
PARAMETER
-5
SYMBOL MIN MAX
UNITS NOTES
DQS read preamble
tRPRE
tRPST
tRRD
0.9
0.4
10
1.1
0.6
tCK
tCK
ns
DQS read postamble
ACTIVE bank A to ACTIVE bank B command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
tCK
ns
DQS write preamble setup time
DQS write postamble
4
0.4
15
0.6
7.8
tCK
ns
Write recovery time
Internal WRITE to READ command
delay
tWTR
tREFI
tPDEX
2
tCK
us
Average periodic refresh interval
Power down exit time
1*tCK
+tIS
ns
Confidential
-40-
Rev.1.0 Sep.2014
AS4C32M32MD1
1. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
tIS
(ps)
0
tIH
(ps)
0
(V/ns)
1.0
0.8
+50
+100
+50
+100
0.6
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns.
2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25 C).
tAC (max) value is measured at the low Vdd(1.7V) and hot temperature(85 C).
tAC is measured in the device with half driver strength and under the AC output load condition.
4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
5. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
tDS
(ps)
0
tDH
(ps)
0
(V/ns)
1.0
0.8
+75
+150
+75
+150
0.6
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns.
6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
tDS
(ps)
tDH
(ps)
0
(ns/V)
0
0
0.25
0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall
Rate =-0.25ns/V.
Confidential
-41-
Rev.1.0 Sep.2014
AS4C32M32MD1
Package Diagram
32Mx32 90-BALL 0.8mm pitch BGA
Confidential
-42-
Rev.1.0 Sep.2014
AS4C32M32MD1
PART NUMBERING SYSTEM
AS4C
32M32MD1
5
B
C/I
N
C=Commercial
32M32=32Mx32
MD1=MobileDDR1
Indicates Pb and
Halogen Free
(-25¡ Cꢀ85¡ C)*
DRAM
5=200MHz
B = FBGA
I=Industrial
(-40¡ Cꢀ85¡ C)
* Extended temperature
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such
use and agrees to indemnify Alliance against all claims arising from such use.
Confidential
-43-
Rev.1.0 Sep.2014
相关型号：
©2020 ICPDF网 联系我们和版权申明